Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.
In a superconducting quantum processor, inductance is a characteristic of superconducting flux qubits and used to achieve coupling between qubits. In general, higher qubit energy scale results in better quantum processor performance. Energy scale of qubits can be increased by reducing inductance. For each Ising spin problem, qubit energy scale can be increased by determining the unused inductance-tuner range for each qubit and the minimum homogenized inductance achievable across all qubits, then adjusting the inductance-tuner to achieve the minimum homogenized inductance. When the inductance of a qubit is changed, there is a shift in the CCJJ bias at which quantum annealing is performed for that qubit. The variation in CCJJ bias shift can be compensated by computing the shift in CCJJ bias due to the applied inductance and applying a compensating CCJJ bias via the CCJJ offset DAC.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
H03K 17/92 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs supraconducteurs
3.
KINETIC INDUCTANCE FOR COUPLERS AND COMPACT QUBITS
A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.
H10N 69/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comportant au moins un élément supraconducteur couvert par le groupe
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G05B 19/042 - Commande à programme autre que la commande numérique, c.-à-d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
5.
INPUT/OUTPUT SYSTEMS AND METHODS FOR SUPERCONDUCTING DEVICES
A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
Topologies for analog processors may include cells comprising at least portions of qubits and couplers. Qubits and couplers may be shared among or extend across multiple cells. A cell may include four sets of partial qubits, and partial qubits may form whole qubits with partial qubits in adjacent cells. First and second sets of partial qubits may include partial qubits that extend substantially parallel to one another and along a first direction. Third and fourth sets may include partial qubits that extend substantially parallel to one another and along a second direction. Each partial qubit in the first and second sets may cross, and be substantially orthogonal to, at least one partial qubit from each of the third and fourth sets. A cell may include first and second sets of intra-cell couplers, and partial couplers that form inter-cell couplers with partial couplers in adjacent cells.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
G06N 3/044 - Réseaux récurrents, p. ex. réseaux de Hopfield
G06N 3/047 - Réseaux probabilistes ou stochastiques
G06N 7/08 - Agencements informatiques fondés sur des modèles mathématiques spécifiques utilisant des modèles de chaos ou des modèles de systèmes non linéaires
8.
SYSTEMS AND METHODS FOR IMPROVING COMPUTATIONAL EFFICIENCY OF PROCESSOR-BASED DEVICES IN SOLVING CONSTRAINED QUADRATIC MODELS
Systems and methods for optimization algorithms, updating samples, and penalizing constraint violations are discussed. A method for updating samples includes receiving a problem definition with an objective function and constraint functions, an initial sample, and a value for a progress parameter. For each variable a total energy change is determined based on an objective energy change based on the sample value for the variable and one or more terms of the objective function that include the variable and a constraint energy change based on the sample value for the variable and each of the constraint functions defined by the variable. A sampling distribution is selected based on the variable type and an updated value is sampled based on the total energy change and the progress parameter. An updated sample is returned with an updated value for each variable of the set of variables. Such may improve operation of processor-based systems.
A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together.
Systems and methods for operating a computer system to generate samples having improved diversity are discussed. A processor receives a problem definition with a problem Hamiltonian defined over a set of variables and samples one or more values for the set of variables from the problem Hamiltonian, the one or more values for the set of variables comprising a first set of samples. At least a subset of the first set of samples is selected, and a diversity Hamiltonian based on the at least a subset of the first set of samples is generated. The problem Hamiltonian and the diversity Hamiltonian are combined to generate a combined Hamiltonian, and one or more values for the set of variables are sampled from the combined Hamiltonian, the one or more values for the set of variables comprising a second set of samples.
Systems and methods for random number generation are discussed. A first processor is in communication with a quantum processor, the quantum processor having an array of superconducting qubits. The first processor instructs the quantum processor to selectively communicatively couple the superconducting qubits to embed a quantum system having a highly entangled nontrivial ground state. The highly entangled nontrivial ground state comprising a uniform distribution of classical ground states. One or more distortions are introduced to the uniform distribution by one or more random variations based on an input value. The quantum processor evolves over the embedded quantum system. A set of one or more random numbers is received from the quantum processor.
G06F 7/58 - Générateurs de nombres aléatoires ou pseudo-aléatoires
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.
Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.
Systems and methods for operation of a computing system to direct a search space for an optimization problem are described. One or more processors initialize an optimization algorithm, and iteratively until a termination criteria is met: receive a sample solution from the optimization algorithm, evaluate quality and feasibility of the sample solution, and where the sample solution is feasible and has the best quality so far, freeze one or more penalty parameters for a set number of iterations. Where the sample solution is not feasible or does not have the best quality so far, the one or more penalty parameters are updated based on a finite state machine, the updated one or more penalty parameters are returned to the optimization algorithm, the optimization algorithm is incremented, the termination criteria is evaluated, and when the termination criteria is met, one or more sample solutions are returned.
There is provided a system and methods of training and predicting an outcome using quantum annealing-assisted reservoir computing. The methods are performed by a digital computer in communication with a quantum processor including a plurality of qubits. Methods include: receiving input data; initializing first states of the qubits; and, for each input: determining values of Hamiltonian parameters based on the input, programming the quantum processor based on the determined Hamiltonian parameters, performing an annealing protocol to evolve the qubits to second states, and applying a linear transformation to the second states to determine a predicted output. During training, a set of linear parameter weights are optimized using linear regression. As part of the annealing protocol, reverse annealing is performed to a point in the quantum critical region having maximally complex dynamics, therefore measured second states are highly separable in the higher dimensional space for providing high-accuracy predicted outputs.
A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.
G06F 3/04847 - Techniques d’interaction pour la commande des valeurs des paramètres, p. ex. interaction avec des règles ou des cadrans
G06F 3/04817 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] fondées sur des propriétés spécifiques de l’objet d’interaction affiché ou sur un environnement basé sur les métaphores, p. ex. interaction avec des éléments du bureau telles les fenêtres ou les icônes, ou avec l’aide d’un curseur changeant de comportement ou d’aspect utilisant des icônes
G06F 16/901 - IndexationStructures de données à cet effetStructures de stockage
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06T 11/20 - Traçage à partir d'éléments de base, p. ex. de lignes ou de cercles
18.
Systems and methods for tuning capacitance in quantum devices
Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
19.
SYSTEMS AND METHODS FOR CONTROLLING QUANTUM COMPONENTS
Programmable components of a quantum processor may be selectively programmed using digital to analog converters (DACs). A DAC with a first stage and a second stage and first and second quantum flux parametron (OFF) loops galvanically coupled to and extending from a respective one of the first stage and the second stage is discussed. The first stage has a first storage loop interrupted by a first Josephson junction and an interface for communicating with an external component. The second stage has a second storage loop interrupted by a second Josephson junction, the second storage loop galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction coupled in series to a first control line. A method of loading flux quanta into targeted DAC stages is also discussed.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
A system, comprising a superconducting integrated circuit and a controller, may be operated to apply, for each power level of a sequence of discrete power levels on a respective one of a plurality of power lines, one or more pulses via a respective one of a plurality of addressing lines to a respective compound Josephson junction of each of a plurality of flux storage devices of the superconducting integrated circuit to cause each of the plurality of flux storage devices to reset. Power levels may be based at least in part on an estimated worst-case asymmetry between Josephson junctions of the compound Josephson junctions. The system may be operated to partition the plurality of addressing lines into groups, and apply a respective sequence of pulses to each addressing line of each pairwise combination of groups to cause one or more of the plurality of flux storage devices to reset.
Methods and systems for calibrating quantum processors are discussed. A model of a portion of the processor to be calibrated has one or more determinable parameters and an uncertainty for the determinable parameter(s). A measurement procedure is iteratively performed by selecting a subset of possible measurements and generating predicted measurement outcomes and predicted uncertainties for the determinable parameter for each measurement in the subset of possible measurements. Based on the predicted reduction in uncertainty for the determinable parameter, one or more measurements is selected. Instructions are transmitted to the quantum processor to perform the selected measurements, and the results are returned to update the model of the portion of the processor to be calibrated. Once a termination criteria is met, a calibrated value is generated for the determinable parameter. Compensating signals can be applied to devices of the quantum processor to calibrate the devices.
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
22.
THERMALLY ISOLATING CABLING ASSEMBLIES, SYSTEMS USING THERMALLY ISOLATING CABLING ASSEMBLIES, AND METHODS OF FABRICATING THERMALLY ISOLATING CABLING ASSEMBLIES
Thermally isolating cable assemblies, systems using the assemblies, and methods for fabricating the assemblies are discussed. A cable assembly includes a first shielding cable comprising a first solderable material interleaved with a section of a second shielding cable comprising an exterior material that is a second solderable material and an inner material that is superconductive at and below a critical temperature. The cable assembly may be fabricated during the assembly of an apparatus, and, following assembly of the apparatus, a segment of the second shielding cable is etched to expose a portion of the inner material. Following fabrication of the cable assemblies, the apparatus may be installed in a cryogenic environment in which the inner material may be operable as a superconductor and may thermally isolate the cabling assembly distal to the exposed portion to reduce heat load to a superconducting circuit.
In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and a magnetic field generator operable to apply a magnetic field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a first capacitor plate having a plane, a second capacitor plate having a plane, and a dielectric interposed between the first capacitor plate and the second capacitor plate. The plane of the second capacitor plate is geometrically parallel to the plane of the first capacitor plate. In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and an electric field generator operable to apply an electric field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a pair of capacitor plates, and a dielectric interposed between the pair of plates.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
Systems and methods for measuring noise in discrete regions of multi-layer superconducting fabrication stacks are described. Methods for measuring noise in spatial regions of a superconducting fabrication stacks may include the use of resonators, each having a different geometry. As many resonators as spatial regions are fabricated. Data collected from the resonators may be used to calculate fill fractions and spin densities for different spatial regions of the superconducting fabrication stack. The data may be collected via on-chip electron-spin resonance. The superconducting fabrications may be part of a fabrication stack for a superconducting processor, for example a quantum processor, and the spatial region studied may be proximate to qubit wiring layers.
Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.
In a superconducting quantum processor, inductance is a characteristic of superconducting flux qubits and used to achieve coupling between qubits. In general, higher qubit energy scale results in better quantum processor performance. Energy scale of qubits can be increased by reducing inductance. For each Ising spin problem, qubit energy scale can be increased by determining the unused inductance-tuner range for each qubit and the minimum homogenized inductance achievable across all qubits, then adjusting the inductance-tuner to achieve the minimum homogenized inductance. When the inductance of a qubit is changed, there is a shift in the CCJJ bias at which quantum annealing is performed for that qubit. The variation in CCJJ bias shift can be compensated by computing the shift in CCJJ bias due to the applied inductance and applying a compensating CCJJ bias via the CCJJ offset DAC.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
27.
Display screen or portion thereof with graphical user interface
Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G05B 19/042 - Commande à programme autre que la commande numérique, c.-à-d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
29.
Systems and methods for heuristic algorithms with variable effort parameters
A heuristic solver is wrapped in a meta algorithm that will perform multiple sub-runs within the desired time limit, and expand or reduce the effort based on the time it has taken so far and the time left. The goal is to use the largest effort possible as this typically increases the probability of success. In another implementation, the meta algorithm iterates the time-like parameter from a small value, and determine the next test-value so as to minimize time to target collecting data at large effort only as necessary. The meta algorithm evaluates the energy of the solutions obtained to determine whether to increase or decrease the value of the time-like parameter. The heuristic algorithm may be Simulated Annealing, the heuristic algorithm may run on a quantum processor, including a quantum annealing processor or a gate-model quantum processor.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
A superconducting integrated circuit has a first superconducting device with a first superconducting loop, where the first superconducting loop has a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device with a second superconducting loop, where the second superconducting loop has a second superconducting trace in a second layer. The first superconducting loop crosses the second superconducting loop in a crossing region. At least a portion of each of the first and the second superconducting trace inside the crossing region is narrower than at least a portion of each of the traces outside the crossing region, and follows a respective circuitous path which is inductively proximate to at least a portion of the other path.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
Methods of forming superconducting integrated circuits are discussed. The method includes depositing a first superconducting metal layer to overlie at least a portion of a substrate, depositing a dielectric layer to cover a first region of the first superconducting metal layer, pattering the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and form an opening, and depositing a second superconducting metal layer at an ambient temperature that is less than a melting temperature of the second superconducting metal layer such that the second superconducting metal layer fills the opening and conductively contacts the at least a portion of the first region of the first superconducting metal layer.
Collaborative filtering systems based on variational autoencoders (VAEs) are provided. VAEs may be trained on row-wise data without necessarily training a paired VAE on column-wise data (or vice-versa), and may optionally be trained via minibatches. The row-wise VAE models the output of the corresponding column-based VAE as a set of parameters and uses these parameters in decoding. In some implementations, a paired VAE is provided which receives column-wise data and models row-wise parameters; each of the paired VAEs may bind their learned column- or row-wise parameters to the output of the corresponding VAE. The paired VAEs may optionally be trained via minibatches. Unobserved data may be explicitly modelled. Methods for performing inference with such VAE-based collaborative filtering systems are also disclosed, as are example applications to search and anomaly detection.
A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
A method of generating a coupling gate between qubits and a superconducting integrated circuit providing a pulse source are discussed. The method includes energizing a power line connected to a pulse source, applying a signal to a control line in communication with a coupler, the coupler in communication between the two qubits, and applying a second signal to a control line in communication with a resonator. The method further includes inducing a tone on a transmission line that selectively communicates with the resonator to bias the resonator, the resonator coupling a signal to the pulse source in combination with the power line, and applying a third signal to a pulse source control line in communication with the pulse source, the pulse source applying a pulse to the coupler in response to the third signal to couple the two qubits for a duration of the coupling gate.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
35.
SYSTEMS AND METHODS FOR TUNABLE PARAMETRIC AMPLIFICATION
In an implementation, a tunable traveling wave parametric amplifier (TWPA) includes a T-stage that includes a first DC-SQUID and a first interface inductively communicatively coupled to the first DC SQUID operable to apply a first bias to the first DC SQUID. The T-stage also includes a second DC-SQUID electrically communicatively coupled to the first DC-SQUID in series via a center node, and a second interface inductively communicatively coupled to the second DC-SQUID operable to apply a second bias to the second DC-SQUID. The TWPA also includes a shunting resonator communicatively coupled to the center node via a coupling capacitance. The shunting resonator includes a third DC-SQUID, and a third interface inductively communicatively coupled to the third DC SQUID operable to apply a third bias to the third DC SQUID. The first, second, and third biases are adjustable to improve a bandwidth of the tunable TWPA.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
H03F 7/04 - Amplificateurs paramétriques utilisant un élément à capacité variableAmplificateurs paramétriques utilisant un élément à permittivité variable
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
36.
Systems and methods for hybrid algorithms using cluster contraction
Systems and methods are described for operating a hybrid computing system using cluster contraction for converting large, dense input to reduced input that can be easily mapped into a quantum processor. The reduced input represents the global structure of the problem. Techniques involve partitioning the input variables into clusters and contracting each cluster. The input variables can be partitioned using an Unweighted Pair Group Method with Arithmetic Mean algorithm. The quantum processor returns samples based on the reduced input and the samples are expanded to correspond to the original input.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06F 17/18 - Opérations mathématiques complexes pour l'évaluation de données statistiques
G06F 18/21 - Conception ou mise en place de systèmes ou de techniquesExtraction de caractéristiques dans l'espace des caractéristiquesSéparation aveugle de sources
G06F 18/23213 - Techniques non hiérarchiques en utilisant les statistiques ou l'optimisation des fonctions, p. ex. modélisation des fonctions de densité de probabilité avec un nombre fixe de partitions, p. ex. K-moyennes
37.
SYSTEMS AND METHODS FOR QUANTUM COMPUTING USING FLUXONIUM QUBITS WITH KINETIC INDUCTORS
A superconducting device may have a body loop comprising a body loop comprising a Josephson junction structure and a kinetic inductor. The superconducting device can be a qubit in a quantum processor for performing gate-model quantum computation. The superconducting device may be fabricated with a single wiring layer embedded in a single-crystalline substrate trench. The superconducting device may be fabricated with a wiring layer and an insulating layer in a single-crystalline substrate trench. The superconducting device may be fabricated with multiple wiring layers embedded in a single-crystalline substrate trench. The device may be fabricated by defining trenches in the single-crystalline substrate, with the trenches having a depth matching the desired numbers of wiring layers and insulating layers.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
38.
SYSTEMS AND METHODS FOR SUPERCONDUCTING FLUX QUBIT READOUT
A superconducting flux qubit readout system may include an input-output system connected to at least one shift register, the shift register comprising a first set, a second set, and a third set of shift register stages arranged in series, the first set of shift register stages coupled to a first set of qubits by a first plurality of latches, and the second set of shift register stages coupled to a second set of qubits by a second plurality of latches. Reading out states of a first set of qubits may include: shifting qubit state information to first holding latches communicatively coupled to a shift register; obtaining, by each shift register stage of the first set of shift register stages, state information from the first holding latches; and, propagating information along the shift register.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
39.
SYSTEMS AND METHODS FOR SCALABLE QUANTUM COMPUTING
A superconducting circuit includes four superconducting qubits communicatively coupled by a 4-qubit even-parity stabilizer. The 4 -qubit even-parity stabilizer includes a superconducting stabilizer loop, and four inductances, each inductance inductively communicatively coupled to an inductance of a respective one of the four superconducting qubits. The 4-qubit even-parity stabilizer also includes a parity-enforcing super-conducting qubit communicatively coupled to the superconducting loop. A quantum processor comprises four Josephson parametric amplifiers communicatively coupled by a 4-qubit even-parity stabilizer. The Josephson parametric amplifiers comprise pairs of superconducting microwave resonators communicatively coupled by a compound-compound Josephson junction. The 4-qubit even-parity stabilizer includes a superconducting loop, four inductances inductively communicatively coupled to an inductance of a respective one of the four Josephson parametric amplifier, and a parity-enforcing Josephson parametric amplifier communicatively coupled to the superconducting loop.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
40.
SYSTEMS AND METHODS FOR FABRICATING SUPERCONDUCTING INTEGRATED CIRCUITS
Methods for mitigating microwave crosstalk and forming a component in a superconducting integrated circuit are discussed. Mitigating microwave crosstalk involves forming a microwave shield within the superconducting integrated circuit, the superconducting integrated circuit including a microwave sensitive component. The microwave shield is formed from a base layer and one or more sides, and the footprint of the microwave sensitive component is contained within the footprint of the microwave shielding base layer, with the one or more sides extending around at least a portion of the microwave sensitive component. Forming a component involves depositing a first metal layer, depositing a dielectric layer overlying the first metal layer, the dielectric layer comprising Nb2O5 that is deposited by atomic layer deposition, and depositing a second metal layer overlying the dielectric layer.
H01L 39/02 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails
H01L 27/18 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants présentant un effet de supraconductivité
H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par ou de leurs parties constitutives
41.
SYSTEMS AND METHODS OF HYBRID ALGORITHMS FOR SOLVING DISCRETE QUADRATIC MODELS
Methods for solving discrete quadratic models are described. The methods compute an energy of each state of each variable based on its interaction with other variables, exponential weights, and normalized probabilities proportional to the exponential weights. The energy of each variable is computed as a function of the magnitude of each variable and a current state of all other variables, exponential weights, the feasible region for each variable, and normalized probabilities, proportional to the exponential weights and respecting constraints. Methods executed via a hybrid computing system obtain two candidate values for each variable; constructs a Hamiltonian that uses a binary value to determine which candidate values each variable should take, then constructs a binary quadratic model based on the Hamiltonian. Samples from the binary quadratic model are obtained via a quantum processor. The methods can be applied to solve resource scheduling optimization problems and/or for side-chain optimization for proteins.
Topologies for analog processors may include cells comprising at least portions of qubits and couplers. Qubits and couplers may be shared among or extend across multiple cells. A cell may include four sets of partial qubits, and partial qubits may form whole qubits with partial qubits in adjacent cells. First and second sets of partial qubits may include partial qubits that extend substantially parallel to one another and along a first direction. Third and fourth sets may include partial qubits that extend substantially parallel to one another and along a second direction. Each partial qubit in the first and second sets may cross, and be substantially orthogonal to, at least one partial qubit from each of the third and fourth sets. A cell may include first and second sets of intra-cell couplers, and partial couplers that form inter-cell couplers with partial couplers in adjacent cells.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
43.
SYSTEMS AND METHODS FOR TUNING CAPACITANCE OF QUBITS
An analog computing system having a qubit which is provided with inductors positioned near to the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. Near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitance for the qubit. The inductors may be tuned to homogenize both capacitance and inductance.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson
44.
SYSTEMS AND METHODS FOR TUNING CAPACITANCE IN QUANTUM DEVICES
Systems and methods for capacitance tuning of devices in quantum processors are described. One implementation is a quantum processor with a first current path having a first loop, a Josephson structure with at least one Josephson junction interrupting the first loop, a second current path connected to the first current path, and a flux bias. The second current path has a first node spaced from a second node, a capacitor separating the first node and the second node, and a voltage gain tuner, the voltage gain tuner being inductively coupled to the inductance of the first current path. The flux bias is coupled to the voltage gain tuner and controls the voltage gain tuner to vary a voltage ratio between the first node and the second node, thereby influencing the capacitance of the first current path.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
45.
Systems and methods for coupling a superconducting transmission line to an array of resonators
A superconducting circuit may include a transmission line having at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. The transmission line inductance may have a value selected to at least partially compensate for a variation in a characteristic impedance of the transmission line, the variation caused at least in part by the coupling capacitance. The coupling capacitance may be distributed along the length of the transmission line. A superconducting circuit may include a transmission line having at least one transmission line capacitance, a superconducting resonator, and a coupling inductance that communicatively couples the superconducting resonator to the transmission line. The transmission line capacitance may be selected to at least partially compensate for a variation in coupling strength between the superconducting resonator and the transmission line.
An accelerated version of a node-weighted path distance algorithm is implemented on a microprocessor coupled to a digital processor. The algorithm calculates an embedding of a source graph into a target graph (e.g., hardware graph of a quantum processor). The digital processor causes the microprocessor to send seeds to logic blocks with a corresponding node in the target graph contained in a working embedding of a node, compute a minimum distance to neighboring logic blocks from each seeded logic block, set the distance to neighboring logic blocks as the minimum distance plus the weight of the seeded logic block, increment the accumulator value by the weight of the seeded logic block, increment the accumulator value by the distance, determine the minimum distance logic block by computing the minimum accumulated value, compute distances to the minimum distance logic block; and read distances from all logic blocks into local memory.
G06N 10/80 - Programmation quantique, p. ex. interfaces, langages ou boîtes à outils de développement logiciel pour la création ou la manipulation de programmes capables de fonctionner sur des ordinateurs quantiquesPlate-formes pour la simulation ou l’accès aux ordinateurs quantiques, p. ex. informatique quantique en nuage
G06N 10/60 - Algorithmes quantiques, p. ex. fondés sur l'optimisation quantique ou les transformées quantiques de Fourier ou de Hadamard
47.
User interface, programmer and/or debugger for embedding and/or modifying problems on quantum processors
A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.
G06F 3/048 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI]
G06F 3/04847 - Techniques d’interaction pour la commande des valeurs des paramètres, p. ex. interaction avec des règles ou des cadrans
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06T 11/20 - Traçage à partir d'éléments de base, p. ex. de lignes ou de cercles
G06F 3/04817 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] fondées sur des propriétés spécifiques de l’objet d’interaction affiché ou sur un environnement basé sur les métaphores, p. ex. interaction avec des éléments du bureau telles les fenêtres ou les icônes, ou avec l’aide d’un curseur changeant de comportement ou d’aspect utilisant des icônes
G06F 16/901 - IndexationStructures de données à cet effetStructures de stockage
48.
SYSTEMS AND METHODS FOR IMPROVING COMPUTATIONAL EFFICIENCY OF PROCESSOR-BASED DEVICES IN SOLVING CONSTRAINED QUADRATIC MODELS
Systems and methods for optimization algorithms, updating samples, and penalizing constraint violations are discussed. A method for updating samples includes receiving a problem definition with an objective function and constraint functions, an initial sample, and a value for a progress parameter. For each variable a total energy change is determined based on an objective energy change based on the sample value for the variable and one or more terms of the objective function that include the variable and a constraint energy change based on the sample value for the variable and each of the constraint functions defined by the variable. A sampling distribution is selected based on the variable type and an updated value is sampled based on the total energy change and the progress parameter. An updated sample is returned with an updated value for each variable of the set of variables. Such may improve operation of processor-based systems.
G06N 10/60 - Algorithmes quantiques, p. ex. fondés sur l'optimisation quantique ou les transformées quantiques de Fourier ou de Hadamard
G06N 10/80 - Programmation quantique, p. ex. interfaces, langages ou boîtes à outils de développement logiciel pour la création ou la manipulation de programmes capables de fonctionner sur des ordinateurs quantiquesPlate-formes pour la simulation ou l’accès aux ordinateurs quantiques, p. ex. informatique quantique en nuage
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
49.
Systems and methods for analog processing of problem graphs having arbitrary size and/or connectivity
Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.
A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson
H01L 39/06 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par le parcours du courant
Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.
H01L 39/02 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails
A digital processor simulates a quantum computing system by implementing a QPU model including a set of representation models and a device connectivity representation to simulate a quantum processor design or a physical quantum processor. The digital processor receives an analog waveform and generates a digital waveform representation comprising a set of waveform values that correspond to biases applied to programmable devices in a quantum processor. The digital processor selects a subset of waveform values based on channels in the device connectivity representation. The digital processor implements a representation model to compute a response based on the waveform values and a plurality of physical parameter values, the physical parameters characterizing a programmable device in a quantum processor. The device connectivity representation can be generated from a design implementation, validated against a set of rules, and adjusted to change the device connectivity representation until all of the rules are passed.
G06F 30/3308 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation
G06J 3/00 - Systèmes pour action en coordination de calculateurs numériques et analogiques
G06N 10/80 - Programmation quantique, p. ex. interfaces, langages ou boîtes à outils de développement logiciel pour la création ou la manipulation de programmes capables de fonctionner sur des ordinateurs quantiquesPlate-formes pour la simulation ou l’accès aux ordinateurs quantiques, p. ex. informatique quantique en nuage
53.
SYSTEMS AND METHODS FOR CONTROLLING QUANTUM COMPONENTS
Programmable components of a quantum processor may be selectively programmed using digital to analog converters (DACs). A DAC with a first stage and a second stage and first and second quantum flux parametron (OFF) loops galvanically coupled to and extending from a respective one of the first stage and the second stage is discussed. The first stage has a first storage loop interrupted by a first Josephson junction and an interface for communicating with an external component. The second stage has a second storage loop interrupted by a second Josephson junction, the second storage loop galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction coupled in series to a first control line. A method of loading flux quanta into targeted DAC stages is also discussed.
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G05B 19/042 - Commande à programme autre que la commande numérique, c.-à-d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
55.
Systems and methods for improving the performance of non-stoquastic quantum devices
A technique for improving the performance of non-stoquastic quantum processors is provided. Clusters of qubits with correlated behavior are identified in a problem for processing by the quantum processor. Couplings between qubits in a common cluster are modified according to a transformation (for example, a gauge transformation) so that they evolve slower and thus their dynamics freeze out later (for example, by flipping anti-ferromagnetic couplings to ferromagnetic couplings). Couplings between qubits that do not belong to the common cluster may be flipped the other way (for example, from ferromagnetic couplings to anti-ferromagnetic couplings) to accelerate their dynamics. The quantum processor is evolved and the results are modified according to an inverse transformation.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
56.
Input/output systems and methods for superconducting devices
A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
A system, comprising a superconducting integrated circuit and a controller, may be operated to apply, for each power level of a sequence of discrete power levels on a respective one of a plurality of power lines, one or more pulses via a respective one of a plurality of addressing lines to a respective compound Josephson junction of each of a plurality of flux storage devices of the superconducting integrated circuit to cause each of the plurality of flux storage devices to reset. Power levels may be based at least in part on an estimated worst-case asymmetry between Josephson junctions of the compound Josephson junctions. The system may be operated to partition the plurality of addressing lines into groups, and apply a respective sequence of pulses to each addressing line of each pairwise combination of groups to cause one or more of the plurality of flux storage devices to reset.
H03K 19/195 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs supraconducteurs
H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson
In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and a magnetic field generator operable to apply a magnetic field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a first capacitor plate having a plane, a second capacitor plate having a plane, and a dielectric interposed between the first capacitor plate and the second capacitor plate. The plane of the second capacitor plate is geometrically parallel to the plane of the first capacitor plate. In some implementations, a superconducting integrated circuit has a tunable parallel-plate capacitor, and an electric field generator operable to apply an electric field to the tunable parallel-plate capacitor to tune a capacitance of the tunable parallel-plate capacitor. The tunable parallel-plate capacitor includes a pair of capacitor plates, and a dielectric interposed between the pair of plates.
H03K 19/195 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs supraconducteurs
H01L 39/12 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par le matériau
H01G 5/16 - Condensateurs dont la capacité varie par des moyens mécaniques, p. ex. en tournant un axeProcédés pour leur fabrication à variation de la distance entre armatures
59.
Kinetic inductance for couplers and compact qubits
A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.
H10N 69/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comportant au moins un élément supraconducteur couvert par le groupe
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
The systems, devices, articles, and methods generally relate to sampling from an available probability distribution. The samples may be used to create a desirable probability distribution, for instance for use in computing values used in computational techniques including: Importance Sampling and Markov chain Monte Carlo systems. An analog processor may operate as a sample generator, for example by: programming the analog processor with a configuration of the number of programmable parameters for the analog processor, which corresponds to a probability distribution over qubits of the analog processor, evolving the analog processor, and reading out states for the qubits. The states for the qubits in the plurality of qubits correspond to a sample from the probability distribution. Operation of the sampling device may be summarized as including updating a set of samples to include the sample from the probability distribution, and returning the set of samples.
A computational system can include digital circuitry and analog circuitry, for instance a digital processor and a quantum processor. The quantum processor can operate as a sample generator providing samples. Samples can be employed by the digital processing in implementing various machine learning techniques. For example, the computational system can perform unsupervised learning over an input space, for example via a discrete variational auto-encoder, and attempting to maximize the log-likelihood of an observed dataset. Maximizing the log-likelihood of the observed dataset can include generating a hierarchical approximating posterior.
A device is dynamically isolated via a broadband switch that includes a plurality of cascade elements in series, wherein each cascade element comprises a first set of SQUIDs in series, a matching capacitor, and a second set of SQUIDs in series. The broadband switch is set to a passing state via flux bias lines during programming and readout of the device and set to a suppression state during device's calculation to reduce operation errors at the device. A device is electrically isolated from high-frequencies via an unbiased broadband switch. A device is coupled to a tunable thermal bath that includes a broadband switch.
A superconducting integrated circuit has a first superconducting device with a first superconducting loop, where the first superconducting loop has a first superconducting trace in a first layer of the superconducting integrated circuit, and a second superconducting device with a second superconducting loop, where the second superconducting loop has a second superconducting trace in a second layer. The first superconducting loop crosses the second superconducting loop in a crossing region. At least a portion of each of the first and the second superconducting trace inside the crossing region is narrower than at least a portion of each of the traces outside the crossing region, and follows a respective circuitous path which is inductively proximate to at least a portion of the other path.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
H01L 39/02 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
64.
METHODS FOR FABRICATING SUPERCONDUCTING INTEGRATED CIRCUITS
Methods of forming superconducting integrated circuits are discussed. The method includes depositing a first superconducting metal layer to overlie at least a portion of a substrate, depositing a dielectric layer to cover a first region of the first superconducting metal layer, pattering the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and form an opening, and depositing a second superconducting metal layer at an ambient temperature that is less than a melting temperature of the second superconducting metal layer such that the second superconducting metal layer fills the opening and conductively contacts the at least a portion of the first region of the first superconducting metal layer.
H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par ou de leurs parties constitutives
H01L 39/06 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par le parcours du courant
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
H01L 27/18 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants présentant un effet de supraconductivité
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
A superconducting integrated circuit is fabricated by depositing a ground plane to at least partially overlie a substrate, depositing an insulating layer to at least partially overlie the ground plane, depositing a superconducting layer to at least partially overlie the insulating layer, and forming a superconducting feature in the superconducting layer. An inductance of the superconducting feature is tunable by adjusting a bias current in the ground plane. The ground plane is electrically communicatively coupleable to an electrical ground. Depositing a ground plane includes depositing a first superconducting material to at least partially overlie the substrate and depositing a second superconducting material to at least partially overlie the first superconducting material. A second critical current density of the second superconducting material is higher than a first critical current density of the first superconducting material.
H01F 6/06 - Bobines, p. ex. dispositions pour l'enroulement, l'isolation, les enveloppes ou les bornes des bobines
H01F 21/00 - Inductances ou transformateurs variables du type pour signaux
H01F 41/04 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants pour la fabrication de bobines
66.
DISCRETE VARIATIONAL AUTO-ENCODER SYSTEMS AND METHODS FOR MACHINE LEARNING USING ADIABATIC QUANTUM COMPUTERS
A computational system can include digital circuitry and analog circuitry, for instance a digital processor and a quantum processor. The quantum processor can operate as a sample generator providing samples. Samples can be employed by the digital processing in implementing various machine learning techniques. For example, the computational system can perform unsupervised learning over an input space, for example via a discrete variational auto-encoder, and attempting to maximize the log-likelihood of an observed dataset. Maximizing the log-likelihood of the observed dataset can include generating a hierarchical approximating posterior. Unsupervised learning can include generating samples of a prior distribution using the quantum processor. Generating samples using the quantum processor can include forming chains of qubits and representing discrete variables by chains.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
Superconducting integrated circuits and methods of forming these circuits are discussed. One superconducting integrated circuit has a substrate and a control device formed by a layer of high kinetic inductance material overlying the substrate. The control device has a loop of material, electrical connections between the loop of material and a power line, a coupling element connected to the loop of material, a pair of Josephson junctions that interrupt the loop of material, and an energy storage element connected to the loop of material. An alternative superconducting integrated circuit has a kinetic inductance device formed in a high kinetic inductance layer. The device has a compound Josephson junction structure with two parallel current paths with respective Josephson junctions, a loop of material connected to the compound Josephson junction structure, and a coupling structure. The circuit also has an additional device that couples to the coupling structure.
H01L 39/02 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails
H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par ou de leurs parties constitutives
H01L 39/12 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par le matériau
68.
Systems and methods for operation of a frequency multiplexed resonator input and/or output for a superconducting device
A superconducting readout system employing a microwave transmission line, and a microwave superconducting resonator communicatively coupled to the microwave transmission line, and including a superconducting quantum interference device (SQUID), may be advantageously calibrated at least in part by measuring a resonant frequency of the microwave superconducting resonator in response to a flux bias applied to the SQUID, measuring a sensitivity of the resonant frequency in response to the flux bias, and selecting an operating frequency and a sensitivity of the microwave superconducting resonator based at least in part on a variation of the resonant frequency as a function of the flux bias. The flux bias may be applied to the SQUID by an interface inductively coupled to the SQUID. Calibration of the superconducting readout system may also include determining at least one of a propagation delay, a microwave transmission line delay, and a microwave transmission line phase offset.
A superconducting circuit includes four superconducting qubits communicatively coupled by a 4-qubit even-parity stabilizer. The 4-qubit even- parity stabilizer includes a superconducting stabilizer loop, and four inductances, each inductance inductively communicatively coupled to an inductance of a respective one of the four superconducting qubits. The 4-qubit even-parity stabilizer also includes a parity-enforcing superconducting qubit communicatively coupled to the superconducting loop. A quantum processor comprises four Josephson parametric amplifiers communicatively coupled by a 4-qubit even-parity stabilizer. The Josephson parametric amplifiers comprise pairs of superconducting microwave resonators communicatively coupled by a compound-compound Josephson junction. The 4-qubit even-parity stabilizer includes a superconducting loop, four inductances inductively communicatively coupled to an inductance of a respective one of the four Josephson parametric amplifier, and a parity-enforcing Josephson parametric amplifier communicatively coupled to the superconducting loop.
A system and method of implementing finite element modeling on a quantum processor is discussed. A representation of a computational problem including a boundary value problem and problem grid points is received by one or more processors. The problem grid points are mapped to a Hilbert space of the qubits of the quantum processor. The boundary value problem is transformed into a problem Hamiltonian. Instructions are transmitted to the quantum processor to cause the quantum processor to evolve from an initial state to a final state based on the problem Hamiltonian. The wavefunction amplitudes of the final state are measured, and the wavefunction amplitudes of the final state are mapped onto the problem grid points based on the Hilbert space of the qubits.
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
71.
Systems, methods and apparatus for sampling from a sampling server
A digital processor runs a machine learning algorithm in parallel with a sampling server. The sampling sever may continuously or intermittently draw samples for the machine learning algorithm during execution of the machine learning algorithm, for example on a given problem. The sampling server may run in parallel (e.g., concurrently, overlapping, simultaneously) with a quantum processor to draw samples from the quantum processor.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
G06N 7/08 - Agencements informatiques fondés sur des modèles mathématiques spécifiques utilisant des modèles de chaos ou des modèles de systèmes non linéaires
H04L 67/10 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau
G06N 7/00 - Agencements informatiques fondés sur des modèles mathématiques spécifiques
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
72.
User in interface, programmer and/or debugger for embedding and/or modifying problems on quantum processors
A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.
G06F 3/048 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI]
G06F 3/04847 - Techniques d’interaction pour la commande des valeurs des paramètres, p. ex. interaction avec des règles ou des cadrans
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06T 11/20 - Traçage à partir d'éléments de base, p. ex. de lignes ou de cercles
G06F 3/04817 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] fondées sur des propriétés spécifiques de l’objet d’interaction affiché ou sur un environnement basé sur les métaphores, p. ex. interaction avec des éléments du bureau telles les fenêtres ou les icônes, ou avec l’aide d’un curseur changeant de comportement ou d’aspect utilisant des icônes
G06F 16/901 - IndexationStructures de données à cet effetStructures de stockage
73.
Systems and methods for achieving orthogonal control of non-orthogonal qubit parameters
Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together.
A quantum annealing schedule for a computational problem can be adjusted by methods and systems involving one or more processors. The one or more processors proceed by receiving a representation of the computation problem, the representation including a plurality of problem values. These problem values are transformed based on a plurality of trained parameters of a machine learning model to generate at least a portion of an annealing schedule including at least one annealing parameter. Instructions are transmitted to the quantum processor to cause the quantum processor to evolve from an initial state to a final state based on the computational problem and the at least a portion of an annealing schedule, the final state producing a result for the computational problem.
H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p. ex. écrans Faraday
H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par ou de leurs parties constitutives
H01L 39/12 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par le matériau
H01L 39/06 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par le parcours du courant
76.
Systems and methods for addressing devices in a superconducting circuit
Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.
Methods for solving discrete quadratic models are described. The methods compute an energy of each state of each variable based on its interaction with other variables, exponential weights, and normalized probabilities proportional to the exponential weights. The energy of each variable is computed as a function of the magnitude of each variable and a current state of all other variables, exponential weights, the feasible region for each variable, and normalized probabilities, proportional to the exponential weights and respecting constraints. Methods executed via a hybrid computing system obtain two candidate values for each variable; constructs a Hamiltonian that uses a binary value to determine which candidate values each variable should take, then constructs a binary quadratic model based on the Hamiltonian. Samples from the binary quadratic model are obtained via a quantum processor. The methods can be applied to solve resource scheduling optimization problems and/or for side-chain optimization for proteins.
An analog computing system having a qubit which is provided with inductors positioned near to the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. Near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitance for the qubit. The inductors may be tuned to homogenize both capacitance and inductance.
A system and method for mitigating flux trapping in a superconducting integrated circuit. A first metal layer is formed having a first critical temperature and a first device, and a flux directing layer is formed having a second critical temperature. The flux directing layer is positioned in communication with an aperture location, and the aperture location is spaced from the first device to isolate the first device from flux trapped in the aperture. The superconducting integrated circuit is cooled from a first temperature that is above both the first and second critical temperatures to a second temperature that is less than both the first and second critical temperatures by a cryogenic refrigerator. A relative temperature difference between the first and second critical temperatures causes the flux directing layer to direct flux away from the first device and trap flux at the aperture location.
H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par ou de leurs parties constitutives
H01L 39/12 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par le matériau
H01L 39/08 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails caractérisés par la forme de l'élément
80.
Systems and methods for collaborative filtering with variational autoencoders
Collaborative filtering systems based on variational autoencoders (VAEs) are provided. VAEs may be trained on row-wise data without necessarily training a paired VAE on column-wise data (or vice-versa), and may optionally be trained via minibatches. The row-wise VAE models the output of the corresponding column-based VAE as a set of parameters and uses these parameters in decoding. In some implementations, a paired VAE is provided which receives column-wise data and models row-wise parameters; each of the paired VAEs may bind their learned column- or row-wise parameters to the output of the corresponding VAE. The paired VAEs may optionally be trained via minibatches. Unobserved data may be explicitly modelled. Methods for performing inference with such VAE-based collaborative filtering systems are also disclosed, as are example applications to search and anomaly detection.
Quantum processors having qubits with tunable capacitance are provided. The qubits include Josephson junctions shunted by capacitors and are tunably coupled to capacitance loops such that the resonant frequencies of the qubits and capacitance loops avoid entanglement with each other. Methods for tuning the capacitance of such qubits by varying the coupler's coupling strength are provided. These methods include methods for calibrating qubits' capacitance.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
82.
Systems and methods for addressing devices in a superconducting circuit
Addressing a superconducting flux storage device may include applying a bias current, a low-frequency flux bias, and a high-frequency flux bias in combination to cause a combined address signal level to exceed a defined address signal latching level for the superconducting flux storage device. A bias current that, in combination with a low-frequency flux bias and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ. A low-frequency flux bias that, in combination with a bias current and a high-frequency flux bias, causes a combined address signal level to exceed a defined address signal latching level for a superconducting flux storage device is at least reduced by an asymmetry in the Josephson junctions of the CJJ.
G11C 11/44 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments supraconducteurs, p. ex. des cryotrons
H03K 3/38 - Générateurs caractérisés par le type de circuit ou par les moyens utilisés pour produire des impulsions par l'utilisation, comme éléments actifs, de dispositifs supraconducteurs
H03K 17/92 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs supraconducteurs
G11C 8/00 - Dispositions pour sélectionner une adresse dans une mémoire numérique
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
Systems, methods and article provide the services of heterogeneous resources, for example the services analog processors, e.g., quantum processors, in a robust manner that can include high availability, failover, and load balancing of the heterogeneous resources. A virtual solver is selected based at least in part on a first set of requirements, a first set of analog processors is identified based at least in part on the first set of requirements, and a first handle returned to the first virtual solver. A load balancer may balance loads. Failure over may be implemented.
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
84.
Systems and methods to generate samples for machine learning using quantum computing
A hybrid computer comprising a quantum processor can be operated to perform a scalable comparison of high-entropy samplers. Performing a scalable comparison of high-entropy samplers can include comparing entropy and KL divergence of post-processed samplers. A hybrid computer comprising a quantum processor generates samples for machine learning. The quantum processor is trained by matching data statistics to statistics of the quantum processor. The quantum processor is tuned to match moments of the data.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06F 18/2415 - Techniques de classification relatives au modèle de classification, p. ex. approches paramétriques ou non paramétriques basées sur des modèles paramétriques ou probabilistes, p. ex. basées sur un rapport de vraisemblance ou un taux de faux positifs par rapport à un taux de faux négatifs
In many cases after degaussing the field distribution in a magnetic material there may be regions within the magnetic material that have ordered domains that contribute a remnant field. There is the need to reduce or eliminate non-uniform fields within a volume of interest left after degaussing a magnetic shield. Degaussing coils surrounding a metal shield can be used to favorably order magnetic domains within the material to counteract the remnant fields left behind following imperfect degaussing. The remnant field value can be measured and a small current may be applied through the degaussing coils. After removing the current, the field can be measured again and a higher current may be applied again through the coils. Repeated applications of currents and field measurement will progressively order domains in the direction of the applied field, resulting in a reduction of the net field and lower field gradient across the volume of interest.
H01F 7/06 - Électro-aimantsActionneurs comportant des électro-aimants
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
H03H 3/00 - Appareils ou procédés spécialement adaptés à la fabrication de réseaux d'impédance, de circuits résonnants, de résonateurs
H01F 41/04 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants pour la fabrication de bobines
H01F 13/00 - Appareils ou procédés pour l'aimantation ou pour la désaimantation
H03H 7/42 - Réseaux permettant de transformer des signaux équilibrés en signaux non équilibrés et réciproquement, p. ex. baluns
H01F 41/076 - Formation de prises ou de bornes lors de l’enroulement, p. ex. par enveloppement ou par brasage du fil sur les broches, ou en formant directement des bornes à partir du fil
H03H 1/00 - Détails de réalisation des réseaux d'impédances dont le mode de fonctionnement électrique n'est pas spécifié ou est applicable à plus d'un type de réseau
H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p. ex. une résistance, un condensateur, une inductance imprimés
H01L 39/14 - Dispositifs à supraconductivité permanente
H01L 39/02 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails
86.
SYSTEMS AND METHODS FOR SIMULATING A QUANTUM PROCESSOR
A digital processor simulates a quantum computing system by implementing a QPU model including a set of representation models and a device connectivity representation to simulate a quantum processor design or a physical quantum processor. The digital processor receives an analog waveform and generates a digital waveform representation comprising a set of waveform values that correspond to biases applied to programmable devices in a quantum processor. The digital processor selects a subset of waveform values based on channels in the device connectivity representation. The digital processor implements a representation model to compute a response based on the waveform values and a plurality of physical parameter values, the physical parameters characterizing a programmable device in a quantum processor. The device connectivity representation can be generated from a design implementation, validated against a set of rules, and adjusted to change the device connectivity representation until all of the rules are passed.
A superconducting circuit may include a transmission line having at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. The transmission line inductance may have a value selected to at least partially compensate for a variation in a characteristic impedance of the transmission line, the variation caused at least in part by the coupling capacitance. The coupling capacitance may be distributed along the length of the transmission line. A superconducting circuit may include a transmission line having at least one transmission line capacitance, a superconducting resonator, and a coupling inductance that communicatively couples the superconducting resonator to the transmission line. The transmission line capacitance may be selected to at least partially compensate for a variation in coupling strength between the superconducting resonator and the transmission line.
Systems, devices, articles, methods, and techniques for advancing quantum computing by removing unwanted interactions in one or more quantum processor. One approach includes creating an updated plurality of programmable parameters based at least in part on a received value for the characteristic magnetic susceptibility of the qubit in the at least one quantum processor, and returning the updated plurality of programmable parameters. Examples programmable parameters include local biases, and coupling values characterizing the problem Hamilton. Also, for example, a quantum processor may be summarized as including a first loop of superconducting material, a first compound Josephson junction interrupting the first loop of superconducting material, a first coupler inductively coupled to the first loop of superconducting material, a second coupler inductively coupled to the first loop of superconducting material, and a second loop of superconducting material proximally placed to the first loop of superconducting material inductively coupled to the first coupler and the second coupler.
A method of fabricating a multilayer superconducting printed circuit board comprises first, forming a bimetal foil to overlie a substrate, the bimetal foil comprising a first layer of a first metal, a layer of a second metal, and a second layer of the first metal, and then etching the second layer of the first metal. Forming a bimetal foil to overlie a substrate may include forming a bimetal foil comprising a first layer of a normal metal, a layer of a superconducting metal, and a second layer of the normal metal. Etching the second layer of the first metal may include preparing a patterned image in the second layer of the first metal for etching, processing the patterned image through a cleaner, rinsing the patterned image, and then, immersing the patterned image in a microetch.
H05K 3/06 - Élimination du matériau conducteur par voie chimique ou électrolytique, p. ex. par le procédé de photo-décapage
H01L 39/24 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement des dispositifs couverts par ou de leurs parties constitutives
90.
INPUT/OUTPUT SYSTEMS AND METHODS FOR SUPERCONDUCTING DEVICES
e.g.e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.
Calibration techniques for devices of analog processors to remove time-dependent biases are described. Devices in an analog processor exhibit a noise spectrum that spans a wide range of frequencies, characterized by 1/f spectrum. Offset parameters are determined assuming only a given power spectral density. The algorithm determines a model for a measurable quantity of a device in an analog processor associated with a noise process and an offset parameter, determines the form of the spectral density of the noise process, approximates the noise spectrum by a discrete distribution via the digital processor, constructs a probability distribution of the noise process based on the discrete distribution and evaluates the probability distribution to determine optimized parameter settings to enhance computational efficiency.
G06N 7/01 - Modèles graphiques probabilistes, p. ex. réseaux probabilistes
G01R 29/26 - Mesure du coefficient de bruitMesure de rapport signal-bruit
G01R 33/24 - Dispositions ou appareils pour la mesure des grandeurs magnétiques faisant intervenir la résonance magnétique pour la mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
B82Y 35/00 - Procédés ou appareils pour la mesure ou l’analyse des nanostructures
92.
Systems and methods for calibrating devices using directed acyclic graphs
A hybrid processor includes a classical (digital) processor and a quantum processor and implements a calibration procedure to calibrate devices in the quantum processor. Parameter measurements are defined as vertices in a directed acyclic graph. Dependencies between measurements are defined as directed edges between vertices. The calibration procedure orders the vertices, respecting the order of the dependencies while at least attempting to reduce the time needed to perform all the measurements. The calibration procedure provides a level of abstraction to allow non-expert users to use the calibration procedure. Each vertex has a set of attributes defining the status of the measurement, time of the measurement and value of the measurement.
A quantum processor performs input and output which may be performed synchronously. The quantum processor executes a problem to generate a classical output state, which is read out at least partially by an I/O system. The I/O system also transmits a classical input state to by the I/O system, which may include the same qubit-proximate devices used for read-out. The classical input state is written to the qubits, and the quantum processor executes based on the classical input state (e.g., by performing reverse annealing to transform the classical input state to quantum state).
Generate an automorphism of the problem graph, determine an embedding of the automorphism to the hardware graph and modify the embedding of the problem graph into the hardware graph to correspond to the embedding of the automorphism to the hardware graph. Determine an upper-bound on the required chain strength. Calibrate and record properties of the component of a quantum processor with a digital processor, query the digital processor for a range of properties. Generate a bit mask and change the sign of the bias of individual qubits according to the bit mask before submitting a problem to a quantum processor, apply the same bit mask to the bit result. Generate a second set of parameters of a quantum processor from a first set of parameters via a genetic algorithm.
G06N 3/126 - Algorithmes évolutionnaires, p. ex. algorithmes génétiques ou programmation génétique
95.
Systems and methods employing new evolution schedules in an analog computer with applications to determining isomorphic graphs and post-processing solutions
A second problem Hamiltonian may replace a first problem Hamiltonian during evolution of an analog processor (e.g., quantum processor) during a first iteration in solving a first problem. This may be repeated during a second, or further successive iterations on the first problem, following re-initialization of the analog processor. An analog processor may evolve under a first non-monotonic evolution schedule during a first iteration, and second non-monotonic evolution schedule under second, or additional non-monotonic evolution schedule under even further iterations. A first graph and second graph may each be processed to extract final states versus a plurality of evolution schedules, and a determination made as to whether the first graph is isomorphic with respect to the second graph. An analog processor may evolve by decreasing a temperature of, and a set of quantum fluctuations, within the analog processor until the analog processor reaches a state preferred by a problem Hamiltonian.
A technique for improving the performance of non-stoquastic quantum processors is provided. Clusters of qubits with correlated behavior are identified in a problem for processing by the quantum processor. Couplings between qubits in a common cluster are modified according to a transformation (for example, a gauge transformation) so that they evolve slower and thus their dynamics freeze out later (for example, by flipping anti-ferromagnetic couplings to ferromagnetic couplings). Couplings between qubits that do not belong to the common cluster may be flipped the other way (for example, from ferromagnetic couplings to anti¬ ferromagnetic couplings) to accelerate their dynamics. The quantum processor is evolved and the results are modified according to an inverse transformation.
A computational method via a hybrid processor comprising an analog processor and a digital processor includes determining a first classical spin configuration via the digital processor, determining preparatory biases toward the first classical spin configuration, programming an Ising problem and the preparatory biases in the analog processor via the digital processor, evolving the analog processor in a first direction, latching the state of the analog processor for a first dwell time, programming the analog processor to remove the preparatory biases via the digital processor, determining a tunneling energy via the digital processor, determining a second dwell time via the digital processor, evolving the analog processor in a second direction until the analog processor reaches the tunneling energy, and evolving the analog processor in the first direction until the analog processor reaches a second classical spin configuration.
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06N 7/08 - Agencements informatiques fondés sur des modèles mathématiques spécifiques utilisant des modèles de chaos ou des modèles de systèmes non linéaires
G06N 3/044 - Réseaux récurrents, p. ex. réseaux de Hopfield
G06N 3/047 - Réseaux probabilistes ou stochastiques
B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
98.
Systems and methods for coupling qubits in a quantum processor
eff of a qubit characterized by a double-well potential energy may advantageously be tuned. Sign-tunable electrostatic coupling of qubits may be implemented, e.g., via resonators, and LC-circuits. YY couplings may be incorporated into a quantum anneaier (e.g., quantum processor).
H01L 39/02 - Dispositifs utilisant la supraconductivité ou l'hyperconductivité; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives - Détails
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
H01L 39/22 - Dispositifs comportant une jonction de matériaux différents, p.ex. dispositifs à effet Josephson
99.
Systems and methods for hybrid analog and digital processing of a computational problem using mean fields
A hybrid computing system for solving a computational problem includes a digital processor, a quantum processor having qubits and coupling devices that together define a working graph of the quantum processor, and at least one nontransitory processor-readable medium communicatively coupleable to the digital processor which stores at least one of processor-executable instructions or data. The digital processor receives a computational problem, and programs the quantum processor with a first set of bias fields and a first set of coupling strengths. The quantum processor generates samples as potential solutions to an approximation of the problem. The digital processor updates the approximation by determining a second set of bias fields based at least in part on the first set of bias fields and a first set of mean fields that are based at least in part on the first set of samples and coupling strengths of one or more virtual coupling devices.
G06F 17/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des fonctions spécifiques
G06N 10/00 - Informatique quantique, c.-à-d. traitement de l’information fondé sur des phénomènes de mécanique quantique
G06N 10/60 - Algorithmes quantiques, p. ex. fondés sur l'optimisation quantique ou les transformées quantiques de Fourier ou de Hadamard
G06F 15/16 - Associations de plusieurs calculateurs numériques comportant chacun au moins une unité arithmétique, une unité programme et un registre, p. ex. pour le traitement simultané de plusieurs programmes
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
H03K 19/00 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion
100.
Systems and methods for simulation of dynamic systems
A highly parallelized parallel tempering technique for simulating dynamic systems, such as quantum processors, is provided. Replica exchange is facilitated by synchronizing grid-level memory. Particular implementations for simulating quantum processors by representing cells of qubits and couplers in grid-, block-, and thread-level memory are discussed. Parallel tempering of such dynamic systems can be assisted by modifying replicas based on isoenergetic cluster moves (ICMs). ICMs are generated via secondary replicas which are maintained alongside primary replicas and exchanged between blocks and/or generated dynamically by blocks without necessarily being exchanged. Certain refinements, such as exchanging energies and temperatures through grid-level memory, are also discussed.
