Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.
System emulation of a floating-point dot product operation can be performed without directly performing the arithmetic by decomposing the Addend into a constituent sign, an exponent, and a fractional part; performing inverse scaling of the Addend by subtracting a scaling exponent (LSCALE) of a scaling of a negative power of two from the exponent to calculate an inverse-scaled addend; comparing a corresponding fractional part of the inverse-scaled addend with notional exponents of the most significant bit (MSB) and the least significant bit (LSB) of a fixed point accumulator to determine which of three cases have been encountered; and adding particular values representing the Addend to the calculation result according to which of the three cases have been encountered. The three cases include the inverse-scaled addend being able to be exactly accumulated into the fixed-point accumulator and the scenarios where the inverse-scaled addend is either too large or too small to be exactly accumulated into the fixed-point accumulator.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
Various implementations described herein are directed to a device having a bank of bitcells split into a plurality of portions including a first row slice of the bitcells and a second row slice of the bitcells. Also, the device may have control circuitry configured to access and repair a first bitcell in the first row slice with a first row address and a second bitcell in the second row slice with a second row address that is different than the first row address.
An apparatus comprises a plurality of interfaces, each couplable to a respective one of a plurality of processing circuitries either in a higher criticality compliance state or a lower criticality compliance state. Each interface can receive from its respective processing circuitry interrupt signals destined to a target processing circuitry of the plurality of processing circuitries and transmit to its respective processing circuitry interrupt signals issued by a source processing circuitry of the plurality of processing circuitries. Control circuitry monitors the flow of the interrupt signals and determines whether the flow of interrupt signals exhibits a discrepancy with respect to an expected flow of interrupt signals, and performs a mitigation action in respect of said discrepancy to avoid violation of the higher criticality compliance state.
Various implementations described herein are directed to a device having a power-gate structure with multiple transistors including a first transistor and a second transistor. The first transistor may be coupled between a first voltage node and a second voltage node, and the second transistor may be coupled between the second voltage node and a third voltage node that is coupled to the second voltage node.
A data processing apparatus includes pointer storage configured to store pointer values for pointers. Increment circuitry, responsive to one or more increment events, increments each of the pointer values in dependence on a corresponding live pointer value update condition from corresponding live pointer value update conditions. The corresponding live pointer value update condition is different for each of the pointers. History storage circuitry stores resolved behaviours of instances of a control flow instruction, each of the resolved behaviours being associated with one of the pointers. At least one of the live pointer value update conditions is changeable at runtime. Consequently, storage can be reduced as compared to a situation where all pointer value update conditions are active.
Various implementations described herein are directed to a device with magnetic plates embedded within a substrate having a first magnetic flux. The device may include one or more conductive cylinders that provide an electric path that passes through the magnetic plates. Also, the magnetic plates may enable a second magnetic flux within the magnetic plates such that the second magnetic flux is greater than the first magnetic flux.
An apparatus is provided for improving the use of multiple-issue operations in a data processor. A variable-issue operation can be recognised is being either a single-issue operation or a multiple-issue operation in dependence on the state of the program at runtime. If a variable-issue operation can be scheduled as a multiple-issue operation, then other operations can be scheduled for performance in the same cycle, when they would have otherwise had to be scheduled for a later cycle. As such, more operations can be performed in fewer cycles thus improving code density and improving data processing performance.
Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to adapt a neural network structure to a target platform. One or more performance metrics of an execution of the neural network structure may be implemented by one or more target hardware elements. A module from a library of modules may be selected to replace one or more elements of the neural network structure based, at least in part, on the observed one or more performance metrics.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/082 - Méthodes d'apprentissage modifiant l’architecture, p. ex. par ajout, suppression ou mise sous silence de nœuds ou de connexions
Disclosed are devices and/or processes to process image frames expressed in part by different lighting components, such as lighting components generated using ray tracing. In an embodiment, different lighting components of a previous image frame may be separately warped and combined with like lighting components in a current image frame.
A data processing apparatus is provided. It includes history storage circuitry that stores historic data of instructions and prediction circuitry that predicts a historic datum of a specific instruction based on subsets of the historic data of the instructions. The history storage circuitry overwrites the historic data of one of the instructions to form a corrupted instruction datum and at least one of the subsets of the historic data of the instructions includes the corrupted historic datum.
Barcelona Supercomputing Center - Centro Nacional de Supercomputación (Espagne)
Inventeur(s)
Siracusa, Marco
Randall, Joshua
Joseph, Douglas James
Moretó Planas, Miquel
Armejach Sanosa, Adrià
Abrégé
A data structure marshalling unit for a processor comprises data structure traversal circuitry to perform data structure traversal processing according to a dataflow architecture. The data structure traversal circuitry comprises two or more layers of traversal circuit units, each layer comprising two or more parallel lanes of traversal circuit units. Each traversal circuit unit triggers loading, according to a programmable iteration range, of at least one stream of elements of at least one data structure from data storage circuitry. For at least one programmable setting for the data structure traversal circuitry, the programmable iteration range for a given traversal circuit unit in a downstream layer is dependent on one or more elements of the at least one stream of elements loaded by at least one traversal circuit unit in an upstream layer. Output interface circuitry outputs to the data storage circuitry at least one vector of elements loaded by respective traversal circuit units in a given active layer of the data structure traversal circuitry.
Various implementations described herein are directed to a device having first transistors arranged as cross-coupled inverters coupled between a disconnect node and ground. The device may have second transistors arranged as passgates coupled between the cross-coupled inverters and bitlines. The device may have third transistors coupled between a voltage supply and the disconnect node.
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
Various implementations described herein are directed to a device having first transistors arranged as cross-coupled inverters coupled between a disconnect node and ground. The device may have second transistors arranged as passgates coupled between the cross-coupled inverters and bitlines. The device may have third transistors coupled between a voltage supply and the disconnect node.
A data processing apparatus is provided. It includes first history storage circuitry that stores control flow information of control flow instructions. Second history storage circuitry stores a subset of the control flow information by considering a subset of the control flow instructions. Prediction circuitry produces a prediction for a specific one of the control flow instructions based on the subset of the control flow information and power control circuitry performs a determination of an extent to which the subset of the control flow information matches the control flow information and disables the prediction circuitry in dependence on a result of the determination.
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
Multiple successively spatially downsampled versions of a rendered image frame are generated for at least one two-dimensional signal component of one or more two-dimensional signal components of an image frame, and one or more versions of the rendered image frame are selected from among the rendered image frame and the spatially downsampled versions of the rendered image frame for sampling a texture feature based, at least in part, on a prediction computed by a neural network.
Disclosed are process and devices for processing an image frame. An image frame rendered on rendering instances may comprise pixel values for one or more lighting components. One or more first buffers may store accumulations of pixel values for the one or more lighting components over at least some past rendering instances. One or more second buffers may store pixel values for the one or more lighting components of a processed image frame. Pixel values in the one or more first buffers may be combined with pixel values in the one or more second buffers to provide pixel values for the one or more lighting components in an accumulated image frame.
According to one implementation of the present disclosure, a power grid comprising: one or more cells; a metal layer; first and second buried power rails; and one or more local interconnects, wherein one or more local interconnect stitches are configured to electrically couple the one or more cells to either of the first or second buried power rails through the metal layer and the one or more local interconnects.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
19.
CORE ALLOCATION FOR TEMPERATURE CONTROL IN UNDER-SUBSCRIBED COMPUTING SYSTEMS
A method of core allocation for temperature control in under-subscribed computing systems can include maintaining, by an allocator component, a virtual to physical core mapping of physical cores of a computing system; identifying a change to a next core allocation according to an allocation pattern; determining a time that a process of a software application can be moved to the next core allocation, wherein the process of the software application is configured with core pinning; and updating, by the allocator component, the virtual to physical core mapping for the process of the software application at the determined time. The allocator component can intercept a process request of the software application; identify a pinned core of the process request; and overwrite the pinned core of the process request with an allocated core indicated by the virtual to physical core mapping.
Methods and systems for reducing the appearance of block-related artifacts are described. The methods include obtaining image frames in a sequence of image frames and adjusting some or all image frames in the sequence of image frames to generate adjusted image frames. The adjusted image frames may be created by generating image data and adding it to one or more edges of the image frame or by discarding image data from the image frame. The adjusted image frames shift a block origin relative to image data in the image frame. The adjusting is performed so that the shift of the block origin varies during the sequence of image frames. A block-based process is applied to each adjusted image frame to generate processed image frames, wherein blocks of image data are selected and processed in each adjusted frame of image data according to the block origin.
When performing tile-based graphics processing, a first vertex shading operation to generate vertex shaded position data for vertices is performed, and the vertex shaded position data used to prepare primitive lists indicating which primitives should be rendered for respective rendering tiles. Then, when processing a tile, a second vertex shading operation is performed for vertices of primitives for the tile for which fragments have been generated by a rasteriser prior to rendering the graphics fragments, to generate vertex shaded non-position attribute data for the vertices, based on the results of early depth testing before the fragments are rendered.
An apparatus has pointer storage to store pointer values for a plurality of pointers and increment circuitry, responsive to a series of increment events, to differentially increment the pointer values of the pointers. Training circuitry comprises tracker circuitry to maintain a plurality of tracker entries and cache circuitry to maintain a plurality of cache entries. Each tracker entry identifies a control flow instruction, and each cache entry stores a resolved behaviour of an instance of a control flow instruction identified by a tracker entry. For a given control flow instruction identified in a given tracker entry, the training circuitry performs a training process to seek to determine, as an associated pointer for the given control flow instruction, a pointer from amongst the plurality of pointers whose pointer value increments in a manner that meets a correlation threshold with occurrence of instances of the given control flow instruction. Promotion circuitry, responsive to detection of the correlation threshold being met for the given control flow instruction, allocates a prediction entry within prediction circuitry to identify the given control flow instruction and the associated pointer, and a behaviour record is established within the prediction entry identifying the resolved behaviour for one or more instances of the given control flow instruction. The behaviour record is arranged such that each resolved behaviour is associated with the pointer value of the associated pointer at the time that resolved behaviour was observed. Responsive to a prediction trigger associated with a replay of a given instance of the given control flow instruction, the prediction circuitry determines, in dependence on a current pointer value of the associated pointer, a predicted behaviour of the given instance of the given control flow instruction from the behaviour record within the prediction entry.
Prediction circuitry generates a prediction associated with a prediction input address, for controlling a speculative action by a processor. The prediction circuitry comprises combiner circuitry to determine a combined prediction by applying a prediction combination function to a given address and sets of prediction information generated by a plurality of predictors corresponding to the given address. A combiner cache structure comprises combiner cache entries. A given combiner cache entry associated with an address indication indicates items of combined prediction information determined by the combiner circuitry for an address corresponding to the address indication and different combinations of possible values for the respective sets of prediction information. Combiner cache lookup circuitry looks up the combiner cache structure based on the prediction input address to identify a selected combiner cache entry, and generates the prediction based on a selected item of combined prediction information selected from the selected combiner cache entry based on the respective sets of prediction information generated by the predictors corresponding to the prediction input address.
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec pré-lecture
Combiner circuitry generates a combined prediction associated with a given address based on combining respective sets of prediction information generated by two or more predictors. Predictor control circuitry determines, based on a lookup of a prediction input address in a combiner hint data structure, whether a second predictor lookup suppression condition is satisfied for the prediction input address indicating that the combined prediction that would be determined by the combiner circuitry for the prediction input address is likely to be derivable from a prediction outcome predicted by the first predictor for the prediction input address. If this condition is satisfied, a lookup of the second predictor is suppressed and the prediction associated with the prediction input address is generated based on the prediction outcome predicted by the first predictor for the prediction input address.
Data processing systems comprising a data processor, the data processor comprising an execution unit and storage for storing input data values for use by and/or output data values generated by the execution unit when executing instructions to perform data processing operations, and methods of control thereof, in which control of storage of data values for data source(s) of the storage is based on indication(s), in instruction(s) requiring use of data source(s) for a data processing operation, that one or more data values in the data source(s) are no longer required to be retained.
Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
27.
MEMORY SYNCHRONISATION SUBSEQUENT TO A MAINTENANCE OPERATION
There is provided an apparatus, system, method, and medium. The apparatus comprises one or more processing elements, each processing element comprising processing circuitry to perform processing operations in one of a plurality of processing contexts. Each processing element further comprises context tracking circuitry to store context tracking data indicative of active contexts. Each processing element comprises control circuitry responsive to a request for a memory synchronisation occurring subsequent to at least one maintenance operation associated with a given set of one or more contexts of the plurality of processing contexts, to determine whether the at least one of the given set of one or more contexts is indicated in the context tracking data. The control circuitry is configured, when the at least one of the given set of one or more contexts is determined to be indicated in the context tracking data, to implement a delay before performing the memory synchronisation, and when each of the given set of one or more contexts is determined to be absent from the context tracking data, to perform the memory synchronisation without implementing the delay.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
28.
TECHNIQUE FOR PREDICTING BEHAVIOUR OF CONTROL FLOW INSTRUCTIONS
An apparatus stores pointer values for pointers which are incremented differentially and has prediction circuitry to maintain prediction entries each identifying a control flow instruction, an associated pointer, and a behaviour record indicating resolved behaviour of the control flow instruction. Resolved behaviour stored in a selected element of the behaviour record identified using a pointer value of the associated pointer may be used as predicted behaviour for a control flow instruction. The prediction entries include a first type of prediction entry and a further type of prediction entry, where prediction circuitry uses each prediction entry of the first type to identify a control flow instruction whose associated pointer is within a first subset of the pointers, and uses each prediction entry of a further type to identify a control flow instruction whose associated pointer is within a further subset of the pointers excluding at least one pointer of the first subset.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
29.
OPERATING SYSTEM PAGESIZE COMPATIBILITY WORKAROUNDS
A method is presented that includes detecting, by a loader, overlapping permissions for a page while loading a binary file. When writable data overlaps with read-only code in a page, the loader copies the code part of the page with the overlapping permissions to a new page. The original page is set non-executable. The new page can be set executable but read-only. When execution reaches the now non-executable original page, a segmentation fault may be raised. A signal handler installed by the loader detects that the fault is coming from the original page and redirects execution to the new page with the copied code part.
A data processing apparatus includes interception circuitry for intercepting an incoming signal corresponding to an instruction from a processor element to a PCI device. Respond circuitry provides a response to the incoming signal back to the processor element and the response is either an acceptance of the incoming signal or a refusal of the incoming signal based on a flow control between the data processing apparatus and the PCI device. Forward circuitry performs a transmission, to the PCI device, of an outgoing signal corresponding to the command after the response has indicated acceptance of the incoming signal.
A message channel functionality for a data processing system is disclosed. This provides communication channels which may be considered to be a shared resource. The approach combines atomic stores, which are fully completed in a single atomic transaction, and non-coherence to provide non-coherent atomic stores that are conditional to implement primitive communications channels that can be used to implement software queues and channels more efficiently. This enables the programmer to execute a store from registers on one side of a communications link and to have that data appear in the registers of a data consumer on that link directly, bypassing both the shared state upgrade problem and the parallel problem of acquiring a synchronization lock before data send.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
A message channel functionality for a data processing system is disclosed. This provides communication channels which may be considered to be a shared resource. The approach combines atomic stores, which are fully completed in a single atomic transaction, and non-coherence to provide non-coherent atomic stores that are conditional to implement primitive communications channels that can be used to implement software queues and channels more efficiently. This enables the programmer to execute a store from registers on one side of a communications link and to have that data appear in the registers of a data consumer on that link directly, bypassing both the shared state upgrade problem and the parallel problem of acquiring a synchronization lock before data send.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 15/167 - Communication entre processeurs utilisant une mémoire commune, p. ex. boîte aux lettres électronique
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
An apparatus comprises at least one register rename table structure comprising rename entries for indicating register mappings between architectural registers and corresponding physical registers, and register rename circuitry to update the register mappings indicated by the rename entries. Rename entries corresponding to at least one set of architectural registers support a cleared-register encoding. In response to an operation specifying a source architectural register for which a corresponding rename entry is set to the cleared-register encoding, the register rename circuitry controls the processing circuitry to process that operation with a source operand corresponding to the source architectural register being treated as having a predetermined value. In response to detection of a register clearing event indicating that at least one set of architectural registers is to be treated as having been cleared to the predetermined value, the register rename circuitry sets rename entries corresponding to the at least one set of architectural registers to the cleared-register encoding.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
45 - Services juridiques; services de sécurité; services personnels pour individus
Produits et services
Electronic data processing equipment; computer hardware; integrated circuits; semiconductors; system-on-chip devices; microprocessors; processors [central processing units]; application specific integrated circuits; graphics processing units; semiconductor intellectual property cores; instruction set architectures; microcontrollers; electronic chips; data processors; interfaces for computers; printed circuit boards; apparatus for wireless communications; electronic data storage devices; electronic devices that send and receive data in a connected network; sim cards; computer software; software, namely communication software as a Multimedia Services Identity Module (ISIM); downloadable open-source software; artificial intelligence, deep learning, neural processing and machine learning computer software; downloadable open-source software development tools; software featuring open source libraries for artificial intelligence; computer software used in and for use in the design, development, modelling, simulation, compiling, de-bugging, verification, construction and interfacing of integrated circuits, microprocessors, microprocessor cores, semiconductor intellectual property cores, macro cells, microcontrollers, bus interfaces and printed circuit boards; computer software used in, and for use in the design, development, modelling, simulation, compiling, de-bugging, verification, construction and interfacing of application software and operating system software to run on integrated circuit based devices; software featuring open source libraries for machine learning training and inference; microprocessor design file software; computer software used in servers; operating system software; web services software; security and cryptographic software; neural processing units and machine learning processors; computer software and computer software libraries for use in relation to machine learning computer hardware platforms, deep learning computer hardware platforms and artificial intelligence computer hardware platforms; downloadable computer software for connecting, updating, operating, controlling, monitoring the connectivity and security of, interfacing with, analyzing the operation of, and managing networked and/or cloud-connected electronic data processing in the internet of things (IoT); downloadable computer software for collecting, analyzing, editing, modifying, organizing, synchronizing, integrating, visualizing, monitoring, transmitting, transferring, storing and sharing data and information; downloadable embeddable subscriber identity module computer software for connecting, updating, operating, controlling, monitoring the connectivity and security of, interfacing with, analyzing the operation of, and managing networked and/or cloud-connected electronic data processing apparatus in the internet of things (IoT); electronic publications, downloadable, in the nature of instruction manuals, user manuals, technical manuals, development manuals, datasheets, brochures, articles and white papers in the field of computer hardware, computer software, neural network processors, neural processing units, machine learning processors, computer hardware accelerators, machine learning computer hardware and software platforms, deep learning computer hardware and software platforms and artificial intelligence computer hardware and software platforms, software-as-a-service (SaaS), platform-as-a-service (PaaS) and infrastructure-as-a-service (IaaS) for managing data, electronic devices and the connectivity of electronic devices in a data network. Design and development of open-source software; design and development of software featuring open source libraries for machine learning training and inference; software-as-a service (SaaS) services namely software for use in relation to electronic data processing apparatus for machine learning, neural processing, artificial intelligence and deep learning; research, development and design all relating to microprocessors, processors, microcontrollers, microprocessor design files, semiconductor intellectual property cores, computer hardware accelerators, neural network processors, neural processing units, machine learning processors and artificial intelligence, deep learning, neural processing, machine learning computer software and security; research, development and design, all relating to computer software used in, and for use in the design, verification and construction of microprocessors, processors, microcontrollers, microprocessor design files, semiconductor intellectual property cores, computer hardware accelerators, neural network processors and machine learning processors; technical consultancy and technical support services in the nature of diagnosing problems with the verification and construction of microprocessors, processors, microcontrollers, microprocessor design files, semiconductor intellectual property cores, computer hardware accelerators, neural network processors and machine learning processors; technical consultancy and technical support services in the nature of diagnosing problems with microprocessors, processors, microcontrollers, application specific integrated circuits, microprocessor design files, semiconductor intellectual property cores, computer hardware accelerators, neural network processors and machine learning processors; design and development of software for secure network operations. Licensing of technology; licensing of trademarks; licensing of patents; licensing of intellectual property; licensing of industrial property rights.
35.
System, devices and/or processes for executing service functions
Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to process requests to execute instance of service functions in a service function chain. In one particular implementation, a request to execute an instance of a second service function in a service function change may be initiated prior to completion of an execution of an instance of a first service function in the service function chain.
H04L 67/60 - Ordonnancement ou organisation du service des demandes d'application, p. ex. demandes de transmission de données d'application en utilisant l'analyse et l'optimisation des ressources réseau requises
H04L 45/302 - Détermination de la route basée sur la qualité de service [QoS] demandée
An apparatus comprising: a storage configured to store data items; and address digest generating circuitry responsive to a request to store a received data item to a location of the storage associated with a store target address, to generate an address digest based on a plurality of bits of the store target address, the address digest having fewer bits than the plurality of bits. The storage is configured to store the address digest in association with the received data item.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
An apparatus comprises a storage configured to store data items associated with error correction codes (ECCs); data retrieval circuitry responsive to a data retrieval request specifying a retrieval address to retrieve a retrieved data item and an associated ECC from a storage location corresponding to the retrieval address; and ECC decoding circuitry to generate a syndrome value by performing an ECC decoding operation on a decoding input value comprising data bits of the retrieved data item, code bits of the associated ECC, and address bits of the retrieval address, and to determine based on the syndrome value whether an error condition has occurred. Each bit of the syndrome value depends on a different combination of bits of the decoding input value. For each data bit of the decoding input value, an odd number of bits of the syndrome value depend on that data bit. For each address bit of the decoding input value, an even number of bits of the syndrome value depend on that address bit.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
A semiconductor die device comprises a die-to-die communication module (104) for communicating with a separate semiconductor die device. The die-to-die communication module includes a sideband interface (302) comprising at least one sideband data pin (306) for communicating under control of a first clock signal, and a main band interface (300) comprising two or more main band data pins (304) for communicating with the external interface. The die-to-die communication module comprises selection circuitry (308) configured to select whether communication over the main band data pins is controlled based on the first clock signal or a second clock signal received from a second clock source, the second clock signal having a higher clock frequency than the first clock signal.
An apparatus has processing circuitry to perform processing operations specified by program instructions and loop control circuitry to identify a program loop specified by the program instructions. On identification of a program loop, the loop control circuitry stores loop control data that indicates a program loop body, excluding any program flow control instructions that specify the program loop. The loop control circuitry controls the processing circuitry to carry out loop iterations of the program loop body indicated by the loop control data. The processing circuitry is responsive to a hint instruction occurring at the beginning of a given program loop body to cause loop control data for the given program loop to exclude the hint instruction from a modified program loop body and to perform a performance modifying operating procedure specified by the hint instruction when carrying out loop iterations of the modified program loop body.
Various implementations described herein are directed to a device having an input-output stage with first transistors coupled between a voltage supply and ground. Also, the device may have a power clamping stage with resistor-capacitor circuitry coupled in parallel with second transistors between the voltage supply and ground. Also, during a power surging event, electro-static discharge is distributed across the first transistors and the second transistors by way of passing from the voltage supply to ground.
Methods and apparatus for performing a flooring divide operation comprised of a plurality of multiply with right shift instructions. Wherein the multiply with right shift instructions comprises decoding the multiply with right shift instruction and obtaining a portion of signed input data. In response to the decoded instruction and receipt of signed input data portions, controlling processing circuitry to process the portion of the signed input data, selecting a multiplier based on a sign of the signed input data, such that when the sign is negative a first derived constant is selected, and when the sign is positive, a second derived constant is selected. Multiplied input data is then generated by multiplying the portion of the signed input data by the multiplier, and then shifting by the constant size. The shifted multiplied input data is then stored in a storage.
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
A data processing system that comprises an encoder, and a communication system is disclosed. Compressed data produced by the encoder is decompressed to produce first decompressed data, and a first signature representative of the first decompressed data is generated. Compressed data that has been transferred by the communication system is decompressed to produce second decompressed data, and a second signature representative of the second decompressed data is generated. The first signature and the second signature are compared, and the comparison is used to determine whether an error has occurred.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une image, une trame ou un champ
When performing rendering in a tile-based graphics processor that comprises plural rendering processors, different regions of the render output are allocated to different ones of the rendering processors for processing. The processing of the render output is tracked to determine when a portion of the render output that is still to be allocated to the rendering processors for processing falls below a threshold, and when it is determined that a portion of the render output that is still to be allocated to the rendering processors for processing falls below the threshold, smaller regions of the render output are thereafter allocated to the rendering processors for processing.
Processing circuitry 10 performs processing in one of at least three domains 82, 84, 86, 88. Address translation circuitry 16 translates a virtual address of a memory access performed from a current domain to a physical address in one of a plurality of physical address spaces 61 selected based at least on the current domain. The domains include a root domain 82 for managing switching between other domains. The physical address spaces 61 include a root physical address space associated with the root domain 82, separate from physical address spaces associated with other domains.
A machine learning and inferencing system to generate a personalised activity plan comprises a trained world context knowledge base; a trained personal digital memory store; a goal engine to establish an activity goal; an activity decomposition engine to decompose an activity into a logically-consistent sub- activities connected by; a ponderation engine to assign value weights to potential sub-activities; a graph generation engine to generate a multi-layer weighted graph to train a model of personalised outcomes of the sub-activities according to the value weights; a scenario generation engine to analyze the network of logically-consistent potential sub-activities connected by paths to determine a selected scenario path to the activity goal according to at least the model of personalised user outcomes; a feedback engine to apply learning from the scenario generation engine to the world context knowledge base and/or the personal digital memory store; and an output channel to output a personalised activity plan comprising recommended actions to implement the selected scenario path.
G06Q 10/0631 - Planification, affectation, distribution ou ordonnancement de ressources d’entreprises ou d’organisations
G06Q 10/0637 - Gestion ou analyse stratégiques, p. ex. définition d’un objectif ou d’une cible pour une organisationPlanification des actions en fonction des objectifsAnalyse ou évaluation de l’efficacité des objectifs
A machine learning and inferencing system to generate a personalised activity plan comprises a trained world context knowledge base; a trained personal digital memory store; a goal engine to establish an activity goal; an activity decomposition engine to decompose an activity into a logically-consistent sub-activities connected by; a ponderation engine to assign value weights to potential sub-activities; a graph generation engine to generate a multi-layer weighted graph to train a model of personalised outcomes of the sub-activities according to the value weights; a scenario generation engine to analyze the network of logically-consistent potential sub-activities connected by paths to determine a selected scenario path to the activity goal according to at least the model of personalised user outcomes; a feedback engine to apply learning from the scenario generation engine to the world context knowledge base and/or the personal digital memory store; and an output channel to output a personalised activity plan comprising recommended actions to implement the selected scenario path.
Provided is a graphics processing unit comprising a texture unit, an execution unit, and a machine-learning neural network engine, all configured in a pipeline in electronic communication with an integrated cache memory; and a visual data processing engine comprising a configurable stencil processor integrated into the pipeline, in electronic communication with the integrated cache memory, and configured to execute repetitive image-to-image processing instructions on visual data fetched from the integrated cache memory; wherein a graphics processing unit scheduler is configured to provide a job control function for the visual data processing engine; and wherein the visual data processing engine is configured responsively to the graphics processing unit scheduler to operate in parallel with at least one of the texture unit, the execution unit, or the machine-learning neural network engine using a separate dataflow.
Methods and apparatus for performing a clipping operation comprised of a plurality of partial clip instructions based on a portion of a clip value. Wherein the partial clip instructions comprise decoding (120) a partial clip instruction using instruction decoding circuitry, and obtaining (110) at least a portion of input data associated with a register having a register size. In response to the decoded instruction the portion of the input data is clipped (130) based on the portion of the clip value; and a flag is set (140) indicating whether further clipping is required. The flag is set when an upper value of the portion of input data is equal to or exceeds the portion of the clip value.
Provided is a data stream processor comprising: a configurable compute unit comprising plural processing units each configured to receive at least one portion of input data and process the at least one portion of a repetitive arithmetical/logical operation on the data; an input memory unit in electronic communication with the configurable compute unit and configured to supply at least one portion of the input data to at least one of the plural processing units in the configurable compute unit; and at least one accumulator unit in electronic communication with the configurable compute unit and configured to receive at least two portions of processed data from the configurable compute unit and to output accumulated data; wherein each of the plural processing units is further configured to forward its processed data to a next processing unit and/or to an accumulator unit.
Provided is a data stream processor comprising a streamed data transceiver interface, a structure of processing units configurable to transform data received from a data source over the streamed data transceiver interface according to a specified output requirement, and a configuration unit operable in electronic communication with a data consumer to receive an output requirement and to configure the operation and linkage of a processing unit in the structure of processing units to transform input data to output data according to the specified output requirement; wherein the structure of processing units is further operable to provide the output data for output over the streamed data transceiver interface.
A method is provided that includes receiving a computer program comprising regions of code, each region of code including at least one function, pruning a search space of the received computer program by applying a high-level model recognizing potential software vulnerabilities to the computer program to determine a region of the code of the regions of code that includes a potential software vulnerability, performing a localized static analysis on the region of the code that include the potential software vulnerability to determine a local condition that causes the potential software vulnerability to be expressed in the computer program, and generating a report that includes the region of the code that includes the potential software vulnerability including a location of the region of the code within the computer program and the local condition that causes the potential software vulnerability to be expressed in the computer program.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
A method of data processing in a data processing system comprising a computer vision system. The method comprises obtaining image data representative of a plurality of pixels of an image, the image data comprising a plurality of pixel intensity values respectively representing said pixels. The method comprises identifying one or more compromised pixel intensity values in the plurality of pixel intensity values. The method comprises generating sensor defect state data relating to the identified compromised pixel intensity values. The method comprises performing, using the computer vision system, a feature recognition process on the image data. The method comprises performing an action based on the sensor defect state data.
G06V 10/98 - Détection ou correction d’erreurs, p. ex. en effectuant une deuxième exploration du motif ou par intervention humaineÉvaluation de la qualité des motifs acquis
G06V 20/56 - Contexte ou environnement de l’image à l’extérieur d’un véhicule à partir de capteurs embarqués
53.
Predicting a load value for a subsequent load operation
Processing circuitry to execute load operations, each associated with an identifier. Prediction circuitry to receive a given load value associated with a given identifier, and to make, in dependence on the given load value, a prediction indicating a predicted load value for a subsequent load operation to be executed by the processing circuitry and an ID-delta value indicating a difference between the given identifier and an identifier of the subsequent load operation. The predicted load value being predicted in dependence on at least one occurrence of each of the given load value and the predicted load value during execution of a previously-executed sequence of load operations. The prediction circuitry is configured to determine the ID-delta value in dependence on a difference between identifiers associated with the at least one occurrence of each of the given load value and the predicted load value in the previously-executed sequence of load operations.
The present disclosure relates to a data processing resource for performing data processing tasks for a host processor, the data processing resource comprising: control circuitry to receive, from the host processor, a request for the data processor unit to perform a processing job; an iterator unit to process the request and generate a workload comprising one or more tasks for the requested processing job; one or more execution units to perform the one or more tasks, wherein the iterator unit is configured to allocate the one or more tasks to the one or more execution units based on control signals from the control circuitry, wherein the control circuitry is further configured to switch an operation mode of at least one execution unit from a normal operation mode to a reduced operation mode by controlling the iterator unit to reduce an amount of task allocated to the at least one execution unit.
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
G06F 1/3228 - Surveillance d’exécution de tâches, p. ex. par utilisation de temporisations d’attente, de commandes d’arrêt ou de commandes d’attente
G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
A system for storing geometry data for use by a graphics processor when rendering a frame that represents a view of a scene using a ray tracing process. The system comprises a processing circuit that is configured to prepare a ray tracing acceleration data structure for use when rendering a frame that represents a view of a scene using a ray tracing process. Graphics primitives for an end point of the ray tracing acceleration data structure is sorted into groups of contiguous graphics primitives, and fewer instances of vertex data is stored for a graphics primitive that is shared by at least two graphics primitives of the group of contiguous graphics primitives than the number of graphics primitives in the group of contiguous graphics primitives that share the vertex.
Multiplication circuitry comprises adder sub-arrays which each add partial products derived from first/second operands. Sub-array result values generated by the adder sub-arrays are added in a result assembly addition to generate at least one multiplication result value representing a result of signed multiplication of the first operand and the second operand. Sign extension emulation is performed for a sign-extension-emulated sub-array result value added in the result assembly addition, by applying a default zero extension to the sign-extension-emulated sub-array result value regardless of its sign and emulating an effect of sign extending the sign-extension-emulated sub-array result value using another of the assembled values. Another example of multiplication circuitry applies default zero extension to a third signed operand being added to a product of first/second signed operands, and emulates sign extension of the third signed operand by adjusting one of the partial products derived from the first/second signed operands.
There is provided a processing apparatus comprising decoder circuitry. The decoder circuitry is configured to generate control signals in response to an instruction. The processing apparatus further comprises processing circuitry which comprising a plurality of processing lanes. The processing circuitry is configured, in response to the control signals, to perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing for that processing lane is enabled. The processing apparatus further comprises control circuitry to monitor each processing lane of the plurality of processing lanes for each instruction of a plurality of instructions performed in the plurality of processing lanes and to modify the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane meeting one or more predetermined conditions.
A method of image processing. The method comprises obtaining a set of image data, the set being associated with one or more parameters representative of one or more image capture characteristics for the set and comprising pixel intensity values representing image pixels having respective pixel locations in an image. The method comprises, for a given pixel intensity value in the set: determining an estimated noise value based on at least: the one or more parameters associated with the set, and a representative intensity value derived from one or more pixel intensity values in the set. The method comprises associating the estimated noise value with the given pixel intensity value.
G06V 10/60 - Extraction de caractéristiques d’images ou de vidéos relative aux propriétés luminescentes, p. ex. utilisant un modèle de réflectance ou d’éclairage
59.
SYSTEM, DEVICES AND/OR PROCESSES FOR EXECUTING A NEURAL NETWORK ARCHITECTURE SEARCH
Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to estimate an execution latency of a candidate neural network in a neural network architecture search (NAS) process.
The present disclosure relates to a graphics processor comprising: storage; execution circuitry to execute programs to perform graphics processing operations using a ray tracing process to generate a render output representative of a view of a scene; and ray tracing circuitry to trace a ray by performing tests to determine whether the ray may intersect geometry in the scene, the ray tracing circuitry being configured to store one or more test record entries for a ray being traced in the storage, each test record entry being indicative of a test to be performed to trace the ray, wherein the ray tracing circuitry is further configured to store distance data respective of one or more test record entries, the distance data respective of a test record entry being data representative of a distance to a volume of the scene associated with the test record entry.
Memory management circuitry (28) supports two-stage address translation based on a stage-1 and stage-2 translation table structures. Stage-2 access permission information specified by a stage-2 translation table entry has an encoding specifying whether a corresponding memory region has a partially-read-only permission indicating that write requests to the memory region corresponding to the target intermediate address, issued when processing circuitry (4) is in a predetermined execution state, are permitted for a restricted subset of write request types (including metadata-updating write requests for updating access tracking metadata in translation table entries) but prohibited for other write request types. The memory management circuitry (28) rejects a memory access request when the stage-2 access permission information of a corresponding stage-2 translation table entry specifies the partially-read-only permission and the memory access request is a write request, other than the restricted subset of write request types, issued in the predetermined execution state.
Disclosed is a method of evaluating trigonometric functions in floating point arithmetic. In particular, a range reduction operation is performed to reduce the input argument x into a desired reduced ranges of values within which the trigonometric function is to be evaluated. The range reduction involves a step of computing the product of the input argument x and R, wherein R is an approximation to m/pi (with m=2, for example). The value for R is obtained as a sum of terms R0+R1+ . . . and the value of the first term R0 is configured to ensure that the expression xR0 modulo 4 can be evaluated without floating point rounding error. This can then provide an improved graphics processor operation.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 7/499 - Maniement de valeur ou d'exception, p. ex. arrondi ou dépassement
G06T 1/20 - Architectures de processeursConfiguration de processeurs p. ex. configuration en pipeline
Aspects of the present disclosure relate to an apparatus comprising prefetch pattern storage circuitry and pattern training circuitry. The pattern training circuitry detects patterns of data access for updating one or more corresponding pattern storage entries. The pattern training circuitry comprises a plurality of training entries, associated with a given accessed storage location. Each said training entry comprises a plurality of regions. For a given training entry, at least one region is configured to store information for which a subsequent access offset is positive, and at least one region is configured to store information for which said offset is negative. The pattern training circuitry is configured to transmit data indicative of said information to the prefetch pattern storage circuitry. The prefetch pattern storage circuitry is responsive to receiving said transmitted data to update at least one corresponding pattern storage element.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec pré-lecture
Apparatuses, methods, systems, and chip-containing products are disclosed, which relate to an arrangement comprising a level N cache level and a level M cache level, where M is greater than N. The level N cache level comprises a plurality of linefill slots and performs a slot allocation procedure in response to a lookup miss in dependence on a linefill slot occupancy criterion. The slot allocation procedure comprises allocation of an available slot of the plurality of slots to a pending linefill request generated in response to the lookup miss. The level N cache level effects a modification of the slot allocation procedure in dependence on the linefill slot occupancy criterion and is responsive to the linefill slot occupancy criterion being fulfilled to cause a linefill delegation action to be instructed to the level M cache level.
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec pré-lecture
G06F 12/0871 - Affectation ou gestion d’espace de mémoire cache
Various implementations described herein are directed to a device having a skew cell architecture with multiple diffusion regions including P-type diffusion regions disposed between N-type diffusion regions. The device may have power rails including a voltage supply rail disposed between ground rails. The device may have poly-gate rails disposed between the ground rails. The poly-gate rails may be cut to provide an open space between at least one N-type diffusion region and at least one P-type diffusion region.
Branch prediction circuitry comprising branch target prediction circuitry to, for an identified block of sequential instructions, generate a branch target prediction identifying a predicted branch target for a selected branch instruction in the block of sequential instructions; output circuitry to output the branch target prediction; and determination circuitry to determine whether at least one condition is met. The branch target prediction circuitry is responsive to the determination circuitry determining that the at least one condition is met to generate the branch target prediction to identify both the predicted branch target for the selected branch instruction and one or more further predicted branch targets for one or more further branch instructions in the block of sequential instructions.
A graphics processor operable to render frames that represent a view of a scene using a ray tracing process includes a ray tracing circuit operable to test rays against a ray tracing acceleration data structure for a ray tracing process. The ray tracing circuit comprises a ray testing circuit operable to perform ray intersection tests for nodes of a ray tracing acceleration data structure and storage local to the ray testing circuit for storing data representative of one or more nodes of a ray tracing acceleration data structure for use by the ray testing circuit. Rays for testing by the ray testing circuit are selected from a pool of one or more rays to be tested based on an indication of the ray tracing acceleration data structure node or nodes that have been stored in the local storage of the ray testing circuit.
Various implementations described herein are related to a device having a first coil-shaped spiral structure for an active shield and a second coil-shaped spiral structure that is wound in-between windings of the first coil-shaped spiral structure. The first coil-shaped spiral structure may provide for a coil-based electro-magnetic (EM) shield as a counter-measure circuit for protecting an underlying circuit.
H05K 9/00 - Blindage d'appareils ou de composants contre les champs électriques ou magnétiques
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
G06F 21/87 - Boîtiers fiables ou inviolables par encapsulation, p. ex. de circuits intégrés
H01F 17/00 - Inductances fixes du type pour signaux
H01F 27/36 - Blindages ou écrans électriques ou magnétiques
H01F 41/04 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants pour la fabrication de bobines
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/057 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur les connexions étant parallèles à la base
H01R 13/639 - Moyens additionnels pour maintenir ou verrouiller les pièces de couplage entre elles après l'engagement
An apparatus is described having decoding circuitry that is responsive to a sequence of instructions to generate control signals, data processing circuitry comprising data processing functional hardware, and a plurality of registers. The data processing circuitry is responsive to the control signals to operate the data processing functional hardware in an operating procedure to perform data processing operations defined by the sequence of instructions, using data stored in the plurality of registers, to produce data processing results. The decoding circuitry is responsive to a register identifying hint instruction preceding the sequence of instructions to generate hint metadata in dependence on at least one register identified by the register identifying hint instruction. The data processing circuitry is arranged, when the hint metadata is present, to be responsive to the control signals to operate the data processing functional hardware in a modified operating procedure to perform the data processing operations defined by the sequence of instructions to produce the data processing results, where the modified operating procedure differs from the operating procedure by implementing one or more performance measures in dependence on the hint metadata.
A system on chip (102) comprising a plurality of logically homogeneous processor cores (104), each processor core comprising processing circuitry (210) to execute tasks allocated to that processor core, and task scheduling circuitry (202) configured to allocate tasks to the plurality of processor cores. The task scheduling circuitry is configured, for a given task to be allocated, to determine, based on at least one physical circuit implementation property associated with a given processor core, whether the given task is allocated to the given processor core.
Various implementations described herein are related to a device having adaptive clocking architecture with multiple stages of latches and buffers coupled in a delay line configuration. In some instances, each latch receives a delayed clock signal as data input and provides a sample out signal as a latched output based on a clock signal. Also, in some instances, each latch provides a delayed edge of a next clock cycle so as to stretch the pulse width of the clock signal.
H03K 5/06 - Mise en forme d'impulsions par augmentation de duréeMise en forme d'impulsions par diminution de durée par l'utilisation de lignes à retard ou d'autres éléments à retard analogues
A method includes receiving precursor alerts from a precursor detector that detects events from a processing unit, wherein each precursor alert comprises information of an event from the processing unit, the information of an event from the processing unit, detecting a first event in the precursor alerts indicating undesirable behavior and including a first score that is above a first value, setting a first timer for a first period of time, accumulating a score update with the first score of the first event. Upon the score update reaching or exceeding a first threshold value within the first period of time, generating a refined alert.
A method includes receiving precursor alerts from a precursor detector that detects events from a processing unit, wherein each precursor alert comprises information of an event from the processing unit, the information of an event from the processing unit, detecting a first event in the precursor alerts indicating undesirable behavior and including a first score that is above a first value, setting a first timer for a first period of time, accumulating a score update with the first score of the first event. Upon the score update reaching or exceeding a first threshold value within the first period of time, generating a refined alert.
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
An apparatus and method are described for handling sealed capabilities. The apparatus has processing circuitry to perform processing operations during which access requests to memory are generated, wherein the processing circuitry is arranged to generate memory addresses for the access requests using capabilities that identify constraining information. Checking circuitry then determines whether a given access request whose memory address is generated using a given capability is permitted based on the constraining information identified by that given capability, and based on a level of trust associated with the given access request. Each capability has a capability level of trust associated therewith, and the level of trust associated with the given access request is dependent on both a current mode level of trust associated with a current mode of operation of the processing circuitry, and the capability level of trust of the given capability. At least one of the capabilities is settable as a sealed capability, and the apparatus further comprises sealed capability handling circuitry to prevent the processing circuitry performing at least one processing operation using a given sealed capability when the current mode level of trust is a lower level of trust than the capability level of trust of the given sealed capability.
An apparatus (10, 30, 50) comprising processing circuitry (51) to execute instructions, and threadlet execution circuitry (23, 49, 52) to execute tasks under control of the processing circuitry. The threadlet execution circuitry is configured to operate asynchronously with respect to the processing circuitry. The threadlet execution circuitry is responsive to a start command issued by the processing circuitry to begin execution of a threadlet comprising at least one delegated task. The processing circuitry is responsive to a threadlet-start instruction, the threadlet-start instruction indicating a request to issue the start command to the threadlet execution circuitry, to determine, in dependence on at least one parameter, whether to trigger execution, by the processing circuitry, of an alternative function instead of issuing the start command to the threadlet execution circuitry.
There is provided an apparatus, a method of operating an apparatus, a computer program, and a computer-readable medium. The apparatus comprises a pipeline for processing instructions. The pipeline comprises decoder circuitry responsive to receipt of the instructions to control the pipeline to perform processing operations. The apparatus further comprises extension processing circuitry responsive to identification, by the pipeline, of a delegated task to perform the delegated task asynchronously to the pipeline and configured to maintain extension state information indicative of an execution context of the extension processing circuitry independent of processing state information associated with the pipeline. The decoder circuitry is responsive an extension context save instruction comprising a storage location identifier, at a point of storing the extension state information, to store the extension state information to a location identified by the storage location identifier.
An apparatus for data processing comprises a data processing pipeline to perform data processing operations, and extension processing circuitry to perform a delegated task asynchronously to the data processing pipeline in response to the decoding circuitry decoding an extension start instruction. The apparatus also comprises hazard detection circuitry to detect data hazards associated with processing operations performed by the data processing pipeline. When the data processing pipeline is in an extension hazard checking state, the presence of a hazard condition can be determined in dependence on whether a given memory access, to be performed in response a given memory access instruction following the extension start instruction in program order, is for accessing an address which falls within a group of addresses anticipated to be accessed by the extension processing circuitry during performance of the delegated task.
Apparatuses, methods of data processing, computer program, and computer-5 readable media are disclosed. A data processing pipeline performs data processing operations in dependence on a received sequence of instructions. Extension processing circuitry associated with the data processing pipeline and performs a delegated task in response to a delegation signal received from the data processing pipeline. Decoding the received sequence of instructions generates control signals to control the data processing pipeline to perform the data processing operations. The decoding is responsive to an extension start instruction specifying the delegated task to: generate the control signals to control the data processing pipeline to issue the delegation signal to the extension processing circuitry to delegate the delegated task to the extension processing circuitry. The extension processing circuitry performs the delegated task asynchronously to the data processing operations performed by the data processing pipeline.
There is provided an apparatus for data processing. The apparatus includes a data processing pipeline that performs one or more data processing operations and extension processing circuitry associated with the data processing pipeline that performs one or more delegated tasks. Page table walk circuitry performs a page table walk operation on memory in response to either the one or more data processing operations or the one or more delegated tasks. The extension processing circuitry performs the one or more delegated tasks asynchronously to the one or more data processing operations performed by the data processing pipeline.
G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB]
80.
INDEXED VECTOR PERMUTATION, VECTOR COMPARISON, AND/OR POPULATION COUNT OPERATIONS
The present disclosure relates generally to integrated circuits and relates more particularly to vector comparison and/or population count operations, such as for vector sorting, merging, and/or intersection.
Apparatuses, methods of data processing, computer programs, and computer- readable media are disclosed. A data processing pipeline performs data processing operations defined by a received sequence of instructions. Extension processing circuitry associated with the data processing pipeline performs a delegated task in response to a delegation signal received from the data processing pipeline, performing the delegated task asynchronously to the data processing pipeline. The data processing pipeline performs speculative instruction execution. In response to an extension start instruction, the data processing pipeline issues the delegation signal to the extension processing circuitry to delegate the delegated task and. the extension processing circuitry responds by commencing the delegated task before a speculation confirmation is generated for the extension start instruction. The extension processing circuitry ensures that no results generated by the delegated task are visible outside the extension processing circuitry until the speculation confirmation is generated for the extension start instruction.
There is provided an apparatus for data processing. A data processing pipeline executes one or more data processing operations. Extension processing circuitry associated with the data processing pipeline executes one or more delegated tasks and event processing circuitry causes at least one of the one or more delegated tasks and/or the one or more data processing operations to begin execution based on an event indicated by a linking instruction. The extension processing circuitry performs the one or more delegated tasks asynchronously to the one or more data processing operations performed by the data processing pipeline.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
83.
SYSTEM, DEVICES AND/OR PROCESSES FOR APPLYING KERNEL COEFFICIENTS
Example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, in techniques to apply convolution operations to values defined in a feature map. In one example implementation in which a resulting output is to be formatted in a higher resolution, interpolation operations may be interleaved with application of kernel coefficients in a convolution operation.
The present disclosure relates generally to integrated circuits and relates more particularly to vector comparison and/or population count operations, such as for vector sorting, merging, and/or intersection.
There is provided address translation circuitry and a method for performing address translation. The address translation circuitry is responsive to receipt of a first address and an identifier to perform an address translation from the first address to a second address by performing a translation table walk comprising one or more translation lookups in a plurality of translation tables that are indexed based on a corresponding portion of the first address. The address translation circuitry is further configured to perform a metadata table walk to determine metadata specific to the identifier and associated with the address translation. The metadata table walk comprises one or more metadata lookups in a plurality of metadata lookup tables, each of the one or more metadata lookups corresponds to one of the one or more translation lookups and is indexed based on a same portion of the first address as that translation.
An apparatus comprises reset circuitry to perform a cold reset and to perform a warm reset by resetting a subset of state that is reset the cold reset, and branch recording circuitry to perform branch recording to store, in branch record storage circuitry, information about processed branch instructions. The branch recording circuitry determines whether warm and cold branch recording configuration values held in at least one register satisfy a predetermined condition; and when the warm and cold branch recording configuration values fail to satisfy the predetermined condition, branch recording is disabled. The branch record storage circuitry is configured to make the information about the processed branch instruction available for diagnostic analysis. The cold reset comprises resetting both of the warm and cold branch recording configuration values, and the warm reset comprises resetting the warm branch recording configuration value and leaving the cold branch recording configuration value unchanged.
A method for processing an image. The method comprises receiving intensity values of pixels for each of a plurality of images captured by an image sensor during a detection window. The method comprises identifying, using the intensity values, a plurality of transitions occurring at different times during the detection window, each transition of the plurality of transitions being identified on the basis of detecting intensity values of pixels that have been clipped in images between which such transitions may occur. The method comprises, based on identifying the plurality of transitions occurring during the detection window, at least one of: adjusting an exposure level of the image sensor; and determining a tonemapping function having a tonemapping strength, and applying the tonemapping function to the intensity values of a current image to generate tonemapped intensity values, wherein the image sensor has a current exposure level when the current image is captured.
A method is provided that includes receiving a source code block of a source code and a sensor configuration associated with the source code block, performing instrumentation on the source code block at least two times to generate corresponding at least two differently instrumented code blocks from the source code block, creating a corresponding model of the sensor configuration for each differently instrumented code block, and receiving a request for an instrumented variant of the source code block for execution by a processing element and deploying the instrumented variant of the source code block to the processing element. The instrumented variant of the source code block comprises one of the at least two differently instrumented code blocks from the source code block.
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
G06F 21/56 - Détection ou gestion de programmes malveillants, p. ex. dispositions anti-virus
Disclosed is an apparatus comprising: instruction decoding circuitry; data storage; and processing circuitry to process data responsive to an instruction decoded by instruction decoding circuitry configured to, responsive to a data transfer instruction specifying a data source and a region of the source to perform data transfer, control processing circuitry to: when the data transfer operation comprises an out-of-bounds memory access corresponding to an attempt to read data outside the indicated region of source storage, read data not associated with the out-of-bounds memory access from source storage and write data not associated with the out-of-bounds memory access to a first portion of target storage by overwriting preloaded values stored in the first portion of the target storage; and omit writing to a different second portion of the target storage data associated with the out-of-bounds memory access to preserve preloaded values stored in the second portion of target storage.
An apparatus has processing circuitry to execute instructions and address prediction storage circuitry to store address prediction information for use in predicting upcoming instructions to be executed by the processing circuitry. The processing circuitry is responsive to an instruction to generate a pointer signature for a pointer to generate the pointer signature for the pointer based on an address of the pointer and a cryptographic key. The address prediction storage circuitry is also configured to store address prediction information for the pointer, the address prediction information including the pointer. The processing circuitry is responsive to an instruction to authenticate a given pointer to obtain, based on the address prediction information for the given pointer, a predicted pointer signature; compare the predicted pointer signature with a pointer signature identified by the instruction to authenticate; and responsive to the comparing detecting a match, determine that the given pointer is valid.
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 21/44 - Authentification de programme ou de dispositif
There is provided a data processing apparatus comprising: memory access circuitry configured to issue access requests to a memory system: estimation circuitry configured to estimate a statistical cardinality count on memory row addresses accessed by the access requests: and decay circuitry configured to apply an exponential time-based decay during estimation of the statistical cardinality count.
G11C 11/4078 - Circuits de sécurité ou de protection, p. ex. afin d'empêcher la lecture ou l'écriture intempestives ou non autoriséesCellules d'étatCellules de test
A computer implemented method is provided. The computer implemented method includes receiving, for execution by a processing element, a relocatable instrumented code block, the relocatable instrumented code block being code that has undergone instrumentation for a monitoring system, duplicating at least one function of the relocatable instrumented code block to produce a plurality of duplicate relocatable code blocks, allocating the instrumented code block and each duplicate relocatable code block of the plurality of duplicate relocatable code blocks to different locations in a memory on a computing device, creating a relocated mapping of the instrumented code block and each duplicate relocatable code block to their corresponding locations in the memory, and transmitting a copy of the mapping of the instrumented code block and each duplicate relocatable code block to their corresponding locations in memory to the monitoring system.
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
Disclosed herein are a method and apparatus for monitoring for a trigger event, where the trigger event is a determination that a user will issue a capture instruction to capture a target scene, and in response to detecting the trigger event, switching an image system at the apparatus from a first mode of operation, in which image data representing a captured target scene is generated at a first level of quality, to a second mode of operation, in which the image data is generated at a second level of quality, where the second quality level is higher than the first quality.
An apparatus has a plurality of event counters, each to maintain a respective count value based on monitoring of events occurring during execution of a sequence of instructions by processing circuitry. At least when a given condition is present, selection circuitry is responsive to a given instruction in the sequence whose execution by the processing circuitry will cause a number of operations to be performed that is dependent on associated instruction control information, where one or more of the operations are associated with a given event being monitored by a given event counter, to apply a selection algorithm to derive a selected update indicator from the instruction control information. The selection algorithm is such that the selected update indicator varies over multiple applications of the selection algorithm. Count control circuitry is then arranged to cause the count value of the given event counter to be adjusted by a default amount to account for execution of the given instruction by the processing circuitry, when a value of the selected update indicator is a first value, or to cause the count value of the given event counter to be adjusted by a non-default amount to account for execution of the given instruction by the processing circuitry, when the value of the selected update indicator is a second value.
An apparatus and method are provided for producing a new output value for inclusion within a sequence of output values that are output in a given representation. An input interface receives a target value, and modification circuitry determines a new output value in the sequence from a current output value in the sequence in dependence on the target value, such that the new output value meets a determined condition. The determined condition requires both that the new output value has a Hamming distance of 1 relative to the current output value when the new output value and the current output value are expressed in the given representation, and that the new output value lies between the current output value and the target value. The modification circuitry is arranged, when there are at least two possible new output values that meet the determined condition, to select as the new output value the possible new output value that is closest to the target value from amongst the at least two possible new output values.
Disclosed is a data processing system comprising a data processor and a cache that is operable to transfer data from memory to the data processor. The data processor is operable to use data of a type that when transferred to the cache can comprise multiple component values. The data processor is however operable to store within a cache line of the cache a subset of less than all of the component values for a multicomponent data element. The cache is configured to further store in association with each cache line an indication of which data element component values are stored in the cache line so that cache lookups can be performed using the indications of which data element component values are stored in which cache lines.
According to the present techniques there is provided a method of operating a data processor unit to generate processing tasks: the data processor unit comprising: a control circuit to receive, from a host processor unit, a request for the data processor unit to perform a processing job; an iterator unit to process the request and generate a workload comprising one or more tasks for the requested job; one or more execution units to perform the one or more tasks; storage to store system information indicative of a status of at least one component of the data processor unit; the method comprising: receiving, at the control circuit, a first request to perform a first processing job; processing, at the iterator unit, the first request and generating a workload comprising one or more tasks for the first processing job based on or in response to the system information in storage, wherein at least one characteristic of the workload is dependent on the system information.
An apparatus, a computer-readable medium, a system, a chip-containing product and a method are provided relating to floating point arithmetic, wherein a combined arithmetic operation with respect to three input floating point values is performed. The combined arithmetic operation comprises a rounded first arithmetic operation on the first and second input floating point values generating a rounded first arithmetic result and a rounded second arithmetic operation on the rounded first arithmetic result and the third input floating point value to generate a final rounded result of the combined arithmetic operation. When a shift operation on a non-zero mantissa of the third input floating point value generates a zero-value shifted mantissa, the zero-value shifted mantissa is adjusted to become non-zero.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
An apparatus with prefetching capabilities is provided in order to produce predictions of a memory address to be accessed by a load instruction in the future. An additional special cache is provided where pre-aligned data can be stored based on that prediction. When that load instruction is eventually received, the prediction can be confirmed and the pre-aligned data returned and loaded into a register file. In accordance with these techniques, the load instruction does not need to access the memory system nor perform alignment of the data before loading it into the register file. Hence the load instruction is performed faster than when loading data via a memory access. Further precautionary functionalities are also provided to manage the pre-aligned data to avoid the possibility of data corruption after a substantive change occurs to the state of memory.
