An integrated circuit assembly comprises an integrated circuit die comprising a first mounting surface, and a substrate having a first mounting surface and a second mounting surface opposite the first mounting surface. The first mounting surface of the substrate is electrically and physically coupled to the first mounting surface of the integrated circuit die, and the substrate further comprises a first plurality of electrical contact pads on the second mounting surface of the substrate. A vertically integrated voltage regulator has a first mounting surface and a second mounting surface opposite the first mounting surface, and is electrically and physically coupled to the substrate on the second mounting surface of the substrate and the first mounting surface of the vertically integrated voltage regulator. The voltage regulator further comprises a second plurality of electrical contact pads on the second mounting surface of the voltage regulator.
There is provided an apparatus comprising processing circuitry to perform data processing in response to a sequence of instructions. The apparatus comprises occurrence count circuitry to store an occurrence count indicative of a number of repeated occurrences of portions of the sequence of instructions. The apparatus comprises pattern storage circuitry to store a plurality of pattern entries, each pattern entry of the plurality of pattern entries associated with an instruction of the sequence of instructions and comprising a parameter for parameterising a relationship correlating the occurrence count with a value associated with the instruction. The apparatus comprises prediction circuitry responsive to receipt of a given occurrence of the instruction associated with a particular pattern entry, to predict the value associated with the given occurrence based on the relationship parameterised using the at least one parameter comprised in the particular pattern entry and the occurrence count for the given occurrence.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/345 - Adressage de l'opérande d'instruction ou du résultat ou accès à l'opérande d'instruction ou au résultat d'opérandes ou de résultats multiples
An apparatus comprises front end circuitry configured to fetch and decode instructions; and processing circuitry to perform data processing operations in response to instructions decoded by the front end circuitry. In an expandable instruction set mode, the front end circuitry decodes the instructions according to an instruction encoding scheme in which each instruction is required to meet an architectural encoding constraint requiring that, for a given instruction processed in the expandable instruction set mode: the given instruction comprises a set of functional bits representing functionality of the given instruction, and a set of one or more expansion bits; and the set of one or more expansion bits is constrained to specify a predetermined value.
Power multiplexer circuitry, systems, and methods. Power multiplexer circuitry includes interface control logic including first SR latch circuitry to generate first and second interface control signals responsive to first and second latch control signals, a PMUX control circuit to provide a first selection control signal responsive to the first interface control signal and to provide a second selection control signal responsive to the second interface control signal, a power output circuit to output a selected voltage at a PMUX output, the power output circuit including first switch circuitry arranged between a first voltage rail and the PMUX output to provide an electrical path therebetween responsive to the first selection control signal, and second switch circuitry arranged between a second voltage rail and the PMUX output to provide an electrical path therebetween responsive to the second selection control signal.
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
An apparatus comprises instruction decoding circuitry configured to decode instructions of a program thread executed by a given processor core; and load/store control circuitry configured to select a target point of a memory system hierarchy at which to allocate data for a target cache line specified by a load/store instruction decoded by the instruction decoding circuitry. The load/store control circuitry is configured to select the target point of the memory system hierarchy depending on whether the load/store instruction is associated with a memory contention hint provided by a contention hint instruction decoded by the instruction decoding circuitry, the memory contention hint indicating that the target cache line is likely to be subject to contention for access from multiple threads of processing.
There is provided an apparatus comprising decoder circuitry, responsive to a mixed-element-combination instruction specifying one or more first registers and a one or more second registers, to trigger the processing circuitry to perform at least one arithmetic operation to combine each first element of a set of first elements from contiguous positions in the first registers with a corresponding second element of a set of second elements selected from the second registers according to the element information to generate a set of intermediate result elements, and to combine the intermediate result elements to generate a result element. A first element size of each first element is different to a second element size of each second element.
In a variable-length instruction set mode, front end circuitry decodes instructions according to an encoding scheme based on an architectural encoding constraint requiring that a given instruction is encoded fully within a G-bit fetch granule, where G is a fixed power-of-2 integer, and no valid instruction is allowed to cross a boundary between G-bit fetch granules. A predetermined subset of bit positions within a given G-bit fetch granule is used to determine whether the granule is encoded according to a first subset of valid encodings encoding instructions corresponding to instructions of a fixed-length legacy instruction set, or a second subset of valid encodings encoding, according to a layout identified by a layout descriptor in the predetermined subset of bit positions, one or more instructions including at least one instruction of different length to the instructions encoded in the first subset of valid encodings.
An apparatus comprises: front end circuitry configured to fetch and decode instructions; and processing circuitry configured to perform data processing operations in response to instructions fetched and decoded by the front end circuitry. In a container-based instruction set mode for processing instructions from a fixed-length instruction set for which each instruction of the fixed-length instruction set is encoded using the same number of functional bits representing functionality of the instruction, the front end circuitry is configured to decode the instructions according to an encoding scheme in which each instruction is required to meet an architectural encoding constraint requiring that, for a given instruction processed in the container-based instruction set mode: the given instruction is one of a plurality of instructions encoded fully within a C-bit container, where C is a fixed power-of-2 integer; each instruction has W functional bits, where W is a fixed non-power-of-2 integer; and no valid instruction is allowed to cross a boundary between C-bit containers. The front end circuitry supports a branch operation specifying as a branch target any one of the plurality of instructions encoded within a given C-bit container.
Systems and methods for determining whether a region of storage has associated meta data. A storage controller can receive, from a requestor, a request for meta data associated with a region of storage, determine whether the region of storage has associated meta data, and when region of storage has associated meta data, obtain, the meta data associated with the region of storage, and send, from the storage controller to the requestor, a response based at least in part on the associated meta data.
A data processing system is disclosed that includes storage storing an array of data elements. In response to a request to process an item, a hash function is implemented to map an identifier identifying the item to a data element of the array of data elements. A data value of the data element of the array of data elements is used to determine whether the request to process the item can be granted, and the item is allowed to be processed when it is determined that the request to process the item can be granted.
An apparatus comprises value prediction storage storing value prediction entries, each value prediction entry providing a data value prediction associated with a corresponding instruction. A value prediction blocklist identifies one or more blocked instructions, and value prediction allocation circuitry is configured to control whether to allocate a given value prediction entry associated with a given instruction to the value prediction storage in dependence on whether the given instruction is identified as a blocked instruction by the value prediction blocklist. Blocklist allocation circuitry determines whether to add a target instruction to the value prediction blocklist in dependence on an allocation count indicating a number of times a value prediction entry associated with the target instruction has been allocated to the value prediction storage.
A method of data processing in a data processing system comprising a computer vision system. The method comprises obtaining image data representative of a plurality of pixels of an image, the image data comprising a plurality of pixel intensity values respectively representing said pixels. The method comprises identifying one or more compromised pixel intensity values in the plurality of pixel intensity values. The method comprises generating sensor defect state data relating to the identified compromised pixel intensity values. The method comprises performing, using the computer vision system, a feature recognition process on the image data. The method comprises performing an action based on the sensor defect state data.
G06V 10/98 - Détection ou correction d’erreurs, p. ex. en effectuant une deuxième exploration du motif ou par intervention humaineÉvaluation de la qualité des motifs acquis
G06V 20/56 - Contexte ou environnement de l’image à l’extérieur d’un véhicule à partir de capteurs embarqués
There is provided an apparatus comprising history storage circuitry to store history records. Each history record is configured to support a multi-taken encoding identifying: first and second address identifiers of first and second control flow altering instructions, and a local history of changes in control flow resulting from the second control flow altering instruction. The apparatus is provided with pointer storage circuitry to store a global pointer. The apparatus is provided with prediction circuitry responsive to receipt of an address to identify a local history record for which the address corresponds to the second address identifier, and to provide a prediction based on the global pointer. The prediction circuitry is responsive to receipt of the address to identify a further local history record for which the address corresponds to the first address identifier, and to provide a further prediction based on the global pointer.
An integrated circuit assembly comprises an integrated circuit die comprising a first mounting surface, and a substrate having a first mounting surface and a second mounting surface opposite the first mounting surface. The first mounting surface of the substrate is electrically and physically coupled to the first mounting surface of the integrated circuit die, and the substrate further comprises a first plurality of electrical contact pads on the second mounting surface of the substrate. A vertically integrated voltage regulator has a first mounting surface and a second mounting surface opposite the first mounting surface, and is electrically and physically coupled to the substrate on the second mounting surface of the substrate and the first mounting surface of the vertically integrated voltage regulator. The voltage regulator further comprises a second plurality of electrical contact pads on the second mounting surface of the voltage regulator.
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
When generating a graphics processing output by assembling a sequence of one or more of primitives to be processed from a set of vertex indices provided for the output based on primitive configuration information provided for the output, one or more vertex packets are generated using the vertex indices for the assembled primitives, each vertex packet comprising a plurality of vertices of the assembled primitives. After a threshold number of vertices have been allocated to a vertex packet, vertex attribute processing for the vertices of the vertex packet is triggered, to thereby generate a vertex packet comprising processed vertex attributes for the vertices of the vertex packet. The assembled primitives and the generated vertex packets are then provided to later stages of the graphics processing pipeline for processing.
A method of operating a data processing system, a data processing system, and a computer program product. The data processing system includes processors operable to process a job, wherein the job is divided into tasks, and each processor of the plurality of processors is operable to process one or more tasks of the job. The data processing system defines a volume having two or more predetermined dimensions, wherein the volume includes at least part of the job, and divides the volume into regions based on one or more predetermined dimensions of the volume, one or more corresponding dimensions of a task and the number of processors, each region having an initial region size and each region includes spatially proximate tasks. Each of the regions are initially allocated to a processor, and a task within a region is allocated to the processor that is allocated to the region.
Interconnect circuitry comprises: receiving interface circuitry configured to receive, from a metadata-transmitting caching agent, discard control metadata for a given cache line previously held in a private cache of the data-transmitting caching agent; and transmitting interface circuitry configured to transmit the discard control metadata for the given cache line to a metadata-receiving caching agent for caching in a private cache of the metadata-receiving caching agent. The discard control metadata indicating whether the given cache line is, or is eligible for becoming, a discardable cache line allowed to be discarded without data writeback even if the discardable cache line is dirty.
G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p. ex. priorité des données ou des instructions, erreurs de maniement ou repérage
An apparatus comprises cache control circuitry to allocate, to a cache hierarchy comprising a plurality of levels of cache, one or more materialised cache lines corresponding to a region of address space indicated by software-provided information, each materialised cache line specifying a predetermined value as cached data; and cache level selection circuitry to select, based on a size of the region of address space indicated by the software-provided information, at least one target level of the plurality of levels of cache to which the one or more materialised cache lines are to be allocated.
Interconnect circuitry comprises: receiving interface circuitry configured to receive, from a metadata-transmitting caching agent, discard control metadata for a given cache line previously held in a private cache of the data-transmitting caching agent; and transmitting interface circuitry configured to transmit the discard control metadata for the given cache line to a metadata-receiving caching agent for caching in a private cache of the metadata-receiving caching agent. The discard control metadata indicating whether the given cache line is, or is eligible for becoming, a discardable cache line allowed to be discarded without data writeback even if the discardable cache line is dirty.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
An apparatus comprises instruction decoding circuitry to decode instructions; processing circuitry to perform data processing in response to instructions decoded by the instruction decoding circuitry; and cache control circuitry to: set, in response to the instruction decoding circuitry decoding a mark-dead instruction specifying mark-dead target address information, one or more target cache lines selected based on the mark-dead target address information as a discardable cache line, wherein the discardable cache line is allowed to be discarded without data writeback even if the discardable cache line is dirty.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
An apparatus comprises cache control circuitry to allocate, to a cache hierarchy comprising a plurality of levels of cache, one or more materialised cache lines corresponding to a region of address space indicated by software-provided information, each materialised cache line specifying a predetermined value as cached data; and cache level selection circuitry to select, based on a size of the region of address space indicated by the software-provided information, at least one target level of the plurality of levels of cache to which the one or more materialised cache lines are to be allocated.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
22.
MARK-LIVE INSTRUCTION THAT SETS DISCARD-ELIGIBILITY METADATA IN CACHE LINES FOR USE BY MARK-DEAD EVENTS
An apparatus comprises instruction decoding circuitry configured to decode instructions; and processing circuitry configured to perform data processing in response to the instructions decoded by the instruction decoding circuitry. Cache control circuitry is configured to set, in response to the instruction decoding circuitry decoding a mark-live instruction specifying mark-live target address information, discard-eligibility metadata associated with one or more target cache lines selected based on the mark-live target address information, to identify the one or more target cache lines as being eligible for being treated as a discardable cache line which is allowed to be discarded without data writeback even if the discardable cache line is dirty. In response to a mark-dead event associated with a given cache line, the cache control circuitry determines depending on the discard-eligibility metadata for the given cache line whether the given cache line is eligible for becoming a discardable cache line.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec mémoire cache dédiée, p. ex. instruction ou pile
23.
ACCELERATOR HAVING PORT TO VIRTUAL MEMORY ADDRESS ASSOCIATION LOGIC
Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuitry comprising a cache to associate a plurality of ports to virtual memory addresses, cache control circuitry to update the cache to associate the first port with the virtual memory address responsive to a transaction latency meeting a threshold latency condition.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
A circuit for selective write pulse extension including: a first circuit path comprising: a delay element; a second circuit path; and a multiplexer configured to select between respective first and second global timing pulse (GTP) signals of the first circuit path and the second circuit path based on a control signal. A method for selective write pulse extension including detecting, by a circuit, one GTP pulse of a first operation mode or two GTP pulses of a second operation mode per unit cycle, where: the one GTP pulse corresponds to either a read operation or a write operation, and the two GTP pulses correspond to both the read operation and the write operation. Also, in response to the detection of the write operation as the one GTP pulse, at a reset edge of a self-timed path signal, extending a reset pulse width of the self-timed path signal.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
An apparatus for data processing comprises a data processing pipeline to perform data processing operations, and extension processing circuitry to perform a delegated task asynchronously to the data processing pipeline in response to the decoding circuitry decoding an extension start instruction. The apparatus also comprises hazard detection circuitry to detect data hazards associated with processing operations performed by the data processing pipeline. When the data processing pipeline is in an extension hazard checking state, the presence of a hazard condition can be determined in dependence on whether a given memory access, to be performed in response a given memory access instruction following the extension start instruction in program order, is for accessing an address which falls within a group of addresses anticipated to be accessed by the extension processing circuitry during performance of the delegated task.
An apparatus comprises instruction decoding circuitry configured to decode instructions; and processing circuitry configured to perform data processing in response to the instructions decoded by the instruction decoding circuitry. Cache control circuitry is configured to set, in response to the instruction decoding circuitry decoding a mark-live instruction specifying mark-live target address information, discard-eligibility metadata associated with one or more target cache lines selected based on the mark-live target address information, to identify the one or more target cache lines as being eligible for being treated as a discardable cache line which is allowed to be discarded without data writeback even if the discardable cache line is dirty. In response to a mark-dead event associated with a given cache line, the cache control circuitry determines depending on the discard-eligibility metadata for the given cache line whether the given cache line is eligible for becoming a discardable cache line.
G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p. ex. priorité des données ou des instructions, erreurs de maniement ou repérage
An apparatus comprises instruction decoding circuitry to decode instructions; processing circuitry to perform data processing in response to instructions decoded by the instruction decoding circuitry; and cache control circuitry to: set, in response to the instruction decoding circuitry decoding a mark-dead instruction specifying mark-dead target address information, one or more target cache lines selected based on the mark-dead target address information as a discardable cache line, wherein the discardable cache line is allowed to be discarded without data writeback even if the discardable cache line is dirty.
G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p. ex. priorité des données ou des instructions, erreurs de maniement ou repérage
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Integrated circuits; semiconductors; system-on-chip devices;
microprocessors; processors [central processing units];
microprocessors in the field of artificial intelligence;
neural network processors; electronic chips;
application-specific integrated circuits; graphics
processing units; semiconductor intellectual property cores;
computer interfaces, namely instruction set architectures;
printed circuit boards; computer software for integrated
circuits; semiconductors for handheld and mobile devices;
downloadable computer operating software; computer hardware
and recorded computer software, namely, computer subsystems
featuring standardized and optimized hardware and software
components for providing specific levels of computing
performance and functionality sold as a unit; electronic
downloadable materials, namely, electronic downloadable
instruction and development manuals, datasheets and
brochures, all in the area of design and development of
integrated circuits, microprocessors, microprocessor cores,
macro cells, microcontrollers, bus interfaces, and printed
circuit boards; none of the aforementioned in relation to
optoelectronic products, pushbutton switches, capacitive
touch switches, micro switches and rocker switches. Design of semiconductors, microprocessors, system-on-chip
devices, processors [central processing units], chips
[integrated circuits], application-specific integrated
circuits, graphics processing units, machine learning
processors and semiconductor cores; research, development,
and design relating to computer hardware for semiconductor
intellectual property, instruction set architectures,
microprocessors; research, development and design, all
relating to computer software used in, and for use in the
design, verification and construction of microprocessors,
processors, microcontrollers, microprocessor design files,
semiconductor intellectual property cores, computer hardware
accelerators, neural network processors and machine learning
processors; none of the aforementioned in relation to
optoelectronic products, pushbutton switches, capacitive
touch switches, micro switches and rocker switches.
29.
DEBUGGING INSTRUCTION EXECUTION ERRORS IN A SIMULATED COMPUTER SYSTEM
A computing system and associated methods are described for validating behavioral equivalence between different builds of a simulator codebase. Two simulator builds, generated using different build configurations and expected to behave identically for a workload, are selected and used to execute the workload. Trace operations are performed during execution, and checksum values are accumulated and reported at a defined reporting frequency. The checksum values from the executions are compared to detect a mismatch indicative of divergent simulator behavior. When a mismatch is detected, an instruction execution deviation is localized based on an instruction count and the reporting frequency. The techniques support comparison of simulator builds executing on different host operating systems, processor architectures, or translation and code generation configurations, and are applicable to workloads including operating system boot code.
40 - Traitement de matériaux; recyclage, purification de l'air et traitement de l'eau
Produits et services
Custom manufacturing of chips [integrated circuits] for
others; custom manufacture of semiconductor wafers; custom
manufacture of semiconductor circuits; custom manufacture of
semiconductor components; encapsulation of semiconductors.
An apparatus (10) and a method are provided, wherein the apparatus comprises interrupt detection circuitry (40) which detects interrupts raised by at least one interrupt source (14), and interrupt tracking circuitry (44) which manages one or more hard-ware-managed linked list data structures to track pending interrupts detected by the interrupt detection circuitry. A computer program comprising computer-readable code for fabrication of the apparatus, and a computer-readable storage medium are also provided.
A graphics processing system that comprises a graphics processor operable to perform ray tracing is disclosed. Instructions of set of ray tracing shader programs that define different elements of a ray tracing pipeline are combined to generate a combined ray tracing shader program, and the combined ray tracing shader program is provided for execution by a graphics processor.
When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted.
There is provided a control apparatus in which assertion circuitry asserts a request for usage devices to change their usage of a resource from an original usage. Receive circuitry receives a response to the request from the usage devices and hint circuitry asserts a hint to those of the plurality of usage devices for which the response has not been received, that a refusal in response to the request is preferred over an acceptance. There is also provided a usage device in which receive circuitry receives a request from a control apparatus to change the usage device's usage of a resource from an original usage, and receives a hint from the control apparatus that a refusal in response to the request is optional and preferred. Determination circuitry makes a determination of whether the request is to be met based on at least one of: the request and the hint and response circuitry provides a response to the request based on the determination.
An integrated circuit assembly comprises a substrate, and an integrated circuit die (202) physically and electrically attached to the substrate (204). A stiffener is attached to the substrate, the stiffener comprising a planar portion (212) and a protruding portion (216), the planar portion to be attached to the substrate and to be positioned approximately parallel to a planar surface of the substrate, the protruding portion to extend away from the planar portion of the stiffener.
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
41 - Éducation, divertissements, activités sportives et culturelles
Produits et services
Electronic publications, downloadable, in the nature of instruction manuals, user manuals, technical manuals, development manuals, datasheets, brochures, articles, newsletters, blogs, books, magazines, journals, research papers and white papers in the field of semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; visual and audio recordings featuring educational videos and podcasts in the field of semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development Arranging and conducting live, virtual or hybrid business exhibitions in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; business networking; organizing business networking events in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; general business networking referral services, namely, promoting the goods and services of others by passing business leads and referrals among group members; advertising, marketing and promotional services related to technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development for the purpose of facilitating networking and socializing opportunities for business purposes Providing online non-downloadable publications in the nature of educational and training materials in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; providing online non-downloadable visual and audio recordings featuring educational videos and podcasts in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; arranging and conducting live, virtual or hybrid conferences and exhibitions in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; educational and training services, namely, conducting classes, seminars, technical sessions, workshops, presentations, educational panels, hosting speakers all in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; arranging and conducting competitions, quizzes and lotteries in the area of testing knowledge about technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development
A monitoring system for high-integrity monitoring of a safety-critical target system comprises an interface for receiving messages from a target system according to a publish-subscribe communication protocol, and one or more processors. The monitoring system is configured to access configuration data representing one or more expected timing characteristics for a succession of messages that are to be published by the target system in accordance with the publish-subscribe communication protocol and to subscribe, using the publish-subscribe communication protocol, to receive the succession of messages. The monitoring system receives the succession of messages, each comprising a respective publication timestamp, at the interface, and uses the configuration data to determine whether the publication timestamps of the received succession of messages are consistent with the expected timing characteristics. If the publication timestamps of the received succession of messages are not consistent with the expected timing characteristics, the monitoring system signals an inconsistency.
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
Graphics processors and methods of operating a graphics processor for determining a performance metric of one or more draw calls. Tile-based graphics processing includes a graphics processing pipeline including a tile-based renderer that produces tiles of a render output data array, such as an output frame to be displayed.
The present disclosure relates to a system for constructing global context from a plurality of artificial intelligence, AI, agents, comprising: a local context coordinator to communicate with the plurality of AI agents, to receive from one or more of the plurality of AI agents a current observed state representative of a current local environment of each AI agent, and to normalise the current observed state to a common form; a conflict handler to receive the current normalised observed states from the local context coordinator and generate a set of conditions based on the current normalised observed states; and a global context generator to receive the set of conditions and generate an integrated context representative of a global environment comprising the respective current local environment of the plurality of AI agents.
Systems and methods of graphics processing in which property values for sub-regions of primitives are defined by micromaps. A property value defined for a sub-region of a primitive by a micromap is used during ray tracing to determine whether and/or how a ray interacts with the sub-region of the primitive. A tree representation of a micromap is generated, and a property value for a primitive sub-region is determined by traversing the tree representation of the micromap.
An integrated circuit assembly comprises a substrate, and an integrated circuit die physically and electrically attached to the substrate. A stiffener is attached to the substrate, the stiffener comprising a planar portion and a protruding portion, the planar portion to be attached to the substrate and to be positioned approximately parallel to a planar surface of the substrate, the protruding portion to extend away from the planar portion of the stiffener.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/498 - Connexions électriques sur des substrats isolants
A throttler based mitigator including circuitry, related methods and state machine, the circuitry including: a first component to: receive a target index corresponding to a target level of throttle for a clock output signal at the clock throttle circuit; determine a current index implemented at the clock throttle circuit, where the current index corresponds to a current level of throttle of the clock output signal; provide, responsive to the determination, an index signal to cause the clock throttle circuit to throttle the clock output signal in accordance with the index signal.
A clock throttler circuit for droop mitigation and disclose circuitry, related methods and state machine, the method performed at a system to select a first clock signal or a second clock signal to be provided to a subsystem, the method including: receiving, from a droop detector, a trigger signal indicative of a droop event at the subsystem; invoking modulation circuitry to throttle the selectable clock signal in accordance with the event; selecting the first clock signal; providing, to the modulation circuitry, the first clock signal to be throttled.
A circuit includes first and second logic gates, where the first logic gate is configured to output a bitline precharge signal based on a global bitline precharge signal and an output of the second logic gate, and the output of the second logic gate is based on at least a sense amplifier precharge signal and a control signal. Also, the circuit is configured to control a precharge of one or more bitcells based on enabling or disabling the bitline precharge signal. A method includes: detecting, by a circuit, one GTP pulse or two GTP pulses per unit cycle, where the one GTP pulse corresponds to either a read operation or a write operation, and the two GTP pulses correspond to both the read operation and the write operation.
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
Disclosed is an apparatus comprising: instruction decoding circuitry; data storage; and processing circuitry to process data responsive to an instruction decoded by instruction decoding circuitry configured to, responsive to a data transfer instruction specifying a data source and a region of the source to perform data transfer, control processing circuitry to: when the data transfer operation comprises an out-of-bounds memory access corresponding to an attempt to read data outside the indicated region of source storage, read data not associated with the out-of-bounds memory access from source storage and write data not associated with the out-of-bounds memory access to a first portion of target storage by overwriting preloaded values stored in the first portion of the target storage; and omit writing to a different second portion of the target storage data associated with the out-of-bounds memory access to preserve preloaded values stored in the second portion of target storage.
Clock throttler architecture including clock throttler circuitry, related methods and state machine, where the clock throttler circuitry includes: first selection circuitry to select a first pattern of a plurality of patterns in storage, where each pattern of the plurality of patterns comprises a plurality of bits; second selection circuitry to sequentially select bits of the first pattern and to provide the selected bits to clock gate circuitry in a successive manner; where the clock gate circuitry is to receive a clock input signal and to pass or gate pulses of the clock input signal responsive to applying the selected bits to generate a clock output signal.
The present disclosure relates to a system for constructing global context from a plurality of artificial intelligence, Al, agents, comprising: a local context coordinator to communicate with the plurality of Al agents, to receive from one or more of the plurality of Al agents a current observed state representative of a current local environment of each Al agent, and to normalise the current observed state to a common form; a conflict handler to receive the current normalised observed states from the local context coordinator and generate a set of conditions based on the current normalised observed states; and a global context generator to receive the set of conditions and generate an integrated context representative of a global environment comprising the respective current local environment of the plurality of Al agents.
The present technology is directed to a method, circuit and system for improved power management, and in an aspect there is provided control circuitry for controlling operation of an associated power multiplexer circuit, the control circuitry including: a first input to receive a first voltage; a second input to receive a second voltage; comparator circuitry to determine the level of the first voltage relative to the second voltage and to generate a first control signal when the second voltage reaches a first threshold level relative to the first voltage, where the first control signal is to indicate a desired output of the associated power multiplexer circuit.
H02J 3/04 - Circuits pour réseaux principaux ou de distribution, à courant alternatif pour connecter des réseaux de même fréquence, mais provenant de sources différentes
Control stack information tracking circuitry tracks, in a last-in-first-out structure, one or more entries tracking items of store target information corresponding to one or more control stack push instructions. Control stack load elimination circuitry determines whether a control stack load elimination condition is satisfied for a given control stack pop instruction, and if satisfied, eliminates a control stack load operation corresponding to the given control stack pop instruction and uses information obtained from an entry of the control stack information tracking circuitry corresponding to a corresponding control stack push instruction to identify load target information for the given control stack pop instruction.
In a graphics processor that is configured to execute a tile-based graphics processing pipeline a geometry buffer is provided that is operable to store ‘temporary’ geometry items that are produced by and then consumed during the initial, geometry processing pass of the tile-based graphics processing pipeline. Access logic is operable and configured to control a maximum amount of storage space within the geometry buffer that is available to be allocated for storing new such temporary geometry items produced by the sequence of one or more geometry processing stages.
In one implementation, a circuit for power-switching includes: power gating circuitry and a first back metal, where a single output of the power gating circuitry is configured to provide at least one of power and ground supply by way of the first back metal to a word line driver circuitry. A method for power-switching includes: providing a power gating circuitry and one or more back metals; and providing, by the power gating circuitry, at least one of power and ground supply through the one or more back metals to a word line driver circuitry. A method of fabrication includes: fabricating a memory macro unit; forming one or more back metals; and coupling power gating circuitry and word line driver circuitry of the memory macro unit by way of the one or more back metals.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
A clock throttler circuit for droop mitigation and disclose circuitry, related methods and state machine, the method performed at a system to select a first clock signal or a second clock signal to be provided to a subsystem, the method including: receiving, from a droop detector, a trigger signal indicative of a droop event at the subsystem; invoking modulation circuitry to throttle the selectable clock signal in accordance with the event; selecting the first clock signal; providing, to the modulation circuitry, the first clock signal to be throttled.
A circuit includes: one or more delay line units, where each of the delay line units has a first portion and one or more second portions. The first portion includes a NAND gate and each of the one or more second portions includes a PMOS device and first, second, and third NMOS devices. Also, each of the one or more delay line units is configured for an AND gate logic operation. In addition, a method includes: receiving first and second input signals at a first portion of a delay line unit; and activating a first NMOS device to provide conduction to an outputof the delay line unit.At a second portion of the delay line unit, the first NMOS device is coupled between a reset input and the output, and the first NMOS device is activated upon receiving the first input signal.
H03K 5/134 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard avec des transistors à effet de champ
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
An apparatus for controlling the voltage supply of one or more digital circuits, the one or more digital circuits having a functional clock unit to provide a clock signal to the one or more digital circuits, the apparatus including: a first feedback generation unit to generate a first feedback signal based on a comparison between a current number of gate delays corresponding to a current clock signal and a target number of gate delays; and a power regulator unit to adjust the power delivery to the one or more digital circuits based on the first feedback signal.
G05F 1/613 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en parallèle avec la charge comme dispositifs de réglage final
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
A throttler based mitigator including circuitry, related methods and state machine, the circuitry including: a first component to: receive a target index corresponding to a target level of throttle for a clock output signal at the clock throttle circuit; determine a current index implemented at the clock throttle circuit, where the current index corresponds to a current level of throttle of the clock output signal; provide, responsive to the determination, an index signal to cause the clock throttle circuit to throttle the clock output signal in accordance with the index signal.
Clock throttler architecture including clock throttler circuitry, related methods and state machine, where the clock throttler circuitry includes: first selection circuitry to select a first pattern of a plurality of patterns in storage, where each pattern of the plurality of patterns comprises a plurality of bits; second selection circuitry to sequentially select bits of the first pattern and to provide the selected bits to clock gate circuitry in a successive manner; where the clock gate circuitry is to receive a clock input signal and to pass or gate pulses of the clock input signal responsive to applying the selected bits to generate a clock output signal.
A data processing apparatus is provided in which receive circuitry receives a memory access instruction containing an indication of a target address. The target address is associated with one of a plurality of memory targets. Prediction circuitry performs a prediction of one of the plurality of memory targets to which the memory access instruction is associated, based on an address associated with the memory access instruction and forward circuitry forwards a memory access request based on the memory access instruction to the one of the plurality of memory targets.
An order controlling interconnect circuit node of a data processing system couples to an interconnect circuit of a network and to target nodes. The node includes transmitting interface circuitry, message receiving interface circuitry, and control circuitry. The control circuitry is configured to monitor incoming “ready” response messages at the message receiving circuitry and to control the message transmitting interface circuity to send a cancellation request message to the target node of the oldest write request of the one or more second write-push requests when a “ready” response message has not been received for the first write-push request within a designated time period. Subsequent to sending the cancellation request message, a continuation request message is to the target node of the oldest write-push request of the one or more second write-push requests when a “ready” response message has been received for the first write-push request.
A data processing system is disclosed that includes a data processing unit and a codec unit. A set of addresses of an address space is associated with the codec unit, and the codec unit, in response to a request from the data processing unit to access an address of the set of addresses associated with the codec unit, provides decoded data to the data processing unit or causes data provided by the data processing unit to be encoded.
There is provided an apparatus comprising processing circuitry to issue a memory access request specifying a target address. The apparatus comprises memory access control circuitry to control handling of the memory access request based on a memory access control attribute associated with the target address. The memory access control circuitry comprises attribute storage circuitry to store entries each identifying a region of address space and a memory access control attribute. The memory access control circuitry is responsive to the memory access request to perform a lookup in the attribute storage circuitry. The processing circuitry comprises current region identifying information indicative of a current region of address space and a current memory access control attribute. The processing circuitry is configured, when the target address is comprised in the current region, to indicate the current memory access control attribute to the memory access control circuitry, and to omit the lookup.
An apparatus includes offload circuitry to transmit to coprocessing circuitry an instruction packet comprising one or more instructions offloaded by processing circuitry for execution by the coprocessing circuitry; and packet merging circuitry to perform a packet merge. The packet merge includes determining whether the instruction packet has capacity to include one or more additional instructions offloaded by the processing circuitry for execution by the coprocessing circuitry; and including the one or more additional instructions in the instruction packet in response to determining that the instruction packet has capacity to include the one or more additional instructions.
An interconnect circuit comprises an unblock-request-receiving interconnect circuit node configured to receive a given write push request specifying write target data and write target address information identifying one or more addressed locations to which the write target data is to be written, and to enforce a requirement that a conflicting read request, which requests a read to one of the one or more addressed locations identified by the write target address information specified by the given write push request, is blocked from completing until an unblocking condition is satisfied for the given write push request, where for at least one type of write push request, satisfaction of the unblocking condition is dependent on an unblock request for the given write push request being received by the unblock-request-receiving interconnect circuit node; and an unblock-request-transmitting interconnect circuit node configured to transmit the given write push request to the unblock-request-receiving interconnect circuit node, and to transmit the unblock request for the given write push request in response to receipt of a completion response for an older write push request transmitted by the unblock-request-transmitting interconnect circuit node.
An apparatus comprises processing circuitry comprising execution units and issue circuitry to issue an instruction. In response to a consumer instruction identifying a source data operand, the issue circuitry identifies a set of one or more candidate producer instructions for the consumer instruction from a plurality of outstanding instructions that have not yet completed, each candidate producer instruction being capable of producing a data value to be used for the source data operand; and in a case where the set comprises two or more candidate producer instructions of which at least one candidate producer instruction is a conditional instruction to be executed in dependence on a respective condition being satisfied, prior to determining which of the two or more candidate producer instructions is an actual producer instruction that will produce the data value to be used for the source data operand, issues the consumer instruction to be executed.
An apparatus includes conditional branch future instruction processing circuitry configured to process a conditional branch future instruction, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition. The apparatus also includes branch condition evaluating circuitry configured to determine whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target.
An apparatus includes decoding circuitry configured to decode instructions; processing circuitry configured to perform data processing operations in response to the instructions decoded by the decoding circuitry; extension processing circuitry configured to perform other data processing operations asynchronously with respect to data processing operations performed by the processing circuitry; an extension task offload interface separate from an interface by which the processing circuitry issues a memory system request to a memory system, wherein the extension task offload interface is responsive to at least one task offloading instruction decoded by the decoding circuitry to offload the other data processing operations to the extension processing circuitry; and resource allocation adjustment circuitry configured to adjust a resource allocation between the processing circuitry and the extension processing circuitry responsive to a resource adjustment indication.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
(1) Integrated circuits; semiconductors; system-on-chip devices; microprocessors; processors [central processing units]; microprocessors in the field of artificial intelligence; neural network processors; electronic chips; application-specific integrated circuits; graphics processing units; semiconductor intellectual property cores; computer interfaces, namely instruction set architectures; printed circuit boards; computer software for integrated circuits; semiconductors for handheld and mobile devices; downloadable computer operating software; computer hardware and recorded computer software, namely, computer subsystems featuring standardized and optimized hardware and software components for providing specific levels of computing performance and functionality sold as a unit; electronic downloadable materials, namely, electronic downloadable instruction and development manuals, datasheets and brochures, all in the area of design and development of integrated circuits, microprocessors, microprocessor cores, macro cells, microcontrollers, bus interfaces, and printed circuit boards; none of the aforementioned in relation to optoelectronic products, pushbutton switches, capacitive touch switches, micro switches and rocker switches. (1) Design of semiconductors, microprocessors, system-on-chip devices, processors [central processing units], chips [integrated circuits], application-specific integrated circuits, graphics processing units, machine learning processors and semiconductor cores; research, development, and design relating to computer hardware for semiconductor intellectual property, instruction set architectures, microprocessors; research, development and design, all relating to computer software used in, and for use in the design, verification and construction of microprocessors, processors, microcontrollers, microprocessor design files, semiconductor intellectual property cores, computer hardware accelerators, neural network processors and machine learning processors; none of the aforementioned in relation to optoelectronic products, pushbutton switches, capacitive touch switches, micro switches and rocker switches.
67.
CHIPLET INTEGRATED CIRCUIT (IC) HAVING ACTIVE AND INACTIVE INTERFACE CIRCUITRY
Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuitry comprising a chiplet having semiconductor circuitry corresponding to an active interface and an inactive interface, where the chiplet may further include contacts connected to the active interface circuitry.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H03K 17/56 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs
There is described delay circuitry including: a pulse generator to generate a pulse responsive to receiving an input signal edge and to buffer and invert the input signal edge; and a signal output element to receive the pulse and the buffered and inverted signal edge from the pulse generator and to generate a delayed signal edge responsive to a trailing edge of the pulse and based on the buffered and inverted signal edge. In addition, there is described delay circuitry including: a buffer-inverter unit to receive, buffer and invert an input signal and to generate a delayed output signal, the buffer-inverter unit including a signal-controlled gate to invert the input signal arranged in series with a mode-controlled gate to pass the input signal. Finally, there is described apparatus including the delay circuitry and a flip flop.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
H03K 5/1534 - Détecteurs de transition ou de front
69.
CHIPLET INTEGRATED CIRCUIT (IC) HAVING CENTRAL AND WING CHIPLETS
Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuitry comprising a plurality of central chiplets and a plurality wing chiplets.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
70.
GRAPHICS PROCESSING APPARATUS AND METHOD FOR PERFORMANCE METRIC SAMPLING
A graphics processing apparatus includes a workload execution circuit to execute workloads and a performance counting circuit to count instances of performance metrics. A workload handling circuit receives commands and responds to performance counter sampling commands that indicate performance counter sampling contexts comprising performance metrics to be sampled and sampling intervals. The workload handling circuit monitors sampling intervals and triggers the workload execution circuit to write out sample values for performance metrics upon interval elapse. A driver receives performance metric sampling indications, allocates memory for sample values, generates performance counter sampling commands, and provides these to the workload handling circuit. The workload handling circuit writes out workload scheduling metadata, configures sampling according to sampling contexts, and manages the writing of sample values either directly to memory or back to the workload handling circuit with associated timestamp information.
There are provided apparatuses, methods, systems, chip-containing products and computer-readable storage media. Prefetching retrieves content from a memory system. History storage stores plural entries, each identifying a basic block of memory addresses, wherein the basic block of memory addresses is a contiguous range of memory addresses from which content has been requested to be retrieved from the memory system. An entry order of the plural entries corresponds to a basic block order in which corresponding basic blocks have been requested to be retrieved from the memory system. An entry-order-older basic block is associated with with an entry-order-younger basic block for which respective entries are stored in the history storage circuitry, these basic blocks being separated by at least a defined minimum number of entries in entry order in the history storage. A sequence of request addresses from which content is requested to be retrieved from the memory system is monitored. When a requested address corresponds to the entry-order-older basic block prefetching corresponding to the entry-order-younger basic block is triggered.
An apparatus includes a branch predictor to generate a prediction associated with a branch instruction outcome for a block of at least one instruction. The branch predictor includes: lookup circuitry configured to perform a lookup of stored prediction information to identify a plurality of prediction entries associated with alternative paths of program flow, the plurality of prediction entries comprising a main prediction entry to be used for generating the prediction and one or more alternative prediction entries each associated with an alternative path of program flow; prediction generation circuitry configured to generate the prediction based on the main prediction entry; and alternative prediction storage circuitry configured to store the one or more alternative prediction entries identified by the lookup circuitry; in which responsive to a flush signal indicative of the prediction being incorrect, the prediction generation circuitry is configured to generate an alternative prediction associated with the block of the at least one instruction based on the one or more alternative prediction entries stored by the alternative prediction storage circuitry.
An integrated circuit assembly comprises an integrated circuit die and a substrate electrically and physically coupled to the integrated circuit die. A capacitor is physically coupled to the substrate at a location physically between the integrated circuit die and the substrate, the capacitor electrically coupled to the integrated circuit die via at least one electrical connection.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
An apparatus comprises branch prediction circuitry to generate predictions in respect of a given block of one or more instructions, the predictions comprising at least a main path prediction in respect of a given branch instruction and at least one alternate path prediction in respect of an alternate path of program flow predicted to be followed if the main path prediction is incorrect. The branch prediction circuitry stores the at least one alternate path prediction in an alternate prediction cache. Block skipping circuitry is responsive to a flush signal indicative of the main path prediction being incorrect to control the branch prediction circuitry to begin generating predictions in respect of a subsequent block of instructions identified by a prediction resumption address, identified based on the at least one alternate path prediction which may indicate that the alternate path of program flow includes at least one taken branch.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec mémoire cache dédiée, p. ex. instruction ou pile
75.
MULTI-TAKEN PREDICTION ENTRIES FOR PREDICTION RESUMPTION
An apparatus comprising prediction storage circuitry to store a plurality of prediction entries, each prediction entry indicative of whether a respective branch instruction is predicted to be taken or not taken. At least one prediction entry supports an encoding of a multi-taken entry indicating that the respective branch instruction and at least one subsequent branch instruction are each predicted to be taken. The apparatus also comprises prediction resumption circuitry to identify, based on stored information dependent on the multi-taken entry, a prediction resumption address in response to a flush signal, where the prediction resumption address is an address in respect of which at least one prediction is to be generated after the flush signal.
Exception control circuitry (40) controls taking of exception by processing circuitry (4), depending on control information stored in at least one register (14), the control information including masking control information settable to a masked state or unmasked state; and trap-masked-exception control information settable to an untrapped state or trapped state. In response to a given exception of a maskable class of exceptions, in at least one scenario when the masking control information is in the masked state and a current exception level is less privileged than a predetermined trap target exception level, the exception control circuitry controls whether to trap the given exception to the predetermined trap target exception level depending on whether the trap-masked-exception control information is in the trapped state. When the masking control information is in the unmasked state, a target exception level for handling the given exception is selected independent of the trap-masked-exception control information.
Processing circuitry 16 performs a stack pointer switch validity checking operation associated with a switch of the stack pointer from an outgoing stack pointer value to an incoming stack pointer value. The validity checking operation comprises verifying whether an incoming data value obtained by memory access circuitry 26 in response to a memory access request specifying an address determined based on the incoming stack pointer value meets at least one stack cap value validity condition, including a condition that a predetermined portion of the incoming data value corresponds to a given page address indicative of a page of address space comprising the address determined based on the incoming stack pointer value. The at least one stack cap value validity condition is determined independent of whether a further portion of the incoming data value other than the predetermined portion corresponds to sub-page address bits of the address determined based on the incoming stack pointer value. An error handling response is triggered in response to determining that the incoming data value fails to meet the at least one stack cap value validity condition.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
An integrated circuit assembly comprises an integrated circuit die and a substrate electrically and physically coupled to the integrated circuit die. A capacitor is physically coupled to the substrate at a location physically between the integrated circuit die and the substrate, the capacitor electrically coupled to the integrated circuit die via at least one electrical connection.
There is provided an apparatus comprising storage circuitry to store a plurality of entries each identifying a corresponding contiguous range of addresses spanning one or more of a plurality of addressable regions. Content stored at each of the plurality of addressable regions is individually retrievable by fetch circuitry. The apparatus is also provided with control circuitry to store information indicative of a candidate new entry identifying a contiguous range of addresses. The control circuitry is responsive to receipt of an indication of a memory access request specifying an addressable region other than one of the plurality of addressable regions which is both contiguous with and subsequent to the contiguous range of addresses, to determine if the addressable region is within a predefined range. The control circuitry is responsive to the addressable region being within the predefined range, to modify the contiguous range of addresses to include the addressable region.
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec pré-lecture
An apparatus comprises bridge circuitry configured to bridge between a memory system interconnect and a port controller. In a first state, the bridge circuitry is configured to control the internal communication link interface to transmit a given type of packet to the port controller using a first type of credit. In a second state, the bridge circuitry is configured to control the internal communication link interface to transmit the given type of packet to the port controller without using the first type of credit. The first type of credit represents availability of buffer storage at the link partner.
There is provided an apparatus comprising bridge circuitry to couple processing circuitry to an allocated subset of a plurality of port controllers for connecting the processing circuitry to link partners. The bridge circuitry is configured to perform a data transfer between the processing circuitry and the allocated subset according to a bandwidth quota. The apparatus is provided with control circuitry to receive configuration information identifying the allocated subset, and to allocate a bandwidth share to each port controller identified in the allocated subset. The control circuitry is configured to determine the bandwidth share based on the configuration information. The control circuitry is configured, for each given port controller identified in the allocated subset, to implement a restriction to limit the data transfer between the given port controller and the processing circuitry according to the bandwidth share allocated to the given port controller.
A method performed by an information processing apparatus is provided. The method may comprise obtaining input data, determining a parameter value of an input data parameter associated with the input data, and configuring a machine learning model to the parameter value, comprising determining a set of inference model parameters associated with the determined parameter value by performing either of: (i) interpolating model parameter values from two or more sets of model parameters to obtain the set of inference model parameters, each set being associated with a respective reference value of the input data parameter, or (ii) applying a second machine learning model to the parameter value to obtain the inference model parameters. The method may further comprise processing the input data using the configured machine learning model to generate output data associated with the parameter value comprising applying the inference model parameters to the input data.
An apparatus comprises bridge circuitry configured to bridge between a memory system interconnect and a port controller. In a first state, the bridge circuitry is configured to control the internal communication link interface to transmit a given type of packet to the port controller using a first type of credit. In a second state, the bridge circuitry is configured to control the internal communication link interface to transmit the given type of packet to the port controller without using the first type of credit. The first type of credit represents availability of buffer storage at the link partner.
There is provided an apparatus comprising bridge circuitry to couple processing circuitry to an allocated subset of a plurality of port controllers for connecting the processing circuitry to link partners. The bridge circuitry is configured to perform a data transfer between the processing circuitry and the allocated subset according to a bandwidth quota. The apparatus is provided with control circuitry to receive configuration information identifying the allocated subset, and to allocate a bandwidth share to each port controller identified in the allocated subset. The control circuitry is configured to determine the bandwidth share based on the configuration information. The control circuitry is configured, for each given port controller identified in the allocated subset, to implement a restriction to limit the data transfer between the given port controller and the processing circuitry according to the bandwidth share allocated to the given port controller.
Disclosed is a graphics processor that comprises a plurality of processing cores and a cache that is operable to transfer data between the processing cores and a memory that the graphics processor has access to. Access logic is provided to control how memory accesses issued by the processing cores are distributed across the cache slices. The cache slice that is used for a memory access is determined using a function computed by the access logic based on one or more properties associated with the memory access, and the function can be changed over time to vary how memory accesses from the plurality of processing cores are distributed across the plural cache slices.
An apparatus comprises: an external port controller to control communication, via an external communication link for communicating with a link partner, of external link protocol packets defined according to an external link protocol; and bridge circuitry to map between the external link protocol packets and memory system interconnect transactions defined according to a memory system interconnect protocol used by a memory system interconnect. The bridge circuitry and the external port controller are coupled via an internal communication link and use an internal link protocol to transport the external link protocol packets between the bridge circuitry and external port controller. The bridge circuitry comprises transaction ordering circuitry to enforce external link protocol transaction ordering rules imposed by the external link protocol to restrict ordering between respective data access transactions corresponding to external link protocol packets communicated with the link partner on the external communication link.
40 - Traitement de matériaux; recyclage, purification de l'air et traitement de l'eau
Produits et services
Custom manufacturing of chips [integrated circuits] for others; Custom manufacture of semiconductor wafers; Custom manufacture of semiconductor circuits; Custom manufacture of semiconductor components; Encapsulation of semiconductors.
40 - Traitement de matériaux; recyclage, purification de l'air et traitement de l'eau
Produits et services
Custom manufacturing of chips [integrated circuits] for others; Custom manufacture of semiconductor wafers; Custom manufacture of semiconductor circuits; Custom manufacture of semiconductor components; Encapsulation of semiconductors.
An apparatus comprising processing circuitry configured to generate an instruction for configuring a hardware accelerator to perform a task. The instruction comprises a predefined set of fields comprising a control field indicative of a selected set of fields of the predefined set of fields to be provided to the hardware accelerator to configure the hardware accelerator to perform the task. The apparatus comprises accelerator control interface circuitry configured to exchange messages, each with a size less than or equal to a predefined size, with the hardware accelerator. To configure the hardware accelerator to perform the task, the accelerator control interface circuitry is configured to send the selected set of fields to the hardware accelerator, using a set of command messages with a combined size greater than the predefined size. The application further relates to a hardware accelerator.
An apparatus comprising storage, an execution unit and a handling unit. The handling unit is configured to obtain task data that describes a task to be executed. The task comprises a plurality of operations representable as a directed graph of operations. The task data comprises task-specific variable data representative of a task-specific variable for use in executing an operation of the plurality of operations. The handling unit is configured to obtain a data move instruction and, based on the data move instruction, move the task-specific variable data into a physical storage location of the storage. The handling unit is configured to dispatch invocation data, based on the task data and the physical storage location, to the execution unit to cause the execution unit to execute the operation.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Integrated circuits; semiconductors; system-on-chip devices;
microprocessors; processors [central processing units];
microprocessors in the field of artificial intelligence;
neural network processors; electronic chips;
application-specific integrated circuits; graphics
processing units; semiconductor intellectual property cores;
computer interfaces, namely instruction set architectures;
printed circuit boards; semiconductors, microprocessors for
Internet of Things (IOT) devices; computer software for
integrated circuits; downloadable computer operating
software; computer hardware and recorded computer software,
namely, computer subsystems featuring standardized and
optimized hardware and software components for providing
specific levels of computing performance and functionality
sold as a unit; electronic downloadable materials, namely,
electronic downloadable instruction and development manuals,
datasheets and brochures, all in the area of design and
development of integrated circuits, microprocessors,
microprocessor cores, macro cells, microcontrollers, bus
interfaces, and printed circuit boards. Design of semiconductors, microprocessors, system-on-chip
devices, processors [central processing units], chips
[integrated circuits], application-specific integrated
circuits, graphics processing units, machine learning
processors and semiconductor cores; research, development,
and design relating to computer hardware for semiconductor
intellectual property, instruction set architectures,
microprocessors; research, development and design, all
relating to computer software used in, and for use in the
design, verification and construction of microprocessors,
processors, microcontrollers, microprocessor design files,
semiconductor intellectual property cores, computer hardware
accelerators, neural network processors and machine learning
processors.
Doorbell physical interrupt control circuitry (20) comprises interrupt detection circuitry (22) to detect an incoming interrupt to be raised as a given virtual interrupt (having a given priority) for a given virtual interrupt handling context, and doorbell physical interrupt generation circuitry (24) responsive to detection of the incoming interrupt by the interrupt detection circuitry, to determine whether the given priority of the given virtual interrupt is indicated, by doorbell-enabled-priority configuration data (28), as enabled for doorbell physical interrupt generation, and if so, to generate a doorbell physical interrupt to be processed in a given physical interrupt handling context. The doorbell physical interrupt indicates to a physical processor handling interrupts for the given physical interrupt handling context that the given virtual interrupt is pending for the given virtual interrupt handling context.
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
A reset generation manager (RGM) of a first die, of a data processing system with two or more dies, has a local state and is configured to observe a remote state of an RGM of at least one second die of the data processing system. The RGM of the first die is configured to transition the local state to a next state when the local state lags the remote state and wait for the remote state to catch up to the local state when the local state leads the remote state. A recovery action may be performed when the remote state is out of synchronization with the local state, or when the RGM of the first die remains in a non-functional state for too long. Operating states of the RGM may include a first functional state, a first resetting state, a second functional state, and a second resetting state.
An apparatus comprises training storage circuitry to store one or more training entries, each training entry associated with a target instruction and storing training data corresponding to the target instruction. Training circuitry is configured to update the training data of the one or more training entries based on monitoring sequences of instructions, and prediction circuitry is configured to make a prediction in respect of a given target instruction based on given training data corresponding to the given target instruction. Selection circuitry is configured to select which target instructions are associated with the one or more training entries of the training storage circuitry, wherein the selection circuitry is responsive to a determination that a candidate instruction is a biased instruction, to select the biased instruction with a higher priority for storage in a training entry of the training storage circuitry than at least one non-biased instruction.
A method is described for processing a neural network. The method comprises generating a Winograd neural network by applying a Winograd convolution to at least a portion of one or more layers of the neural network and quantizing at least one operation in the Winograd convolution. The Winograd neural network is trained with at least two of a weight scale matrix, a data scale matrix, and an output scale matrix as trainable parameters by comparing an output of the neural network and an output of the Winograd neural network and adjusting the trainable parameters to generate a trained Winograd neural network. The method generates data, such as trained scale matrices, to process the trained Winograd neural network on a processing unit.
An apparatus comprising processing circuitry configured to generate an instruction for configuring a hardware accelerator to perform a task. The instruction comprises a predefined set of fields comprising a control field indicative of a selected set of fields of the predefined set of fields to be provided to the hardware accelerator to configure the hardware accelerator to perform the task. The apparatus comprises accelerator control interface circuitry configured to exchange messages, each with a size less than or equal to a predefined size, with the hardware accelerator. To configure the hardware accelerator to perform the task, the accelerator control interface circuitry is configured to send the selected set of fields to the hardware accelerator, using a set of command messages with a combined size greater than the predefined size. The application further relates to a hardware accelerator.
Storage circuitry devices, systems, and methods including a bitcell array having a plurality of bitcells, each bitcell accessible via a bitline and wordline, where the bitcell array is provided at a first layer of the storage circuitry; a redundant array associated with the bitcell array, the redundant array having a plurality of redundant bitcells, each redundant bitcell accessed via a redundant bitline and redundant wordline, where the bitcell array is provided at a second layer of the storage circuitry.
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
There is provided an apparatus comprising training storage circuitry configured to store training entries, each comprising training data indicative of a trigger memory access request to local storage. The apparatus comprises filter circuitry to generate a filtered sequence of memory access requests by applying a filter to a sequence of memory access requests. The apparatus comprises training circuitry to monitor the filtered sequence, and responsive to observation of the trigger memory access request indicated in a training entry, to update the training data in the training entry. The filter circuitry is configured for each memory access request of the sequence that resulted in a hit on a data item in the local storage, to include the memory access request in the filtered sequence in dependence on a filter criterion independent of a type of request that resulted in the data item being allocated to the local storage.
The present disclosure relates generally to multi-processor arrangements and, more particularly, to dynamic frequency adjustments for multi-chiplet arrangements.
An apparatus comprises a plurality of hardware counters each corresponding to a separate sub-range of a contiguous range of target values, and histogram control circuitry to perform an indexing operation to identify and increment a selected hardware counter corresponding to a selected sub-range comprising an input value. Responsive to a histogram range update trigger, adding circuitry adds a count value of one or more first hardware counters corresponding to one or more first sub-ranges to a second hardware counter corresponding to a second sub-range neighbouring the one or more first sub-ranges, and the histogram control circuitry updates a previous indexing operation to an updated indexing operation, wherein the updated indexing operation identifies one of the one or more first hardware counters in response to an input value lying within a newly defined sub-range of the contiguous range of target values.
