One example discloses a wireless communications device, including: a controller configured to switch the wireless communications device from a first operating channel to a second operating channel according to a set of operating parameters; wherein the set of operating parameters include at least one of: a padding delay or a switching delay which defines a delay for switching to the second operating channel from the first operating channel; a transition delay or a switch back delay which defines a delay for switching back to the first operating channel from the second operating channel.
A hub device and method for transmitting signals between at least one controller and target devices on multiple bus segments through the hub device uses a plurality of drivers coupled a plurality of target ports that are configured to be operably coupled to the bus segments. An input/output driver controller is coupled to the plurality of drivers to disable the drivers during a time window to allow the target devices to drive the bus segments and to enable the drivers to drive a value on all the bus segments at an end of the time window. A frame decoder is coupled to the input/output driver controller and at least one controller port to transmit data between the at least one controller port and the target ports via input/output driver controller.
An amplifier device is presented that may include an integrated passive device (IPD). The IPD includes a substrate and a power splitter on the substrate. The power splitter includes a power splitter input terminal, a first power splitter output terminal having a first output impedance, and a second power splitter output terminal having a second output impedance that is different from the first output impedance. The power splitter is an asymmetric Wilkinson power splitter configured to receive a first signal at the power splitter input terminal, divide the first signal into a first output signal and a second output signal, output the first output signal at the first power splitter output terminal, and output the second output signal at the second power splitter output terminal.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
4.
SEMICONDUCTOR DEVICE INCLUDING A ROUTABLE HEAT SPREADER
A semiconductor device may include a circuit substrate, a processor device, and a routable heat spreader (RHS). The circuit substrate may include a build-up portion formed from multiple layers including metal layers separated by dielectric layers and including interconnections between at least some of the metal layers. The circuit substrate may include multiple contact terminals including a first contact terminal and one or more second contact terminals. The processor device may include a first side and a second side. The processor device may be coupled to the first contact terminal on the first side. The RHS may be formed from a thermally conductive and electrically conductive material and may extend over the second side of the processor device. The RHS may include one or more conductive terminals electrically isolated from a remainder of the RHS and electrically coupled to one of the one or more second contact terminals.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
One example discloses a bridge controller, including: a slope detector coupled between the first input node and the second output node; wherein the slope detector is configured to measure a rate of change of an input voltage across the first input node and the second input node; and wherein the bridge controller is configured to blank at least one of the first switch and the second switch if the measured rate of change exceeds a predetermined value.
H02M 7/5387 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur dans une configuration en pont
H02M 7/46 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge sans électrode de commande
6.
POWER MANAGEMENT SYSTEM WITH TIMING FROM AN ANALOG SOFT START CIRCUIT
Examples of an apparatus and method for power management are disclosed. In an example, a device includes a charge circuit, a discharge circuit, an undervoltage detection circuit, wherein the charge circuit and the discharge circuit are couplable to a capacitor, and wherein the charge circuit includes an analog soft start circuit, and control logic configured to determine a discharge time of the capacitor in response to a timing signal that is generated in response to a voltage from the analog soft start circuit.
G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
G05F 1/565 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
Methods and apparatus for coordinated time domain multiple access (C-TDMA) sharing of a wireless frequency resource by a first access point (AP) of a device. In a method, the first AP obtains a Transmit Opportunity (TXOP) for the frequency resource and transmits a Buffer Status Report Poll (BSRP) trigger frame addressed to at least a second AP. In this example, the BSRP trigger frame includes control information indicating a time allocation of the TXOP available for use by the second AP. In response to the BSRP trigger frame, the first AP receives a response frame (e.g., a QoS Null frame) including resource request information of the second AP with respect to the time allocation of the TXOP. The control information may include one or more of a duration of the time allocation, a reference bandwidth, or a start time of the time allocation.
A system for cloud-based emergency services in vehicles includes a vehicle. A plurality of detectors are coupled to the vehicle. Each detector is configured to generate a respective diagnostic data, wherein the detectors comprise at least an oxygen sensor in a cabin of the vehicle. A data collection system is configured to receive at least one of the diagnostic data prior to an incident, and to autonomously transmit the at least one of the diagnostic data to a cloud processor, wherein the cloud processor is configured to transmit a request based on the diagnostic data received by the cloud processor, to mitigate an effect on an occupant of the vehicle in response to the incident.
G07C 5/00 - Enregistrement ou indication du fonctionnement de véhicules
G08G 1/0968 - Systèmes impliquant la transmission d'indications de navigation au véhicule
H04W 4/44 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p. ex. communication véhicule-piétons pour la communication entre véhicules et infrastructures, p. ex. véhicule à nuage ou véhicule à domicile
H04W 4/90 - Services pour gérer les situations d’urgence ou dangereuses, p. ex. systèmes d’alerte aux séismes et aux tsunamis
9.
CONTROL DEVICE FOR A BATTERY, SYSTEM AND METHOD FOR THE CONTROL DEVICE
The present invention relates to a control device for a battery for generating a current for an electrochemical impedance spectroscopy. The device is configured to activate two different circuits of the battery via a common energy buffer, so that electrical energy is alternately exchanged between at least two parts of the battery via the energy buffer. Further, the invention relates to a system comprising the control device and the battery. Furthermore, the invention relates to a method for the control device.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
G01R 31/396 - Acquisition ou traitement de données pour le test ou la surveillance d’éléments particuliers ou de groupes particuliers d’éléments dans une batterie
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
10.
SEGMENT PARSER FOR MULTIPLE RESOURCE UNIT (MRU) OPERATIONS
Embodiments of a segment parser, a wireless transmitter, and a method for operating a segment parser are disclosed. In an embodiment, a segment parser includes a controller configured to track a data subcarrier allocation pattern of a multiple resource unit (MRU) and a rate matching buffer configured to balance data throughput based on the data subcarrier allocation pattern of the MRU.
One example discloses a method for encoding a message, comprising: receiving a set of message-data-bits; generating a set of parity-bits based on the set of message-data-bits; wherein the parity-bits are generated by multiplying the set of message-data-bits with a generator matrix derived from a corresponding parity-check matrix (PCM) of an LDPC code; wherein the LDPC code has a total codeword block length of 2×1944 bits; and generating an encoded message that includes both the set of message-data-bits and the set of parity-bits.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
12.
NANOSHEET TRANSISTORS WITH REDUCED SOURCE/DRAIN RESISTANCE AND ASSOCIATED METHOD OF MANUFACTURE
A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (12-18, 25) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source/drain regions (27, 28) and to form control terminal electrodes (36A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source/drain regions, thereby forming a nanosheet transistor device.
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
13.
SYSTEMS AND METHODS FOR HIGH ACCURACY OPEN LOOP TRANSCONDUCTANCE AMPLIFIER HAVING GAIN SET BY OUTPUT LOAD
Some examples of the disclosure are directed to systems and methods for calibrating and operating transconductance amplifiers for high-bandwidth applications configured in open loop configurations. Some examples of the disclosure are directed to setting a gain of the transconductance amplifiers based upon a value of an output load. Some examples of the disclosure are directed to using auto-zeroing circuitry and gain correction circuitry to modify a biasing of a transconductance amplifier.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
A process for making a capacitor in an interconnect layer of a semiconductor die. The process includes forming interconnect structures that include portions located in a metal layer of the interconnect layer. The interconnect structures are laterally separated by dielectric material in the metal layer. Dielectric material of the metal layer is selectively removed to form an opening where a capacitor dielectric layer and then a conductive material are formed in the opening. The wafer is planarized to form a remaining structure in the metal layer. One electrode of the capacitor includes the remaining structure, and a second electrode of the capacitor includes the interconnect structure. A portion of the capacitor dielectric layer serves as a capacitor dielectric for the capacitor.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
15.
METHOD AND APPARATUS FOR ENCODING AND MULTIPLEXING A STREAM IN A SERIAL CHANNEL
A state transition for a stream and a timing of when the state transition is detected with respect to a duration of a frame which is to be transmitted over the serial channel. The state transition and timing of the state transition is coded into a codeword which is inserted into a portion of a frame which is transmitted over the serial channel to transmit the stream over the serial channel.
A hardware- and software-aware metagraph is deployed in conjunction with a corresponding artificial intelligence/machine learning (AIML) model onto heterogeneous and mixed-precision devices to enable flexible generic runtime with minimum control overhead for synchronization, automatic insertion of data transfers and conversions, reuse of graphs from application to application for different hardware and software configurations, and enablement of single, batch, and pipeline execution. The metagraph is independent of the existing AIML training/inference frameworks and can extend to broader scope of general heterogenous computation, also can be used by offline/runtime to enable solutions from heterogenous deployment to optimal execution scheduling and network structure fine tuning.
The disclosure relates to an AC battery system, methods for operating such as system and a controller for an AC battery system. Example embodiments include a battery system comprising: a plurality of series-connected battery modules, each comprising a plurality of series-connected cells, a first switch connected in series with the plurality of cells and a second switch connected in parallel with the plurality of cells; an H-bridge circuit connected across the plurality of battery modules and having first and second output terminals; and a controller configured to control switching of the H-bridge circuit and the first and second switches in each battery module to transfer electrical power between the first and second output terminals and the plurality of battery modules.
H01M 50/519 - Interconnecteurs pour connecter les bornes des batteries adjacentesInterconnecteurs pour connecter les cellules en dehors d'un boîtier de batterie comprenant des circuits imprimés
A driver circuit for controlling a high-power switch. The driver circuit comprises a flyback converter and a driving stage. The flyback converter includes a controller that configured to: receive a PWM control signal, which is for controlling the high-power switch; receive a feedback voltage signal, representative of a measured voltage of a positive output rail or the negative output rail of the flyback converter; and provide a primary-side switch control signal that comprises a bursts of pulses for operating the primary switch, wherein the controller is configured to start a burst of pulses in response to an edge of the PWM control signal, and stop the burst of pulses in response to the feedback voltage crossing a threshold. The driving stage is connected between the positive output rail and the negative output rail. The driving circuit is configured to provide a high-power switch control signal for controlling the state of the high-power switch based on the PWM control signal.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/00 - Détails d'appareils pour transformation
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
19.
THROUGH SUBSTRATE VIA (TSV) VALIDATION STRUCTURE FOR AN INTEGRATED CIRCUIT AND METHOD TO FORM THE TSV VALIDATION STRUCTURE
An integrated circuit comprises a substrate that includes a first surface and a second surface. A first through substrate via (TSV) is formed between the first surface and the second surface and a first conductive material is arranged within the first TSV to form a conductive path between the first surface and the second surface through the substrate. A second TSV is formed between the first surface and the second surface and a second conductive material arranged within the second TSV to form a conductive path between the first surface and the second surface through the substrate. In examples the first TSV has a larger cross-sectional area than the second TSV, the cross-section of the first TSV and second TSV being in a plane parallel to the first surface or the second surface.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
G01R 27/02 - Mesure de résistances, de réactances, d'impédances réelles ou complexes, ou autres caractéristiques bipolaires qui en dérivent, p. ex. constante de temps
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
20.
RTS-CTS PROCEDURE FOR EXTENDED RANGE PACKET TRANSMISSION
Methods and apparatus for wireless channel reservation using extended range Request to Send (RTS)/Clear to Send (CTS) procedures to minimize collisions with OBSS devices. In a method, a first wireless device transmits an extended range RTS frame and receives, in response, a non-extended range CTS frame from a second wireless device. The first wireless device then transmits an extended range physical layer protocol data unit (PPDU) for reception by the second wireless device. This method may further include fragmenting the extended range PPDU into a plurality of extended range fragments, transmitting a first extended range fragment, receiving a non-extended range acknowledgement (ACK) from the second wireless device, and transmitting a second extended range fragment.
H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
An electronic device may include semiconductor wafer including a semiconductor substrate and multiple layers on the semiconductor substrate. The multiple layers may include metal layers and dielectric layers forming a circuit and an on-chip pad configured to receive a signal. The device may include a ring-based matching network and a wire trace. The network may include one or more rings arranged within the multiple layers and extending around the on-chip pad to provide a selected impedance compensation to the received signal to produce a compensated signal. Each ring may have a selected width and a selected spacing relative to one or more of the on-chip pad or another ring. The wire trace may be configured to couple the on-chip pad to the circuit to provide the compensated signal. In some embodiments, one of the rings may be connected to or may be capacitively coupled to the on-chip pad.
An electronic device includes a device substrate with a mounting surface, an electronic circuit coupled to the mounting surface, and encapsulant material over the electronic circuit and the mounting surface. The encapsulant material has an upper encapsulant surface and a plurality of encapsulant sidewalls extending between the mounting surface of the device substrate and the upper encapsulant surface. The electronic device also includes a sidewall antenna coupled to one of the encapsulant sidewalls, and a shield structure embedded within the encapsulant material between the sidewall antenna and the electronic circuit. The sidewall antenna is electrically coupled to the electronic circuit through the device substrate. The shield structure extends from the mounting surface of the device substrate toward the upper surface of the encapsulant material. The sidewall antenna may be selected from an end-fire type of antenna and a broadside-fire type of antenna.
A transceiver circuit for transmitting and receiving pulse amplitude modulation, PAM, network signals within a network, wherein the PAM network signals can take a value according to a PAM modulation level of any of two-level modulation, three-level modulation or four-level modulation. The transceiver circuit comprises: a receiver-input-terminal for receiving a network signal, an interference cancellation block and an adaptive filtering circuit. The adaptive filtering circuit comprises: a filter-input-terminal; a filter-output-terminal; and a plurality of tap weighting blocks. Each tap weighting block comprises: a tap-input-terminal, a coefficient-input-terminal and a multiplexer. The adaptive filtering circuit also comprises one or more tap summation blocks configured to combine the output of each tap weighting block to provide an interference-error signal to the filter-output-terminal. The interference cancellation block subtracts the interference-error signal from the network signal to provide the processed-network-signal.
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a gate electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
25.
SEMICONDUCTOR DEVICE WITH EMBEDDED BATTERY AND METHOD THEREFOR
A method of manufacturing a packaged semiconductor device is provided. The method includes affixing a sensor system to a die pad portion of a leadframe. A battery is affixed to the lead frame including a first terminal of the battery affixed to a first leg of the leadframe and a second terminal of the battery affixed to a second leg of the leadframe. An encapsulant encapsulates the sensor system, battery, and leadframe.
A dynamic random access memory (DRAM) array has a first portion configured as a data array and a second portion configured as a reference array. The DRAM array includes read bit lines which include a first plurality of read bit lines in the data array and a second plurality of read bit lines in the reference array. Read circuitry includes a plurality of sensing circuits, each sensing circuit coupled to a corresponding read bit line of the first plurality of read bit lines and configured to receive a first reference voltage generated by a first read bit line of the second plurality of read bit lines and a second reference voltage generated by a second read bit line of the second plurality of bit lines. The plurality of sensing circuits is configured to provide a corresponding bit of an output read value.
A transceiver circuit comprising: a transceiver clock input terminal to receive a transceiver clock signal defining a network frequency; a clock provision circuit to provide a coefficient clock signal, defining a coefficient frequency, and a coefficient adaption unit for providing a coefficient signal that represents one or more coefficient values. The coefficient adaption unit updates the one or more coefficient values at the coefficient frequency. The transceiver circuit also includes an adaptive filtering circuit that receives the coefficient signals at the network frequency, a filter input terminal to sequentially receive a stream of interference-symbols, and a filter output terminal to provide an interference-error signal to be removed from a network signal. The adaptive filtering circuit applies scaling factors to the coefficient signal to create scaled coefficient signals and uses the received interference-symbol to select one of the scaled coefficient signals to provide the interference-error signal.
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
28.
TRANSISTORS WITH SELF-ALIGNED SOURCE-CONNECTED FIELD PLATES
Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers. Relative positioning of the control electrode and the field plate are determined by a single processing step such that the field plate is self-aligned to the control electrode in order to reduce variations in transistor performance associated with manufacturing process variations.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
A connector body such as a coaxial electrical connectors or fiber optic connector can be mounted above a device die that is encapsulated with molding material forming part of a molded device package by bonding the connector body to a redistribution structure formed on the device die. After the device die is molded, a lower portion of the connector body is surrounded by the molding material and an upper portion of the connector body is exposed at an exterior surface of the package. The redistribution structure can be configured to couple connector body to the device while preventing unwanted mechanical stress on the connector body and the device die.
H01R 24/38 - Dispositifs de couplage en deux pièces, ou l'une des pièces qui coopèrent dans ces dispositifs, caractérisés par leur structure générale ayant des contacts disposés concentriquement ou coaxialement
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01R 43/20 - Appareils ou procédés spécialement adaptés à la fabrication, l'assemblage, l'entretien ou la réparation de connecteurs de lignes ou de collecteurs de courant ou pour relier les conducteurs électriques pour assembler les pièces de contact avec le socle isolant, le boîtier ou le manchon ou pour les en désassembler
Seamless roaming in seamless mobile domain (SMD) of a wireless network includes receiving from an access point multi-link device (AP MLD) in the wireless network information of one or more candidate target AP MLDs to seamlessly roam to, the information including a seamless roaming domain element that identifies the seamless roaming domain of the one or more candidate target AP MLDs; selecting a target AP MLD from the one or more candidate AP MLDs based on the information; and roaming to the target AP MLD.
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless device includes a controller configured to generate an announcement regarding whether the wireless device is capable of initiating a peer device's switch from a low-capability state of a low-capability mode to a high-capability state of the low-capability mode and a wireless transceiver configured to transmit the announcement to a second wireless device.
H04W 8/22 - Traitement ou transfert des données du terminal, p. ex. statut ou capacités physiques
H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
One example discloses a first wireless communication device, including: a transceiver configured to be coupled to an antenna; a controller coupled to the transceiver; wherein the controller is configured to calculate a range to a second wireless communication device based on a set of exchanged messages; wherein the controller is configured to calculate the range while limiting at least one of: a set of allowed message repetitions and a set of allowed LTF (long training frame) totals, for channel bandwidths (BW) greater than 160 MHz.
An artificial intelligence-based optimization method, system, and apparatus are provided for solving non-convex, high dimension optimization problems and tuning complex, multi-parameter systems by converting the default Cartesian search space into a simplex search space to improve search efficiency, evaluating search sampling points for making next-search point decisions by applying a surrogate gradient boost tree function which learns from objective-function query results from historical search samples, and then applying a next search-point determining strategy.
A checker pipeline for checking integrity of an instruction decoder of a primary processor pipeline of a processing system including an instruction fetch checker and an instruction decoder checker. The processor pipeline includes an instruction fetch stage that receives an instruction with fields and the instruction decoder stage that decodes the instruction into instruction field values. The instruction fetch checker receives and converts instruction correction information provided with the instruction into instruction byte parity information. The instruction decoder checker includes a parity converter that converts the instruction byte parity information and instruction field information into predicted field parity information used to check the integrity of the instruction decoder. The instruction correction information is ECC bits or the like which are converted into instruction byte parity bits. The parity converter combines instruction byte parity bits with corresponding instruction bits using a logic operation into the predicted field parity information.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
An electronic package with a battery and method for producing the electronic package uses a domed lid that is attached to a substrate with an electronic component, such as a die. The battery is attached to an inner surface of the domed lid and electrically connected to the electronic component via the domed lid.
H01L 23/043 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base conductrice qui sert de support et en même temps de connexion électrique pour le corps semi-conducteur
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/10 - ConteneursScellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p. ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
36.
ELECTROMAGNETIC SHILEDING FOR LEADLESS SEMICONDUCTOR PACKAGE
Structures and methods for electromagnetic shielding of leadless semiconductor packages provide complete module-level electromagnetic shielding by combining plated shielding with proposed modified ground lead arrangement and ground pad grounding. A package including a leadframe, ground leads, and signal leads is stamped to form a “bump” in the ground leads around the perimeter of the package. After overmolding, the package is cut to expose the bumps; then, a full shielding enclosure is formed over the top of the package into contact with the exposed ground leads. Components of the leadframe that extend to the perimeter of the device, such as corner bars connecting to the center flag, can also be stamped and brought into contact with the shield. The ground leads may further be connected to a center flag of the leadframe for full-enclosure shielding. The signal leads remain electrically isolated from the leadframe and the shielding enclosure.
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
Structures and methods for full-enclosure electromagnetic shielding of leadless semiconductor packages provide complete module-level electromagnetic shielding by combining plated shielding with proposed modified leadframe peripheral structure and ground pad grounding. A first cut into an overmolded leadless module exposes the peripheral ring of the leadframe; then, with controlled metal plating a full shielding enclosure is formed over the top of the package into contact with the exposed peripheral ring. The proposed approach provides complete electromagnetic shielding for the module with significantly improved electromagnetic shielding performance. The full enclosure shielding solution is especially important for high frequency and high-speed application and sensing products with high sensitivity to electromagnetic interference.
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
Disclosed is a packaged semiconductor device, comprising: a semiconductor die, having an array of contact pads, in a central region of a first major surface thereof and for contacting to an array of solder balls; encapsulant, partially encapsulating the semiconductor die and having an aperture in a first major surface thereof exposing the array of contact pads; and a plurality of leads extending from side faces of the encapsulant and extending beyond the first major surface of the encapsulant. Corresponding methods are also disclosed.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
39.
MULTIPLE-PATH POWER AMPLIFIER WITH CAPACITOR FOR COMPENSATING FOR A COUPLING BETWEEN AMPLIFIER PATHS
Aspects of this disclosure are directed to various circuit topologies for mitigating coupling. In some embodiments, an amplifier circuit is provided that includes a first amplifier path, a second amplifier path, and a capacitor. The first amplifier path may include a first input, a first transistor, and a first wire coupled between the first input and a first terminal of the first transistor. The second amplifier path may include a second input, a second transistor, and a second wire coupled between the second input and a first terminal of the second transistor. The capacitor may include a first terminal coupled to the first input and a second terminal coupled to the second input. Under such an arrangement, the capacitor may be configured to compensate for a coupling between the first wire and the second wire. Other embodiments are disclosed.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
A wireless communication system, apparatus, and methodology are described for encoding Low-Density Parity Check (LDPC) PPDUs by selecting a first LDPC codeword length of N×1944 bits from an encoding parameter table having a plurality of LDPC codeword lengths based on comparing the number of available bits (Navbits) to one or more Navbits threshold values and/or one or more selection conditions for choosing the first LDPC codeword length of N×1944 bits, where N is an integer that is greater than or equal to 2.
H03M 13/25 - Détection d'erreurs ou correction d'erreurs transmises par codage spatial du signal, c.-à-d. en ajoutant une redondance dans la constellation du signal, p. ex. modulation codée en treillis [TMC]
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
41.
SIGNALING OF MODULATION AND/OR CODING IN A WIRELESS COMMUNICATIONS SYSTEM
Embodiments of a wireless device and method are disclosed. In an embodiment, a wireless device comprises a wireless transceiver to receive and transmit frames, and a controller operably coupled to the wireless transceiver to process the frames, wherein the controller is configured to generate a frame that includes an indication selected from a first indication of an unequal modulation and/or coding and a second indication of equal modulation and/or coding.
A current measurement system and a corresponding method are described, where the current measurement system includes a resistor structure having a sense resistor and a calibration resistor where a single metal layer of the resistor structure includes the sense resistor and the calibration resistor, calibration circuitry configured to provide a calibration current through the calibration resistor, and sense amplifiers configured to measure respective voltages across each of the calibration resistor and the sense resistor.
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
Electronic device packages that allow batteries to be incorporated in the package directly above or below semiconductor die or other devices can enable reduced package footprints while also protecting batteries against exposure to undesirable high temperatures during assembly of the package and protecting molded portions of the package from stresses that may arise from swelling of the battery over its useful lifetime. One terminal of the battery is bonded a conductive lead integrated within a molded cover by an electrically conductive bond. Bonding the cover to a circuit board or other substrate also electrically couples to battery terminal to a contact on the substrate. The other terminal of the batter can be bonded to another contact on the substrate using a suitable conductive bond such as one formed by an electrically conductive adhesive.
Improved transistor performance for RF switching and amplification can be achieved by providing a transistor such as a electron mobility transistor with one or more field plate electrodes coupled to the channel of the transistor that can be biased independently of the gate electrode and the current terminals of the transistor. For example, when the field plate electrode(s) are biased to at least partially deplete the channel near the field plate electrode(s), the breakdown voltage characteristics of the transistor can be improved. In RF applications, circuitry that biases the field plate electrodes can be powered by RF signals already present in the circuitry in which the transistor is incorporated, removing the need to provide a separate bias voltage source for the field plate electrode(s).
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H03F 3/213 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
45.
LOW FREQUENCY PERIODIC SIGNALING (LFPS) AND LOSS OF SIGNAL (LOS) DETECTION
Embodiments of devices for signal detection, communications devices, and methods for signal detection are disclosed. In an embodiment, a device for signal detection includes a low-pass filter (LPF) coupled to a communications channel and configured to generate a filtered input, a rectifier coupled to the LPF and configured to generate a rectified signal based on the filtered input, and a comparator configured to generate an output based on the rectified signal. Programmable bandwidth and speed provide a wideband signal detector.
A display controller includes a first manager unit and a second manager unit. The first manager unit receives first display data from a first data source by way of a service manager unit, and produces first composed data using the first display data. The second manager unit receives second display data directly from a second data source, and produces second composed data using the second display data. The display controller provides the first composed data and the second composed data to a graphic processing unit to perform rendering process using the first composed data and the second composed data, and to produce rendered display data to be provided to a display apparatus.
A packaged semiconductor device includes a substrate, an interface for signal communication with an external power splitter, and a first and second stages of a multiple-stage amplifier. The interface includes first, second, and third leads coupled to the substrate. The first amplifier stage includes a first amplifier die with a first input, a first output, and a first power transistor that functions as a driver amplifier. The second amplifier stage includes first and second amplifier paths. The first amplifier path has a second amplifier die with a second input, a second output, and a second transistor that functions as a first final stage amplifier. The second amplifier path has a third amplifier die with a third input, a third output, and a third transistor that functions as a second final stage amplifier. The first output, second input, and third input are coupled to the first, second, and third leads, respectively.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
48.
METHODS FOR BATTERY CONNECTION IN MICROELECTRONIC PACKAGES
A self-powered microelectronic semiconductor device includes low temperature interconnection and encapsulation materials to enable integration of a battery with the microelectronics package during manufacture. The package includes a partially exposed leadframe or leads of a substrate for connecting the battery. The battery includes one or more terminal connectors that can either be manufactured by the battery vendor or externally attached using spot/laser or resistance welding. The steps of connecting the battery to the package are performed after the microelectronic package assembly to ensure the battery does not experience any high temperatures from the package assembly process. Cavities are formed in an overmolded molding compound to expose the leadframe or battery pads for electronic connection. A low temperature electrically conductive bonding agent is used to create the electrical and mechanical bond of the battery tabs to the leadframe. A low temperature encapsulant is then applied over the package and mounted battery.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
49.
FAULT DETECTION SYSTEM AND METHOD FOR SWITCHED CAPACITOR CONVERTER
System and methods of fault detection for switched capacitor converters are provided. A system includes a switched capacitor converter and fault detection circuitry. The switched capacitor converter is configured to perform direct current (DC)-to-DC conversion at a predefined conversion ratio and includes a first power stage having first switches and includes first capacitors having first terminals and second terminals. The fault detection circuitry is coupled to second terminals of the first capacitors and is configured to monitor second terminal voltages of the first capacitors and to assert at least one fault signal in response to determining that any of the second terminal voltages indicates a fault during a startup sequence of the switched capacitor converter.
H02H 7/12 - Circuits de protection de sécurité spécialement adaptés aux machines ou aux appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou de ligne, et effectuant une commutation automatique dans le cas d'un changement indésirable des conditions normales de travail pour convertisseursCircuits de protection de sécurité spécialement adaptés aux machines ou aux appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou de ligne, et effectuant une commutation automatique dans le cas d'un changement indésirable des conditions normales de travail pour redresseurs pour convertisseurs ou redresseurs statiques
G01R 31/3835 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge ne faisant intervenir que des mesures de tension
H02H 1/00 - Détails de circuits de protection de sécurité
50.
SELF-CALIBRATING SLOPE COMPENSATION IN MULTI-PHASE DC-DC CONVERTERS
Self-calibrating slope compensation in multi-phase DC-DC converters is discussed. In some embodiments, a slope compensation circuit comprises a reference generator configured to output a reference ramp and a bias signal, where the bias signal is usable by each of a plurality of ramp generators to provide a replica ramp to a power block of a multi-phase DC-DC converter; and control loop logic coupled to the reference generator and configured to produce a feedback signal based upon the reference ramp, where the reference generator is configured to modify a current of the bias signal based upon the feedback signal.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
H02M 1/00 - Détails d'appareils pour transformation
51.
DEVICE WITH ELECTRICAL COMPONENT FORMED OVER A CAVITY AND METHOD THEREFOR
A semiconductor device and method of manufacture is presented. A silicon-on-insulator (SOI) substrate includes a layer of gallium nitride on a first surface of the SOI substrate. A device is formed over the first surface of the substrate and a first conductive feature is formed over the first surface of the substrate and electrically coupling the first conductive feature to the device. A first cavity is formed in a second surface of the SOI substrate directly below the first conductive feature, wherein the first cavity includes first upper cavity surface defined by a surface of a layer of silicon dioxide in the SOI substrate.
LE CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (France)
L'UNIVERSITE PAUL SABATIER (TOULOUSE III) (France)
L'INSTITUT NATIONAL POLYTECHNIQUE DE TOULOUSE (France)
Inventeur(s)
Guendouz, Badr
Abouda, Pascal Kamel
Tico, Olivier
Abrégé
A switching circuit for cell balancing in a battery management system, BMS. The switching circuit comprises: a first battery connection terminal, for connecting to a first battery terminal; a second battery connection terminal, for connecting to a second battery terminal; and a cell balancing field effect transistor, FET. The cell balancing FET comprises: a gate terminal; a drain terminal connected to the first battery connection terminal; a source terminal connected to the second battery connection terminal; and a body terminal. The switching circuit also comprises a FET control circuit that is configured to connect the gate terminal and the body terminal of the cell balancing FET to the battery connection terminal that has the lowest voltage.
An electronic device includes a routing structure, an electronic circuit, an antenna, and an RF reflector. The electronic circuit is coupled to a mounting surface of the routing structure above a circuit zone. The antenna is coupled to the routing structure in an antenna zone. The RF reflector is coupled to the mounting surface above a reflector zone. The RF reflector includes an inner boundary portion that is adjacent to the antenna zone, and a circuit-adjacent segment positioned between the inner boundary portion and the electronic circuit. At least part of an upper extent of the inner boundary portion is at a first height above the mounting surface. An upper extent of the circuit-adjacent segment is at a second height above the mounting surface that is greater than the first height. The routing structure may be a printed circuit board or a redistribution layer structure.
H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01Q 19/10 - Combinaisons d'éléments actifs primaires d'antennes avec des dispositifs secondaires, p. ex. avec des dispositifs quasi optiques, pour donner à une antenne une caractéristique directionnelle désirée utilisant des surfaces réfléchissantes
54.
SYSTEM AND METHOD FOR DETERMINING ELECTRONIC DEVICE THERMAL RESISTANCE CHARACTERISTICS
A system and method for determining a thermal characteristic of an electronic device is presented. A controller is configured to cause a voltage source to forward-bias a transistor. A thermal slope of the control terminal of the transistor is determined. A first voltage V1 of the control terminal of the transistor is measured and a voltage pulse is applied across the first current carrying terminal and the second current carrying terminal of the transistor. A second voltage V2 of the control terminal of the transistor is measured and a magnitude of a current ID flowing into the first current carrying terminal of the transistor is measured. The thermal resistance characteristic of the electronic device is determined using the first voltage, the second voltage, and the magnitude of the current.
A voltage regulation circuit and method of operation are described, where the voltage regulation circuit includes an error amplifier configured to provide an error signal based on a comparison of a reference voltage and a voltage at a first voltage divider coupled to an output node of the voltage regulation circuit, a pass transistor configured to selectively pass current from an input node to the output node based, at least in part, on the error signal, current limiter circuitry including a current limiting transistor that is configured to limit electrical current through the pass transistor, and logic circuitry configured to configure the current limiting transistor as a diode-connected transistor in a first state and configure the current limiting transistor as part of a current control loop in a second state.
G05F 1/573 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance à des fins de protection avec détecteur de surintensité
A switching circuit for cell-balancing in a battery management system, BMS. The switching circuit comprises: a first battery connection terminal, for connecting to a first battery terminal; a second battery connection terminal, for connecting to a second battery terminal; and a cell balancing field effect transistor, FET. The cell balancing FET comprises: a gate terminal; a drain terminal connected to the first battery connection terminal; a source terminal for connected to the second battery connection terminal; and a body terminal. The switching circuit further comprises: a gate control circuit that is configured to connect the gate terminal of the cell balancing FET to the battery connection terminal that has the lowest voltage; and a bias resistor that is connected in series between the body terminal of the cell balancing FET and one of the first and second battery connection terminals.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
Embodiments of a method and apparatus for communications are disclosed. In an embodiment, a wireless device includes a controller configured to generate a first protected control frame using an encryption key and a wireless transceiver configured to transmit the first protected control frame to a second wireless device.
A semiconductor device includes a silicon (Si) base substrate having a first crystal orientation, a first device region formed over the Si base substrate, wherein the first device region includes a gallium nitride (GaN) layer formed over the Si base substrate and a transition layer having a second crystal orientation disposed between the GaN layer and the Si base substrate. First and second current-carrying electrodes are formed over the GaN layer in a first active area with a first control electrode between the first and second current-carrying electrodes. A second device region is formed laterally adjacent the first device region, wherein the second device region includes a second Si layer formed over the Si base substrate. Third and fourth current-carrying electrodes are formed over the second Si layer in a second active area with a second control electrode formed between the third and fourth current-carrying electrodes.
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
59.
METHOD AND SYSTEM TO IDENTIFY AND RECOVER FROM FAULTS IN NON-SAFETY TARGETS AND SAFETY TARGETS
A method and system to increase system availability during a fault of a non-safety target is disclosed. A fault signal is received indicative of a response to a request from an initiator not being received from one of a safety target and non-safety target within a response time. Based on the response not being received from the non-safety target, only the non-safety target is reset to increase the system availability rather than also resetting safety targets. Because a target did not respond to the request, a dummy responder further sends to the initiator a response to the request to prevent the initiator from entering into a hang state.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
A voltage regulator is described that includes an error amplifier configured to provide an error signal based on a comparison of a reference voltage and a voltage at a voltage divider coupled to an output node of the voltage regulation circuit, a pass transistor configured to selectively pass current from an input node to the output node based on the error signal, and switching circuitry configured to selectively couple one of a first voltage supply input and a second voltage supply input to the input node. The switching circuitry includes a first leg that includes a first switch and a transistor that is coupled in a cascode arrangement with the pass transistor and a second leg that includes a second switch.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
G05F 1/569 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance à des fins de protection
The disclosure relates to self-calibration of non-linearity in a digital to analog converter (DAC). Example embodiments include a method for calibrating non-linearity of a segmented non-binary DAC in a self-calibrating DAC system, the method comprising: providing first calibration input digital signals to a thermometric weighted segment and measuring first outputs of the DAC with an ADC; providing second calibration input digital signals to the thermometric weighted segment and measuring second outputs of the DAC with the ADC; calculating a first scaling factor for first switches and resistive elements by dividing each of the second outputs of the DAC by a difference between adjacent ones of the first outputs of the DAC; calculating a second scaling factor for second switches from a sum of the first outputs of the DAC divided by a measured output range of the DAC; and storing the first and second scaling factors in a memory module.
Various embodiments relate to a system and method for joint sounding by a client with a master access point (AP) and a slave (AP), including: receiving a message from the master AP; applying network allocation vector (NAV) rules to update a NAV values, wherein the received message is treated as an intra-basic service set (BSS) message when the transmit address (TA) of the received message has a prespecified value; receiving a first trigger frame; and transmitting a first channel state information (CSI) to the master AP when the channel is idle based upon the updated NAV value in response to the trigger frame.
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
A method of assigning a respective controller area network (CAN) ID to each of a plurality of devices, wherein the each of the plurality of devices is coupled with a CAN bus and comprises at least one input and at least one output by which the plurality of devices are connected, in a chain, to a controller of the CAN bus having at least one output, the method comprising: resetting the CAN ID of the each of the plurality of devices to a same initial value; using the at least one output of the controller to set the at least one input of a first device of the plurality of devices to a first value; using the first value to set the CAN ID of the first device; using the at least one output of the first device to set the at least one input of a second device of the plurality of devices to a second value, wherein the second device is connected to the first device; and using the second value to set the CAN ID of the second device. A system of assigning a respective CAN ID to each of a plurality of devices is also presented.
Embodiments of a method and apparatus for communications are disclosed. In an embodiment, a wireless device includes a controller configured to determine an arrangement of control information and a wireless transceiver configured to announce the arrangement of the control information in a first frame exchange with a second wireless device in a transmit opportunity (TXOP) and to conduct subsequent frame exchanges with the second wireless device based on the arrangement of the control information.
H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
H04W 28/02 - Gestion du trafic, p. ex. régulation de flux ou d'encombrement
An integrated circuit die is provided that includes a substrate, a semiconductor device formed on the substrate, and a passivation layer formed over the substrate. The passivation layer has chamfered corners disposed in corner regions of the integrated circuit die. The chamfered corners of the passivation layer are dimensioned to mitigate damage to the passivation layer in the corner regions during die singulation.
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
H01L 21/8252 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie III-V
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
66.
ADAPTIVE TRANSITION TIME MEASUREMENT IN AN ASYMMETRICAL HALF BRIDGE
An adaptive transition controller for a resonant converter system, including: a derivative circuit configured to receive a first signal indicative of a resonant current through an inductor in the resonant converter system and produce a derivative signal indicative of a derivative of the first signal; a peak detector circuit configured to produce a peak signal indicative of a peak value of the derivative signal over a time period; an integrator circuit configured to integrate the peak signal to produce an extension signal; and a comparator circuit configured to produce an end transition signal when the extension signal exceeds a second signal indicative of the magnetizing current in a magnetizing inductance of a transformer in the resonant converter system.
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
G01R 19/04 - Mesure des valeurs de pointe d'un courant alternatif ou des impulsions
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
67.
Refresh operations in embedded dynamic random access memories (DRAMs)
A data processing system includes a dynamic random access memory (DRAM), a prefetcher, and a refresh controller. The DRAM includes a plurality of DRAM cells, each with a capacitive storage element. The prefetcher is configured to prefetch information from the DRAM into a prefetch buffer in accordance with a prefetch pattern of addresses in the DRAM. The refresh controller includes a dynamic refresh control circuit configured to detect prefetch patterns of the prefetcher, and, in response to a detected prefetch pattern, refresh locations of the DRAM in accordance with a refresh pattern of addresses which is based on the prefetch pattern of addresses.
G11C 11/40 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
A Controller Area Network (CAN) module includes a first transmit data (TXD) interface, a first receive data (RXD) interface, a CAN controller, a wake-up unit, and a bypass unit. The CAN controller is coupled to the first TXD and RXD interfaces. The bypass unit is coupled to the first TXD interface. The CAN controller is configured only in an operation state to send a CAN frame to a CAN transceiver via the first TXD interface. The wake-up unit is configured to control the CAN controller such that the CAN controller changes from a sleep state to the operation state. The bypass unit is configured to send a predefined bit pattern, referred to as a wake-up pattern, to the CAN transceiver via the first TXD interface. The wake-up unit is configured to control the bypass unit so that the bypass unit sends the wake-up pattern via the first TXD interface.
An electronic package with a battery and method for producing the electronic package uses a bent leadframe having flanged ends that are physically and electrically connected to a substrate so that the battery is encircled by the bent leadframe and the substrate, and the substrate is positioned between the battery and an electronic component. A first terminal of the battery is physically and electrically connected to the substrate and a second terminal of the battery is physically and electrically connected to the bent leadframe, which provides an electrical connection between the battery and the electronic component.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
A delay locked loop circuit comprising: a voltage-controlled delay line (VCDL); a phase detector circuit that is configured to process a first and a last output signal of the VCDL in order to provide: i) an up-pulse signal; and ii) a down-phase signal; a charge pump that is configured to provide a feedback voltage signal based on the up-pulse signal and the down-pulse signal; a phase signal processor that is configured to process the up-pulse signal and the down-pulse signal in order to provide a delay code locking signal, which is representative of whether or not the first output signal is 2Π radians out of phase with the last output signal; a delay code setter that is configured to provide a delay code setting signal that represents one of a sequence of different candidate delay codes. When the delay locked loop circuit is in a calibration mode of operation: a fixed voltage source provides a fixed voltage signal as a control-voltage signal for the voltage-controlled delay line; while the delay code locking signal represents the first output signal not being 2Π radians out of phase with the last output signal: the delay code setter applies the delay code setting signal to the VCDL such that it sequentially applies different candidate delay codes to the voltage-controlled delay line until a selected-delay-code is assigned; and when the delay locked loop circuit is in the active mode of operation: a charge pump provides a feedback voltage signal as the control-voltage signal for the voltage-controlled delay line; and the VCDL uses the selected-delay-code as the delay code.
H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
A trusted execution environment (TEE) includes a first requestor, a first local interconnect, an access controller, and a first memory encryption circuit, and the access controller allows or denies access requests to a shared memory external to the TEE. A normal execution environment (NEE) communicates with the TEE via a set of address lines and a set of data lines, and includes a second requestor and a second local interconnect. The first memory encryption circuit encrypts write data corresponding to allowed access requests to the shared memory generated by only one of the first requestor and the second requestor prior to the TEE providing the write data for storage into the shared memory. Any write data corresponding to allowed access requests to the shared memory generated by another one of the first requestor and the second requestor is provided as unencrypted write data for storage into the shared memory.
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
Electronic device packages that include a cavity which can be gas-filled, evacuated, or filled by another material can be formed by stacking multiple circuit substrates (“carriers”) which are joined to together by interposers disposed between pairs of circuit substrates such that one or more cavities are formed between adjacent carriers. The interposers can include interconnections which can electrically couple devices or other structures on or within a first carrier to devices or structures on or within another carrier, including contacts formed on an exterior surface of a package.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
Molded device packages which allow electrical contacts to coupled to a first surface of a circuit substrate such as a printed circuit board while allowing the opposite surface to remain exposed for other purposes such as bonding thermal structures such as heatsinks include electrically-conductive pillars which are bonded to the first surface of the substrate and encapsulated in molding material. The molding material can one or more cavities over disposed over the first surface of the substrate which can be evacuated or gas-filled. The electrically-conductive pillars protrude from connected manifold and are joined to each other by a frame portion of the manifold. The manifold is patterned with a masking material that protects the pillars from being etched during a selective etching process which removes the frame portion of the manifold to separate the electrically-conductive pillars from each other.
A controller for a resonant converter. The resonant converter comprising: a first switch and a second switch connected in series with each other between the supply source and a reference terminal; and a resonant tank that is electrically connected to the first and second switches, wherein the resonant tank comprises a resonant capacitor. The controller is configured to: receive a measured voltage signal that represents the voltage at a predetermined point in the resonant tank; determine voltage-correction-signalling based on a measured current signal, which represents the current flowing in the resonant tank; and in response to the measured voltage signal crossing a voltage threshold value, after the application of the voltage-correction-signalling to either the measured voltage signal or the voltage threshold value as an offset, change the state of the first switch and the second switch.
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
75.
PITCH-REDUCING SOLDER INTERCONNECT FOR RF TRANSITIONS
A radio frequency (RF) transition mechanism between an integrated circuit (IC) package and an interposer circuit board includes elongated structures to reduce a distance between conductors. Pairs of electrical interconnect pads on the IC package and/or pairs of electrical interconnect pads on the interposer circuit board are elongated on a common axis. The reduced distance between conductors reduces insertion loss at frequencies of interest.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
76.
PANEL LEVEL FABRICATION OF STACKED ELECTRONIC DEVICE PACKAGES WITH ENCLOSED CAVITIES
Electronic device packages that include one or more circuit substrates, one or more cavities defined by a cover separated from a circuit substrate by an interposer substrate with an aperture disposed above the circuit substrate can be formed by panel-level fabrication processes in which multiple assemblies are formed by singulating a larger panel assembly formed by multiples panels bonded to each other. A panel that includes multiple levels is partially diced to form channels which are filled with molding material. The subsequent structure is diced again to singulate individual stacked packages that include a portion of the molding material surrounding one or more interposers. The molding material can seal gaps between an interposer and a circuit substrate to which it is bonded, as well as providing electrical isolation between electrical interconnects that would otherwise be exposed at edges of each package.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A power management integrated circuit (PMIC) and method of operating a PMIC is described. The PMIC is configured to be coupled to a system on chip (SoC) including a number of power and clock domains. Each of the PMIC and the SoC have a shared key. The PMIC is configured to generate a challenge, output the challenge to the SoC and generate an expected-challenge-response determined from the challenge and the shared key. The PMIC is further configured to receive a challenge-response from the SoC and compare the challenge response with the expected-challenge-response. If the challenge response is different to the expected response, the PMIC may (i) apply a reset to the SoC, (ii) supply power to a subset of the SoC power domains and/or (iii) enable clocks of a subset of SoC clock domains.
H03K 3/01 - Circuits pour produire des impulsions électriquesCircuits monostables, bistables ou multistables Détails
G06F 21/81 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur en agissant sur l’alimentation, p. ex. en branchant ou en débranchant l’alimentation, les fonctions de mise en veille ou de reprise
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
78.
Communication Network, Method and Device for operating with a Distributed Memory Space
A communication network (401) for operating a distributed memory system (DMS) is described. The communication network (401) comprises a plurality of non-operating system (non-OS) embedded devices having at least one memory (390) wherein the at least one memory (390) of the plurality of non-OS embedded devices is configured to have a first portion of memory (310, 330, 350, 370) reserved for the non-OS embedded device and a second portion of memory (320, 340, 360, 380) reserved and available for at least one other non-OS embedded device from the plurality of non-OS embedded devices within the communication network to use.
Embodiments of a method and apparatus for communications are disclosed. In an embodiment, a communications device includes a controller configured to generate a null data packet (NDP) announcement (NDPA) frame carrying a special station (STA) information (info) field, where the special STA info field contains information that indicates the NDPA frame as having an Ultra High Reliability (UHR) NDPA frame format, and a wireless transceiver configured to wirelessly transmit the NDPA frame to a second wireless device.
Embodiments of a wireless device and method are disclosed. In an embodiment, a wireless device comprises a wireless transceiver arranged to receive and transmit signals, and a controller operably coupled to the wireless transceiver to process the signals, wherein the controller is configured to transmit the signals to different end devices using different sized bandwidths, wherein the signals transmitted to a first end device use a first bandwidth of a first size and the signals transmitted to a first end device use a second bandwidth of a second size.
A controller for a resonant converter. If a measured current signal is greater than an upper-low-load-current-threshold, then the controller sets an upper-voltage-threshold-value based on the measured current signal. If the measured current signal is not greater than the upper-low-load-current-threshold, then the controller sets the upper-voltage-threshold-value based on the power setting signal but independent of the measured current signal. If the measured current signal is less than a lower-low-load-current-threshold, then the controller sets a lower-voltage-threshold-value based on the measured current signal. If the measured current signal is not less than the lower-low-load-current-threshold, then the controller sets the lower-voltage-threshold-value based on the power setting signal but independent of the measured current signal. In response to a measured voltage signal exceeding the upper-voltage-threshold-value, the controller opens the first switch and closes the second switch. In response to the measured voltage signal dropping below a lower-voltage-threshold-value, the controller opens the second switch and closes the first switch.
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
H02M 1/42 - Circuits ou dispositions pour corriger ou ajuster le facteur de puissance dans les convertisseurs ou les onduleurs
82.
FAULT INTERFACE ARCHITECTURE IN SAFETY-RELEVANT SYSTEMS
A method for handling faults in an integrated circuit system includes receiving fault interface signals from safety-critical logic and generating a fault request indicating a fault and a domain identifier based on the fault interface signals. The fault interface signals include a fault signal and a fault domain identifier signal. In an embodiment of the method, the fault interface signals include synchronous signals received from the safety-critical logic using a synchronous interface and the synchronous signals include a fault clock signal. In an embodiment of the method, generating the fault request includes asserting the fault request in response to the fault signal having a first asserted signal level and maintaining assertion of the fault request until a fault acknowledgement is received from a fault collection and control circuit.
A method of forming a package-on-package semiconductor device is provided. The method includes mounting a packaged radio frequency (RF) semiconductor device on a first major side of a package substrate. The packaged RF semiconductor device includes a semiconductor die, an encapsulant encapsulating the semiconductor die, and a redistribution layer (RDL) formed over an active side of the semiconductor die and a portion of the encapsulant. A signal launcher is formed from a conductive layer of the RDL. The signal launcher is configured for propagation of an RF signal through a waveguide formed through the package substrate.
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01P 11/00 - Appareils ou procédés spécialement adaptés à la fabrication de guides d'ondes, résonateurs, lignes ou autres dispositifs du type guide d'ondes
H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
84.
DEVICE, SYSTEM, AND METHOD FOR RESTRICTED TARGET WAKE TIME COORDINATION BETWEEN ACCESS POINTS
A method and system for restricted target wake time (r-TWT) coordination where a first AP in a basic service set (BSS) respects an r-TWT schedule of a second AP, where the second AP is in an overlapping basic service set (OBSS). The first AP acquires the r-TWT schedule of the second AP and indicates to the second AP that the first AP respects the r-TWT schedule of the second AP. The first AP provides to a station associated with the first AP an indication of the r-TWT schedule of the second AP to cause a frame exchange with the STA of the first AP to end at a beginning of a r-TWT service period of the second AP to respect the r-TWT schedule of the second AP.
Methods and apparatus are described for millimeter wave (mmWave) link beam failure recovery. A wireless multi-link device (MLD), such as a non-AP MLD, establishes mmWave link and a non-mmWave link with a second wireless MLD. Upon detecting a beam failure of the mmWave link, the wireless MLD transmits, via the non-mmWave link, an indication of the beam failure which may also include a request frame for a candidate beam training procedure to be initiated by the second wireless MLD. In response, the wireless MLD receives, via the mmWave link, candidate beam training packets from the second wireless MLD. The wireless MLD further transmits, via the non-mmWave link, beam training feedback information regarding the candidate beam training packets. In an example, a new Tx beam (e.g., a Tx beam with a highest received signal strength) is selected for maintaining the mmWave link.
Methods and apparatus for generating trigger frames that solicit PPDUs from one or more client devices. In an example method, a trigger frame is generated in accordance with the IEEE 802.11bn amendment (UHR) to the IEEE 802.11 standard. The method begins by determining a time duration requirement (or padding field length requirement) for preparing an uplink transmission from a client device. A trigger frame is generated (e.g., by an access point) that includes a frame check sequence (FCS) field, a padding field, and an intermediate FCS value that is included in the padding field. In an example, the dedicated fields of the trigger frame do not explicitly indicate the location of the intermediate FCS value. For a protected trigger frame, a MIC value is further included in the padding field. In other examples, the intermediate FCS value is included within one or more User Info fields of the trigger frame.
A method for forming features on a wafer that includes forming a first opening in a first layer over a layer including carbon and removing material of the layer including carbon through the first opening to form a cavity. The method includes forming spacer material on the sidewalls of the layer including carbon in the cavity with a material forming process, wherein the spacer material is inhibited from forming on the bottom surface portion of the cavity during the material forming process. The formed spacer material formed a spacer that defines a second opening that is has a smaller lateral dimension in a first lateral direction than the first opening.
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
88.
SEMICONDUCTOR DEVICE WITH MULTI-STEP GATE AND MULTI-STEP FIELD PLATE AND METHOD OF FABRICATION THEREFOR
A semiconductor device includes a semiconductor substrate, surface passivation over the semiconductor substrate, and a first interlayer dielectric over the surface passivation. A gate electrode includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate, a first gate field plate with a first horizontal bottom extent that overlies the upper surface of the surface passivation, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate includes a first field plate with a third horizontal bottom extent that overlies and contacts the upper surface of the surface passivation, and a second field plate with a fourth horizontal bottom extent that is at least as high as the first horizontal bottom extent of the first gate field plate.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
89.
SEMICONDUCTOR DEVICE WITH MULTI-STEP GATE AND RECESSED MULTI-STEP FIELD PLATE AND METHOD OF FABRICATION THEREFOR
A semiconductor device includes a semiconductor substrate, surface passivation over the semiconductor substrate, and a first interlayer dielectric over the surface passivation. A gate electrode includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate, a first gate field plate with a first horizontal bottom extent that overlies and contacts the upper surface of the surface passivation, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate includes a first field plate with a third horizontal bottom extent that is recessed below the upper surface of the surface passivation, and a second field plate with a fourth horizontal bottom extent that is higher than the first horizontal bottom extent of the first gate field plate.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
One example discloses A first wireless communications device, including: a transceiver configured to be coupled to a set of antennas; a controller coupled to the transceiver; wherein the transceiver is configured to transmit a first signal to a second wireless communications device; wherein the transceiver is configured to receive a second signal from the second wireless communications device; wherein the second wireless communications device harvests power from the first signal to enable generation of the second signal; and wherein the first signal is backward compatible with WiFi compliant devices.
G06K 7/10 - Méthodes ou dispositions pour la lecture de supports d'enregistrement par radiation électromagnétique, p. ex. lecture optiqueMéthodes ou dispositions pour la lecture de supports d'enregistrement par radiation corpusculaire
H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
91.
SEMICONDUCTOR DEVICE WITH MULTI-STEP GATE AND RECESSED MULTI-STEP FIELD PLATE WITH FIELD PLATE SPACERS AND METHOD OF FABRICATION
A semiconductor device includes a semiconductor substrate, surface passivation over the semiconductor substrate, and a first interlayer dielectric over the surface passivation. A gate electrode includes a gate channel portion that extends through the surface passivation to contact the upper surface of the semiconductor substrate, a first gate field plate with a first horizontal bottom extent that overlies and contacts the upper surface of the surface passivation, and a second gate field plate with a second horizontal bottom extent that is higher than the first horizontal bottom extent. A conductive field plate includes a first field plate with a third horizontal bottom extent that is recessed below the upper surface of the surface passivation, and a second field plate with a fourth horizontal bottom extent that is higher than the first horizontal bottom extent of the first gate field plate.
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A controller for a resonant converter. The controller is configured to: compare a measured current signal with a positive current threshold; compare the measured current signal with a negative current threshold; and set a power reduction mode as active if either or both: the measured current signal is less than the positive current threshold at the end of the preceding high-side switch half cycle; and the measured current signal is greater than the negative current threshold at the end of the preceding low-side switch half cycle. While the power reduction mode is active: the controller gradually decreases the value of a reduced power signal. While the power reduction mode is inactive: the controller gradually increases the value of the reduced power signal. the controller sets an upper voltage threshold value and a lower voltage threshold value based on the lower of: i) the reduced power signal; and ii) a power setting signal.
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/14 - Dispositions de réduction des ondulations d'une entrée ou d'une sortie en courant continu
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
A controller for a resonant converter. The controller is configured to: receive a measured current signal that represents current flowing in the resonant tank; receive a measured voltage signal that represents the voltage at a predetermined point in the resonant tank; receive a power setting signal, which defines a requested power level for the load; set a protected power signal based on a time delay between a change in state of one of first and second switches and a subsequent zero-crossing of the measured current signal; set an upper voltage threshold value and a lower threshold value based on the lower of: i) the protected power signal; and ii) the power setting signal; in response to the measured voltage signal exceeding the upper voltage threshold value, open the first switch and close the second switch; and in response to the measured voltage signal dropping below the lower voltage threshold value, open the second switch and close the first switch.
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
94.
SYSTEM AND METHOD FOR NON-PRIMARY CHANNEL ACCESS (NPCA)
Embodiments of a method and apparatus for wireless communications are disclosed. In an embodiment, a wireless device includes a controller configured to determine backoff channels for a Basic Service Set (BSS) operating channel that include a primary channel and a non-primary channel access (NPCA) primary channel and a wireless transceiver configured to announce to a second wireless device the backoff channels of the BSS operating channel and to switch to the NPCA primary channel for communicating between the wireless device and the second wireless device.
A method of manufacturing a semiconductor device is provided. The method includes forming a first non-conductive layer over a top side a semiconductor die and patterning the first non-conductive layer to form an opening exposing a top surface of a bond of the semiconductor die. A metal trace of a redistribution layer is formed over a portion of the first non-conductive layer and exposed top surface of the bond pad. A surrounding bump metallization (SBM) structure is formed on a portion of the metal trace. The SBM structure includes a plurality of vertical metal wall segments surrounding a central opening.
Current sensing circuits for motor control applications are discussed. In some embodiments, a circuit may include a shunt resistor network coupled to an inverter having a plurality of phase legs, where each of the plurality of phase legs is configured to drive a respective phase of an electrical motor, and an Operational Amplifier (Op Amp) coupled across the shunt resistor network, where the Op Amp enables a processor to reconstruct electrical currents in each of the plurality of phase legs.
H02P 27/12 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par le type de tension d'alimentation utilisant une tension d’alimentation à fréquence variable, p. ex. tension d’alimentation d’onduleurs ou de convertisseurs utilisant des convertisseurs de courant continu en courant alternatif ou des onduleurs avec modulation de largeur d'impulsions appliquant des impulsions en guidant le vecteur-flux, le vecteur-courant, ou le vecteur-tension sur un cercle ou une courbe fermée, p. ex. pour commande directe du couple
97.
AMPLIFIER DEVICE HAVING A TUNABLE ELEMENT AND METHOD THEREFOR
An amplifier device includes an input port, an output port, a first amplifier that includes a first input terminal electrically coupled to the input port and a first output terminal electrically coupled to the output port, and a second amplifier that includes a second input terminal electrically coupled to the input port and a second output terminal electrically coupled to the output port. A first network that includes a first tunable element is electrically coupled to the first output terminal and is electrically coupled to a combining node. A second network that includes a second tunable element is electrically coupled to the combining node and electrically coupled to the output port.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
Disclosed is a QFN packaged semiconductor device, having a first major surface, an opposing second major surface and sidewalls therebetween, and comprising: a lead-frame, having a lead-frame lower surface and comprising a central die-pad region and a plurality of peripheral landing regions; a semiconductor die, attached to the die-pad on a top surface thereof; a plurality of bond-wires providing electrical connection between the semiconductor die and the plurality of peripheral landing regions; and encapsulant material, encapsulating the semiconductor die and bond-wires; wherein the encapsulant material forms a frame extending below the lead-frame lower surface, and defining the second major surface, the frame having an opening therein in a central region thereof under the semiconductor die, and wherein the sidewalls are spaced apart from the frame thereby exposing the lead-frame lower surface at the plurality of peripheral landing regions.
In an integrated circuit, a first always on (AON) domain generates an isolation signal to enter standby mode. A switchable power domain propagates the isolation signal. A voltage level detector outputs an indicator which indicates whether a voltage of the switchable power supply is above or below a voltage threshold. An isolation wrapper circuit includes a pass-through latch selectively enabled based on the output of the voltage level detector. The pass-through latch receives the propagated isolation signal and provides a value of the propagated isolation signal at its output while enabled, but maintains a latched value at its output, regardless of changes in value of the propagated isolation signal, while disabled. The wrapper circuit also includes an isolation circuit which receives signals from circuitry within the switchable power domain and selectively isolates the received signals from a second AON power domain based on the output of the pass-through latch.
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
G05F 1/59 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de réglage final pour une charge unique
G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
100.
CIRCUIT MODULES WITH ENCAPSULANT-EMBEDDED LEADFRAME TERMINALS, AND METHODS OF FABRICATING SUCH CIRCUIT MODULES
A circuit module includes a module substrate with a mounting surface, and a plurality of conductive features and electronic circuitry coupled to the mounting surface. Encapsulant material covers the electronic circuitry and the mounting surface, and an upper surface of the encapsulant material defined a first surface of the circuit module. A plurality of leadframe terminals, each separated from a non-planar leadframe unit, extend from the conductive features at the mounting surface through the encapsulant material toward the first surface of the circuit module. Each of the leadframe terminals is formed from an elongated planar conductive feature of a leadframe unit, and the plurality of leadframe terminals is electrically coupled to the electronic circuitry through the conductive features and the module substrate. Encapsulant divots may extend into the encapsulant material from the first surface of the circuit module, and proximal ends of the leadframe terminals terminate at the encapsulant divots.
