Example automatic test equipment (ATE) includes a transmitter to output a waveform to a transmission line; circuitry to detect data for the waveform on the transmission line, with the circuitry being configured to scan the waveform across a range of times and across a range of voltages to obtain the data for the waveform; and memory to store the data detected by the circuitry.
Example automatic test equipment (ATE) includes a transmitter to output a waveform to a transmission line; circuitry to detect data for the waveform on the transmission line, with the circuitry being configured to scan the waveform across as range of times and across a range of voltages to obtain the data for the waveform; and memory to store the data detected by the circuitry.
An example system includes an apparatus configured to output an audio signal having a power level sufficient to generate a vibration in a transmission line comprising, or associated with, a device under test (DUT). The vibration exposes an intermittent fault in the transmission line. A detector is configured to monitor the transmission line and to detect information associated with the intermittent fault in the transmission line.
An example system includes an apparatus configured to output an audio signal having a power level sufficient to generate a vibration in a transmission line comprising, or associated with, a device under test (OUT). The vibration exposes an intermittents fault in the transmission line. A detector is configured to monitor the transmission line and to detect information associated with the intermittent fault in the transmission line.
G01R 31/58 - Test de lignes, de câbles ou de conducteurs
G01R 31/67 - Test de connexions dans des appareils ou des circuits pour s’assurer qu’elles ont été établies correctement
B06B 1/02 - Procédés ou appareils pour produire des vibrations mécaniques de fréquence infrasonore, sonore ou ultrasonore utilisant l'énergie électrique
An example system is configured to convert a first digital signal having a first sampling rate into a second digital signal having a second sampling rate that is different from the first sampling rate. The system includes an input circuit to receive the first digital signal at the first sampling rate; a fractional finite impulse response (FIR) circuit configured to shift the first digital signal by a value corresponding coefficients of the FIR circuit, with the value being based on an integer value or a non-integer value; memory to store the coefficients for the FIR circuit; and processing circuitry to receive information corresponding to the second sampling rate, to obtain the value based on the information, to obtain the coefficients from the memory based on the value, and to provide the coefficients to the FIR circuit.
An example probe head includes probe needles that are electrically conductive and configured to create electrical connections to conductive pads on light emitting diodes (LEDs) on a wafer under test; power supplies to power the LEDs; multimeters to 5 measure at least one of a voltage across or a current through individual ones of the LEDs; and micro-electromechanical (MEM) switches configured to create, for each of the LEDs, an electrical connection between ones of the probe needles and both a power supply and a multimeter to cause the power supply to power the LED while the multimeter measures the at least one of the voltage across or the current through the 10 LED.
An example probe head includes probe needles that are electrically conductive and configured to create electrical connections to conductive pads on light emitting diodes (LEDs) on a wafer under test; power supplies to power the LEDs; multimeters to measure at least one of a voltage across or a current through individual ones of the LEDs; and micro-electromechanical (MEM) switches configured to create, for each of the LEDs, an electrical connection between ones of the probe needles and both a power supply and a multimeter to cause the power supply to power the LED while the multimeter measures the at least one of the voltage across or the current through the LED.
Example circuitry is usable in testing a device under test (DUT). The circuitry includes test inputs; a resistor ladder including resistors electrically connected in series, with the resistor ladder being electrically connected to each of the test inputs; and first operational amplifiers, with each first operational amplifier including a first input and a first output, with each first input being electrically connected to the resistor ladder, and with each first output to electrically connect to the DUT. The circuitry includes floating circuitry which includes a second operational amplifier. The second operational amplifier includes a second input electrically connected to the resistor ladder and a reference input; a first power input to receive a first voltage; and a second power input to receive a second voltage. The floating circuitry is configured to apply the first voltage and the second voltage to power inputs of each of the first operational amplifiers.
Example circuitry is usable in testing a device under test (OUT). The circuitry includes test inputs; a resistor ladder including resistors electrically connected in series, with the resistor ladder being electrically connected to each of the test inputs; and first operational amplifiers, with each first operational amplifier including a first input and a first output, with each first input being electrically connected to the resistor ladder, and with each first output to electrically connect to the OUT. The circuitry includes floating circuitry which includes a second operational amplifier. The second operational amplifier includes a second input electrically connected to the resistor ladder and a reference input; a first power input to receive a first voltage; and a second power input to receive a second voltage. The floating circuitry is configured to apply the first voltage and the second voltage to power inputs of each of the first operational amplifiers.
An example apparatus includes a circuit board. The circuit board includes one or more layers that form first electrically conductive regions and electrically non-conductive regions; an edge at an angle relative to the one or more layers; and second electrically conductive regions on the edge that are electrically connected to one or more of the first electrically conductive regions. The second electrically conductive regions are substantially flat and each has a connection surface that is substantially parallel to a surface of the edge.
H05K 1/14 - Association structurale de plusieurs circuits imprimés
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 3/02 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué à la surface du support isolant et est ensuite enlevé de zones déterminées de la surface, non destinées à servir de conducteurs de courant ou d'éléments de blindage
H05K 3/04 - Élimination du matériau conducteur par voie mécanique, p. ex. par poinçonnage
H05K 3/06 - Élimination du matériau conducteur par voie chimique ou électrolytique, p. ex. par le procédé de photo-décapage
An example method includes the following operations: receiving information about tests performed on a device, where the tests are associated with one or more parameters; performing an optimization process that includes varying the one or more parameters to optimize one or more criteria associated with the tests, where the optimization process includes an artificial intelligence process or a machine learning process; and outputting information that is based on which of the one or more parameters optimizes the one or more criteria.
An example system includes a signal generator to output signals based on multiple carrier frequencies; a wired transmission medium for carrying the signals, where the wired transmission medium is configured as open ended to produce reflections on the wired transmission medium of the signals; and a signal analyzer to receive the reflections and to determine a transmission time of a signal along the wired transmission medium based on the reflections. The signal analyzer is configured to perform operations that include performing a search based on an estimated transmission time of the signal along the wired transmission medium and the reflections to determine the transmission time. The search is to determine which of multiple candidate transmission times to select for the transmission time.
An example test system includes a plenum including an air inlet and a rack including slots to hold devices under test. The rack is adjacent to the plenum. The slots are arranged on the rack in a matrix such that part of each device held in a slot borders the plenum and is in fluid communication with the air inlet. One or more blowers are configured to force temperature-conditioned air into the air inlet of the plenum to thereby increase air pressure in the plenum and force the temperature-conditioned air over the devices and out of the plenum.
An example test system includes a plenum including an air inlet and a rack including slots to hold devices under test. The rack is adjacent to the plenum. The slots are arranged on the rack in a matrix such that part of each device held in a slot borders the plenum and is in fluid communication with the air inlet. One or more blowers are configured to force temperature-conditioned air into the air inlet of the plenum to thereby increase air pressure in the plenum and force the temperature-conditioned air over the devices and out of the plenum.
An example method includes the following operations: (i) receiving a device signal from a device under test (DUT); (ii) setting an attenuation value; (iii) applying the attenuation value to the device signal to produce an attenuated device signal for a frequency spectrum analyzing device, where the frequency spectrum analyzing device produces a noise signal; (iv) obtaining a power spectral density value using the frequency spectrum analyzing device, where a power spectral density comprises a power, at a frequency value, of a combined signal that is based on the attenuated device signal and the noise signal; (v) repeating operations (ii), (iii), and (iv) one or more times to produce multiple power spectral density values; (vi) repeating operations (i), (ii), (iii), (iv), and (v) one or more times to add power spectral density values to the multiple power spectral density values; and (vii) obtaining a power spectral density of the device signal.
An example method includes following operations: (i) receiving a device signal from a device under test (DUT); (ii) setting an attenuation value; (iii) applying the attenuation value to the device signal to produce an attenuated device signal for a frequency spectrum analyzing device, where the frequency spectrum analyzing device produces a noise signal and intermodulation interference; (iv) obtaining a power spectral density value, where the power spectral density value comprises a power, at a frequency value, of a combined signal that is based on the attenuated device signal, the noise signal, and the intermodulation interference; (v) repeating operations (ii), (iii), and (iv) one or more times to produce multiple power spectral density values; (vi) repeating operations (i), (ii), (iii), (iv), and (v) one or more times to add power spectral density values to the multiple power spectral density values; and (vii) obtaining a power spectral density of the device signal.
G01R 23/18 - Analyse de spectreAnalyse de Fourier avec possibilité d'enregistrement du spectre de fréquences
G01R 27/30 - Mesure de l'atténuation, du gain, du déphasage ou des caractéristiques qui en dérivent dans des réseaux électriques quadripoles, c.-à-d. des réseaux à double entréeMesure d'une réponse transitoire avec dispositions pour l'enregistrement des caractéristiques, p. ex. par traçage d'un diagramme de Nyquist
G01R 29/26 - Mesure du coefficient de bruitMesure de rapport signal-bruit
17.
Controlling storage of test data based on prior test program execution
An example system includes a first memory that includes primary storage; a second memory that includes secondary storage; and a control system for predicting paths through a test program that will be taken during a planned execution of the test program, and for causing test data associated with the test program to be stored in the first memory or the second memory based on the paths predicted.
G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
An example system includes a first memory that includes primary storage; a second memory that includes secondary storage; and a control system for predicting paths through a test program that will be taken during a planned execution of the test program, and for causing test data associated with the test program to be stored in the first memory or the second memory based on the paths predicted.
An example system is for testing a device under test (DUT) that includes a first core and a second core. The system includes channels in parallel for connecting to a number of pins on the DUT. The channels are for sending test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. Circuitry associated with the channels is configured to compare the measurement data with expected data, and to determine pass/fail status for the first core and for the second core based on the comparison.
An example system is for testing a device under test (DUT) that includes a first core and a second core. The system includes channels in parallel for connecting to a number of pins on the DUT. The channels are for sending test data to the DUT and for receiving measurement 5 data from the DUT based on the test data. The measurement data includes time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. Circuitry associated with the channels is configured to compare 10 the measurement data with expected data, and to determine pass/fail status for the first core and for the second core based on the comparison.
An example cable assembly includes a coaxial cable. A layer encases at least part of the coaxial cable. A memory on, or in contact with, the layer, the memory is configured to store calibration data for the coaxial cable.
H01B 11/18 - Câbles coaxiauxCâbles analogues ayant plusieurs conducteurs intérieurs dans un conducteur extérieur commun
H01B 7/18 - Protection contre les dommages provoqués par des facteurs extérieurs, p. ex. gaines ou armatures par l'usure, la contrainte mécanique ou la pression
H01B 3/30 - Isolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques matières plastiquesIsolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques résinesIsolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques cires
G11B 33/12 - Disposition des éléments de structure dans les appareils, p. ex. d'alimentation, des modules
An example cable assembly includes a coaxial cable. A layer encases at least part of the coaxial cable. A memory on, or in contact with, the layer, the memory is configured to store calibration data for the coaxial cable.
H01R 24/54 - Pièces intermédiaires, p. ex. adaptateurs, répartiteurs ou coudes
H01R 24/48 - Dispositifs de couplage en deux pièces, ou l'une des pièces qui coopèrent dans ces dispositifs, caractérisés par leur structure générale ayant des contacts disposés concentriquement ou coaxialement spécialement adaptés à la haute fréquence comprenant des moyens d'adaptation d'impédance ou des composants électriques, p. ex. des filtres ou des interrupteurs comprenant des dispositifs de protection, p. ex. de protection contre les surtensions
H01R 24/50 - Dispositifs de couplage en deux pièces, ou l'une des pièces qui coopèrent dans ces dispositifs, caractérisés par leur structure générale ayant des contacts disposés concentriquement ou coaxialement spécialement adaptés à la haute fréquence montés sur une PCB [carte de circuits imprimés]
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; computer component testing
and calibrating equipment; computer hardware for testing and
analyzing computer hardware, memory and logic devices,
semiconductors and chips; recorded computer software for
testing and analyzing computer hardware, memory and logic
devices, semiconductors and chips.
An example test system includes a test instrument configured to test a device under test (DUT). The test instrument is configured to interact with the DUT using first commands having a first syntax. The test system also includes one or more processing devices configured (i) to receive a definitions file, where the definitions file includes information defining a second syntax that is used by a third party to communicate with the DUT, (ii) to receive second commands having the second syntax, (iii) to convert the second commands into the first commands having the first syntax based on the definitions file, and (iv) to send the first commands to the test instrument to enable the test instrument to interact with the DUT.
An example system for testing a device under test (DUT) includes one or more processing devices configured to receive first data from the DUT over a communication channel, and to analyze the first data to identify an error associated with the communication channel; and a power supply controller configured to receive second data based on a power disturbance from the DUT, and to compare the first data and the second data to determine if there is a correlation between the power disturbance and the error.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 11/273 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductor testing apparatus; downloadable computer
software development tools; downloadable and recorded
computer software for testing and analyzing computer
hardware, semiconductors and chips, circuit boards, memory
and logic devices, and data networks. Design and development of computer software for others;
providing temporary use of non-downloadable cloud-based
software for testing and analyzing computer hardware,
semiconductors and chips, circuit boards, memory and logic
devices, and data networks.
27.
DETERMINING A CORRELATION BETWEEN POWER DISTURBANCES AND DATA ERORS IN A TEST SYSTEM
An example system for testing a device under test (DUT) includes one or more processing devices configured to receive first data from the DUT over a communication channel, and to analyze the first data to identify an error associated with the communication channel; and a power supply controller configured to receive second data based on a power disturbance from the DUT, and to compare the first data and the second data to determine if there is a correlation between the power disturbance and the error.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; Computer component testing and calibrating equipment; computer hardware for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips; recorded computer software for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
(1) Semiconductor testing apparatus; downloadable computer software development tools; downloadable and recorded computer software for testing and analyzing computer hardware, semiconductors and chips, circuit boards, memory and logic devices, and data networks. (1) Design and development of computer software for others; providing temporary use of non-downloadable cloud-based software for testing and analyzing computer hardware, semiconductors and chips, circuit boards, memory and logic devices, and data networks.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductor testing apparatus; downloadable computer software development tools; downloadable and recorded computer software for testing and analyzing computer hardware, semiconductors and chips, circuit boards, memory and logic devices, and data networks Design and development of computer software for others; providing temporary use of non-downloadable cloud-based software for testing and analyzing computer hardware, semiconductors and chips, circuit boards, memory and logic devices, and data networks
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; computer component testing
and calibrating equipment; computer hardware for testing and
analyzing computer hardware, memory and logic devices,
semiconductors and chips; recorded computer software for
testing and analyzing computer hardware, memory and logic
devices, semiconductors and chips.
32.
Method for reduction of SIC MOSFET gate voltage glitches
Aspects of the present disclosure are directed to a circuit and methods of operating the same to provide an off-state circuit path with a programmable impedance in combination with a negative gate-to-source voltage Vgs for power transistors in an inverter configuration to prevent gate voltage glitches. Gate voltage glitch may occur due to Miller current generation across the gate path of a power transistor in the off state during rapid voltage transient dV/dt when the other, complementary power transistor is switched on or off. According to one aspect, using a negative gate-to-source voltage to turn-off a power transistor may mitigate gate voltage spikes caused by a large voltage transient when the complimentary power transistor is turned on, thus preventing parasitic turn-on of the power transistor. According to another aspect, an off-state circuit path with a programmable impedance is provided that is controllable to be in a low impedance state prior to a complementary power transistor is being turned on, such that the gate voltage glitches of the power transistor is prevented by the low impedance off-state circuit path.
G01R 31/26 - Test de dispositifs individuels à semi-conducteurs
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
H02M 7/537 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur
33.
METHOD FOR REDUCTION OF SIC MOSFET GATE VOLTAGE GLITCHES
Aspects of the present disclosure are directed to a circuit and methods of operating the same to provide an off-state circuit path with a programmable impedance in combination with a negative gate-to- source voltage Vgs for power transistors in an inverter configuration to prevent gate voltage glitches. Gate voltage glitch may occur due to Miller current generation across the gate path of a power transistor in the off state during rapid voltage transient dV/dt when the other, complementary power transistor is switched on or off. According to one aspect, using a negative gate-to-source voltage to turn-off a power transistor may mitigate gate voltage spikes caused by a large voltage transient when the complimentary power transistor is turned on, thus preventing parasitic tum-on of the power transistor. According to another aspect, an off-state circuit path with a programmable impedance is provided that is controllable to be in a low impedance state prior to a complementary power transistor is being turned on, such that the gate voltage glitches of the power transistor is prevented by the low impedance off-state circuit path.
An example method of flattening a circuit board assembly includes attaching the circuit board assembly to a structure having dimensions that partly enclose a space, where attachment of the circuit board assembly to the structure creates an air-tight seal over the space, and where the structure has at least one port in fluid communication with the space. The method also includes applying vacuum pressure to the space via the at least one port, where the vacuum pressure forces at least part of the circuit board assembly toward the space, and dispensing thermal interface material selectively onto parts of the circuit board assembly while the vacuum pressure is applied.
An example method of flattening a circuit board assembly includes attaching the circuit board assembly to a structure having dimensions that partly enclose a space, where attachment of the circuit board assembly to the structure creates an air-tight seal over the space, and where the structure has at least one port in fluid communication with the space. The method also includes applying vacuum pressure to the space via the at least one port, where the vacuum pressure forces at least part of the circuit board assembly toward the space, and dispensing thermal interface material selectively onto parts of the circuit board assembly while the vacuum pressure is applied.
An example process determines a first error vector magnitude (EVM) of a signal output by a device under test (DUT). The process includes adding attenuation on a signal path between the DUT and a vector signal analyzer (VSA), where the attenuation is changeable; measuring, at the VSA, at least two second EVMs for different values of attenuation of the signal output by the DUT, where the at least two second EVMs are corrupted by noise from the VSA, and where each of the at least two second EVMs is based on two or more measurements; and determining the first EVM based on a linear relationship that is based on the first EVM, the at least two second EVMs, and a function based on the attenuation, where the first EVM is without at least some of the noise from the VSA.
A system is configured to test a device. The device is or includes a MIMO wireless device having antennas. The antennas include at least two antennas for receiving or transmitting. The system includes a test instrument and probes having wired connections to the test instrument over which signals are communicated between the probes and the test instrument. A probe is configured to communicate signals with an antenna on the device wirelessly in a reactive near-field region of the antenna.
An example process determines a first error vector magnitude (EVM) of a signal output by a device under test (DUT). The process includes adding attenuation on a signal path between the DUT and a vector signal analyzer (VSA), where the attenuation is changeable: measuring, at the VSA, at least two second EVMs for different values of attenuation of the signal output by the DUT, where the at least two second EVMs are corrupted by noise from the VSA, and where each of the at least two second EVMs is based on two or more measurements; and determining the first EVM based on a linear relationship that is based on the first EVM, the at least two second EVMs, and a function based on the attenuation, where the first EVM is without at least some of the noise from the VSA.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; Computer component testing and calibrating equipment; Computer hardware for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips; Recorded computer software for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips
An example system includes a first circuit board having first conductive traces, where a first conductive trace is for conducting an alternating current (AC) digital signal having an edge; a second circuit board having second conductive traces, where a second conductive trace is within a predefined distance of the first conductive trace to produce a contactless coupling with the first conductive trace, and where the contactless coupling enables electrical energy on the first conductive trace to manifest on the second conductive trace as a transient response that is based on the edge; and circuitry to reconstruct the edge based on the transient response from the second conductive trace.
An example test system includes memory (e.g., one or more memory devices) storing (i) instructions that are executable, and (ii) a mapping function that relates first error vector magnitudes (EVMs) for first symbols to second EVMs for the first symbols, where the first EVMs are corrupted by radio frequency (RF) noise and the second EVMs are corrupted by both RF noise and symbol decoding errors. The test system also includes a decoder to receive a signal from a device under test, and to obtain a third EVM for a second symbol that is based on the signal, where the third EVM is corrupted by both RF noise and a symbol decoding error. One or more processing devices are configured to execute the instructions to adjust the third EVM using the mapping function to correct the symbol decoding error in the third EVM.
H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
42.
System and method for using pulsed radio frequency (RF) signals and a modulated scattering probe (MSP) to enable measurements of distance to and planarity of a surface of a device under test (DUT)
Systems and methods are provided for systems and methods for using pulsed radio frequency (RF) signals to stimulate one or more modulated scattering probes (MSPs) to enable measurements of distance to and planarity of a surface of a wireless device under test (DUT).
An example probe for a test system includes a conductor to carry direct current (DC) signals between a DC testing resource and a signal trace on the test system, where the signal trace is for carrying the DC signals and alternating current (AC) signals to and from a device under test; and an inductor connected in series with the conductor. A mechanism is included in the probe for enabling the conductor to move toward the signal trace or a pin electrically connected to the signal trace to create an electrical connection between the conductor and the signal trace to enable the testing resource to transmit the DC signals to the signal trace, and to move away from the signal trace or the pin so that no electrical connection is created between the conductor and the signal trace when the DC signals are not to be transmitted to the signal trace.
An example probe for a test system includes a conductor to carry direct current (DC) signals between a DC testing resource and a signal trace on the test system, where the signal trace is for carrying the DC signals and alternating current (AC) signals to and from a device under test; and an inductor connected in series with the conductor. A mechanism is included in the probe for enabling the conductor to move toward the signal trace or a pin electrically connected to the signal trace to create an electrical connection between the conductor and the signal trace to enable the testing resource to transmit the DC signals to the signal trace, and to move away from the signal trace or the pin so that no electrical connection is created between the conductor and the signal trace when the DC signals are not to be transmitted to the signal trace.
An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (OUT) to be tested.
An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/263 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
Example techniques may be implemented as a method, a system or more nontransitory machine-readable media storing instructions that are executable by one or more processing devices. Operations performed by the example techniques include obtaining data representing results of tests executed by one or more test instruments on an initial set of devices under test (DUTs) in a test system; and using the data to train a machine learning model. The machine learning model is for predicting which of the tests will produce failing results for a different set of DUTs. DUTs in the different set have one or more features in common with DUTs in the initial set.
Example techniques may be implemented as a method, a system or more non-transitory machine-readable media storing instructions that are executable by one or more processing devices, Operations performed by the example techniques include obtaining data representing results of tests executed by one or more test instruments on an initial set of devices under test (DUTs) in a test system; and using the data to train a machine learning model. The machine learning model is for predicting which of the tests will produce failing results for a different set of DUTs. DUTs in the different set have one or more features in common with DUTs in the initial set.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
System and method for compensating for power loss due to a radio frequency (RF) signal probe mismatch in conductive RF signal testing of a RF data signal transceiver device under test (DUT). Sourcing the RF test signal with the RF vector signal transceiver at multiple test frequencies enables isolation of and compensation for power loss due to a mismatch between the RF signal probe and RF DUT connection based on predetermined losses of the RF signal path.
System and Method for using a Single Radio Frequency (RF) Data Packet Signal Receiver to Perform Time-Switched Multiple Input, Multiple Output (MIMO) Data Packet Signal Analysis
System and method for implementing a time-switched MIMO signal analysis using a single RF signal receiver to capture the multiple incoming data packet signals. In accordance with example embodiments, like portions of repetitive data slots may be captured with a periodicity equal to that of their host repetitive data frames.
H04B 7/08 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station de réception
H04B 7/0456 - Sélection de matrices de pré-codage ou de livres de codes, p. ex. utilisant des matrices pour pondérer des antennes
51.
SYSTEM AND METHOD FOR USING A SINGLE RADIO FREQUENCY (RE) DATA PACKET SIGNAL RECEIVER TO PERFORM TIME-SWITCHED MULTIPLE INPUT, MULTIPLE OUTPUT (MIMO) DATA PACKET SIGNAL ANALYSIS
System and method for implementing a time-switched MIMO signal analysis using a single RF signal receiver to capture the multiple incoming data packet signals. In accordance with example embodiments, like portions of repetitive data slots may be captured with a periodicity equal to that of their host repetitive data frames.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; computer component testing
and calibrating equipment; computer hardware for testing and
analyzing computer hardware, memory and logic devices,
semiconductors and chips; recorded computer software for
testing and analyzing computer hardware, memory and logic
devices, semiconductors and chips.
An example test socket for a test system includes a receptacle to make electrical and mechanical connections to a device under test (OUT) and a lid to cover the OUT in the receptacle. The lid is controllable to open automatically to enable receipt of the OUT in the receptacle and, following receipt of the OUT, to close automatically to cover the OUT in the receptacle. Closing the lid applies force to the OUT to complete the electrical and mechanical connections between the test socket and the OUT.
System and method for measuring path loss of a conductive radio frequency (RF) signal path used in testing a RF data signal transceiver device under test (DUT) with a RF vector signal transceiver. A path loss measurement may be performed by initially leaving an open connection at the RF signal path end normally connected to the DUT during DUT testing. Sourcing the RF test signal with the RF vector signal transceiver at multiple test frequencies avoids need for additional testing with shorted and loaded connections at the RF signal path end.
System and method for compensating for power loss due to a radio frequency (RF) signal probe mismatch in conductive RF signal testing of a RF data signal transceiver device under test (DUT). Sourcing the RF test signal with the RF vector signal transceiver at multiple test frequencies enables isolation of and compensation for power loss due to a mismatch between the RF signal probe and RF DUT connection based on predetermined losses of the RF signal path.
G01R 23/15 - Indication de ce qu'une fréquence d'impulsions est, soit supérieure ou inférieure à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée, en utilisant des éléments non linéaires ou numériques
System and method for measuring path loss of a conductive radio frequency (RF) signal path used in testing a RF data signal transceiver device under test (DUT) with a RF vector signal transceiver. A path loss measurement may be performed by initially leaving an open connection at the RF signal path end normally connected to the DUT during DUT testing. Sourcing the RF test signal with the RF vector signal transceiver at multiple test frequencies avoids need for additional testing with shorted and loaded connections at the RF signal path end.
An example test socket for a test system includes a receptacle to make electrical and mechanical connections to a device under test (DUT) and a lid to cover the DUT in the receptacle. The lid is controllable to open automatically to enable receipt of the DUT in the receptacle and, following receipt of the DUT, to close automatically to cover the DUT in the receptacle. Closing the lid applies force to the DUT to complete the electrical and mechanical connections between the test socket and the DUT.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
58.
Waveguide connector for connecting first and second waveguides, where the connector includes a male part, a female part and a self-alignment feature and a test system formed therefrom
An example waveguide connector is for making a blind-mate electrical connection between a first waveguide and a second waveguide. The waveguide connector includes a male part connected to the first waveguide, where the first waveguide includes a first conductive channel, and a female part connected to the second waveguide, where the second waveguide includes a second conductive channel. The female part includes a receptacle into which the male part slides to create the blind-mate electrical connection between the first conductive channel and the second conductive channel. A self-alignment feature is on at least one of the male part or the female part. The self-alignment feature is configured to guide the male part into the receptacle while correcting for misalignment of the male part and the female part.
An example waveguide connector is for making a blind-mate electrical connection between a first waveguide and a second waveguide. The waveguide connector includes a male part connected to the first waveguide, where the first waveguide includes a first conductive channel, and a female part connected to the second waveguide, where the second waveguide includes a second conductive channel. The female part includes a receptacle into which the male part slides to create the blind-mate electrical connection between the first conductive channel and the second conductive channel. A self-alignment feature is on at least one of the male part or the female part. The self-alignment feature is configured to guide the male part into the receptacle while correcting for misalignment of the male part and the female part.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; Computer component testing and calibrating equipment; computer hardware for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips; recorded computer software for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips
An example front-end module includes a channel to connect to a device under test (DUT). The front-end module includes a transmission line between the DUT and the front-end module that is configured for bidirectional transmission of oscillating signals including test signals and response signals, and in-phase and quadrature (IQ) circuitry configured to modulate a test signal for transmission over the transmission line to the DUT and to demodulate a response received over the transmission line from the DUT. The front-end module include at least four taps into the transmission line to obtain direct current (DC) voltage values based on the oscillating signals. Scattering (s) parameters of the channel are based on the DC voltage values. The front-end module includes at least six ports.
An example contact head includes coaxial contacts configured for transmission of radio frequency (RF) signals or digital signals between a test system and a device under test (DUT). Each of the coaxial contacts is configured to target a specific impedance. Each of the coaxial contacts includes a coaxial structure having an open-curve shape. The coaxial structure includes a spring material that bends in response to applied force and that returns to the open-curve shape absent the applied force. The coaxial structure includes a center conductor terminating in a contact pin and a return conductor separated by a dielectric from the center conductor. At least part of the center conductor and the return conductor include an electrically-conductive material. Flexible contacts on the coaxial contact include the electrically-conductive material.
H01R 9/05 - Dispositifs de connexion conçus pour assurer le contact avec plusieurs des conducteurs d'un câble multiconducteur pour câbles coaxiaux
H01R 13/6582 - Structure du blindage avec des moyens élastiques destinés à venir en contact avec le connecteur correspondant
63.
System and method for over-the-air (OTA) testing to detect faulty elements in an active array antenna of an extremely high frequency (EHF) wireless communication device
Systems and methods for detecting faulty elements in an active planar antenna array of an extremely high frequency (EHF) wireless communication device. A planar antenna array having a matrix of dual-polarization modulated scattering probes is disposed within a near-field region of the antenna under test (AUT). Electromagnetic energy received from the AUT is converted to a complex electrical signal that is modulated by an electrical modulation signal and radiated as a scattering signal. The resulting electromagnetic scattering signal, received and converted to an electrical signal by another antenna, is used in a holographic image reconstruction operation via a backward-propagation transformation to reconstruct the signal spectrum radiated from the surface of the AUT. Configurable (e.g., electrically) scatter probes provide maximized modulation depths (MDs) over wide frequency ranges.
G01R 27/28 - Mesure de l'atténuation, du gain, du déphasage ou des caractéristiques qui en dérivent dans des réseaux électriques quadripoles, c.-à-d. des réseaux à double entréeMesure d'une réponse transitoire
H01Q 3/26 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la phase relative ou l’amplitude relative et l’énergie d’excitation entre plusieurs éléments rayonnants actifsDispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la distribution de l’énergie à travers une ouverture rayonnante
An example printed circuit board (PCB) includes a substrate having layers of a dielectric material, where the layers of dielectric material include a first layer and a second layer; a conductive trace that is between the first layer and the second layer and that is parallel to the first layer and the second layer along at least part of a length of the conductive trace; and a conductive via that extends at least part-way through the layers of dielectric material and that connects electrically to the conductive trace, where the conductive via is configured also to connect electrically to a signal input to receive or to transmit a signal that has a center frequency span.
An example apparatus is for contacting a device to change a temperature of the device. The apparatus includes a plate configured to contact the device and a channel within the plate configured to enable flow of fluid between an input port and an output port. The plate includes a thermally conductive material to conduct heat between the device and the fluid. The channel includes multiple islands arranged in series. An island among the multiple islands is arranged to receive the fluid at a first side. The island is for splitting the fluid into a first flow and a second flow and for causing the first flow and the second flow to merge at a second side of the island that is downstream of the first side of the island.
An example apparatus is for contacting a device to change a temperature of the device. The apparatus includes a plate configured to contact the device and a channel within the plate configured to enable flow of fluid between an input port and an output port. The plate includes a thermally conductive material to conduct heat between the device and the fluid. The channel includes multiple islands arranged in series. An island among the multiple islands is arranged to receive the fluid at a first side. The island is for splitting the fluid into a first flow and a second flow and for causing the first flow and the second flow to merge at a second side of the island that is downstream of the first side of the island.
F28D 1/047 - Appareils échangeurs de chaleur comportant des ensembles de canalisations fixes pour une seule des sources de potentiel calorifique, les deux sources étant en contact chacune avec un côté de la paroi de la canalisation, dans lesquels l'autre source de potentiel calorifique est une grande masse de fluide, p. ex. radiateurs domestiques ou de moteur de voiture avec des canalisations d'échange de chaleur immergées dans la masse du fluide avec canalisations tubulaires les canalisations étant courbées, p. ex. en serpentin ou en zigzag
F24F 11/30 - Aménagements de commande ou de sécurité en relation avec le fonctionnement du système, p. ex. pour la sécurité ou la surveillance
F24F 11/74 - Systèmes de commande caractérisés par leurs grandeurs de sortieDétails de construction de tels systèmes pour la commande de l’apport en air traité, p. ex. commande de la pression pour la commande du débit d'air ou de la vitesse de l’air
F24F 11/76 - Systèmes de commande caractérisés par leurs grandeurs de sortieDétails de construction de tels systèmes pour la commande de l’apport en air traité, p. ex. commande de la pression pour la commande du débit d'air ou de la vitesse de l’air par des moyens sensibles à la température, p. ex. ressorts bilames
An example front-end module includes a channel to connect to a device under test (DUT). The front-end module includes a transmission line between the DUT and the front-end module that is configured for bidirectional transmission of oscillating signals including test signals and response signals, and in-phase and quadrature (IQ) circuitry configured to modulate a test signal for transmission over the transmission line to the DUT and to demodulate a response received over the transmission line from the DUT. The front-end module include at least four taps into the transmission line to obtain direct current (DC) voltage values based on the oscillating signals. Scattering (s) parameters of the channel are based on the DC voltage values. The front-end module includes at least six ports.
An example printed circuit board (PCB) includes a substrate having layers of a dielectric material, where the layers of dielectric material include a first layer and a second layer; a conductive trace that is between the first layer and the second layer and that is parallel to the first layer and the second layer along at least part of a length of the conductive trace; and a conductive via that extends at least part-way through the layers of dielectric material and that connects electrically to the conductive trace, where the conductive via is configured also to connect electrically to a signal input to receive or to transmit a signal that has a center frequency span.
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
An example test head manipulator includes a tower having a base and a track, where the track is vertical relative to the base, and arms to enable support for the test head. The arms are connected to the track to move the test head vertically relative to the tower, and the arms are configured to control rotation of the test head. Each of the arms includes a cam that is rotatable, and at least one plunger in contact with the cam and that is configured to contact the test head. Rotation of the cam is controllable to move the at least one plunger to offset an uncontrolled rotation the test head.
An example test head manipulator includes a tower having a base and a track, where the track is vertical relative to the base, and arms to enable support for the test head. The arms are connected to the track to move the test head vertically relative to the tower, and the arms are configured to control rotation of the test head. Each of the arms includes a cam that is rotatable, and at least one plunger in contact with the cam and that is configured to contact the test head. Rotation of the cam is controllable to move the at least one plunger to offset an uncontrolled rotation the test head.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
B25J 9/04 - Manipulateurs à commande programmée caractérisés par le mouvement des bras, p. ex. du type à coordonnées cartésiennes par rotation d'au moins un bras en excluant le mouvement de la tête elle-même, p. ex. du type à coordonnées cylindriques ou polaires
G01N 29/265 - Dispositions pour l'orientation ou le balayage en déplaçant le capteur par rapport à un matériau fixe
An interposer for a test system includes coaxial cables, each of which is configured to transport a first portion of current originating from a current source, and printed circuit boards (PCBs), each of which is connected to a set of the coaxial cables in order to receive the first portion of the current from each coaxial cable in the set and to transport a second portion of the current. A spring leaf assembly includes spring leaves, each of which is connected to a PCB in order to transport a third portion of the current obtained from the PCB to a device interface board (DIB) that connects to devices under test (DUTs) to be tested by the test system. The coaxial cables on each PCB are arranged in parallel, the PCBs are arranged in parallel, and the spring leaves on each PCB are arranged in parallel.
An example test system includes a test head, and a device interface board (DIB) configured to connect to the test head. The DIB is for holding devices under test (DUTs). The DIB includes electrical conductors for transmitting electrical signals between the DUTs and the test head. Servers are programmed to function as test instruments. The servers are external to, and remote from, the test head and are configured to communicate signals over fiber optic cables with the test head. The signals include serial signals.
An example polarity inverter includes multiple contactors, each of which includes switches that are controllable to configure a current path. Each of the multiple contactors includes contacts, which are interleaved such that first contacts to receive voltage having a first polarity alternate with second contacts to receive voltage having a second polarity, where the first polarity and the second polarity are different. The polarity inverter also includes a first conductive plate to connect electrically to each of the first contacts, and a second conductive plate to connect electrically to each of the second contacts. The first conductive plate and the second conductive plate are in parallel. A dielectric material is between the first conductive plate and the second conductive plate.
G01R 31/26 - Test de dispositifs individuels à semi-conducteurs
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
H01H 9/00 - Détails de dispositifs de commutation non couverts par
H01H 9/22 - Mécanismes d'interverrouillage, verrouillage ou accrochage pour interverrouillage entre enveloppe, capot ou volet de protection et le mécanisme actionnant les contacts
H01H 1/58 - Connexions électriques avec ou entre contactsBornes
74.
Automatic test equipement having fiber optic connections to remote servers
An example test system includes a test head, and a device interface board (DIB) configured to connect to the test head. The DIB is for holding devices under test (DUTs). The DIB includes electrical conductors for transmitting electrical signals between the DUTs and the test head. Servers are programmed to function as test instruments. The servers are external to, and remote from, the test head and are configured to communicate signals over fiber optic cables with the test head. The signals include serial signals.
An interposer for a test system includes coaxial cables, each of which is configured to transport a first portion of current originating from a current source, and printed circuit boards (PCBs), each of which is connected to a set of the coaxial cables in order to receive the first portion of the current from each coaxial cable in the set and to transport a second portion of the current. A spring leaf assembly includes spring leaves, each of which is connected to a PCB in order to transport a third portion of the current obtained from the PCB to a device interface board (DIB) that connects to devices under test (DUTs) to be tested by the test system. The coaxial cables on each PCB are arranged in parallel, the PCBs are arranged in parallel, and the spring leaves on each PCB are arranged in parallel.
H01R 13/6587 - Matériau de blindage entourant individuellement des contacts espacés les uns des autres ou interposé entre ces derniers pour séparer des modules de connecteurs multibroches pour montage sur des cartes de circuits imprimés
H01R 12/51 - Connexions fixes pour circuits imprimés rigides ou structures similaires
H01R 13/24 - Contacts pour coopération par aboutage élastiquesContacts pour coopération par aboutage montés élastiquement
An example polarity inverter includes multiple contactors, each of which includes switches that are controllable to configure a current path. Each of the multiple contactors includes contacts, which are interleaved such that first contacts to receive voltage having a first polarity alternate with second contacts to receive voltage having a second polarity, where the first polarity and the second polarity are different. The polarity inverter also includes a first conductive plate to connect electrically to each of the first contacts, and a second conductive plate to connect electrically to each of the second contacts. The first conductive plate and the second conductive plate are in parallel. A dielectric material is between the first conductive plate and the second conductive plate.
An example test system includes a test socket for testing a DUT, a lid for the test socket, and an actuator configured to force the lid onto the test socket and to remove the lid from the test socket. The actuator includes an upper arm to move the lid, an attachment mechanism connected to the upper arm to contact the lid, where the attachment mechanism is configured to allow the lid to float relative to the test socket to enable alignment between the lid and the test socket, and a lower arm to anchor the actuator to a board containing the test socket. The actuator is configured to move the upper arm linearly towards and away from the test socket and to rotate the upper arm towards and away from the test socket.
An example test system includes packs. The packs include test sockets for testing devices under test (DUTs) and at least some test electronics for performing tests on the DUTs in the test sockets. Different packs are configured to have different configurations. The different configurations include at least different numbers of test sockets arranged at different pitches.
A system and method for using a wireless radio frequency (RF) data packet signaling link to enable non-link control of testing of a data packet signal transceiver device under test (DUT) in which a communication session between a tester and a DUT for purposes of testing the DUT may first be initiated by a separate, commonly available, and lower cost, communication device. Following its establishment, the tester may monitor the communication session, e.g., via wireless signal sniffing, to acquire and use associated device identification information to join the session and transmit trigger based test (TBT) data packets for initiating a test sequence within the DUT. Hence, use of a non-link capable tester to perform parametric testing of a DUT at the lowest network architecture layer, e.g., the physical (PHY) layer, may be enabled.
An example test system includes test sites that include sockets for testing devices under test (DUTs), pickers for picking DUTs from the sockets or placing the DUTs in the sockets, and a gantry on which the pickers are mounted. The gantry is configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the sockets or placing the DUTs into the sockets. The test system also includes one or more LASER range finders mounted on the gantry for movement over the DUTs in the sockets and in conjunction with movement of the pickers. A LASER range finder among the one or more LASER rangefinders mounted on the gantry is configured to detect a distance to a DUT placed into a socket.
An example test system includes packs. The packs include test sockets for testing devices under test (DUTs) and at least some test electronics for performing tests on the DUTs in the test sockets. Different packs are configured to have different configurations. The different configurations include at least different numbers of test sockets arranged at different pitches.
An example test system includes a test socket for testing a DUT, a lid for the test socket, and an actuator configured to force the lid onto the test socket and to remove the lid from the test socket. The actuator includes an upper arm to move the lid, an attachment mechanism connected to the upper arm to contact the lid, where the attachment mechanism is configured to allow the lid to float relative to the test socket to enable alignment between the lid and the test socket, and a lower arm to anchor the actuator to a board containing the test socket. The actuator is configured to move the upper arm linearly towards and away from the test socket and to rotate the upper arm towards and away from the test socket.
A system and method for using a wireless radio frequency (RF) data packet signaling link to enable non-link control of testing of a data packet signal transceiver device under test (DUT) in which a communication session between a tester and a DUT for purposes of testing the DUT may first be initiated by a separate, commonly available, and lower cost, communication device. Following its establishment, the tester may monitor the communication session, e.g., via wireless signal sniffing, to acquire and use associated device identification information to join the session and transmit trigger based test (TBT) data packets for initiating a test sequence within the DUT. Hence, use of a non-link capable tester to perform parametric testing of a DUT at the lowest network architecture layer, e.g., the physical (PHY) layer, may be enabled.
An example test system includes test sites for testing devices under test (DUTs), where the test sites include a test site configured to hold a DUT for testing. The test system includes a thermal control system to control a temperature of the DUT separately from control over temperatures of other DUTs in other test sites. The thermal control system includes a thermoelectric cooler (TEC) and a structure that is thermally conductive. The TEC is in thermal communication with the DUT to control the temperature of the DUT by transferring heat between the DUT and the structure.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
F25B 21/04 - Machines, installations ou systèmes utilisant des effets électriques ou magnétiques utilisant l'effet PeltierMachines, installations ou systèmes utilisant des effets électriques ou magnétiques utilisant l'effet Nernst-Ettinghausen réversibles
G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
An example test system includes test sites comprising test sockets for testing devices under test (DUTs) and pickers for picking DUTs from the test sockets or placing the DUTs into the test sockets. Each picker may include a picker head for holding a DUT. The test system also includes a gantry on which the pickers are mounted. The gantry may be configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the test sockets or placing the DUTs into the test sockets. The test sockets are arranged in at least one array that is accessible to the pickers on the gantry.
An example test system includes test sites that include sockets for testing devices under test (DUTs), pickers for picking DUTs from the sockets or placing the DUTs in the sockets, and a gantry on which the pickers are mounted. The gantry is configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the sockets or placing the DUTs into the sockets. The test system also includes one or more LASER range finders mounted on the gantry for movement over the DUTs in the sockets and in conjunction with movement of the pickers. A LASER range finder among the one or more LASER rangefinders mounted on the gantry is configured to detect a distance to a DUT placed into a socket.
An example test system includes test sites comprising test sockets for testing devices under test (DUTs) and pickers for picking DUTs from the test sockets or placing the DUTs into the test sockets. Each picker may include a picker head for holding a DUT. The test system also includes a gantry on which the pickers are mounted. The gantry may be configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the test sockets or placing the DUTs into the test sockets. The test sockets are arranged in at least one array that is accessible to the pickers on the gantry.
An example test system includes test sites for testing devices under test (DUTs), where the test sites include a test site configured to hold a DUT for testing. The test system includes a thermal control system to control a temperature of the DUT separately from control over temperatures of other DUTs in other test sites. The thermal control system includes a thermoelectric cooler (TEC) and a structure that is thermally conductive. The TEC is in thermal communication with the DUT to control the temperature of the DUT by transferring heat between the DUT and the structure.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
89.
APPARATUS AND METHOD FOR OPERATING SOURCE SYNCHRONOUS DEVICES
Circuitry and methods of operating the same to strobe a DQ signal with a gated DQS signal are described. Some aspects are directed to a gating scheme to selectively pass a received strobe signal such as a DQS strobe signal based on a state of a drive enable (DE) signal in a drive circuit in the ATE, such that edges generated by the drive circuit are prevented from mistakenly strobing a received data signal such as a DQ signal.
Circuitry and methods of operating the same to strobe a DQ signal with a gated DQS signal are described. Some aspects are directed to a gating scheme to selectively pass a received strobe signal such as a DQS strobe signal based on a state of a drive enable (DE) signal in a drive circuit in the ATE, such that edges generated by the drive circuit are prevented from mistakenly strobing a received data signal such as a DQ signal.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
Example systems for determining a configuration of a test system execute operations that include receiving first parameters specifying at least part of an operation of a test system; receiving second parameters specifying at least part of a first configuration of the test system; determining a second configuration of the test system based, at least in part, on the first parameters and the second parameters, with the second configuration being determined to impact a cost of test of the test system; generating, by one or more processing devices, data for a graphical user interface representing information about the second configuration and the cost of test; and outputting the data for the graphical user interface for rendering on a display device.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G06Q 10/06 - Ressources, gestion de tâches, des ressources humaines ou de projetsPlanification d’entreprise ou d’organisationModélisation d’entreprise ou d’organisation
An example includes the following operations: identifying parameters associated with a test program, where the parameters are based on at least one of a device under test (DUT) to be tested by the test program or a type of test to be performed on the DUT by the test program; assigning weights to the parameters; generating a numerical value for the test program based on the parameters, the weights, and equations that are based on the parameters and the weights, where the numerical value is indicative of a complexity of the test program; and using the numerical value to obtain information about effort needed to develop future test programs.
An example test system includes a device interface board (DIB) having one or more signal transmission paths and an interface for connecting to one or more other components of the test system. Test circuitry is configured to inject test signals into the one or more signal transmission paths and to measure transmitted versions of the test signals at the interface to obtain measurement signals. One or more processing devices are configured to generate calibration factors based on differences between the injected test signals and the measurement signals, and to store the calibration factors in computer memory. The calibration factors are for correcting for effects on the test signals of the one or more signal transmission paths.
An example test system includes a device interface board (DIB) having one or more signal transmission paths and an interface for connecting to one or more other components of the test system. Test circuitry is configured to inject test signals into the one or more signal transmission paths and to measure transmitted versions of the test signals at the interface to obtain measurement signals. One or more processing devices are configured to generate calibration factors based on differences between the injected test signals and the measurement signals, and to store the calibration factors in computer memory. The calibration factors are for correcting for effects on the test signals of the one or more signal transmission paths.
Example circuitry includes a first circuit to provide a low signal; a second circuit to provide a high signal, where the high signal has a greater voltage magnitude than the low signal; and a differential amplifier configured to receive the low signal from the first circuit and the high signal from the second circuit. The differential amplifier is for producing an output voltage that is based on the high signal and the low signal. The example circuitry includes a first measurement circuit to measure the output voltage; a second measurement circuit to measure the low signal at the first circuit; and processing logic to determine a differential measurement based on the output voltage measured by the first measurement circuit, the low signal measured by the second measurement circuit, and calibration values obtained for the circuitry.
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
Example circuitry includes a first circuit to provide a low signal; a second circuit to provide a high signal, where the high signal has a greater voltage magnitude than the low signal; and a differential amplifier configured to receive the low signal from the first circuit and the high signal from the second circuit. The differential amplifier is for producing an output voltage that is based on the high signal and the low signal. The example circuitry includes a first measurement circuit to measure the output voltage; a second measurement circuit to measure the low signal at the first circuit; and processing logic to determine a differential measurement based on the output voltage measured by the first measurement circuit, the low signal measured by the second measurement circuit, and calibration values obtained for the circuitry.
An example apparatus includes a block configured to connect mechanically to a circuit board. The circuit board includes a first conductive path running to a first electrical contact on the circuit board and a second conductive path running to a second electrical contact on the circuit board. The first electrical contact and the second electrical contact are arranged in an area of the circuit board. The block includes a component having a surface that is configured to cover at least part of the area. A conductive layer is attached to at least part of the surface. The conductive layer is for creating a short circuit between the first electrical contact and the second electrical contact following connection of the block to the circuit board.
A probe card in an automated test equipment (ATE) and methods for operating the same for testing electronic devices. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins. The probe card has a pad geometry that compensates for misalignment with corresponding probe pins due to manufacturing error or a mismatch of coefficient of thermal expansion, enabling reliable operation of the ATE over a wide range of test temperatures. The pad array may have a plurality of elongated pads, each of uniquely designed size, tilt angle, and/or center location, with the characteristics of each pad being dependent on a distance between each pad and a centroid of the pad array, such that a probe pin to pad location errors can be mitigated.
A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a probe card having ground vias in a coaxial arrangement around a signal via that provide electromagnetic shielding to a signal via to reduce crosstalk between adjacent signal vias.
G01R 3/00 - Appareils ou procédés spécialement adaptés à la fabrication des appareils de mesure
G01R 31/01 - Passage successif d'articles similaires aux tests, p. ex. tests "tout ou rien" d'une production de sérieTest d'objets en certains points lorsqu'ils passent à travers un poste de test
