The present application relates to the technical field of control, and provides an authority control method, an authority control apparatus, an electronic device, and a storage medium. The method comprises: performing identity authentication on an object identity of a target object; if the identity authentication is passed, acquiring a service platform bound to the target object, and determining a channel bound to the service platform, wherein a preset character of the preset object and data operation authority of the service platform associated with the preset character are allocated to the channel; and if the target object is the same as the preset object, allocating the data operation authority to the target object, so that the target object operates data of the service platform on the basis of the data operation authority. In this way, unified authority management can be performed on a plurality of service platforms, thereby facilitating maintenance of authority management, and improving the efficiency and security of authority management.
Embodiments of the present application relate to the technical field of data processing, and provide a data sending method and system, an electronic device, and a storage medium. The method comprises: preprocessing data items in an initial data set, so as to attach data identifiers to the data items, and classifying the data items into corresponding object tags according to the data identifiers; in response to an acquisition request of a data acquisition policy of a POS terminal, determining a first region where the POS terminal is located and a region protocol corresponding to the first region; enabling or disabling the data items in the object tags according to the region protocol, and generating a data acquisition policy according to enabled data items and disabled data items; and issuing the data acquisition policy to the POS terminal, so that the POS terminal collects the data items according to the data acquisition policy. Therefore, system deployment does not need to be performed in different regions in a targeted manner according to regional protocols of different regions, thus the development cost and the maintenance difficulty of the system are reduced.
Embodiments of the present application relate to the technical field of remote control, and provide a remote control reconnection method and apparatus, an electronic device, and a storage medium. The method comprises: acquiring a reconnection request sent by a target controlled end, wherein the reconnection request carries a reconnection long connection address and a reconnection pairing mark; performing matching determination on the reconnection pairing mark according to the reconnection long connection address and a preset pairing database, wherein the pairing database comprises an initial pairing mark and an initial main control end corresponding to the initial pairing mark; using the initial pairing mark matching the reconnection pairing mark as a target pairing mark, and using the initial main control end corresponding to the target pairing mark as a target main control end; and establishing a reconnection channel between the target main control end and the target controlled end. The embodiments of the present application can improve the remote control reconnection efficiency.
The present application relates to the technical field of payment security, and discloses a payment terminal data item automatic configuration method and device, and a storage medium. The method comprises: acquiring payment data of a target region where a payment terminal is located, the payment data comprising a service type and a service scenario; then performing feature extraction on the payment data on the basis of the target region to obtain a service type initial feature, a service scenario initial feature and region feature data; then performing feature selection according to feature priorities to obtain a service type feature and a service scenario feature; inputting the service type feature, the service scenario feature and the region feature data into a data item prediction model for prediction, so as to obtain a corresponding predicted data item; and finally performing data item configuration on the payment terminal according to the predicted data item. The payment data comprises supervision requirement data of corresponding regions, thus self-adaptive automatic configuration can be carried out on the payment terminal in different regions, the configuration process is optimized, and manual intervention and time cost are reduced.
The present application belongs to the technical field of electronic communications. Provided in the embodiments of the present application are a communication control method and apparatus for dual chips, a device and a storage medium. The method is applied to a terminal, the terminal comprising an application processing chip and a security processing chip. The method comprises: acquiring interface indication information of the terminal; according to the interface indication information, performing interface configuration, so as to obtain a target interface, the term "target interface" comprising a UART interface or an SPI interface; and activating the target interface, so that the application processing chip and the security processing chip communicate with each other via the target interface. The embodiments of the present application achieve flexible interface configuration, thus improving communication flexibility.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
6.
INTER-CHIP COMMUNICATION METHOD AND STORAGE MEDIUM
The present application relates to the technical field of communications. Disclosed are an inter-chip communication method and a storage medium. The inter-chip communication method comprises: packaging slave data by means of a first communication protocol layer of a slave to obtain a first protocol packet; packaging the first protocol packet by means of a first data link layer of the slave to obtain a first data packet; pulling an active uploading data pin of the slave to a low level, so that a host detects the low level and reads the slave data according to the low level; and sending the first data packet to the host. The inter-chip communication method provided in the present application ensures the timeliness of data transmission, thus allowing data interaction to be more rapid.
H04L 69/324 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche liaison de données [couche OSI 2], p. ex. HDLC
Brushes for vacuum cleaners; Vacuum cleaners; Vacuum cleaners for household purposes; Vacuum cleaners for industrial purposes; Commercial and industrial vacuum cleaners; Cordless vacuum cleaners; Electric vacuum cleaners and their components; Electric fan units for vacuum cleaners; Fitted covers for swimming pool vacuum cleaners; Hand-held vacuum cleaners; Hoses for vacuum cleaners; Robotic vacuum cleaners; Suction nozzles for vacuum cleaners
Air pumps, hand-operated; Battery-powered animal nail grinders; Can openers, non-electric; Cheese slicers, non-electric; Depilation appliances, electric and non-electric; Ear piercing needles; Electric animal nail grinders; Electric ear hair trimmers; Electric hair curling irons; Electric hair straightener; Electric irons; Fish forks; Fish scoops; Fish slicing kitchen knives; Foot care implements, namely, foot files; Hair-removing tweezers; Hand-operated CD or DVD case openers; Hand tools, namely, planers; Hand tools, namely, scrapers; Knives, forks, and spoons being tableware; Manually-operated jacks; Hand tools in the nature of pail lid openers; Hand tools in the nature of paint lid openers; Non-electric can openers; Windows openers and closers being hand-operated reaching tool; Nail buffers, electric or non-electric; Nail clippers, electric or non-electric; Nail files; Nail files, electric; Nail scissors; Nail skin treatment trimmers; Pedicure sets; Razors, electric or non-electric; Scissors; Tattoo machines
03 - Produits cosmétiques et préparations de toilette; préparations pour blanchir, nettoyer, polir et abraser.
05 - Produits pharmaceutiques, vétérinaires et hygièniques
12 - Véhicules; appareils de locomotion par terre, par air ou par eau; parties de véhicules
18 - Cuir et imitations du cuir
20 - Meubles et produits décoratifs
21 - Ustensiles, récipients, matériaux pour le ménage; verre; porcelaine; faience
24 - Tissus et produits textiles
28 - Jeux, jouets, articles de sport
35 - Publicité; Affaires commerciales
Produits et services
Skin cleansing lotion; Bath oils; Hair shampoo; Shampoos for babies; Perfumed soaps; Cosmetic soaps; Non-medicated industrial soap; Laundry soap; Facial cleansers; Body lotion; Fragrances; Room fragrances; Perfume; Perfume oils; Perfumed powder; Lipsticks; Facial beauty masks; Skin whitening creams; Eye compresses for cosmetic purposes; Lip balm, non-medicated; Nonmedicated mouthwashes; Toothpaste; Breath freshening sprays; Dental bleaching gels; Tooth whitening pastes; Air fragrance reed diffusers; Essential oils; Aromatic essential oils; Aromatic oils for the bath Vitamin preparations; Cod liver oil; food additives, namely, lecithin for medical purposes; Dietary fiber to aid digestion; Hemoglobin; Dietetic foods adapted for medical use; Appetite suppressants; Antibiotics; Collagen for medical purposes; Mineral food supplements; Food supplements; Air purifying preparations; Bacterial poisons; Vaginal washes for medical purposes; Vaginal lubricants; Protein dietary supplements Remotely controlled land vehicle for transport; Photography drones; Electric bicycles; Bicycles; Self-balancing scooters; Electric vehicles, namely, low-speed electric vehicles; Push scooters and structural parts therefor; Baby carriages; Air pumps for automobiles; Air pumps for motorcycles; Air pumps for bicycles; Safety seats for children, for vehicles School bags; Backpacks; Purses; Handbags; Rucksacks; Pouch baby carriers; Baby carriers worn on the body; Leather for furniture; Trekking poles; Leashes for animals; Umbrellas and parasols Beauty salon furniture; Furniture, mirrors, picture frames; furniture, namely, mirrors; Decorative mirrors; Hand mirrors, a part of a dresser; Fitted crib rail covers; Cradles; Infant cradles; Sideboards; Bottle racks; Reclining chairs; furniture, namely, recliners; Deck chairs; Infant beds; Portable infant beds Cookware, namely, steamers; Cookware, namely, pots and pans; Cookware, namely, roasting pans; Containers for household or kitchen use; Household containers for foods; Lunch boxes; Cooking pots; Pastry molds; Chocolate molds; Cookery molds; Confectioners' molds; Pancake molds; Rice molds; Pudding molds; Filters for use in cat litter boxes; Coffee filters not of paper being part of non-electric coffee makers; Non-electric food mixers for household purposes; Funnels; Pressure cookers, non-electric; Non-electric kettles; Chopsticks; Garlic presses; Reusable glass water bottles sold empty; Drinking vessels; Drinking glasses; Wine glasses; Wine bottle vests specially adapted for decorating wine bottles; Wine jugs; Wine openers; Wine strainers; Wine tasters; Tea services in the nature of tableware; Tea sets; Coffee cups; Coffee scoops; Coffee services in the nature of tableware; Non-electric coffee percolators; Tea strainers; Trash cans; Hand-operated devices for scratching pets; Dishwashing brushes; Cleaning brushes for household use; Bath brushes; Shaving brushes; Electric devices for cleaning cosmetic brushes; Electric toothbrush replacement handles and recharging docks sold as a unit; Food preserving jars of glass; Insulated carriers for food and beverages; Ice cube molds; Coolers for wine; Steel wool for cleaning; Mops; Rubber household gloves; Gloves for household purposes; Plug-in diffusers for mosquito repellents; Mouse traps Bed blankets; Bed sheets; Fitted bed sheets; Flat bed sheets; Bedspreads; Children's bed sheets, pillow cases, and blankets; Linen for household purposes; Blankets for household pets; Household linen, including face towels; Towels; Towels of textile; Knitted fabrics; Worsted fabrics; Jute fabrics; Flax fabrics; Woven felt; Press felt; Felt and non-woven textile fabrics; Quilts; Silk fabrics; Baby bedding, namely, bundle bags, swaddling blankets, crib bumpers, fitted crib sheets, crib skirts, crib blankets, and diaper changing pad covers not of paper Equipment sold as a unit for playing a memory game; Arcade-type electronic video games; Amusement game machines; Controllers and joysticks for video games; Tabletop units for playing electronic games other than in conjunction with a television or computer; Joysticks for video games; Computer game joysticks; Hand-held games with liquid crystal displays; Amusement machines, namely, hand-held electronic game units adapted for use with an external display screen or monitor; Portable game console with LCD display; Toy scooters; Dolls; Dolls for Christmas; Toy drones; Toy robots; Toy tricycles for children; Smart robot toys; Sports equipment, namely, lower body alignment apparatus; Exercise equipment, namely, shoulder stretcher using a cable; Exercise equipment, namely, virtual reality training cycles; Handle grips for sporting equipment; Manually-operated exercise equipment for physical fitness purposes; Sports equipment for boxing and martial arts, namely, boxing gloves, mixed martial arts gloves, punching mitts, and shin guards; Athletic protective elbow pads for skateboarding; Shin guards for athletic use; Waist trimmer exercise belts; Kidney belts for sports; Roller skates Retail store services for pharmaceutical, veterinary and sanitary preparations and medical supplies
36 - Services financiers, assurances et affaires immobilières
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Fund investments; Financial evaluation [insurance, banking, real estate]; Financing services; Credit card services; Debit card services; Electronic Funds transfer; Instalment loans; Leasing of real estate; Real Estate management; Capital investments. Technical research; Technical Project studies; Research and development for others; Computer rental; Computer programming; Computer software design; Consultancy in the design and development of computer hardware; Rental of computer Software; Maintenance of Computer software; Computer system design; Duplication of computer programs; Conversion of data or documents from physical to electronic media; Computer software Consultancy; Rental of web servers; Creating and maintaining web sites for others; Hosting computer sites [web sites]; Installation of computer software; Data conversion of computer programs and data [not physical conversion]; Digitization of documents [scanning]; Monitoring of computer systems by remote access.
12.
Apparatus and method for monitoring operation of an insulated gate bipolar transistor
Operation of an insulated gate bipolar transistor (IGBT) is monitored by an apparatus that has a capacitor connected between a collector of the IGBT and an input node. A processing circuit, coupled to the input node, responds to current flowing through the capacitor by providing an indication whether a voltage level at the collector is changing and the rate of that change. The processing circuit also employs the capacitor current to provide an output voltage that indicates the voltage at the IGBT collector.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
G01R 31/26 - Test de dispositifs individuels à semi-conducteurs
G01R 31/327 - Tests d'interrupteurs de circuit, d'interrupteurs ou de disjoncteurs
H01H 9/00 - Détails de dispositifs de commutation non couverts par
13.
Protection method for data information about electronic device and protection circuit therefor
Disclosed is a method for protecting data information of an electronic device, comprising the following steps: 1) performing power-on detection on an electronic device of which production and installation are completed, detecting the stray capacitance of a signal line thereof, and recording same as a standard value of the signal line; 2) during a power-on operation, monitoring the stray capacitance of the signal line; 3) comparing the monitored capacitance value with the standard value, and entering step 4) when exceeding the set threshold value, otherwise entering step 2); and 4) erasing significant data in the electronic device. The method uses the manner of monitoring the stray capacitance to monitor the contact of outside foreign matter with the signal line, guarantees the security of data in the electronic device, and has the characteristics that the implementation process is simple and easy, safe and reliable, and the cost is low.
G06F 21/00 - Dispositions de sécurité pour protéger les calculateurs, leurs composants, les programmes ou les données contre une activité non autorisée
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p. ex. pour empêcher l'ingénierie inverse
G07G 3/00 - Indicateurs d'alarme, p. ex. sonneries
G06F 21/82 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion
G05F 5/00 - Systèmes de régulation de variables électriques par détection des écarts du signal électrique à l'entrée du système et par commande par ces écarts d'un dispositif intérieur au système pour obtenir un signal de sortie régulé
G06F 1/32 - Moyens destinés à économiser de l'énergie
14.
Semiconductor device and related fabrication methods
Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure (100) includes a trench gate structure (114), a lateral gate structure (118), a body region (124) having a first conductivity type, a drain region (125) and first and second source regions (128, 130) having a second conductivity type. The first and second source regions (128, 130) are formed within the body region (124). The drain region (125) is adjacent to the body region (124) and the first source region (128) is adjacent to the trench gate structure (114), wherein a first portion of the body region (124) disposed between the first source region (128) and the drain region (125) is adjacent to the trench gate structure (114). A second portion of the body region (124) is disposed between the second source region (130) and the drain region (125), and the lateral gate structure (118) is disposed overlying the second portion of the body region (124).
H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
H01L 31/062 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails adaptés comme dispositifs de conversion photovoltaïque [PV] caractérisés par au moins une barrière de potentiel ou une barrière de surface les barrières de potentiel étant uniquement du type métal-isolant-semi-conducteur
H01L 31/113 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par un fonctionnement par effet de champ, p.ex. phototransistor à effet de champ à jonction du type conducteur-isolant-semi-conducteur, p.ex. transistor à effet de champ métal-isolant-semi-conducteur
H01L 31/119 - Dispositifs sensibles au rayonnement d'ondes très courtes, p.ex. rayons X, rayons gamma ou rayonnement corpusculaire caractérisés par un fonctionnement par effet de champ, p.ex. détecteurs du type MIS
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
A method for 3D device packaging utilizes through-substrate pillars to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal pillars. The first die and the second die are stacked such that each metal pillar extends from a surface of the second die to a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal pillars and the corresponding pads.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/52 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 21/304 - Traitement mécanique, p. ex. meulage, polissage, coupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
16.
Method and device for generating floating-point values
A floating-point value can represent a number or something that is not a number (NaN). A floating-point value that is a NaN includes a portion that stores information about the source operands of the instruction.
G06F 7/38 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 7/499 - Maniement de valeur ou d'exception, p. ex. arrondi ou dépassement
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
17.
Non-volatile memory (NVM) and high-k and metal gate integration using gate-last methodology
A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure.
A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
19.
Electronic component package and method for forming same
An electronic component package includes a substrate and dielectric structure. The dielectric structure includes a top surface having a protrusion portion and a lower portion. The protrusion portion is located at first height that is greater than a second height of the lower portion. A conductive bond pad is located over the dielectric structure. A ball bond electrically couples the bond pad and a bond wire. An intermetallic compound located between the ball bond and bond pad is formed of material of the ball bond and bond pad and electrically couples the bond pad to the ball bond. A portion of the bond pad is vertically located between a portion of the lower portion of the top surface of the dielectric structure and the intermetallic compound. No portion of the bond pad is vertically located between at least a portion of the protrusion portion and the intermetallic compound.
A system method of initializing operation of a semiconductor device including detecting de-assertion of an external reset signal while the semiconductor device in a reset state, monitoring a temperature level of the semiconductor device, and while the temperature level is below a predetermined minimum operating temperature level that allows the semiconductor device to operate at a maximum performance level, keeping the semiconductor device in the reset state and asserting at least one operating parameter on the semiconductor device at an elevated level to generate heat on the semiconductor device, and releasing the reset condition when the temperature level is at least the predetermined minimum operating temperature level. The operating parameter may be clock frequency or supply voltage level or a combination of both. Different elevated clock frequencies and/or different minimum operating temperature levels are contemplated. Additionally turning off an external cooling system during the heating process is contemplated.
H03L 7/00 - Commande automatique de fréquence ou de phaseSynchronisation
H03L 7/16 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase
H03L 1/02 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p. ex. de l'alimentation en énergie contre les variations de température uniquement
21.
Devices and stacked microelectronic packages with parallel conductors and intra-conductor isolator structures and methods of their fabrication
Embodiments of devices and methods of their manufacture include coupling first and second package surface conductors to a package surface with an intra-conductor insulating structure between the package surface conductors. The package surface conductors extend between and electrically couple sets of pads that are exposed at the package surface. Elongated portions of the package surface conductors are parallel with and adjacent to each other. The intra-conductor insulating structure is coupled between the package surface conductors along an entirety of the parallel and adjacent elongated portions, and the intra-conductor insulating structure electrically insulates the elongated portions of the package surface conductors from each other. Some embodiments may be implemented in conjunction with a stacked microelectronic package that includes sidewall conductors and an intra-conductor insulating structure between and electrically insulating the sidewall conductors from each other.
H05K 7/00 - Détails de construction communs à différents types d'appareils électriques
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H05K 3/10 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché
H05K 3/32 - Connexions électriques des composants électriques ou des fils à des circuits imprimés
22.
Devices and stacked microelectronic packages with in-trench package surface conductors and methods of their fabrication
Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body between exposed ends of first and second device-to-edge conductors, and forming a package surface conductor in the trench to electrically couple the first and second device-to-edge conductors. In one embodiment, the package surface conductor is formed by first forming a conductive material layer over the package surface, where the conductive material layer substantially fills the trench, and subsequently removing portions of the conductive material layer from the package surface adjacent to the trench. In another embodiment, the package surface conductor is formed by dispensing one or more conductive materials in the trench between the first and second exposed ends (e.g., using a technique such as spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispense). Excess conductive material may then be removed from the package surface adjacent to the trench.
H05K 7/10 - Montage de composants à contact par fiches
H05K 7/12 - Moyens élastiques ou moyens de serrage pour fixer un composant à la structure de l'ensemble
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 1/09 - Emploi de matériaux pour réaliser le parcours métallique
H05K 3/12 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché utilisant la technique de l'impression pour appliquer le matériau conducteur
H05K 3/14 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché utilisant la technique de la vaporisation pour appliquer le matériau conducteur
H05K 3/26 - Nettoyage ou polissage du parcours conducteur
H05K 3/04 - Élimination du matériau conducteur par voie mécanique, p. ex. par poinçonnage
H05K 3/06 - Élimination du matériau conducteur par voie chimique ou électrolytique, p. ex. par le procédé de photo-décapage
H05K 3/08 - Élimination du matériau conducteur par décharge électrique, p. ex. par érosion par étincelles
23.
Non-volatile memory (NVM) with dynamically adjusted reference current
A sense amplifier is configured to sense a current from a selected bit cell of a non-volatile memory array and compare the sensed current to a reference current to determine a logic state stored in the bit cell. A controller is configured to perform a program/erase operation on at least a portion of the memory array to change a logic state of at least one bit cell of the portion of the memory array; determine a number of program/erase pulses applied to the at least one bit cell during the program/erase operation to achieve the change in logic state; and when the number of program/erase pulses exceeds a pulse count threshold, adjust the reference current of the sense amplifier for a subsequent program/erase operation.
Protection device structures and related fabrication methods and devices are provided. An exemplary device includes a first interface, a second interface, a first protection circuitry arrangement coupled to the first interface, and a second protection circuitry arrangement coupled between the first protection circuitry arrangement and the second interface. The second protection circuitry arrangement includes a first transistor and a diode coupled to the first transistor, wherein the first transistor and the diode are configured electrically in series between the first protection circuitry arrangement and the second interface.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
25.
Temperature dependent biasing for leakage power reduction
Temperature dependent biasing for leakage power reduction. In some embodiments, a semiconductor device may include a biasing circuit configured to generate a voltage that varies dependent upon a temperature of the semiconductor device and a logic circuit operably coupled to the biasing circuit, where the voltage is applied to a bulk terminal of one or more transistors within the logic circuit, and where the voltage has a value outside of a voltage supply range of the logic circuit. In another embodiment, a semiconductor device may include a biasing circuit configured to generate a voltage that varies according to a temperature of the semiconductor device and a power switch operably coupled to the biasing circuit, where the voltage is applied to a gate terminal of the power switch, and where the voltage has a value outside of a voltage supply range of the power switch.
H03K 3/01 - Circuits pour produire des impulsions électriquesCircuits monostables, bistables ou multistables Détails
G05F 3/24 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor dans lesquelles les transistors sont uniquement du type à effet de champ
H03K 17/14 - Modifications pour compenser les variations de valeurs physiques, p. ex. de la température
A microelectronic device package including a package substrate, microelectronic component disposed on a first surface of a first portion of the substrate, and encapsulant material surrounding the microelectronic electronic component. An exposed surface of the first portion of the substrate is exposed through an opening in a first major surface of the encapsulant material. The exposed surface of the first portion has an edge. Encapsulant material is adjacent to the edge at the first major surface. The exposed surface is opposite the first surface. A stress relief feature located in one of the first major surface or a second major surface of the encapsulant material. The second major surface is opposite the first major surface. The stress relief feature reduces an amount of the encapsulant material and is 1 mm or less of a plane of the edge of the exposed surface. The plane is generally perpendicular to the exposed surface.
A method of programming a memory includes selecting a logic state for programming a first bitcell of the memory. A first one-time-programmable (OTP) element of the first bitcell is programmed using a first set of conditions intended to achieve a first target resistance in accordance with the selected logic state which results in a first degree of programming of the first OTP element. A second OTP element of the first bitcell is programmed using a second set of conditions different from the first set of conditions intended to achieve a second target resistance in accordance with the selected logic state which results in a second degree of programming of the second OTP element, wherein the first and second degrees of programming are visually indistinguishable.
G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
G11C 7/24 - Circuits de protection ou de sécurité pour cellules de mémoire, p. ex. dispositions pour empêcher la lecture ou l'écriture par inadvertanceCellules d'étatCellules de test
A diagnostic circuit is provided that includes a FET having a source connected to a first node, a drain, and a gate; a first switch connecting a current-supply node to one of the gate and a second node; a second switch connecting the first node and the second node; a variable current source providing one of a drive current and a test current to the current-supply node; a fire current source configured to provide a fire current to the drain; an error-detecting circuit connected to the second node, a reference terminal, and an error node, the error-detecting circuit generating an error signal to the error node indicating whether an error-detecting parameter at the second node exceeds a reference parameter at the reference terminal; and a control circuit generating control signals to control the variable current source, and the first and second switches.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
B60R 21/264 - Moyens gonflables de retenue ou d'immobilisation des occupants prévus pour se gonfler lors d'un choc ou en cas de choc imminent, p. ex. sacs gonflables caractérisés par la source de fluide de gonflage ou par les moyens de commande de l'écoulement du fluide de gonflage utilisant une génération instantanée de gaz, p. ex. pyrotechnique
B60R 21/017 - Circuits électriques pour déclencher le fonctionnement des dispositions de sécurité en cas d'accident, ou d'accident imminent, de véhicule comportant des dispositions pour alimenter les dispositions de sécurité en courant électrique
A semiconductor sensor device has a pressure sensing die and at least one other die mounted on a substrate, and electrical interconnections that interconnect the pressure sensing die and the at least one other die. An active region of the pressure sensing die is covered with a pressure sensitive gel material, and a cap having a cavity is mounted over the pressure sensing die such that the pressure sensing die is positioned within the cavity. The cap has a side vent hole that exposes the gel covered active region of the pressure sensing die to ambient atmospheric pressure outside the sensor device. Molding compound on an upper surface of the substrate encapsulates the at least one other die and at least a portion of the cap.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
B81B 3/00 - Dispositifs comportant des éléments flexibles ou déformables, p. ex. comportant des membranes ou des lamelles élastiques
A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device (160) includes a metal gate (124), an upper high-k gate dielectric layer (120), a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack (108, 110) formed with one or more low-k gate oxide layers (22), where each DGO transistor device (161) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a middle gate dielectric layer (114) formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device (162) includes a metal gate (124), an upper high-k gate dielectric layer (120), and a base oxide layer (118) formed with one or more low-k gate oxide layers.
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
31.
Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays
Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.
A method of making a semiconductor device includes depositing a layer of polysilicon in a non-volatile memory (NVM) region and a logic region of a substrate. The layer of polysilicon is patterned into a gate in the NVM region while the layer of polysilicon remains in the logic region. A memory cell is formed including the gate in the NVM region while the layer of polysilicon remains in the logic region. The layer of polysilicon in the logic region is removed and the substrate is implanted to form a well region in the logic region after the memory cell is formed. A layer of gate material is deposited in the logic region. The layer of gate material is patterned into a logic gate in the logic region.
Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.
A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.
Embodiments of methods of fabricating a sensor device includes attaching a first wafer to a sensor wafer with a first bond material, and attaching a second wafer to the sensor wafer with a second bond material, the second bond material having a lower bonding temperature than the first bond material. After attaching the second wafer, an opening (e.g., a trench cut) through the second wafer is formed, and an adhesive material is provided through the opening to further secure the second wafer to the sensor wafer. Embodiments of sensor devices formed using such methods include a first device cavity having a first pressure, and a second device cavity having a second pressure.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 23/10 - ConteneursScellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p. ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
H01L 29/84 - Types de dispositifs semi-conducteurs commandés par la variation d'une force mécanique appliquée, p.ex. d'une pression
A method of measuring a negative voltage using a device including a first transistor and a second transistor is provided. The first transistor is coupled to the second transistor and the negative voltage is supplied to a gate of the second transistor. A plurality of voltages are provided to a source input of the device. For each voltage of the plurality of voltages, whether a first voltage across the first transistor is equivalent to a second voltage across the second transistor is determined, and, when the first voltage across the first transistor is equivalent to the second voltage across the second transistor, the negative voltage is determined by measuring a magnitude of a positive voltage of the device.
A multi-mass resonator and a common-mode detection circuit are provided. The common-mode detection circuit, for example, may include a plurality of sensing electrodes, an interface circuit configured to interface with the plurality of sensing electrodes, and a common-mode capacitance extractor circuit electrically coupled in parallel to the interface circuit and configured to detect common-mode capacitance between the plurality of sensing electrodes and output a voltage representative the detected common-mode capacitance, and a differential-mode capacitance extractor circuit electrically coupled in parallel to the interface circuit and configured to detect differential-mode capacitance between the plurality of sensing electrodes and output a voltage representative the detected differential-mode capacitance.
G01R 27/26 - Mesure de l'inductance ou de la capacitanceMesure du facteur de qualité, p. ex. en utilisant la méthode par résonanceMesure de facteur de pertesMesure des constantes diélectriques
G01D 5/24 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier la capacité
G01C 19/00 - GyroscopesDispositifs sensibles à la rotation utilisant des masses vibrantesDispositifs sensibles à la rotation sans masse en mouvementMesure de la vitesse angulaire en utilisant les effets gyroscopiques
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
H03B 5/30 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique
38.
Microelectronic packages containing opposing devices and methods for the fabrication thereof
Microelectronic packages and methods for fabricating microelectronic packages are provided. The fabrication method may be carried-out utilizing a preformed panel having a frontside cavity and a backside cavity in which first and second microelectronic devices are positioned, respectively. One or more frontside RDL layers are produced over the frontside of the preformed panel in ohmic contact with or otherwise electrically coupled to the first microelectronic device. Similarly, one or more backside RDL layers are formed over the backside of the preformed panel in ohmic contact with or otherwise electrically coupled to the second microelectronic device. A frontside contact array is produced over the frontside of the preformed panel and electrically coupled to at least the first microelectronic device through the frontside RDL layers. Lastly, the preformed panel is singulated to yield a microelectronic package including a package body in which the first and second microelectronic devices are embedded.
H01L 23/043 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base conductrice qui sert de support et en même temps de connexion électrique pour le corps semi-conducteur
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
A process integration is disclosed for fabricating non-volatile memory (NVM) cells having spacer control gates (108) along with a high-k-metal-poly select gate (121, 123, 127) and one or more additional in-laid high-k metal CMOS transistor gates (121, 124, 128) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
H01L 29/51 - Matériaux isolants associés à ces électrodes
th address in the RAM banks and defining k status words for valid data among the (k+1) RAM banks. Write data is written to the write address of a valid RAM bank for a write operation in the absence of RAM bank read address contention. Write data is written to the write address of a different RAM bank that has no valid data for a write operation if there is contention with the RAM bank read address RADDR of a read operation. The status register is updated to identify the RAM bank of the write operation.
Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
42.
Multiple sense axis MEMS gyroscope having a single drive mode
A gyroscope includes a first drive mass driven in a first drive motion along a first axis, the first drive motion generating a first sense motion of a first sense mass in response to rotation of the gyroscope. The gyroscope further includes a second drive mass driven in a second drive motion along a second axis that is transverse to the first axis. The second drive motion generates a second sense motion of a second sense mass in response to rotation of the gyroscope. A drive spring system interconnects the two drive masses to couple the first and second drive motions so that a single drive mode can be implemented. The sense motion of each sense mass is along a third axis, where the third axis is transverse to the other axes. The sense motion is translational motion such the sense masses remain parallel to the surface of the substrate.
G01C 19/56 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p. ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis
G01C 19/5747 - Details de structure ou topologie les dispositifs ayant deux masses de détection en mouvement en opposition de phase chaque masse de détection étant reliée à une masse d'entraînement, p. ex. cadres d'entraînement
43.
Method for forming a packaged semiconductor device
A method of fabricating a packaged semiconductor device includes integrating a plurality of singulated semiconductor die in a die carrier, and forming one or more interconnect layers on the die carrier. The interconnect layers include at least one of conductive intra-layer structures and inter-layer structures coupled to contact pads on the plurality of singulated semiconductor die. A set of landing pads is formed coupled to a first subset of the contact pads via a first set of the conductive intra-layer structures and inter-layer structures. A set of probe pads is formed coupled to a second subset of the contact pads via a second set of the conductive intra-layer structures and inter-layer structures. The die carrier is singulated to form a plurality of packaged semiconductor devices. The set of probe pads is removed during the singulating the die carrier.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
A data processing system includes a boot read only memory (ROM) configured to store boot code; one time programmable (OTP) storage circuitry configured to store patch instructions; a random access memory (RAM); and a processor coupled to the boot ROM, the OTP storage circuitry, and the RAM. The processor is configured to: in response to a reset of the data processing system, copy one or more patch instructions from the OTP storage circuitry into the RAM, and during execution of the boot code, execute a patch instruction from the RAM in place of a boot instruction of the boot code.
G06F 9/00 - Dispositions pour la commande par programme, p. ex. unités de commande
G06F 15/177 - Commande d'initialisation ou de configuration
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
45.
Method and circuit for controlling turnoff of a semiconductor switching element
A circuit performs a method for controlling turn-off of a semiconductor switching element. The method includes determining at least one operating parameter for the semiconductor switching element during an operating cycle and determining a gate discharge current based on the at least one operating parameter. The method further includes supplying the gate discharge current to a gate of the semiconductor switching element during a subsequent operating cycle to turn off the semiconductor switching element.
H03K 17/04 - Modifications pour accélérer la commutation
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
46.
Integrated split gate non-volatile memory cell and logic structure
A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
A decryption key management system includes a memory, a memory controller, a decryption engine, and an on-chip crypto-accelerator. A key blob and an encrypted code are stored in the memory. The memory controller fetches the key blob and stores it in a memory buffer. The decryption engine fetches the key blob and decrypts it using an OTP key to generate a decryption key. The decryption key is used to decrypt the encrypted code and generate a decrypted code.
G06F 9/00 - Dispositions pour la commande par programme, p. ex. unités de commande
G06F 15/177 - Commande d'initialisation ou de configuration
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates
A process integration is disclosed for fabricating non-volatile memory (NVM) cells (105-109, 113-115) on a first flash cell substrate area (111) which are encapsulated in one or more planar dielectric layers (116) prior to forming an elevated substrate (117) on a second CMOS transistor area (112) on which high-k metal gate electrodes (119-120, 122-126, 132, 134) are formed using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
49.
Power switch with current limitation and zero direct current (DC) power consumption
Power switches with current limitation and zero Direct Current (DC) power consumption. In an embodiment, an integrated circuit includes switching circuitry coupled between a voltage supply node and a given one of a plurality of power domains, the switching circuitry configured to limit an amount of current drawn by the given power domain from the voltage supply node during a transition period, the switching circuitry further configured to consume zero DC power outside of the transition period. In another embodiment, a method includes controlling, via a switching circuit coupled between a voltage supply and an integrated circuit, an amount of current drawn by the integrated circuit from the voltage supply during a transition period; and causing the switching circuit to consume no static power during periods of time other than the transition period.
A level shifter includes a static precharge circuit. During a precharge phase, two nodes of the level shifter are precharged to a voltage at or near a reference voltage. During an evaluate phase, the level shifter maintains one of the nodes at the precharge voltage, while the other node is pulled to a different voltage level, such as at or near a ground voltage level, wherein the node that is maintained is selected based on the state of data input signals of the level shifter. The voltage at the nodes determines the state of the level shifter output signals, such that the output signals represent the input signals at a shifted voltage level. The level shifter can include a capacitor to feed forward a signal that causes the precharging to terminate more quickly.
A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
52.
Steering traffic among multiple network services using a centralized dispatcher
A network service dispatcher is provided that transparently navigates network traffic through network service appliances utilizing sub-session connection information generated in accordance with policies pertaining to a client-server session. The network service dispatcher intercepts a first data packet of a new session between two computer systems and generates sub-session connection information that navigates the data packet through one or more network service appliances in a manner transparent to the client or server. In turn, the network service dispatcher utilizes the sub-session connection information to navigate subsequent forward or reverse data packets in the session without performing a policy-based search for each data packet.
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
H04L 12/721 - Procédures de routage, p.ex. routage par le chemin le plus court, routage par la source, routage à état de lien ou routage par vecteur de distance
53.
Nonvolatile memory bitcell with inlaid high k metal select gate
A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates (118, 128) on a first substrate area (111) which are encapsulated in one or more planar dielectric layers (130) prior to forming in-laid high-k metal select gates and CMOS transistor gates (136, 138) in first and second substrate areas (111, 113) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata, which contains the tag, way, and line for a corresponding cache entry, along with a valid bit, allowing a memory access which hits a location in the cache to go directly to the cache's data array, avoiding the need to look up the address in the cache's tag array. When a cache line is evicted, any metadata referring to the line is marked as invalid. By reducing the number of tag lookups performed to access data in a cache's data array, the power that would otherwise be consumed by performing tag lookups is saved, thereby reducing power consumption of the information processing system, and the cache area needed to implement a cache having a desired level of performance may be reduced.
G06F 12/0895 - Mémoires cache caractérisées par leur organisation ou leur structure de parties de mémoires cache, p. ex. répertoire ou matrice d’étiquettes
55.
MEMS device with differential vertical sense electrodes
A MEMS device includes a first sense electrode and a first portion of a sense mass formed in a first structural layer, where the first sense electrode is fixedly coupled with the substrate and the first portion of the sense mass is suspended over the substrate. The MEMS device further includes a second sense electrode and a second portion of the sense mass formed in a second structural layer. The second sense electrode is spaced apart from the first portion of the sense mass in a direction perpendicular to a surface of the substrate, and the second portion of the sense mass is spaced apart from the first sense electrode in the same direction. A junction is formed between the first and second portions of the sense mass so that they are coupled together and move concurrently in response to an imposed force.
B81B 3/00 - Dispositifs comportant des éléments flexibles ou déformables, p. ex. comportant des membranes ou des lamelles élastiques
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
H01L 41/113 - Eléments piézo-électriques ou électrostrictifs à entrée mécanique et sortie électrique
G01P 15/125 - Mesure de l'accélérationMesure de la décélérationMesure des chocs, c.-à-d. d'une variation brusque de l'accélération en ayant recours aux forces d'inertie avec conversion en valeurs électriques ou magnétiques au moyen de capteurs à capacité
G01C 19/574 - Details de structure ou topologie les dispositifs ayant deux masses de détection en mouvement en opposition de phase
G01P 15/08 - Mesure de l'accélérationMesure de la décélérationMesure des chocs, c.-à-d. d'une variation brusque de l'accélération en ayant recours aux forces d'inertie avec conversion en valeurs électriques ou magnétiques
56.
Embedded software debug system with partial hardware acceleration
An embedded software debug system with partial hardware acceleration includes a computer that executes a debug software stack. The debug software stack includes high level operations. The system also includes a remote microcontroller electronically connected to the computer. The system further includes an embedded processor electronically connected to the remote microcontroller. The remote microcontroller receives an applet from the computer and executes the applet in conjunction with the computer executing the debug software stack to debug the embedded processor. The applet includes low level protocol operations including performance critical tight-loops precompiled into machine code. The debug software stack may include a stub that replaces the tight-loops of the applet. The computer may send the applet to the remote microcontroller in response to executing the stub.
A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension.
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
58.
Systems and methods for locking branch target buffer entries
A data processing system includes a processor configured to execute processor instructions and a branch target buffer having a plurality of entries. Each entry is configured to store a branch target address and a lock indicator, wherein the lock indicator indicates whether the entry is a candidate for replacement, and wherein the processor is configured to access the branch target buffer during execution of the processor instructions. The data processing system further includes control circuitry configured to determine a fullness level of the branch target buffer, wherein in response to the fullness level reaching a fullness threshold, the control circuitry is configured to assert the lock indicator of one or more of the plurality of entries to indicate that the one or more of the plurality of entries is not a candidate for replacement.
The embodiments described herein can provide improved signal feeding between hybrid couplers and associated transistors. As such, these embodiments can improve the performance of amplifiers and other such RF devices that utilize these components. In one embodiment a device includes a distribution network and a compensation resonator. The distribution network is configured to output a signal through a relatively wide output feedline. This relatively wide output feedline provides distributed signal feeding that can improve signal distribution and performance. The output feedline is coupled to the compensation resonator. In general, the compensation resonator is configured to resonate with the distribution network at the frequency band of the signal. Thus, the distribution network and compensation resonator together can provide improved signal distribution while maintaining performance at the frequencies of interest.
H03H 7/01 - Réseaux à deux accès sélecteurs de fréquence
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
A semiconductor device includes a substrate, a dielectric layer supported by the substrate, an interconnect adjacent the dielectric layer, the interconnect including a conduction material and a barrier material disposed along sidewalls of the interconnect between the conduction material and the dielectric layer, and a layer disposed over the interconnect to establish an interface between the conduction material, the barrier material, and the layer. A plate is disposed along a section of the interconnect to interrupt the interface.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
61.
Data processing system with protocol determination circuitry
A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal.
A method of forming an electronic component includes masking a lead frame to form a mask defining an exposed area, oxidizing the exposed area of the lead frame, wherein the mask inhibits oxidation of an unexposed area, and removing the mask from the lead frame following oxidizing. A lead frame can include a metal sheet patterned to define a pad region and leads. The metal sheet includes metal oxide in a select area. The pad region is substantially free of metal oxide.
H05K 3/28 - Application de revêtements de protection non métalliques
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus.
G06F 13/14 - Gestion de demandes d'interconnexion ou de transfert
G06F 3/00 - Dispositions d'entrée pour le transfert de données destinées à être traitées sous une forme maniable par le calculateurDispositions de sortie pour le transfert de données de l'unité de traitement à l'unité de sortie, p. ex. dispositions d'interface
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
64.
Method and system for facilitating viewing of information in a machine
Methods and systems for facilitating viewing of information by machine users associated with machines, such as vehicle users in vehicles, are disclosed. In one example embodiment, a method for facilitating viewing of first information comprises (a) determining second information concerning a viewing direction of the machine user, and (b) adapting at least one operation of at least one display device so as to display the first information. Also, in an additional example embodiment, the method further comprises (c) additionally determining whether a first condition has been met, where the first condition is indicative of whether the machine user has failed to view in a sufficient manner the first information for or during a first predetermined amount of time. Additionally, the method comprises (d), upon the first condition being additionally determined to have been met, one or both of (i) repeating (a), (b), and (c), and (ii) outputting a signal configured to be sensed by the machine user.
B60Q 1/00 - Agencement des dispositifs de signalisation optique ou d'éclairage, leur montage, leur support ou les circuits à cet effet
B60K 35/00 - Instruments spécialement adaptés aux véhiculesAgencement d’instruments dans ou sur des véhicules
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
A61B 5/18 - Dispositifs pour l'exécution des tests de capacité pour conducteurs de véhicules
B60K 28/06 - Dispositifs de sécurité pour la commande des ensembles de propulsion spécialement adaptés aux véhicules ou aménagés dans ceux-ci, p. ex. empêchant l'alimentation en carburant ou l'allumage en cas de danger sensibles à des conditions relatives au conducteur sensibles à l'incapacité du conducteur
A device includes a Doherty amplifier. The Doherty amplifier has a carrier path and a peaking path. The Doherty amplifier includes a carrier amplifier configured to amplify a signal received from the carrier path and a peaking amplifier configured to amplify a signal received from the peaking path. The device includes a resistive switch having a first terminal connected to the peaking path and a second terminal connected to a voltage reference, and a controller configured to set the resistive switch to a first resistance value when a power input of the Doherty amplifier is below a threshold and to a second resistance value when the power input of the Doherty amplifier is above the threshold.
A pressure sensor device is assembled by forming cavities on a surface of a metal sheet and then forming an electrically conductive pattern having traces and bumps over the cavities. An insulating layer is formed on top of the pattern and then processed to form exposed areas and die attach areas on the surface of the metal sheet. The exposed areas are plated with a conductive metal and then electrically connected to respective ones of the bumps. A gel is dispensed on the die attach areas and sensor dies are attached to respective die attach areas. One or more additional semiconductor dies are attached to the insulating layer and bond pads of these dies are electrically connected to the exposed plated areas. A molding compound is dispensed such that it covers the sensor die and the additional dies. The metal sheet is removed to expose outer surfaces of the bumps.
H01L 29/84 - Types de dispositifs semi-conducteurs commandés par la variation d'une force mécanique appliquée, p.ex. d'une pression
H01L 29/34 - Corps semi-conducteurs ayant des surfaces polies ou rugueuses les défectuosités étant sur la surface
H01L 29/74 - Dispositifs du type thyristor, p.ex. avec un fonctionnement par régénération à quatre zones
H01L 31/111 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par au moins trois barrières de potentiel, p.ex. photothyristor
Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
68.
Reducing microelectromechanical systems stiction by formation of a silicon carbide layer
A mechanism is provided for reducing stiction in a MEMS device by forming a near-uniform silicon carbide layer on silicon surfaces using carbon from TEOS-based silicon oxide sacrificial films used during fabrication. By using the TEOS as a source of carbon to form an antistiction coating, all silicon surfaces can be coated, including those that are difficult to coat using standard self-assembled monolayer (SAM) processes (e.g., locations beneath the proof mass). Controlled processing parameters, such as temperature, length of time for annealing, and the like, provide for a near-uniform silicon carbide coating not provided by previous processes.
Methods and systems are disclosed for adaptive erase recovery of non-volatile memory (NVM) cells within NVM systems. The adaptive erase recovery embodiments adaptively adjust the erase recovery discharge rate and/or discharge time based upon the size of NVM block(s) being erased and operating temperature. In one example embodiment, the erase recovery discharge rate is adjusted by adjusting the number of discharge transistors enabled within the discharge circuitry, thereby adjusting the discharge current for erase recovery. A lookup table is used to store erase recovery discharge rates and/or discharge times associated with NVM block sizes to be recovered and/or operating temperature. By adaptively controlling erase recovery discharge rates and/or times, the disclosed embodiments improve overall erase performance for a wide range of NVM block sizes while avoiding possible damage to high voltage circuitry within the NVM system.
G11C 11/34 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs
G11C 16/06 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
70.
Wire bonding capillary with working tip protrusion
A method for bonding a wire to a substrate includes forming a wire ball at a working tip of a capillary and contacting the wire ball to a substrate via the capillary. The method also includes driving a protrusion at the working tip of the capillary into contact with a region of the substrate surrounding the wire ball. A capillary for wire bonding includes a working face, an annular chamfer section, and a cylindrical bore offsetting the annular chamfer section from the working face. A capillary for wire bonding includes a capillary body comprising a working tip having a working face. The capillary body defines an axial passage extending from the working face along a longitudinal axis of the capillary. The axial passage includes a cylindrical bore extending internally from the working face, and a first annular chamfer having a major diameter defined by the cylindrical bore.
B23K 31/02 - Procédés relevant de la présente sous-classe, spécialement adaptés à des objets ou des buts particuliers, mais non couverts par un seul des groupes principaux relatifs au brasage ou au soudage
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
B23K 20/00 - Soudage non électrique par percussion ou par une autre forme de pression, avec ou sans chauffage, p. ex. revêtement ou placage
A method of fabricating an electronic apparatus includes forming an active layer over a wafer, forming a backscatter layer over the wafer, and directing radiation toward the wafer to anneal the active layer. The backscatter layer is not transparent to the radiation, more reflective than absorptive of the radiation, and positioned such that the backscatter layer inhibits exposure of the wafer to the radiation apart from the active layer.
H01L 21/22 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire
72.
Quad flat semiconductor device with additional contacts
A Quad Flat Package (QFP) semiconductor device has a multi-stepped lead frame for forming rows of external contacts. A semiconductor die is attached to a die pad of the lead frame and electrically connected to lead with bond wires. The die and bond wires are encapsulated with a mold compound and then multiple cuts are made to the lead frame to form the rows of external contacts.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/52 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
A semiconductor device includes a first substrate having opposing first and second main surfaces, a first die disposed on the first main surface of the first substrate, a first bond wire coupled to the first die, a first packaging material encapsulating the first die and the first bond wire, and a lead frame disposed on the first main surface of the first substrate and in electrical communication with the first bond wire. At least a portion of the lead frame extends outside of the packaging material. A top package includes first and second main surfaces and an electrical contact on the second main surface. The electrical contact is electrically connected to the lead frame and connects the top package to either the first die and/or external circuitry.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A transmission node for use in a wireless communication network includes a first CPRI unit for transmitting auxiliary data to a second CPRI unit in the transmission node. A memory unit stores control word data of the auxiliary data. A memory write block is connected between the first CPRI unit and the memory unit for writing the control word data to the memory unit based on a first set of frame timing signals received from the first CPRI unit. A memory read and merge block is connected to the memory unit for reading the control word data stored in the memory unit based on a second set of frame timing signals, merging the control word data with IQ data, and transmitting the merged auxiliary data to the second CPRI unit.
A transmission node for use in a wireless communication network includes a first register for storing a set of first mask bits, a second register for storing a set of second mask bits, and a mask switching block for multiplexing the set of first mask bits and the set of second mask bits and outputting the set of third mask bits. The transmission node further includes a CPRI unit with an auxiliary interface for receiving the set of third mask bits. An activation block is connected between the CPRI unit and the mask switching block for causing the mask switching block to output the set of second mask bits based on data in a current frame in the CPRI unit.
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p. ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
A Quad Flat Pack (QFP) type semiconductor device includes four corner tie bars that, instead of being trimmed, are used for power and/or ground connections, and alternatively, to control mold flow during the encapsulation step of the assembly process.
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
77.
Systems and methods for reducing power consumption in semiconductor devices
A method of making a first timing path includes developing a first design of the first timing path with a first logic circuit and a first functional cell, wherein the first functional cell comprises a first transistor that is spaced from a first well boundary. The timing path is analyzed to determine if the first timing path has positive timing slack. If the analyzed speed of operation shows positive timing slack, the design is changed to a modified design to reduce power consumption of the first timing path by moving the first transistor closer to the first well boundary. Also the first timing path is then built using the modified design to reduce power consumption of the first timing path by reducing leakage power consumption of the first transistor.
H03K 19/094 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs à semi-conducteurs utilisant des transistors à effet de champ
78.
Microelectronic packages having frontside thermal contacts and methods for the fabrication thereof
Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes forming one or more redistribution layers over an encapsulated die having a frontside bond pad area and a frontside passivated non-bond pad area. The redistribution layers are formed to have a frontside opening over the non-bond pad area of the encapsulated die. A primary heat sink body is provided in the frontside opening and thermally coupled to the encapsulated die. A contact array is formed over the redistribution layers and is electrically coupled to a plurality bond pads located on the frontside bond pad area of the encapsulated die.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
79.
Microelectronic packages and methods for the fabrication thereof
Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output.
A semiconductor device includes a semiconductor die having a first major surface and a second major surface opposite the first major surface, a first minor surface and a second minor surface opposite the first minor surface, a plurality of contact pads on the first major surface, and a notch which extends from the first minor surface and the second major surface into the semiconductor die. The notch has a notch depth measured from the second major surface into the semiconductor die, wherein the notch depth is less than a thickness of the semiconductor die, and a notch length measured from the first minor surface into the semiconductor die, wherein the notch length is less than a length of the semiconductor die measured between the first and second minor surfaces. The device includes a lead having a first end in the notch, and an encapsulant over the first major surface.
A system comprises a first plurality of flip-flop circuits, a second plurality of flip-flop circuits, and a gating control module. At a first processor frequency, gating of clock signals is enabled for the first and second plurality of flip-flop circuits. At a second processor frequency, gating of a first of the clock signals is disabled for the first plurality of flip-flop circuits and gating of a second of the clock signals is enabled for the second plurality of flip-flop circuits.
A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.
H03F 3/68 - Combinaisons d'amplificateurs, p. ex. amplificateurs à plusieurs voies pour stéréophonie
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
H01L 23/047 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base conductrice qui sert de support et en même temps de connexion électrique pour le corps semi-conducteur les autres connexions étant parallèles à la base
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
H01L 23/24 - Matériaux de remplissage caractérisés par le matériau ou par ses propriétes physiques ou chimiques, ou par sa disposition à l'intérieur du dispositif complet solide ou à l'état de gel, à la température normale de fonctionnement du dispositif
84.
Die-to-die inductive communication devices and methods
Embodiments of inductive communication devices include first and second galvanically isolated IC die and a dielectric structure. Each IC die has a coil proximate to a first surface of the IC die. The IC die are arranged so that the first surfaces of the IC die face each other, and the first coil and the second coil are aligned across a gap between the first and second IC die. The dielectric structure is positioned within the gap directly between the first and second coils, and a plurality of conductive structures are positioned in or on the dielectric structure and electrically coupled with the second IC die. The conductive structures include portions configured to function as bond pads, and the bond pads may be coupled to package leads using wirebonds. During operation, signals are conveyed between the IC die through inductive coupling between the coils.
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H02J 5/00 - Circuits pour le transfert d'énergie électrique entre réseaux à courant alternatif et réseaux à courant continu
H01F 19/08 - Transformateurs à polarisation magnétique, p. ex. pour le maniement d'impulsions
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
An integrated circuit includes a device of a first conductivity type formed in a first well; a voltage regulator configured to provide a bias voltage to the first well based on a first reference voltage which is generated using a first band gap reference generator; and a monitor circuit configured to compare a voltage of the first well to an upper limit and a lower limit of a first voltage range, wherein each of the upper limit and lower limit is provided using a second band gap reference generator, separate from the first band gap reference generator, wherein, in response to determining that the voltage of the first well is outside of the first voltage range, providing a first out of range indicator.
A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.
A method of making a semiconductor structure includes forming a select gate stack on a substrate. The substrate includes a non-volatile memory (NVM) region and a high voltage region. The select gate stack is formed in the NVM region. A charge storage layer is formed over the NVM region and the high voltage region of the substrate. The charge storage layer includes charge storage material between a bottom layer of dielectric material and a top layer of dielectric material. The charge storage material in the high voltage region is oxidized while the charge storage material in the NVM region remains unoxidized.
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
H01L 29/66 - Types de dispositifs semi-conducteurs
A packaged semiconductor device includes a lead frame having a plurality of leads; a semiconductor die mounted onto the lead frame; and an encapsulant surrounding the semiconductor die. At least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead includes a thin portion external to the encapsulant and a thick portion that is surrounded by the encapsulant, wherein the thin portion is thinner than the thick portion.
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
89.
Optimizing error parsing in an integrated development environment
A system to enable an integrated development environment to efficiently parse error expressions generated by tools used to generate processing environment-specific executable code, where the tools are external to the integrated development environment, is provided. The system groups error parsers configured to parse the error expressions into two groups: error parsers that handle output from a tool using a single output line of regular expression, and error parsers that require something more than a single output line of regular expression to determine the nature of an error. Embodiments of the system can determine whether a particular output regular expression should be analyzed by a selected set of the error parsers by comparing the output regular expression against a concatenated list of all the regular expressions corresponding to those error parsers that handle output from the tool using a single output line of regular expression.
A mechanism is provided for extending useable lifetimes of semiconductor devices that are subject to trapped charge carriers in a gate dielectric. Embodiments of the present invention provide heat to the gate dielectric region from one or more sources, where the heat sources are included in a package along with the semiconductor device. It has been determined that heat, when applied during a period when the channel region of a transistor is in accumulation mode or is not providing a current across the channel, can at least partially recover the device from trapped charge carrier effects. Embodiments of the present invention supply heat to the affected gate dielectric region using mechanisms available where the semiconductor device is used (e.g., in the field).
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
H01L 29/43 - Electrodes caractérisées par les matériaux dont elles sont constituées
G05F 1/10 - Régulation de la tension ou de l'intensité
91.
Debug method and device for handling exceptions and interrupts
A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.
Methods and systems are disclosed for frequency-domain amplitude normalization for symbol correlation in multi-carrier communication systems. Digital samples associated with input signals received from a communication medium are processed using a Fast Fourier Transform (FFT) to generate complex frequency components. Each complex frequency component is normalized with respect to its amplitude, and the frequency-domain, amplitude-normalized frequency components are multiplied with frequency components for reference symbol(s) to generate frequency-domain correlation values. These frequency-domain correlation values are analyzed to determine if a correlation exists between the amplitude-normalized frequency components and the predetermined reference frequency components. A correlation detection output is then generated that indicates whether or not a symbol synchronization was achieved. The disclosed embodiments are particularly useful for symbol correlation in received signals for power line communication (PLC) systems.
H04K 1/10 - Communications secrètes en utilisant deux signaux transmis simultanément ou successivement
H04L 27/28 - Systèmes utilisant des codes à fréquences multiples à émission simultanée de fréquences différentes, chacune représentant un élément de code
H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
93.
Frequency-domain frame synchronization in multi-carrier systems
Methods and systems are disclosed for frequency-domain frame synchronization for multi-carrier communication systems. Received signals are sampled and converted into frequency domain components associated with subcarriers within the multi-carrier communication signals. A sliding-window correlation (e.g., two-dimensional sliding window) is applied to the received symbols represented in the frequency domain to detect frame boundaries for multi-carrier signals. The sliding-window frame synchronization can be applied by itself or can be applied in combination with one or more additional frame synchronization stages. The disclosed embodiments are particularly useful for frame synchronization of multi-carrier signals in PLC (power line communication) systems.
H04K 1/10 - Communications secrètes en utilisant deux signaux transmis simultanément ou successivement
H04L 27/28 - Systèmes utilisant des codes à fréquences multiples à émission simultanée de fréquences différentes, chacune représentant un élément de code
H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
94.
Frequency-domain symbol and frame synchronization in multi-carrier systems
Methods and systems are disclosed for frequency-domain symbol and frame synchronization for multi-carrier communication systems. Received signals are sampled and converted into frequency components associated with subcarriers within the multi-carrier communication signals. Symbol synchronization is performed in the frequency domain by performing correlation(s) between frequency components of the received signal and frequency-domain synchronization symbol(s). After symbol synchronization, frame synchronization correlation is also performed in the frequency domain between frequency components of the received signal and frequency-domain synchronization symbol(s). The disclosed embodiments are particularly useful for symbol and frame synchronization in multi-carrier received signals for power line communication (PLC) systems and/or other harsh noisy communication environments.
H04K 1/10 - Communications secrètes en utilisant deux signaux transmis simultanément ou successivement
H04L 27/28 - Systèmes utilisant des codes à fréquences multiples à émission simultanée de fréquences différentes, chacune représentant un élément de code
A method entails providing a substrate with a structural layer having a thickness. A partial etch process is performed at locations on the structural layer so that a portion of the structural layer remains at the locations. An oxidation process is performed at the locations which consumes the remaining portion of the structural layer and forms an oxide having a thickness that is similar to the thickness of the structural layer. The oxide electrically isolates microstructures in the structural layer, thus producing a structure. A device substrate is coupled to the structure such that a cavity is formed between them. An active region is formed in the device substrate. A short etch process can be performed to expose the microstructures from an overlying oxide layer.
A multi-die sensor system comprises a package and one or more transducer dies mounted in the package. Each transducer die includes one or more transducers, a temperature control element, and temperature sensor. The temperature control element changes the temperature of at least a portion of the transducer during operation of the temperature control element. A temperature sensor senses the temperature of at least the portion of the transducer. An output circuitry die mounted in the package receives transducer signals and a sensed temperature signal from the temperature sensor.
G01K 7/00 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur
G01D 18/00 - Test ou étalonnage des appareils ou des dispositions prévus dans les groupes
G01D 3/036 - Dispositions pour la mesure prévues pour les objets particuliers indiqués dans les sous-groupes du présent groupe pour atténuer les influences indésirables, p. ex. température, pression sur les dispositions de mesure elles-mêmes
97.
Die fracture detection and humidity protection with double guard ring arrangement
An electronic apparatus includes a semiconductor substrate, outer and inner guard rings disposed along a periphery of the semiconductor substrate, and first and second contact pads electrically coupled to the outer and inner guard rings, respectively. The outer and inner guard rings are electrically coupled to one another to define a conduction path between the first and second contact pads. Each of the outer and inner guard rings includes an Ohmic metal layer having a plurality of gaps and further includes conductive bridges across the gaps. The gaps of the outer guard ring are laterally offset from the gaps of the inner guard ring such that the Ohmic metal layers of the outer and inner guard rings laterally overlap.
G01R 27/08 - Mesure de la résistance par mesure à la fois de la tension et de l'intensité
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
98.
Angular rate sensor with quadrature error compensation
An angular rate sensor includes a substrate, a drive mass flexibly coupled to the substrate, and a sense mass suspended above the substrate and flexibly coupled to the drive mass via flexible support elements. An electrode structure is mechanically coupled to, but electrically isolated from, the drive mass and is spaced apart from the substrate so that it is not in contact with the substrate. The electrode structure is configured to produce a signal that indicates movement of the sense mass relative to the electrode when the sensor is subjected to angular velocity. When the angular rate sensor experiences quadrature error, the drive mass, the sense mass, and the electrode structure move together relative to the sense axis. Since the sense mass and the electrode structure move together in response to quadrature error, there is little relative motion between the sense mass and the electrode structure so that quadrature error is largely eliminated.
G01C 19/5762 - Details de structure ou topologie les dispositifs ayant une seule masse de détection la masse de détection étant reliée à une masse d'entraînement, p. ex. cadres d'entraînement
G01C 19/5712 - Dispositifs sensibles à la rotation utilisant des masses vibrantes, p. ex. capteurs vibratoires de vitesse angulaire basés sur les forces de Coriolis utilisant des masses entraînées dans un mouvement de rotation alternatif autour d'un axe les dispositifs comportant une structure micromécanique
G01C 19/574 - Details de structure ou topologie les dispositifs ayant deux masses de détection en mouvement en opposition de phase
G01C 19/5747 - Details de structure ou topologie les dispositifs ayant deux masses de détection en mouvement en opposition de phase chaque masse de détection étant reliée à une masse d'entraînement, p. ex. cadres d'entraînement
A semiconductor package has a substrate with a solder mask layer, and upper and lower surfaces. Conductive traces and electrical contacts are formed on the substrate, and vias are formed in the substrate to electrically connect the conductive traces and electrical contacts. A semiconductor die is attached on the upper surface of the substrate. A mold cap is formed on the upper surface of the substrate and covers the die and the conductive traces. The mold cap includes a mold body having clipped corners and extensions that extend from each of the clipped corners. The extensions and clipped corners help prevent package cracking.
A high density, low power, high performance information system, method and apparatus are described in which perpendicularly oriented processor and memory die stacks (130, 140, 150, 160, 170) include integrated deflectable MEMS optical beam waveguides (e.g., 190) at each die edge to provide optical communications (182-185) in and between die stacks by supplying deflection voltages to a plurality of deflection electrodes (195-197) positioned on and around each MEMS optical beam waveguide (193-194) to provide two-dimensional alignment and controlled feedback to adjust beam alignment and establish optical communication links between die stacks.
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
G02B 6/35 - Moyens de couplage optique comportant des moyens de commutation
G02B 26/08 - Dispositifs ou dispositions optiques pour la commande de la lumière utilisant des éléments optiques mobiles ou déformables pour commander la direction de la lumière
