Micron Technology, Inc.
United States of America
New patents and trademarks in the last week
Last updated : 2026-04-18
Summary
Patents |
Trademarks |
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29 | 0 |
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Viewing 1 - 29 of 29
trademarks
patents
| # | ID | Jurisdiction | Title |
|---|---|---|---|
| 1 | G12602189 |
|
Selecting superblock partitions for scanning in memory devices |
| 2 | 18914477 |
|
UNALIGNED PARTITION TRACKING IN MEMORY DEVICES |
| 3 | 19354508 |
|
REDUCING RESISTANCE IN MEMORY SYSTEMS |
| 4 | 18916497 |
|
APPARATUSES, SYSTEMS, AND METHODS FOR STORING METADATA IN A MEMORY DEVICE |
| 5 | 19327768 |
|
SYSTEMS AND METHODS FOR REDUCING ELECTRICAL STRESS OF SWITCHING DEVICE |
| 6 | 19418795 |
|
MICROELECTRONIC DEVICES INCLUDING CAP STRUCTURES, AND RELATED ELECTRONIC SYSTEMS AND METHODS |
| 7 | 19337784 |
|
SYSTEMS AND METHODS FOR ADJUSTABLE POLLING OF REFRESH FLAG BASED ON TRAFFIC TO MEMORY DEVICE |
| 8 | 19418866 |
|
NANO THROUGH SUBSTRATE VIAS FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS |
| 9 | 19333341 |
|
TSV TO COMMAND DECODER CONNECTION FOR HIGHER BANDWIDTHS |
| 10 | 19418843 |
|
MICROELECTRONIC DEVICES INCLUDING STACK STRUCTURES HAVING STRENGTHENED INTERMEDIATE REGIONS OF ASSOCIATED INSULATIVE STRUCTURES, AND RELATED SYSTEMS |
| 11 | 19306157 |
|
OPTIMIZED DATA COMPRESSION WITH REDUCED PADDING |
| 12 | 19345949 |
|
THERMAL MITIGATION FOR MULTI-CHIP MEMORY SYSTEMS |
| 13 | 19369064 |
|
REPEATER SCHEME FOR INTER-DIE SIGNALS IN MULTI-DIE PACKAGE |
| 14 | 18913733 |
|
RELIABILITY ENABLED HARD INFORMATION DECODER |
| 15 | 18913707 |
|
HARD INFORMATION DECODER AIDED BY A SOFT INFORMATION DECODER |
| 16 | 19305064 |
|
CORRUGATED SIDEWALL STRUCTURE FOR MEMORY DEVICE |
| 17 | 18913790 |
|
DECODING DATA USING A CONSTRAINED BIT-FLIPPING TECHNIQUE |
| 18 | 19354160 |
|
TRANSISTOR CHANNEL COMPRESSION FOR SEMICONDUCTOR DEVICES |
| 19 | 19342169 |
|
CORRECTIVE READ TECHNIQUES FOR MEMORY SYSTEMS |
| 20 | 18914480 |
|
MERGING BLOCK FAMILIES IN MEMORY DEVICES |
| 21 | 18775715 |
|
NEAR-CACHE COMPUTE |
| 22 | 18911867 |
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CONDITIONAL BLOCK FOLDING DELAY DURING BOOT-UP |
| 23 | 19177901 |
|
MEMORY DEVICES HAVING STAGGERED OPERATIONS FOR ERROR CHECK AND SCRUB REPORTS |
| 24 | 19422820 |
|
ADAPTIVE OPTIMIZATION OF ERROR-HANDLING FLOWS IN MEMORY DEVICES |
| 25 | 19422821 |
|
VERTICALLY STACKED STORAGE NODES AND ACCESS DEVICES WITH HORIZONTAL ACCESS LINES |
| 26 | 19418814 |
|
MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS, AND METHODS OF FORMING THE SAME |
| 27 | 19177962 |
|
MANAGING POWER LOSS RECOVERY USING A DIRTY SECTION WRITE POLICY FOR AN ADDRESS MAPPING TABLE IN A MEMORY SUB-SYSTEM |
| 28 | 18916521 |
|
APPARATUSES, SYSTEMS, AND METHODS FOR STORING METADATA IN A MEMORY DEVICE |
| 29 | 19357289 |
|
DETECTING RESOURCE LEAKAGE IN A MEMORY SUB-SYSTEM |
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