Micron Technology, Inc.

United States of America

New patents and trademarks in the last week

Last updated : 2026-10-17

Summary

Patents

Trademarks
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trademarks


patents

# ID Jurisdiction Title
1 19176554 Method Used In Forming Memory Circuitry
2 19175454 HOST SYSTEM USING AN ARRAY PAIR TO ACCESS A NON-VOLATILE MEMORY DEVICE
3 19466234 MEMORY DEVICE WITH DYNAMIC PROCESSING LEVEL CALIBRATION
4 19174807 PROGRAM VOLTAGE ADJUSTMENT FOR WEAK DIES IN A MEMORY SUB-SYSTEM
5 19707689 METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICE STRUCTURES
6 19717251 ATOMICITY ASSURANCE IN WRITE THROUGH MODE
7 19663807 CONFIGURABLE PROGRAM VERIFY LEVELS ACCORDING TO PROGRAM-ERASE CYCLES AT A MEMORY SYSTEM
8 19442913 METHODS OF FORMING A DEVICE, AND RELATED DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
9 19175572 SCAN AHEAD AND ANALYSIS OF NVMe COMMAND SUBMISSION QUEUES ON HOST SYSTEM
10 19635213 VOLTAGE-DEPENDENT CONFIGURATIONS FOR MEMORY SYSTEMS
11 19467429 MEMORY DEVICE INCLUDING CONTROL GATES HAVING TUNGSTEN STRUCTURE
12 19718435 MEMORY SUB-SYSTEM ENCLOSURE
13 19467622 OVERWRITING DATA
14 19535135 POST PACKAGING REPAIR IN MEMORY
15 19467604 AUTHENTICATION-BASED AND HARDWARE-BASED LOCKDOWN FEATURES FOR A MEMORY SYSTEM
16 19570944 DYNAMIC PAGE MAPPING USING HEADER TO IDENTIFY COMPRESSED DATA
17 US2026022901 SCAN AHEAD AND ANALYSIS OF NVMe COMMAND SUBMISSION QUEUES ON HOST SYSTEM FOR COMMAND PRIORITIZATION
18 US2026022070 NON-BINARY FULLY DIFFERENTIAL SAR ADC FOR AI-NAND
19 US2026022882 HIGH-BANDWIDTH MEMORY DEVICES WITHOUT THROUGH SUBSTRATE VIAS AND ASSOCIATED SYSTEMS AND METHODS
20 US2026021908 STRESS LINER INTEGRATION IN MEMORY DEVICES
21 US2026018776 MICROELECTRONIC DEVICES, AND RELATED METHODS AND MEMORY DEVICES
22 US2026022393 SCAN AHEAD AND ANALYSIS OF NVMe COMMAND SUBMISSION QUEUES ON HOST SYSTEM
23 US2026022519 HOST SYSTEM USING AN ARRAY PAIR TO ACCESS A NON-VOLATILE MEMORY DEVICE
24 19177839 APPARATUSES, SYSTEMS, AND METHODS FOR DATA STEERING AND COLUMN ADDRESS REMAPPING FOR METADATA STORAGE
25 19174117 TERMINATING ERROR CORRECTION USING PARTIAL SYNDROME CALCULATIONS
26 19718403 PROBABLISTICALLY DETERMINING MEMORY PORTIONS FOR SELECT GATE SCANNING
27 19467011 INFORMATION LOGGING VIA A SIDEBAND WITHIN A MEMORY SYSTEM
28 19179226 ENHANCED MULTI-WORDLINE RAIN IN A MEMORY SUB-SYSTEM
29 19719879 Integrated Assemblies, and Methods of Forming Integrated Assemblies
30 19635185 MEMORY REPLACEMENT TECHNIQUES FOR MEMORY SUBSYSTEMS
31 19465324 APPARATUSES, SYSTEMS, AND METHODS FOR ECS ADDRESS GENERATION AND CONTROL
32 19465577 DATA IDENTITY RECOGNITION FOR SEMICONDUCTOR DEVICES
33 19466865 HYBRID DEVICE WITH BACKSIDE POWER DELIVERY NETWORKS AND ASSOCIATED SYSTEMS AND METHODS
34 19720043 PAGE-LEVEL AND STRIPE-BASED READ ERROR HANDLING
35 19464410 MICROELECTRONIC DEVICES AND ASSOCIATED SYSTEMS AND METHODS
36 19577883 PILLAR STRUCTURE FOR MEMORY DEVICES
37 19175585 SCAN AHEAD AND ANALYSIS OF NVMe COMMAND SUBMISSION QUEUES ON HOST SYSTEM FOR COMMAND ABORT
38 19467103 DICE FAILURE CORRECTION USING PARITY DICE
39 19177363 BATCHING MEMORY COMMANDS VIA A GRID OF QUEUE PAIRS
40 19467136 REGULATORS HAVING IMPROVED TRANSIENT RESPONSE
41 19637480 ROM FAULT CHECK DURING MEMORY BOOT
42 19179148 Memory Circuitry And Methods Used In Forming Memory Circuitry
43 19467633 OVERWRITING PAGES OF DATA
44 19638976 INTERFACES FOR COUPLING SEMICONDUCTOR SYSTEMS WITH SOLDER-MASKED SUBSTRATES
45 19635236 REPAIR SCHEME TESTING IN A MEMORY SYSTEM
46 19177804 APPARATUSES, SYSTEMS, AND METHODS FOR DATA STEERING AND COLUMN ADDRESS REMAPPING FOR METADATA STORAGE
47 US2026022169 BURST POWER FOR ASYNCHRONOUS POWER LOSS IN A MEMORY DEVICE
48 US2026022171 PROGRAM VOLTAGE ADJUSTMENT FOR WEAK DIES IN A MEMORY SUB-SYSTEM
49 US2026022727 SCAN AHEAD AND ANALYSIS OF NVMe COMMAND SUBMISSION QUEUES ON HOST SYSTEM FOR COMMAND ABORT
50 US2026022518 BATCHING MEMORY COMMANDS VIA A GRID OF QUEUE PAIRS