Micron Technology, Inc.

United States of America

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Last updated : 2026-02-07

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# ID Jurisdiction Title
1 19267888 INTERFACE HAVING SELECTABLE EQUALIZATION MODES
2 18790752 DIRECT ACCESS OF A DATASET IN A FABRIC-ATTACHED MEMORY FOR A DISTRIBUTED WORKFLOW
3 19265499 MEMORY DEVICES WITH WEAVED DIGIT LINES
4 19254596 MICROELECTRONIC DEVICES AND RELATED MEMORY DEVICES
5 18788681 MEMORY SUB-SYSTEM INCOMPLETE SHUTDOWN DEBUGGING
6 19357659 RAID REGION ALIGNMENT FOR FDP COMPLIANT SSD
7 19269633 METHODS OF CONSTRUCTION OF CROSS-POINT MEMORY STRUCTURES
8 19302943 TRIGGERING A REFRESH FOR NON-VOLATILE MEMORY
9 18789974 DYNAMIC MEMORY OPERATIONS BASED ON HOST PROFILE
10 19356779 Memory Circuitry Comprising Strings of Memory Cells and Method Used in Forming a Memory Array Comprising Strings of Memory Cells
11 19283750 APPARATUSES AND METHODS FOR MULTIPLE POWER DOWN AND EXIT MODES IN MEMORY DEVICES
12 19280029 AUTO CALIBRATED READ WITH WORD LINE LINEAR-RAMP AND EFFICIENT PROGRAM VERIFICATION
13 19281350 APPARATUSES, SYSTEMS AND METHODS FOR DATA BUFFER CONTROL
14 19353893 SHARING DATA BETWEEN COMPUTING DEVICES
15 19305335 DATA DEFRAGMENTATION CONTROL
16 19281264 PARTIAL BLOCK ALLOCATIONS FOR MEMORY SYSTEMS
17 19234153 SEMICONDUCTOR DEVICE WITH INDEPENDENT SOURCE-DRAIN REGION PROFILES FOR LOW VOLTAGE AND HIGH VOLTAGE FINFET TRANSISTORS
18 19293013 WRITE BOOSTER PINNING
19 18791028 HARDWARE-PROTECTED SYSTEM MEASUREMENTS
20 19274323 DETECTION AND RETIREMENT OF DEFECTIVE BLOCKS
21 18791243 READ DISTURB SCAN USING FAILED BIT COUNT
22 19274342 HYBRID BONDING TECHNIQUES FOR STACKED SEMICONDUCTOR SYSTEMS
23 19274336 STATUS INDICATIONS FOR STORING DATA TO A MEMORY SYSTEM VIA COMMAND HEADERS
24 19254982 MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ASSOCIATED SYSTEMS AND METHODS
25 18791202 LIMITED WRITE COMPLETION RETURN FOR RATE CONTROL IN A MEMORY SUB-SYSTEM WITH SINGLE-LEVEL CELL MEMORY CACHING
26 18791206 MEMORY DEVICE HAVING IN-TIER ACCESS LINE DRIVERS
27 19276789 MANAGED MEMORY PERFORMANCE CONTROL
28 18789120 SHUNTING NETWORKS FOR ACCESS LINES IN A MEMORY ARRAY
29 18789361 ENHANCED ERROR HANDLING IN MEMORY SYSTEMS
30 19277654 MEMORY DEVICES INCLUDING CHARGE TRAP MEMORY CELLS AND FERROELECTRIC MEMORY CELLS
31 19280819 DESTINATION BASED MEDIA MANAGEMENT OPERATION
32 19280842 DIE SIDE INTERCONNECT
33 18788467 TEMPERATURE-BASED READ DISTURB OPERATIONS
34 19254569 MICROELECTRONIC DEVICES AND RELATED MEMORY DEVICES
35 19254462 MICROELECTRONIC DEVICES, AND RELATED METHODS AND MEMORY DEVICES
36 19269730 ERROR HANDLING AVOIDANCE
37 18790870 PLATE ROUTING ARCHITECTURE FOR MULTIPLE DECK MEMORY
38 19278689 MEMORY DIE BONDING IN STACKED SEMICONDUCTOR SYSTEMS
39 18789610 MEMORY SUB-SYSTEM FOR BLOCK STRIPE SELECTION AND TESTING
40 19269772 TRIGGER RATE IMPROVEMENT POST PROGRAM SUSPEND
41 18789604 DETERMINING DATA MIGRATION PRIORITIES IN A MEMORY SUB-SYSTEM
42 19246417 Selectable Wordline Driver
43 19255367 METHOD OF FABRICATING SEMICONDUCTOR PACKAGES TO MITIGATE VOIDS THEREIN
44 19188851 Testmode Revision Control Circuitry
45 19269560 WORDLINE CONTACT ISOLATION STRUCTURE AND METHOD
46 18788961 SENSE AMP BALANCING COMPONENT
47 19279582 RIVET ISOLATION AND METHOD
48 18790803 MEMORY SUBSYSTEM SUPPORTED QUALITY OF SERVICE LEVELS FOR VIRTUALIZED STORAGE
49 19271624 APPARATUSES, SYSTEMS, AND METHODS TO REFRESH MULTIPLE MEMORY BANKS
50 19352269 TEMPORARY PARITY BUFFER ALLOCATION FOR ZONES IN A PARITY GROUP
51 19281210 PANEL-LEVEL FORMATION OF LOGIC-UPPERMOST SEMICONDUCTOR DEVICE ASSEMBLIES WITH MULTI-RETICLE DIES AND RETICLE-BRIDGING CONDUCTORS
52 19281222 ENHANCED GARBAGE COLLECTION AT A MEMORY SYSTEM
53 19281012 SEMICONDUCTOR DEVICE ASSEMBLIES WITH MULTI-RETICLE DIES AND RETICLE-BRIDGING CONDUCTORS
54 19222197 MULTI-DIMENSION METAL-INSULATOR-METAL CAPACITOR
55 18791079 Method and Apparatus for Sharing a Sense Amplifier between Memory Cells of a Memory Device
56 18791192 RATE CONTROL IN A MEMORY SUB-SYSTEM WITH SINGLE-LEVEL CELL MEMORY CACHING
57 19272432 ROW ERROR MONITORING FOR MEMORY SYSTEMS
58 18791178 ELASTIC CONFIGURATION OF DATA RATE CONTROL PARAMETERS IN A MEMORY SUB-SYSTEM WITH SINGLE-LEVEL CELL MEMORY CACHING
59 19281140 LOGIC-UPPERMOST SEMICONDUCTOR DEVICE ASSEMBLIES WITH RECONSTITUTED WAFERS AND MULTI-RETICLE DIES COUPLED BY RETICLE-BRIDGING CONDUCTORS
60 19274883 INDUCTOR-BASED VOLTAGE CONVERTERS FOR MEMORY APPARATUSES
61 18791158 PROGRAM AND READ OPERATIONS USING UNBALANCED READ WINDOW BUDGETS ACROSS PAGE TYPES
62 19261333 Usage-Based-Disturbance Pattern Detector
63 19275754 THERMAL STRUCTURES FOR HYBRID BONDING
64 19275751 VOLTAGE DRIVERS WITH CONFIGURABLE PULL-UP AND PULL-DOWN AMPLIFIERS
65 19283136 SINGLE COMMAND SHADOW PROGRAMMING
66 19282049 RIVET STRUCTURE AND METHOD
67 18789059 UNIT CELL STRUCTURE FOR SPIN ORBIT TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY
68 19272478 CURVED PLUG FOR PROTECTION OF BACKSIDE SOURCE FORMATION OF VERTICAL PLANAR MEMORY CELLS
69 19275748 PLUG FOR PROTECTION OF BACKSIDE SOURCE FORMATION OF VERTICAL PLANAR MEMORY CELLS
70 18790036 APPARATUSES SYSTEMS AND METHODS FOR LINKED BANK REFRESH
71 19276405 Controlling Error Reporting for Usage-Based-Disturbance Mitigation
72 18791349 PADDING MEMORY BY PROGRAMMING USER DATA IN PARALLEL
73 18792436 IN-MEMORY QUERY PROCESSING USING PROBABILISTIC DATA STRUCTURES
74 19276420 THREE-DIMENSIONAL MEMORY STRUCTURES, AND RELATED METHODS OF OPERATION AND CONSTRUCTION
75 19265549 MEMORY DEVICE INCLUDING CAPACITIVE SENSING CIRCUIT
76 US2025036645 MICROELECTRONIC DEVICES, AND RELATED METHODS OF FORMING MICROELECTRONIC DEVICES
77 US2025036220 ROW AND COLUMN ACCESS OF MATRICES STORED IN MEMORY
78 US2025037547 CROSS-POINT MEMORY STRUCTURES, AND RELATED METHODS OF CONSTRUCTION AND OPERATION
79 US2025037770 APLHARATUSES AND METHODS FOR INDIVIDUALIZATION OF ACTIVATION COUNTER.INITIALIZATION
80 US2025037101 MEMORY RESET READ USING PRIORITY-BASED BLOCK POOL
81 US2025039541 SEMICONDUCTOR DEVICE ASSEMBLIES WITH MULTI-RETICLE DIES AND RETICLE-BRIDGING CONDUCTORS
82 US2025039533 PROBABLISTICALLY DETERMINING MEMORY PORTIONS FOR SELECT GATE SCANNING
83 US2025039750 MANAGED MEMORY PERFORMANCE CONTROL
84 US2025039508 SELECTIVE USAGE OF CONCURRENT READ SCANS FOR READ DISTURB SCANNING
85 US2025038894 MICROELECTRONIC DEVICES AND RELATED MEMORY DEVICES
86 US2025039503 WORD LINE GROUP DEPENDENT READ RECOVERY PERIOD RAMP-DOWN
87 US2025039760 SYSTEM FOR HANDLING REPEATED PROGRAMMING ERRORS
88 US2025039762 SINGLE COMMAND SHADOW PROGRAMMING
89 US2025039757 MEMORY SUB-SYSTEM FOR BLOCK STRIPE SELECTION AND TESTING
90 US2025039484 PARTIAL BLOCK ALLOCATIONS FOR MEMORY SYSTEMS
91 US2025039487 DEPOSITING CARBON FILMS USING A SINGLE PRECURSOR
92 US2025039486 MEMORY DIE BONDING IN STACKED SEMICONDUCTOR SYSTEMS
93 US2025039296 POWER LOSS NOTIFICATION POWER PROCESSING FOR MEMORY SYSTEMS
94 US2025038722 SUB BLOCK ACCESS VIA CONFIGURING A DATA SIZE OF LOGICAL BLOCK ADDRESSING IN A MEMORY SUB-SYSTEM
95 US2025037845 ERROR HANDLING AVOIDANCE
96 US2025038706 HYBRID BONDING TECHNIQUES FOR STACKED SEMICONDUCTOR SYSTEMS
97 US2025036332 MICROELECTRONIC DEVICES, AND RELATED METHODS OF FORMING MICROELECTRONIC DEVICES
98 US2025037421 MICROELECTRONIC DEVICES AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
99 US2025038512 MEMORY CELL FORMATION IN PIER & PILLAR ARCHITECTURE
100 US2025039630 GARBAGE COLLECTION WITH REDUCED BUFFER USAGE