MicroLink Devices, Inc.

United States of America

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IPC Class
H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof 9
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof 6
H01L 31/0687 - Multiple junction or tandem solar cells 6
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof 5
B60L 8/00 - Electric propulsion with power supply from forces of nature, e.g. sun or wind 4
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Status
Pending 3
Registered / In Force 34
Found results for  patents

1.

MOSAIC COVERGLASS FOR SPACE POWER MODULES

      
Application Number 19188350
Status Pending
Filing Date 2025-04-24
First Publication Date 2025-10-30
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Youtsey, Christopher
  • Drees, Martin

Abstract

A space power module (SPM) can include a plurality of solar cells, a plurality of interconnect elements, and a plurality of planar pieces of cover glass forming a mosaic sheet of cover glass overlaying light receiving surfaces of the plurality of solar cells. Each interconnect element can connect two adjacent solar cells of the plurality of solar cells and can be arranged in-plane relative to the two adjacent cells. The plurality of planar pieces of cover glass can cover at least portions of the plurality of interconnect elements.

IPC Classes  ?

  • H10F 19/80 - Encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells
  • H10F 19/35 - Structures for the connecting of adjacent photovoltaic cells, e.g. interconnections or insulating spacers
  • H10F 71/00 - Manufacture or treatment of devices covered by this subclass

2.

FLEXIBLE SPACE SOLAR SHEETS AND METHODS FOR THEIR MANUFACTURE AND USE

      
Application Number 18644708
Status Pending
Filing Date 2024-04-24
First Publication Date 2024-10-31
Owner Microlink Devices, Inc. (USA)
Inventor
  • Youtsey, Christopher
  • Witting, Ian

Abstract

Systems and methods are presented including solar cells or solar sheets having textured coversheets that provide increased light collection efficiency. Some embodiments include a textured solar coversheet configured for installation on a surface of a space-based vehicle or on a surface of a component of a space-based vehicle. The textured solar sheet includes a plurality of solar cells, a polymer coversheet to which the plurality of solar cells are attached, and an ultraviolet rejection film disposed over the polymer coversheet.

IPC Classes  ?

  • H01L 31/054 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means
  • H01L 31/0392 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates
  • H01L 31/0445 - PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

3.

SOLAR SHEETS WITH IMPROVED LIGHT COUPLING AND METHODS FOR THEIR MANUFACTURE AND USE

      
Application Number 17962101
Status Pending
Filing Date 2022-10-07
First Publication Date 2023-06-08
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Youtsey, Christopher
  • Osowski, Mark
  • Tatavarti, Rao

Abstract

Systems and methods are presented including solar cells or solar sheets having textured coversheets that provide increased light collection efficiency. Some embodiments include a textured solar sheet configured for installation on a surface of a UAV or on a surface of a component of a UAV. The textured solar sheet includes a plurality of solar cells and a polymer layer to which the plurality of solar cells are attached. Some embodiments include a kit for supplying solar power in a battery-powered or fuel cell powered unmanned aerial vehicle (UAV) by incorporating flexible, textured solar cells into a component of a UAV, affixing flexible, textured solar cells to a surface of a UAV, or affixing flexible, textured solar cells to a surface of a component of a UAV. The kit also includes a power conditioning system configured to operate the solar cells within a desired power range and configured to provide power having a voltage compatible with an electrical system of the UAV.

IPC Classes  ?

  • B64U 50/31 - Supply or distribution of electrical power generated by photovoltaics
  • H01L 31/0392 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates
  • H01L 31/054 - Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means

4.

Strain balanced direct bandgap aluminum indium phosphide quantum wells for light emitting diodes

      
Application Number 17651838
Grant Number 12581772
Status In Force
Filing Date 2022-02-21
First Publication Date 2022-08-25
Grant Date 2026-03-17
Owner
  • Alliance for Energy Innovation, LLC (USA)
  • MicroLink Devices, Inc. (USA)
  • South Dakota Board of Regents (USA)
Inventor
  • Alberi, Kirstin
  • Stender, Christopher Leo
  • Ahrenkiel, Scott Phillip

Abstract

1-xP and may be grown on commercially available GaAs substrates.

IPC Classes  ?

  • H10H 20/815 - Bodies having stress relaxation structures, e.g. buffer layers
  • H10H 20/811 - Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
  • H10H 20/812 - Bodies having quantum effect structures or superlattices, e.g. tunnel junctions within the light-emitting regions, e.g. having quantum confinement structures
  • H10H 20/824 - Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
  • H10H 20/81 - Bodies

5.

Methods for fabricating thin film III-V compound solar cell

      
Application Number 17170133
Grant Number 11901476
Status In Force
Filing Date 2021-02-08
First Publication Date 2021-10-21
Grant Date 2024-02-13
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Hillier, Glen
  • Vu, Duy Phach
  • Tatavarti, Rao
  • Youtsey, Christopher
  • Mccallum, David
  • Martin, Genevieve

Abstract

The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0687 - Multiple junction or tandem solar cells

6.

Deep photoenhanced wet material etching using high-power ultraviolet light emitting diodes

      
Application Number 16044448
Grant Number 10685843
Status In Force
Filing Date 2018-07-24
First Publication Date 2019-03-21
Grant Date 2020-06-16
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Youtsey, Christopher
  • Mccarthy, Robert

Abstract

Methods and systems for etching a substrate using photoenhanced wet etching techniques are described. At least one light emitting diode source is used to create a high intensity of ultraviolet light at the surface of the substrate or at one or more layers formed on the substrate. Etching rates in GaN substrates and GaN layers are improved by an order of magnitude over conventional systems. Systems and methods for forming a device structure free of a substrate are described. The device structure is grown or applied over a release layer on a substrate. The device structure is exposed to photoenhanced wet etch environments to vertically and laterally etch the release layer to separate the device structure from the substrate.

IPC Classes  ?

  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/3063 - Electrolytic etching
  • H01L 31/0236 - Special surface textures
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers

7.

Systems and methods for perforation and ohmic contact formation for GaN epitaxial lift-off using an etch stop layer

      
Application Number 16044479
Grant Number 10522363
Status In Force
Filing Date 2018-07-24
First Publication Date 2019-03-21
Grant Date 2019-12-31
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Youtsey, Christopher
  • Mccarthy, Robert
  • Reddy, Rekha

Abstract

Methods and systems for forming a device structure free of a substrate are described. Exemplary embodiments include a device structure comprising of device layers, a release layer, an etch stop layer, and a substrate. The device structure is exposed to photoenhanced wet etch environments to vertically and laterally etch the release layer to separate the device layers from the substrate. The device structure can include a contact layer, an etch stop layer, or both in some embodiments.

IPC Classes  ?

  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/3063 - Electrolytic etching
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 31/0236 - Special surface textures
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers

8.

DEEP PHOTOENHANCED WET MATERIAL ETCHING USING HIGH-POWER ULTRAVIOLET LIGHT EMITTING DIODES

      
Application Number US2018043564
Publication Number 2019/023281
Status In Force
Filing Date 2018-07-24
Publication Date 2019-01-31
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Youtsey, Christopher
  • Mccarthy, Robert

Abstract

Methods and systems for etching a substrate using photoenhanced wet etching techniques are described. At least one light emitting diode source is used to create a high intensity of ultraviolet light at the surface of the substrate or at one or more layers formed on the substrate. Etching rates in GaN substrates and GaN layers are improved by an order of magnitude over conventional systems. Systems and methods for forming a device structure free of a substrate are described. The device structure is grown or applied over a release layer on a substrate. The device structure is exposed to photoenhanced wet etch environments to vertically and laterally etch the release layer to separate the device structure from the substrate.

IPC Classes  ?

  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/3063 - Electrolytic etching
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 31/0236 - Special surface textures
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers

9.

SYSTEMS AND METHODS FOR PERFORATION AND OHMIC CONTACT FORMATION FOR GAN EPITAXIAL LIFT-OFF USING AN ETCH STOP LAYER

      
Application Number US2018043571
Publication Number 2019/023282
Status In Force
Filing Date 2018-07-24
Publication Date 2019-01-31
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Youtsey, Christopher
  • Mccarthy, Robert
  • Reddy, Rekha

Abstract

Methods and systems for forming a device structure free of a substrate are described. Exemplary embodiments include a device structure comprising of device layers, a release layer, an etch stop layer, and a substrate. The device structure is exposed to photoenhanced wet etch environments to vertically and laterally etch the release layer to separate the device layers from the substrate. The device structure can include a contact layer, an etch stop layer, or both in some embodiments.

IPC Classes  ?

  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/3063 - Electrolytic etching
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 31/0236 - Special surface textures
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers

10.

Back-contact thin film semiconductor device structures and methods for their production

      
Application Number 15947683
Grant Number 11398575
Status In Force
Filing Date 2018-04-06
First Publication Date 2018-10-11
Grant Date 2022-07-26
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Youtsey, Christopher
  • Reddy, Rekha
  • Stender, Christopher

Abstract

Systems and methods taught herein provide thin film semiconductor devices such as thin film photovoltaic devices having via holes that enable electrical connection with a bottom surface of a topside contact of the thin film semiconductor device via the back side of the device (e.g., during mounting of the device). In some embodiments, the via holes are electrically insulated.

IPC Classes  ?

  • H01L 31/0463 - PV modules composed of a plurality of thin film solar cells deposited on the same substrate characterised by special patterning methods to connect the PV cells in a module, e.g. laser cutting of the conductive or active layers
  • H01L 31/048 - Encapsulation of modules
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0224 - Electrodes
  • H01L 31/0392 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

11.

BACK-CONTACT THIN FILM SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR THEIR PRODUCTION

      
Application Number US2018026599
Publication Number 2018/187775
Status In Force
Filing Date 2018-04-06
Publication Date 2018-10-11
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Youtsey, Christopher
  • Reddy, Rekha
  • Stender, Christopher

Abstract

Systems and methods taught herein provide thin film semiconductor devices such as thin film photovoltaic devices having via holes that enable electrical connection with a bottom surface of a topside contact of the thin film semiconductor device via the back side of the device (e.g., during mounting of the device). In some embodiments, the via holes are electrically insulated.

IPC Classes  ?

  • H01L 31/0224 - Electrodes
  • H01L 31/0392 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

12.

INTEGRATION OF HIGH-EFFICIENCY, LIGHTWEIGHT SOLAR SHEETS ONTO UNMANNED AERIAL VEHICLE FOR INCREASED ENDURANCE

      
Application Number US2017028108
Publication Number 2018/013193
Status In Force
Filing Date 2017-04-18
Publication Date 2018-01-18
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Chan, Raymond
  • Miyamoto, Haruki
  • Wibowo, Andree
  • Osowski, Mark
  • Youtsey, Christopher
  • Mccallum, David

Abstract

Some embodiments include a kit for supplying solar power in a battery-powered or fuel cell powered unmanned aerial vehicle (UAV) by incorporating flexible solar cells into a component of a UAV, affixing flexible solar cells to a surface of a UAV, or affixing flexible solar cells to a surface of a component of a UAV. The kit also includes a power conditioning system configured to operate the solar cells within a desired power range and configured to provide power having a voltage compatible with an electrical system of the UAV. Another embodiments include a solar sheet configured for installation on a surface of a UAV or on a surface of a component of a UAV. The solar sheet includes a plurality of solar cells and a polymer layer to which the plurality of solar cells are attached.

IPC Classes  ?

13.

High-efficiency, lightweight solar sheets

      
Application Number 15589342
Grant Number 10214295
Status In Force
Filing Date 2017-05-08
First Publication Date 2017-10-26
Grant Date 2019-02-26
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Chan, Raymond
  • Miyamoto, Haruki
  • Wibowo, Andree
  • Osowski, Mark
  • Youtsey, Christopher
  • Mccallum, David

Abstract

Some embodiments include a high efficiency, lightweight solar sheet. Some embodiments include a solar sheet configured for installation on a surface of a UAV or on a surface of a component of a UAV. The solar sheet includes a plurality of solar cells and a polymer layer to which the plurality of solar cells are attached. Some embodiments include a kit for supplying solar power in a battery-powered or fuel cell powered unmanned aerial vehicle (UAV) by incorporating flexible solar cells into a component of a UAV, affixing flexible solar cells to a surface of a UAV, or affixing flexible solar cells to a surface of a component of a UAV. The kit also includes a power conditioning system configured to operate the solar cells within a desired power range and configured to provide power having a voltage compatible with an electrical system of the UAV.

IPC Classes  ?

  • H01L 31/046 - PV modules composed of a plurality of thin film solar cells deposited on the same substrate
  • B64D 27/24 - Aircraft characterised by the type or position of power plants using steam or spring force
  • B60L 8/00 - Electric propulsion with power supply from forces of nature, e.g. sun or wind
  • B64C 39/02 - Aircraft not otherwise provided for characterised by special use
  • H02S 10/40 - Mobile PV generator systems
  • B60L 11/18 - using power supplied from primary cells, secondary cells, or fuel cells

14.

Integration of high-efficiency, lightweight solar sheets onto unmanned aerial vehicle for increased endurance

      
Application Number 15131754
Grant Number 09650148
Status In Force
Filing Date 2016-04-18
First Publication Date 2017-01-19
Grant Date 2017-05-16
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Chan, Raymond
  • Miyamoto, Haruki
  • Wibowo, Andree
  • Osowski, Mark
  • Youtsey, Christopher
  • Mccallum, David

Abstract

Some embodiments include a kit for supplying solar power in a battery-powered or fuel cell powered unmanned aerial vehicle (UAV) by incorporating flexible solar cells into a component of a UAV, affixing flexible solar cells to a surface of a UAV, or affixing flexible solar cells to a surface of a component of a UAV. The kit also includes a power conditioning system configured to operate the solar cells within a desired power range and configured to provide power having a voltage compatible with an electrical system of the UAV. Another embodiments include a solar sheet configured for installation on a surface of a UAV or on a surface of a component of a UAV. The solar sheet includes a plurality of solar cells and a polymer layer to which the plurality of solar cells are attached.

IPC Classes  ?

  • B64D 27/24 - Aircraft characterised by the type or position of power plants using steam or spring force
  • B60L 8/00 - Electric propulsion with power supply from forces of nature, e.g. sun or wind
  • B64C 39/02 - Aircraft not otherwise provided for characterised by special use
  • H01L 31/046 - PV modules composed of a plurality of thin film solar cells deposited on the same substrate
  • H02S 10/40 - Mobile PV generator systems
  • H02S 10/00 - PV power plantsCombinations of PV energy systems with other systems for the generation of electric power
  • B60L 11/18 - using power supplied from primary cells, secondary cells, or fuel cells

15.

HIGH EFFICIENCY, LIGHTWEIGHT, FLEXIBLE SOLAR SHEETS

      
Application Number US2013048728
Publication Number 2014/005102
Status In Force
Filing Date 2013-06-28
Publication Date 2014-01-03
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Chan, Raymond
  • Miyamoto, Haruki

Abstract

The method of the invention includes the sequential steps of providing a plurality of solar cells, interconnecting the solar cells using one or more interconnect tabs, attaching the interconnect tabs to a top side of the solar cell to interconnect the plurality of solar cells by coupling an exposed top surface of a first solar cell to a top surface of an adjacent second solar cell, attaching one or more bypass diodes to a top side of the solar cell, then next applying an adhesive to a first film layer, placing the plurality of solar cells onto the first film layer, then next applying an adhesive to a second film layer, placing the plurality of solar cells and first film layer onto the second film layer to form a sheet assembly, and then forming the solar sheet from the sheet assembly.

IPC Classes  ?

  • H01L 31/042 - PV modules or arrays of single PV cells

16.

High efficiency, lightweight, flexible solar sheets

      
Application Number 13931463
Grant Number 08993366
Status In Force
Filing Date 2013-06-28
First Publication Date 2014-01-02
Grant Date 2015-03-31
Owner MicroLink Devices, Inc. (USA)
Inventor
  • Chan, Raymond
  • Miyamoto, Haruki

Abstract

The method of the invention includes the sequential steps of providing a plurality of solar cells, interconnecting the solar cells using one or more interconnect tabs, attaching the interconnect tabs to a top side of the solar cell to interconnect the plurality of solar cells by coupling an exposed top surface of a first solar cell to a top surface of an adjacent second solar cell, attaching one or more bypass diodes to a top side of the solar cell, then next applying an adhesive to a first film layer, placing the plurality of solar cells onto the first film layer, then next applying an adhesive to a second film layer, placing the plurality of solar cells and first film layer onto the second film layer to form a sheet assembly, and then forming the solar sheet from the sheet assembly.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/05 - Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells

17.

Integration of high-efficiency, lightweight solar sheets onto unmanned aerial vehicle for increased endurance

      
Application Number 13769223
Grant Number 09315267
Status In Force
Filing Date 2013-02-15
First Publication Date 2013-10-31
Grant Date 2016-04-19
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Chan, Raymond
  • Miyamoto, Haruki
  • Wibowo, Andree
  • Osowski, Mark
  • Youtsey, Christopher
  • Mccallum, David

Abstract

Some embodiments include a kit for increasing endurance of a battery-powered unmanned aerial vehicle (UAV) by incorporating flexible solar cells or applying flexible solar cells on a surface of a UAV or on a surface of a component of a UAV. The kit further include a power conditioning system configured to operate the solar cells within a desired power range and configured to provide power having a voltage compatible with an electrical system of the UAV.

IPC Classes  ?

  • B64C 39/02 - Aircraft not otherwise provided for characterised by special use
  • B60L 8/00 - Electric propulsion with power supply from forces of nature, e.g. sun or wind
  • H02S 10/00 - PV power plantsCombinations of PV energy systems with other systems for the generation of electric power

18.

INTEGRATION OF HIGH-EFFICIENCY, LIGHTWEIGHT SOLAR SHEETS ONTO UNMANNED AERIAL VEHICLE FOR INCREASED ENDURANCE

      
Application Number US2013026525
Publication Number 2013/123459
Status In Force
Filing Date 2013-02-15
Publication Date 2013-08-22
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Chan, Raymond
  • Miyamoto, Haruki
  • Wibowo, Andree
  • Osowski, Mark
  • Youtsey, Christopher
  • Mccallum, David

Abstract

Some embodiments include a kit for increasing endurance of a battery-powered unmanned aerial vehicle (UAV) by incorporating flexible solar cells or applying flexible solar cells on a surface of a UAV or on a surface of a component of a UAV. The kit further include a power conditioning system configured to operate the solar cells within a desired power range and configured to provide power having a voltage compatible with an electrical system of the UAV.

IPC Classes  ?

  • B60L 8/00 - Electric propulsion with power supply from forces of nature, e.g. sun or wind
  • B64C 39/02 - Aircraft not otherwise provided for characterised by special use

19.

THIN FILM INP-BASED SOLAR CELLS USING EPITAXIAL LIFT-OFF

      
Application Number US2012057966
Publication Number 2013/101317
Status In Force
Filing Date 2012-09-28
Publication Date 2013-07-04
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Hillier, Glen
  • Wanlass, Mark
  • Youtsey, Christopher
  • Adams, Jessica

Abstract

Methods of producing single-junction or multi-junction InP-based solar cells grown latticed-matched on a InP substrate or grown on metamorphic layers on a GaAs substrate, with the substrate subsequently removed in a nondestructive manner via the epitaxial lift-off (ELO) technique, and devices produced using the methods are described herein.

IPC Classes  ?

  • H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 31/0352 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
  • H01L 31/0687 - Multiple junction or tandem solar cells
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

20.

LIGHT EMITTING DIODE FABRICATED BY EPITAXIAL LIFT-OFF

      
Application Number US2012057986
Publication Number 2013/049614
Status In Force
Filing Date 2012-09-28
Publication Date 2013-04-04
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Elarde, Victor, C.
  • Youtsey, Christopher
  • Osowski, Mark

Abstract

A method of fabricating a light emitting diode using an epitaxial lift-off process includes forming a sacrificial layer on a substrate, forming a light emitting diode structure on the sacrificial layer with an epitaxial material, forming a light reflecting layer on the light emitting diode structure, and removing the sacrificial layer using an etching process to separate the substrate from the light emitting diode structure.

IPC Classes  ?

  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

21.

Assembly techniques for solar cell arrays and solar cells formed therefrom

      
Application Number 13649355
Grant Number 08440492
Status In Force
Filing Date 2012-10-11
First Publication Date 2013-02-14
Grant Date 2013-05-14
Owner MicroLink Devices, Inc. (USA)
Inventor
  • Chan, Raymond
  • Youtsey, Christopher

Abstract

An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

22.

Assembly techniques for solar cell arrays and solar cells formed therefrom

      
Application Number 13649367
Grant Number 08426237
Status In Force
Filing Date 2012-10-11
First Publication Date 2013-02-07
Grant Date 2013-04-23
Owner MicroLink Devices, Inc. (USA)
Inventor
  • Chan, Raymond
  • Youtsey, Christopher

Abstract

An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

23.

HBT and field effect transistor integration

      
Application Number 13080212
Grant Number 08450162
Status In Force
Filing Date 2011-04-05
First Publication Date 2012-04-12
Grant Date 2013-05-28
Owner MicroLink Devices, Inc. (USA)
Inventor
  • Pan, Noren
  • Wibowo, Andree

Abstract

Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BiFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

24.

Methods for fabricating thin film III-V compound solar cell

      
Application Number 13165318
Grant Number 10923617
Status In Force
Filing Date 2011-06-21
First Publication Date 2011-12-29
Grant Date 2021-02-16
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Hillier, Glen
  • Vu, Duy Phach
  • Tatavarti, Rao
  • Youtsey, Christopher
  • Mccallum, David
  • Martin, Genevieve

Abstract

The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.

IPC Classes  ?

  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0687 - Multiple junction or tandem solar cells

25.

ASSEMBLY TECHNIQUES FOR SOLAR CELL ARRAYS AND SOLAR CELLS FORMED THEREFROM

      
Application Number US2010033570
Publication Number 2010/129566
Status In Force
Filing Date 2010-05-04
Publication Date 2010-11-11
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Chan, Raymond
  • Youtsey, Christopher

Abstract

An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

26.

Assembly techniques for solar cell arrays and solar cells formed therefrom

      
Application Number 12773582
Grant Number 08361827
Status In Force
Filing Date 2010-05-04
First Publication Date 2010-11-04
Grant Date 2013-01-29
Owner MicroLink Devices, Inc. (USA)
Inventor
  • Chan, Raymond
  • Youtsey, Christopher

Abstract

An assembly technique for assembling solar cell arrays is provided. During the fabrication of a solar cell, openings through the semiconductor layer are etched through to a top surface of the backmetal layer. The solar cells include an exposed top surface of the backmetal layer. A plurality of solar cells are assembled into a solar cell array where adjacent cells are interconnected in an electrically serial or parallel fashion solely from the top surface of the solar cells.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

27.

HIGH EFFICIENCY GROUP III-V COMPOUND SEMICONDUCTOR SOLAR CELL WITH OXIDIZED WINDOW LAYER

      
Application Number US2010022385
Publication Number 2010/088370
Status In Force
Filing Date 2010-01-28
Publication Date 2010-08-05
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Youtsey, Christopher
  • Mccallum, David, S.
  • Elarde, Victor, C.
  • Dallesasse, John, M.

Abstract

The present application utilizes an oxidation process to fabricating a Group III- V compound semiconductor solar cell device. By the oxidation process, a window layer disposed on a cell unit is oxidized to enhance the efficiency of the solar cell device. The oxidized window has an increased band gap to minimize the surface recombination of electrons and holes. The oxidized window also improves transparency at the wavelengths that were absorbed in the conventional window layer.

IPC Classes  ?

  • H01L 31/04 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices

28.

HIGH EFFICIENCY GROUP III-V COMPOUND SEMICONDUCTOR SOLAR CELL WITH OXIDIZED WINDOW LAYER

      
Document Number 02750656
Status In Force
Filing Date 2010-01-28
Open to Public Date 2010-08-05
Grant Date 2016-08-23
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Youtsey, Christopher
  • Mccallum, David S.
  • Elarde, Victor C.
  • Dallesasse, John M.

Abstract

The present application utilizes an oxidation process to fabricating a Group III-V compound semiconductor solar cell device. By the oxidation process, a window layer disposed on a cell unit is oxidized to enhance the efficiency of the solar cell device. The oxidized window has an increased band gap to minimize the surface recombination of electrons and holes. The oxidized window also improves transparency at the wavelengths that were absorbed in the conventional window layer.

IPC Classes  ?

  • H10F 71/00 - Manufacture or treatment of devices covered by this subclass
  • H10F 77/124 - Active materials comprising only Group III-V materials, e.g. GaAs

29.

High efficiency group III-V compound semiconductor solar cell with oxidized window layer

      
Application Number 12695671
Grant Number 09356162
Status In Force
Filing Date 2010-01-28
First Publication Date 2010-07-29
Grant Date 2016-05-31
Owner MicroLink Devices, Inc. (USA)
Inventor
  • Pan, Noren
  • Youtsey, Christopher
  • Mccallum, David S.
  • Elarde, Victor C.
  • Dallesasse, John M.

Abstract

The present application utilizes an oxidation process to fabricating a Group III-V compound semiconductor solar cell device. By the oxidation process, a window layer disposed on a cell unit is oxidized to enhance the efficiency of the solar cell device. The oxidized window has an increased band gap to minimize the surface recombination of electrons and holes. The oxidized window also improves transparency at the wavelengths that were absorbed in the conventional window layer.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0216 - Coatings
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L 31/0687 - Multiple junction or tandem solar cells
  • H01L 31/0735 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells

30.

SOLAR CELL WITH A BACKSIDE VIA TO CONTACT THE EMITTER LAYER

      
Application Number US2009065982
Publication Number 2010/062991
Status In Force
Filing Date 2009-11-25
Publication Date 2010-06-03
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Youtsey, Christopher
  • Tuminello, Francis
  • Elarde, Victor, C.

Abstract

A solar cell structure is provided for reducing shadow losses without increasing series resistance in the solar cell device. The solar cell device may form an electrical contact to a solar cell emitter layer from the backside of the solar cell device. With this structure, the emitter contact shadow losses may be reduced significantly while simultaneously decreasing device series resistance.

IPC Classes  ?

  • H01L 31/0376 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
  • H01L 31/18 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

31.

Solar cell with a backside via to contact the emitter layer

      
Application Number 12626522
Grant Number 08993873
Status In Force
Filing Date 2009-11-25
First Publication Date 2010-05-27
Grant Date 2015-03-31
Owner MicroLink Devices, Inc. (USA)
Inventor
  • Youtsey, Christopher
  • Tuminello, Francis
  • Elarde, Victor C.

Abstract

A solar cell structure is provided for reducing shadow losses without increasing series resistance in the solar cell device. The solar cell device may form an electrical contact to a solar cell emitter layer from the backside of the solar cell device. With this structure, the emitter contact shadow losses may be reduced significantly while simultaneously decreasing device series resistance.

IPC Classes  ?

  • H01L 31/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
  • H01L 31/0224 - Electrodes
  • H01L 31/0687 - Multiple junction or tandem solar cells
  • H01L 31/0725 - Multiple junction or tandem solar cells
  • H01L 31/078 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier including different types of potential barriers provided for in two or more of groups

32.

Methods for fabricating thin film III-V compound solar cell

      
Application Number 12167583
Grant Number 07994419
Status In Force
Filing Date 2008-07-03
First Publication Date 2009-02-19
Grant Date 2011-08-09
Owner MicroLink Devices, Inc. (USA)
Inventor
  • Pan, Noren
  • Hillier, Glen
  • Vu, Duy Phach
  • Tatavarti, Rao
  • Youtsey, Christopher
  • Mccallum, David
  • Martin, Genevieve

Abstract

The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.

IPC Classes  ?

  • H01L 31/0256 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by the material

33.

THIN FILM III-V COMPOUND SOLAR CELL

      
Application Number US2008008262
Publication Number 2009/005824
Status In Force
Filing Date 2008-07-03
Publication Date 2009-01-08
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Hillier, Glen
  • Vu, Duy, Phach
  • Tatavarti, Rao
  • Youtsey, Christopher
  • Mccallum, David
  • Martin, Genevieve

Abstract

The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film HI-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.

IPC Classes  ?

  • H01L 31/042 - PV modules or arrays of single PV cells

34.

METHODS FOR FABRICATING THIN FILM III-V COMPOUND SOLAR CELL

      
Application Number US2008008263
Publication Number 2009/005825
Status In Force
Filing Date 2008-07-03
Publication Date 2009-01-08
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Pan, Noren
  • Hillier, Glen
  • Vu, Duy Phach
  • Tatavarti, Rao
  • Youtsey, Christopher
  • Mccallum, David
  • Martin, Genevieve

Abstract

The present invention utilizes epitaxial lift-off in which a sacrificial layer is included in the epitaxial growth between the substrate and a thin film III-V compound solar cell. To provide support for the thin film III-V compound solar cell in absence of the substrate, a backing layer is applied to a surface of the thin film III-V compound solar cell before it is separated from the substrate. To separate the thin film III-V compound solar cell from the substrate, the sacrificial layer is removed as part of the epitaxial lift-off. Once the substrate is separated from the thin film III-V compound solar cell, the substrate may then be reused in the formation of another thin film III-V compound solar cell.

IPC Classes  ?

  • H01L 31/042 - PV modules or arrays of single PV cells

35.

HBT and field effect transistor integration

      
Application Number 12069044
Grant Number 07923318
Status In Force
Filing Date 2008-02-07
First Publication Date 2008-09-25
Grant Date 2011-04-12
Owner MicroLink Devices, Inc. (USA)
Inventor
  • Pan, Noren
  • Wibowo, Andree

Abstract

Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

36.

HBT AND FIELD EFFECT TRANSISTOR INTEGRATION

      
Application Number US2008001614
Publication Number 2008/097604
Status In Force
Filing Date 2008-02-07
Publication Date 2008-08-14
Owner MICROLINK DEVICES, INC. (USA)
Inventor
  • Wibowo, Andree
  • Pan, Noren

Abstract

Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BiFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology

37.

High on-state breakdown heterojunction bipolar transistor

      
Application Number 11153078
Grant Number 07687886
Status In Force
Filing Date 2005-06-14
First Publication Date 2006-03-09
Grant Date 2010-03-30
Owner MicroLink Devices, Inc. (USA)
Inventor
  • Pan, Noren
  • Wibowo, Andree

Abstract

CE. The improvement of the on-state breakdown voltage for the HBT improves the output power characteristics of the HBT and the ability of the HBT to withstand large impedance mismatch (large VSWR). The improvement in the on-state breakdown voltage is related to the suppression of high electric fields adjacent a junction of a collector layer and a sub-collector layer forming a collector region of the HBT.

IPC Classes  ?

  • H01L 27/082 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only