The disclosed and claimed subject matter relates to a ferroelectric tunnel junction that is BEOL compatible having a film comprising crystalline ferroelectric materials that include a mixture of hafnium oxide and zirconium oxide having a substantial (i.e., approximately 40% or more) or majority portion of the material in a ferroelectric phase as deposited (i.e., without the need for further processing, such as a subsequent capping or annealing) and methods for preparing and depositing these materials. An interfacial layer is formed by oxidizing one or more of a first electrode and a second electrode. The FTJ has a memory window of between about 2× and 10× and is stable over 4 resistance states for at least 10's. The FTJ is produced at temperatures less than or equal to 400 degrees Celsius.
The disclosure relates to a method of producing an intrinsic or doped transition metal dichalcogenide film comprising: providing a substrate in a deposition chamber; providing a reducing environment and an excess of chalcogen in the deposition chamber; and forming the intrinsic or doped transition metal dichalcogenide film on a surface of the substrate. The transition metal may be Mo or W, and the chalcogen may be S, Se, or Te. The reducing environment may be a hydrogen rich environment.
i.e.i.e.i.e., without the need for further processing, such as a subsequent capping or annealing) and methods for preparing and depositing these materials. An interfacial layer is formed by oxidizing one or more of a first electrode and a second electrode. The FTJ has a memory window of between about 2X and 10X and is stable over 4 resistance states for at least 103s. The FTJ is produced at temperatures less than or equal to 400 degrees Celsius.
Techniques for creating a high aspect feature and testing the efficacy of a gas-phase deposition process are provided. An example of a method for thin film deposition in a high aspect ratio feature includes preparing a first substrate for a material deposition process, depositing a plurality of spacers on a top surface of the first substrate, disposing a bottom surface of a second substrate on the plurality of spacers, and performing a gas-phase material deposition on the first substrate and the second substrate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/66 - Testing or measuring during manufacture or treatment
6.
Current compliance layers and memory arrays comprising thereof
Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
7.
HEAT TREATABLE COATED ARTICLE HAVING ZIRCONIUM NITRIDE AND ITO BASED IR REFLECTING LAYERS
Coated articles include two or more functional infrared (IR) reflecting layers optionally sandwiched between at least dielectric layers. The dielectric layers may be of or including silicon nitride or the like. At least one of the IR reflecting layers is of or including zirconium nitride (e.g., ZrN) and at least another of the IR reflecting layers is of or including indium-tin-oxide (ITO).
C03C 17/34 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
8.
Current compliance layers and memory arrays comprising thereof
Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
9.
Vapor based site-isolated processing systems and methods
Embodiments provided herein describe systems and method for processing substrates. A substrate is provided. A showerhead is positioned above the substrate. The showerhead includes a plurality of injection ports, at least one isolation channel, and at least one exhaust port on a bottom surface thereof. The at least one isolation channel separates the plurality of injection ports into two or more sections. The at least one exhaust port is positioned within the at least one isolation channel. The plurality of injection ports are not in fluid communication with the at least one exhaust port within the showerhead. At least one processing fluid is caused to be delivered from the plurality of injection ports onto the substrate. At least some of the at least one processing fluid is caused to be removed from the substrate through the at least one exhaust port.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
10.
TITANIUM NICKEL NIOBIUM ALLOY BARRIER FOR LOW-EMISSIVITY COATINGS
A method for making low emissivity panels, including control the composition of a barrier layer formed on a thin conductive silver layer. The barrier structure can include a ternary alloy of nickel, titanium, and niobium, which showed improvements in overall performance than those from binary barrier results. The percentage of nickel can be between 5 and 15 wt%. The percentage of titanium can be between 30 and 50 wt%. The percentage of niobium can be between 40 and 60 wt%.
B32B 15/08 - Layered products essentially comprising metal comprising metal as the main or only constituent of a layer, next to another layer of a specific substance of synthetic resin
C03C 17/36 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
C23C 14/00 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
C03C 17/34 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
11.
DOPED NARROW BAND GAP NITRIDES FOR EMBEDDED RESISTORS OF RESISTIVE RANDOM ACCESS MEMORY CELLS
Provided are memory cells, such as resistive random access memory (ReRAM) cells, and methods of fabricating such cells. A cell includes an embedded resistor and resistive switching layer connected in series within the embedded resistor. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state. The embedded resistor includes a stoichiometric nitride that has a bandgap of less than 2 eV. The embedded resistor is configured to maintain a substantially constant resistance throughout fabrication and operation of the cell, such as annealing the cell and subjecting the cell to forming and switching signals. The stoichiometric nitride may be one of hafnium nitride, zirconium nitride, or titanium nitride. The embedded resistor may also include a dopant, such as tantalum, niobium, vanadium, tungsten, molybdenum, or chromium.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
12.
DOPED TERNARY NITRIDE EMBEDDED RESISTORS FOR RESISTIVE RANDOM ACCESS MEMORY CELLS
Provided are resistive random access memory (ReRAM) cells with embedded resistors and methods of fabricating these cells. An embedded resistor may include a metal silicon nitride of a first metal and may be doped with a second metal, which is different from the first metal. The second metal may have less affinity to form covalent bonds with nitrogen than the first metal. As such, the second metal may be unbound and more mobile in the embedded resistor that the first metal. The second metal may help establishing conductive paths in the embedded resistor in addition to the metal nitride resulting in more a stable resistivity despite changing potential applies to the ReRAM cell. In other words, the embedded resistor having such composition will have more linear I-V performance. The concentration of the second metal in the embedded resistor may be substantially less than the concentration of the first metal.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
13.
Doped ternary nitride embedded resistors for resistive random access memory cells
Provided are resistive random access memory (ReRAM) cells with embedded resistors and methods of fabricating these cells. An embedded resistor may include a metal silicon nitride of a first metal and may be doped with a second metal, which is different from the first metal. The second metal may have less affinity to form covalent bonds with nitrogen than the first metal. As such, the second metal may be unbound and more mobile in the embedded resistor that the first metal. The second metal may help establishing conductive paths in the embedded resistor in addition to the metal nitride resulting in more a stable resistivity despite changing potential applies to the ReRAM cell. In other words, the embedded resistor having such composition will have more linear I-V performance. The concentration of the second metal in the embedded resistor may be substantially less than the concentration of the first metal.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
14.
ELECTRON BARRIER HEIGHT CONTROLLED INTERFACES OF RESISTIVE SWITCHING LAYERS IN RESISTIVE RANDOM ACCESS MEMORY CELLS
Provided are resistive switching memory cells and method of forming such cells. A memory cell includes a resistive switching layer disposed between two buffer layers. The electron barrier height of the material used for each buffer layer is less than the electron barrier height of the material used for the resistive switching layer. Furthermore, the thickness of each buffer layer may be less than the thickness of the resistive switching layer. The buffer layers reduce diffusion between the resistive switching layer and electrodes. Furthermore, the buffer layers improve data retention and prevent unintentional resistive switching when a reading signal is applied to the memory cell. The reading signal uses a low voltage and most of the electron tunneling is blocked by the buffer layers during this operation. On the other hand, the buffer layers allow electrode tunneling at higher voltages used for forming and switching signals.
Provided are resistive switching cells and methods of using such cells for controlling operation of liquid crystal display (LCD) cells in LCD devices. A resistive switching cell has two electrodes formed from transparent conductive oxides, such as indium oxide, indium tin oxide, or zinc oxide. One electrode may be connected to a LCD cell thereby forming an in series connection between the resistive switching cell and LCD cell. The other electrode may be used to power the LCD cell through the resistive switching cell. The resistive switching cell also includes a resistive switching layer disposed between the two electrodes. When the resistive switching layer is in its low resistive state, the LCD cell is subjected to an operating potential and produces light. However, when the resistive switching layer is in its high resistive state, the LCD cell is not subjected to the operating potential and does not produce light.
G02F 1/1365 - Active matrix addressed cells in which the switching element is a two-electrode device
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
16.
Doped narrow band gap nitrides for embedded resistors of resistive random access memory cells
Provided are memory cells, such as resistive random access memory (ReRAM) cells, and methods of fabricating such cells. A cell includes an embedded resistor and resistive switching layer connected in series within the embedded resistor. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state. The embedded resistor includes a stoichiometric nitride that has a bandgap of less than 2 eV. The embedded resistor is configured to maintain a substantially constant resistance throughout fabrication and operation of the cell, such as annealing the cell and subjecting the cell to forming and switching signals. The stoichiometric nitride may be one of hafnium nitride, zirconium nitride, or titanium nitride. The embedded resistor may also include a dopant, such as tantalum, niobium, vanadium, tungsten, molybdenum, or chromium.
H01L 21/06 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS
H01L 31/062 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the metal-insulator-semiconductor type
H01L 31/113 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect photo- transistor being of the conductor-insulator- semiconductor type, e.g. metal- insulator-semiconductor field-effect transistor
H01L 31/119 - Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation characterised by field-effect operation, e.g. MIS type detectors
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A reflective layer is formed above the transparent substrate. A dielectric layer is formed between the transparent substrate and the reflective layer. The dielectric layer includes niobium, tin, and aluminum.
B32B 17/06 - Layered products essentially comprising sheet glass, or fibres of glass, slag or the like comprising glass as the main or only constituent of a layer, next to another layer of a specific substance
18.
Embedded nonvolatile memory elements having resistive switching characteristics
Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
19.
Amorphous silicon doped with fluorine for selectors of resistive random access memory cells
Provided are resistive switching memory cells having selectors and methods of fabricating such cells. A selector may be disposed between an electrode and resistive switching layer. The selector is configured to undergo an electrical breakdown when a voltage applied to the selector exceeds a selected threshold. The selector is formed from amorphous silicon doped with fluorine. The concentration of fluorine may be between about 0.01% atomic and 3% atomic, such as about 1% atomic. Amorphous silicon has a larger band gap than, for example, crystalline silicon and, therefore, has a lower leakage. Dangling bond and weak bond states appearing in the mid-gap position of amorphous silicon are eliminated by adding fluorine. Fluorine binds to and passivates defects. In some embodiments, a fluorine reservoir is positioned in a low current density region of the memory cell to counter diffusion of fluorine from the selector into other components.
A co-sputter technique is used to deposit In-Ga-Zn-O films using PVD. The films are deposited in an atmosphere including both oxygen and argon. A heater setpoint of about 300C results in a substrate temperature of about 165C. One target includes an alloy of In, Ga, Zn, and O with an atomic ratio of In:Ga:Zn of about 1:1:1. The second target includes a compound of zinc oxide. The third target includes a compound of indium oxide. The films exhibit the c-axis aligned crystalline (CAAC) phase in an as-deposited state, when deposited at room temperature, without the need of a subsequent anneal treatment.
H01L 21/203 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
H01L 31/0392 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates
A co-sputter technique is used to deposit In-Ga-Zn-O films using PVD. The films are deposited in an atmosphere including both oxygen and argon. A heater setpoint of about 300C results in a substrate temperature of about 165C. One target includes an alloy of In, Ga, Zn, and O with an atomic ratio of In:Ga:Zn of about 1:1:1. The second target includes a compound of zinc oxide. The films exhibit the c-axis aligned crystalline (CAAC) phase in an as-deposited state, without the need of a subsequent anneal treatment.
H01L 21/465 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
23.
TERNARY METAL NITRIDE FORMATION BY ANNEALING CONSTITUENT LAYERS
Ternary metal nitride layers suitable for thin-film resistors are fabricated by forming constituent layers of complementary components (e.g., binary nitrides of the different metals, or a binary nitride of one metal and a metallic form of the other metal), then annealing the constituent layers to interdiffuse the materials, thus forming the ternary metal nitride. The constituent layers (e.g., 2-5nm thick) may be sputtered from binary metal nitride targets, from metal targets in a nitrogen-containing ambient, or from metal targets in an inert ambient. Optionally, a nitrogen-containing ambient may also be used for the annealing. The annealing may be 10 seconds to 10 minutes at 500-1000°C and may also process another component on the same substrate (e.g., activate a diode).
H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant
24.
SCHOTTKY BARRIERS FOR RESISTIVE RANDOM ACCESS MEMORY
Provided are resistive random access memory (ReRAM) cells having Schottky barriers and methods of fabricating such ReRAM cells. Specifically, a ReRAM cell includes two Schottky barriers, one barrier limiting an electrical current through the variable resistance layer in one direction and the other barrier limiting a current in the opposite direction. This combination of the two Schottky barriers provides current compliance during set operations and limits undesirable current overshoots during reset operations. The Schottky barriers' heights are configured to match the resistive switching characteristics of the cell. Conductive layers of the ReRAM cells operable as electrodes may be used to form these Schottky barriers together with semiconductor layers. These semiconductor layers may be different components from a variable resistance layer and, in some embodiments, may be separated by intermediate conductive layers from the variable resistance layers.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The resistive switching nonvolatile memory cells may include a first layer disposed. The first layer may be operable as a bottom electrode. The resistive switching nonvolatile memory cells may also include a second layer disposed over the first layer. The second layer may be operable as a resistive switching layer that is configured to switch between a first resistive state and a second resistive state. The resistive switching nonvolatile memory cells may include a third layer disposed over the second layer. The third layer may be operable as a resistive layer that is configured to determine, at least in part, an electrical resistivity of the resistive switching nonvolatile memory element. The third layer may include a semi-metallic material. The resistive switching nonvolatile memory cells may include a fourth layer that may be operable as a top electrode.
Provided are resistive random access memory (ReRAM) cells having diffusion barrier layers formed from various materials, such as beryllium oxide or titanium silicon nitrides. Resistive switching layers used in ReRAM cells often need to have at least one inert interface such that substantially no materials pass through this interface. The other (reactive) interface may be used to introduce and remove defects from the resistive switching layers causing the switching. While some electrode materials, such as platinum and doped polysilicon, may form inert interfaces, these materials are often difficult to integrate. To expand electrode material options, a diffusion barrier layer is disposed between an electrode and a resistive switching layer and forms the inert interface with the resistive switching layer. In some embodiments, tantalum nitride and titanium nitride may be used for electrodes separated by such diffusion barrier layers.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
27.
Methods to characterize an embedded interface of a CMOS gate stack
Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. Surface treatments can be inserted at three possible steps during the formation of the MOSCAP structures. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate dielectric deposition, gate dielectric patterning, metal-based semiconductor deposition, metal-based patterning, etch stop deposition, etch stop patterning, source/drain deposition, or source/drain patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.
H01L 21/16 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising cuprous oxide or cuprous iodide
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/465 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/66 - Testing or measuring during manufacture or treatment
In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility.
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
30.
RESISTIVE SWITCHING SCHMITT TRIGGERS AND COMPARATORS
A resistive switching element can be used in a nonvolatile digital Schmitt trigger circuit or a comparator circuit. The Schmitt trigger circuit can include a resistive switching circuit, and a reset circuit. The resistive switching circuit can provide a hysteresis behavior suitable for Schmitt trigger operation. The reset circuit can be operable to reset the resistive switching circuit to a high resistance state. The comparator circuit can include a resistive switching circuit, a reset circuit, and a threshold setting circuit. The resistive switching circuit can include a resistive switching element, and can be operable to provide a signal comparing an input voltage with the set or reset threshold voltage of the resistive switching element. The threshold setting circuit can be operable to modify the set or reset threshold of the resistive switching element, effectively changing the reference voltage for the comparator circuit.
Embodiments provided herein describe abrasion resistant glass coatings and methods for forming abrasion resistant glass coatings. A glass body is provided. An abrasion resistant layer is formed above the glass body. The abrasion resistant layer includes an amorphous carbon. A pull-up layer is formed above the abrasion resistant layer. A protective layer is formed above the pull-up layer. The protective layer may include a titanium-based nitride. The pull-up lay may include tungsten oxide, zirconium oxide, manganese oxide, molybdenum oxide, titanium oxide, or a combination thereof.
C03C 17/34 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
B05D 7/00 - Processes, other than flocking, specially adapted for applying liquids or other fluent materials to particular surfaces or for applying particular liquids or other fluent materials
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
33.
Doped oxide dielectrics for resistive random access memory cells
Provided are methods of fabricating memory cells such as resistive random access memory (ReRAM) cells. A method involves forming a first layer including two high-k dielectric materials such that one material has a higher dielectric constant than the other material. In some embodiments, hafnium oxide and titanium oxide form the first layer. The higher-k material may be present at a lower concentration. In some embodiments, a concentration ratio of these two high-k materials is between about 3 and 7. The first layer may be formed using atomic layer deposition. The first layer is then annealed in an oxygen-containing environment. The method may proceed with forming a second layer including a low-k dielectric material, such as silicon oxide, and forming an electrode. After forming the electrode, the memory cell is annealed in a nitrogen containing environment. The nitrogen anneal may be performed at a higher temperature than the oxygen anneal.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
34.
Embedded resistors for resistive random access memory cells
Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The methods may include forming a first layer on a substrate, where the first layer is operable as a bottom electrode. The methods may also include forming a second layer, where the second layer includes a resistive portion and a resistive switching portion. The resistive portion may be configured to determine, at least in part, an electrical resistivity of the resistive switching nonvolatile memory element. The resistive portion may have a substantially constant resistance. The resistive portion may include, at least in part, a conductive silicon oxide. The resistive switching portion may be configured to switch between a first resistive state and a second resistive state. The resistive switching portion may include, at least in part, silicon oxide. The methods may also include forming a third layer, where the third layer is operable as a top electrode.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
35.
Methods for forming resistive switching memory elements by heating deposited layers
Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer.
G11C 13/02 - Digital stores characterised by the use of storage elements not covered by groups , , or using elements whose operation depends upon chemical change
38.
ReRAM materials stack for low-operating-power and high-density applications
A switching element for resistive-switching memory (ReRAM) provides a controllable, consistent filament break-point at an abrupt structural discontinuity between a layer of high-k high-ionicity variable-resistance (VR) material and a layer of low-k low-ionicity VR material. The high-ionicity layer may be crystalline and the low-ionicity layer may be amorphous. The consistent break-point and characteristics of the low-ionicity layer facilitate lower-power operation. The defects (e.g., oxygen or nitrogen vacancies) that constitute the filament originate either in the high-ionicity VR layer or in a source electrode. The electrode nearest to the low-ionicity layer may be intrinsically inert or may be rendered effectively inert. Some electrodes are rendered effectively inert by the creation of the low-ionicity layer over the electrode.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
39.
NONVOLATILE RESISTIVE MEMORY WITH SILICON-BASED SWITCHING LAYER
A nonvolatile resistive memory element includes a novel switching layer and methods of forming the same. The switching layer includes a material having bistable resistance properties and formed by bonding silicon to oxygen or nitrogen. The switching layer may include at least one of SiOx, SiOxNy, or SiNx. Advantageously, the SiOx, SiOxNy, and SiNx generally remain amorphous after thermal anneal processes are used to form the devices, such as ReRAM devices.
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
40.
RERAM MATERIALS STACK FOR LOW-OPERATING-POWER AND HIGH-DENSITY APPLICATIONS
A switching element for resistive-switching memory (ReRAM) provides a controllable, consistent filament break-point at an abrupt structural discontinuity between a layer of high-k high-ionicity variable-resistance (VR) material and a layer of low-k low-ionicity VR material. The high-ionicity layer may be crystalline and the low-ionicity layer may be amorphous. The consistent break-point and characteristics of the low-ionicity layer facilitate lower-power operation. The defects (e.g., oxygen or nitrogen vacancies) that constitute the filament originate either in the high-ionicity VR layer or in a source electrode. The electrode nearest to the low-ionicity layer may be intrinsically inert or may be rendered effectively inert. Some electrodes are rendered effectively inert by the creation of the low-ionicity layer over the electrode.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
42.
Creating an embedded ReRAM memory from a high-k metal gate transistor structure
An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
43.
ATOMIC LAYER DEPOSITION OF HFAIC AS A METAL GATE WORKFUNCTION MATERIAL IN MOS DEVICES
ALD of HfxA1yCz films using hafnium chloride (HfC14) and Trimethylaluminum (TMA) precursors can be combined with post-deposition anneal processes and ALD liners to control the device characteristics in high-k metal-gate devices. Variation of the HfC14 pulse time allows for control of the A1 % incorporation in the HfxA1yCz film in the range of 10-13%. Combinatorial process tools can be employed for rapid electrical and materials characterization of various materials stacks. The effective work function (EWF) in metal oxide semiconductor capacitor (MOSCAP) devices with the HfxA1yCz work function layer coupled with ALD deposited HfO2 high-k gate dielectric layers was quantified to be mid-gap at ~4.6 eV. Thus, HfxA1yCz is a promising metal gate work function material allowing for the tuning of device threshold voltages (Vth) for anticipated multi-Vth integrated circuit (IC) devices.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
44.
TITANIUM NICKEL NIOBIUM ALLOY BARRIER FOR LOW-EMISSIVITY COATINGS
A method for making low emissivity panels, including control the composition of a barrier layer formed on a thin conductive silver layer. The barrier structure can include a ternary alloy of titanium, nickel and niobium, which showed improvements in overall performance than those from binary barrier results. The percentage of titanium can be between 5 and 15 wt%. The percentage of nickel can be between 30 and 50 wt%. The percentage of niobium can be between 40 and 60 wt%.
C03C 17/36 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
B32B 9/00 - Layered products essentially comprising a particular substance not covered by groups
45.
METHOD OF FABRICATING IGZO BY SPUTTERING IN OXIDIZING GAS
In some embodiments, oxidants such as ozone (O3) and/or nitrous oxide (N2O) are used during the reactive sputtering of metal-based semiconductor layers used in TFT devices. The O3 and N2O gases are stronger oxidants and result in a decrease in the concentration of oxygen vacancies within the metal-based semiconductor layer. The decrease in the concentration of oxygen vacancies may result in improved stability under conditions of negative bias illumination stress (NBIS).
H01L 31/032 - Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups
H01L 21/203 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
H01L 21/363 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using physical deposition, e.g. vacuum deposition, sputtering
H01L 31/0392 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates
Methods to improve the reflection of light emitting devices are disclosed. A method consistent with the present disclosure includes forming a light generating layer over a site-isolated region of a substrate. Next, forming a first transparent conductive layer over the light generating layer. Forming a low refractive index material over the first transparent conductive layer, and in time, forming a second transparent conductive layer over the low refractive index material. Subsequently, forming a reflective material layer thereon. Accordingly, methods consistent with the present disclosure may form a plurality of light emitting devices in various site-isolated regions on a substrate.
Disclosed herein are systems, methods, and apparatus for forming low emissivity panels. In some embodiments, a partially fabricated panel may be provided that includes a substrate, a reflective layer formed over the substrate, and a barrier layer formed over the reflective layer such that the reflective layer is formed between the substrate and the barrier layer. The barrier layer may include a partially oxidized alloy of three or more metals. A first interface layer may be formed over the barrier layer. A top dielectric layer may be formed over the first interface layer. The top dielectric layer may be formed using reactive sputtering in an oxygen containing environment. The first interface layer may prevent further oxidation of the partially oxidized alloy of the three or more metals when forming the top dielectric layer. A second interface layer may be formed over the top dielectric layer.
B32B 15/04 - Layered products essentially comprising metal comprising metal as the main or only constituent of a layer, next to another layer of a specific substance
48.
IMPROVED LOW-E GLAZING PERFORMANCE BY SEED-STRUCTURE OPTIMIZATION
A bi-layer seed layer can exhibit good seed property for an infrared reflective layer, together with improved thermal stability. The bi-layer seed layer can include a thin zinc oxide layer having a desired crystallographic orientation for a silver infrared reflective layer disposed on a bottom layer having a desired thermal stability. The thermal stable layer can include aluminum, magnesium, or bismuth doped tin oxide (AlSnO, MgSnO, or BiSnO), which can have better thermal stability than zinc oxide but poorer lattice matching for serving as a seed layer template for silver (111).
Low emissivity panels can include a protection layer of silicon nitride on a layer of ZnO on a layer of Zn2SnOx. The low emissivity panels can also include NiNbTiOx as a barrier layer. The low emissivity panels have high light to solar gain, color neutral, together with similar observable color and light transmission before and after a heat treatment process.
Anti-reflection (AR) coating for a glass substrate is prepared by blending at least two different sols to form a coating sol which is used to coat a substrate such as transparent glass substrate. In certain example embodiments, a method includes forming a first sol formulation including a colloidal solution having a tri- alkoxysilane based binder; forming a second sol formulation including a colloidal solution having a tetra-alkoxysilane based binder; blending the first and second sol formulations to form a coating sol formulation; coating at least a portion of said coating sol formulation onto the glass substrate to form a coating; and heating (e.g., for curing and/or annealing) the glass substrate and the coating thereon. Anti-reflection glasses show improved mechanical strength and higher transmittances (e.g., Tqe% gain).
Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a first reflective layer, a second reflective layer, and a spacer layer disposed between the first reflective layer and the second reflective layer. In some embodiments, the spacer layer may have a thickness of between about 20 nm and 90 nm. The spacer layer may include a bi-metal oxide that may include tin, and may further include one of zinc, aluminum, or magnesium. The spacer layer may have a substantially amorphous structure. Moreover, the spacer layer may have a substantially uniform composition throughout the thickness of the spacer layer. The low emissivity panel may be configured to have a color change as determined by Rg ΔE (i.e. as determined on the glass side) that is less than about 1.7 in response to an application of a heat treatment to the low emissivity panel.
B32B 15/04 - Layered products essentially comprising metal comprising metal as the main or only constituent of a layer, next to another layer of a specific substance
C03C 17/36 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a substrate and a reflective layer formed over the substrate. The low emissivity panels may further include a top dielectric layer formed over the reflective layer such that the reflective layer is formed between the top dielectric layer and the substrate. The top dielectric layer may include a ternary metal oxide, such as zinc tin aluminum oxide. The top dielectric layer may also include aluminum. The concentration of aluminum may be between about 1 atomic% and 15 atomic% or between about 2 atomic% and 10 atomic%. An atomic ratio of zinc to tin in the top dielectric layer may be between about 0.67 and about 1.5 or between about 0.9 and about 1.1.
B32B 15/04 - Layered products essentially comprising metal comprising metal as the main or only constituent of a layer, next to another layer of a specific substance
53.
IMPROVED HIGH SOLAR GAIN LOW-E PANEL AND METHOD FOR FORMING THE SAME
Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A reflective layer is formed above the transparent substrate. An over-coating layer is formed above the reflective layer. The over-coating layer includes first, second, and third sub-layers. The second sub-layer is between the first and third sub-layers, and the first and third sub-layers include the same material
B32B 17/06 - Layered products essentially comprising sheet glass, or fibres of glass, slag or the like comprising glass as the main or only constituent of a layer, next to another layer of a specific substance
Low emissivity panels can include a layer of AlZnSnO between a top dielectric layer and an upper protective layer. The low emissivity panels can also include Ni-Nb-based alloy such as NiNbTiOx as barrier layer. The low emissivity panels have high light to solar gain, color neutral, together with similar observable color before and after a heat treatment process.
C03C 17/36 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
C23C 14/06 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
B32B 17/06 - Layered products essentially comprising sheet glass, or fibres of glass, slag or the like comprising glass as the main or only constituent of a layer, next to another layer of a specific substance
55.
ANISOTROPIC DIELECTRIC LAYERS WITH ORIENTATIONALLY MATCHED SUBSTRATE
A dielectric layer can achieve a crystallography orientation similar to a base dielectric layer with a conductive layer disposed between the two dielectric layers. By providing a conductive layer having similar crystal structure and lattice parameters with the base dielectric layer, the crystallography orientation can be carried from the base dielectric layer, across the conductive layer to affect the dielectric layer. The process can be used to form capacitor structure for anisotropic dielectric materials, along the direction of high dielectric constant.
Metal-oxide films (e.g., aluminum oxide) with low leakage current suitable for high-k gate dielectrics are deposited by atomic layer deposition (ALD). The purge time after the metal-deposition phase is 5-15 seconds, and the purge time after the oxidation phase is prolonged beyond 60 seconds. Prolonging the post-oxidation purge produced an order-of-magnitude reduction of leakage current in 30-thick Al2O3 films.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
57.
ANTI-REFLECTION GLASS MADE FROM AGED SOL INCLUDING MIXTURE OF TRI-ALKOXYSILANE AND TETRA-ALKOXYSILANE
A method of making a coated article including an anti-reflection coating on a glass substrate, the method comprising: mixing at least a tri-alkoxysilane based binder and a tetra-alkoxysilane based binder with at least silica based nanoparticles and a solvent in forming a coating sol formulation; aging the coating sol formulation at least about two weeks so as to provide an aged coating sol formulation; coating at least a portion of said aged coating sol formulation onto the glass substrate to form a coating; and heating said glass substrate and said coating. Anti-reflection (AR) glasses show improved mechanical strength and higher transmittances (e.g., Tqe% gain).
C03C 17/00 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating
C03C 17/30 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with organic material with silicon-containing compounds
58.
CONFINED DEFECT PROFILING WITHIN RESISTIVE RANDOM MEMORY ACCESS CELLS
Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A stack including a defect source layer, a defect blocking layer, and a defect acceptor layer disposed between the defect source layer and the defect blocking layer may be subjected to annealing. During the annealing, defects are transferred in a controllable manner from the defect source layer to the defect acceptor layer. At the same time, the defects are not transferred into the defect blocking layer thereby creating a lowest concentration zone within the defect acceptor layer. This zone is responsible for resistive switching. The precise control over the size of the zone and the defect concentration within the zone allows substantially improvement of resistive switching characteristics of the ReRAM cell. In some embodiments, the defect source layer includes aluminum oxynitride, the defect blocking layer includes titanium nitride, and the defect acceptor layer includes aluminum oxide.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
59.
METHOD TO GENERATE HIGH LSG LOW-EMISSIVITY COATING WITH SAME COLOR AFTER HEAT TREATMENT
Low emissivity panels can include a separation layer of Zn2SnOx between multiple infrared reflective stacks. The low emissivity panels can also include NiNbTiOx as barrier layer. The low emissivity panels have high light to solar gain, color neutral, together with similar observable color before and after a heat treatment process.
C03C 17/36 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
60.
SYSTEMS, METHODS, AND APPARATUS FOR PRODUCTION COATINGS OF LOW-EMISSIVITY GLASS
Disclosed herein are systems, methods, and apparatus for forming a low emissivity panel. In various embodiments, a partially fabricated panel may be provided. The partially fabricated panel may include a substrate, a reflective layer formed over the substrate, and a top dielectric layer formed over the reflective layer such that the reflective layer is formed between the substrate and the top dielectric layer. The top dielectric layer may include tin having an oxidation state of +4. An interface layer may be formed over the top dielectric layer. A top diffusion layer may be formed over the interface layer. The top diffusion layer may be formed in a nitrogen plasma environment. The interface layer may substantially prevent nitrogen from the nitrogen plasma environment from reaching the top dielectric layer and changing the oxidation state of tin included in the top dielectric layer.
C03C 17/34 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
61.
BARRIER LAYERS FOR SILVER REFLECTIVE COATINGS AND HPC WORKFLOWS FOR RAPID SCREENING OF MATERIALS FOR SUCH BARRIER LAYERS
Provided is High Productivity Combinatorial (HPC) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors. The tested barrier layers may include all or at least two of nickel, chromium, titanium, and aluminum. In some embodiments, the barrier layers include oxygen. This combination allows using relative thin barrier layers (e.g., 5-30 Angstroms thick) that have high transparency yet provide sufficient protection to the silver reflector. The amount of nickel in a barrier layer may be 5-10% by weight, chromium - 25-30%, titanium and aluminum - 30%-35% each. The barrier layer may be co-sputtered in a reactive or inert environment using one or more targets that include all four metals. An article may include multiple silver reflectors, each having its own barrier layer.
Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a first spacer dielectric layer and the second spacer dielectric layer formed between a first reflective layer and a second reflective layer. The first spacer dielectric layer may include zinc tin oxide. The second spacer dielectric layer may include tin aluminum oxide. The low emissivity panel may have a Rg ΔE of less than about 2.0 in response to the application of a heat treatment to the low emissivity panel. A combined thickness of the first spacer dielectric layer and the second spacer dielectric layer is between about 40 nm and 90 nm. An atomic ratio of tin to aluminum in the second spacer dielectric layer is between about 0.8 and 1.2, and an atomic ratio of zinc to tin in the first spacer dielectric layer may be between about 1.8 and 2.2.
Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and resistive switching layer connected in series. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state, thereby preventing over-programming. The embedded resistor includes aluminum, nitrogen, and one or more additional metals (other than aluminum). The concentration of each component is controlled to achieve desired resistivity and stability of the embedded resistor. In some embodiments, the resistivity ranges from 0.1 Ohm-centimeter to 40 Ohm- centimeter and remains substantially constant while applying an electrical field of up 8 mega-Volts /centimeter to the embedded resistor. The embedded resistor may be made from an amorphous material, and the material is operable to remain amorphous even when subjected to typical annealing conditions.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
65.
NONVOLATILE RESISTIVE MEMORY ELEMENT WITH AN OXYGEN-GETTERING LAYER
A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (ΔfG ̊) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
66.
LOW-E PANEL WITH IMPROVED BARRIER LAYER PROCESS WINDOW AND METHOD FOR FORMING THE SAME
Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A reflective layer is formed above the transparent substrate. A barrier layer is formed above the reflective layer. A nitride-containing layer is formed above the barrier layer. The nitride-containing layer has a thickness that is 1 nm or less. A over-coating layer is formed above the nitride-containing layer. The over-coating layer includes a different material than that of the nitride-containing layer.
C03C 17/36 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating being a metal
67.
Combinatorial methods for developing electrochromic materials and devices
A substrate having a plurality of site-isolated regions defined thereon is provided. A first electrochromic material, or a first electrochromic device stack, is formed above a first of the plurality of site-isolated regions using a first set of processing conditions. A second electrochromic material, or a second electrochromic device stack, is formed above a second of the plurality of site-isolated regions using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions.
B05D 5/06 - Processes for applying liquids or other fluent materials to surfaces to obtain special surface effects, finishes or structures to obtain multicolour or other optical effects
H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups
B08B 3/04 - Cleaning involving contact with liquid
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
C23C 14/22 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
69.
High productivity combinatorial screening for stable metal oxide TFTs
Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/465 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
70.
ANTI-GLARE COATINGS WITH AQUEOUS PARTICLE DISPERSIONS
Embodiments provided herein describe optical coatings, panels having optical coatings thereon, and methods for forming optical coatings and panels. A substrate is provided. A coating formulation is applied to the substrate. The coating formulation includes an aqueous-based suspension of particles. The particles have a sheet-like morphology and a thickness of less than about 100 nanometers (nm). The coating formulation is cured to form an anti-glare coating above the substrate. The anti-glare coating has a thickness of between 1 micrometer (μm) and 100 μm.
B05D 5/06 - Processes for applying liquids or other fluent materials to surfaces to obtain special surface effects, finishes or structures to obtain multicolour or other optical effects
B32B 5/16 - Layered products characterised by the non-homogeneity or physical structure of a layer characterised by features of a layer formed of particles, e.g. chips, chopped fibres, powder
B32B 17/06 - Layered products essentially comprising sheet glass, or fibres of glass, slag or the like comprising glass as the main or only constituent of a layer, next to another layer of a specific substance
71.
High productivity combinatorial workflow to screen and design chalcogenide materials as non volatile memory current selector
Combinatorial workflow is provided for evaluating materials and processes for current selector devices in a cross point memory array. Blanket layers, metal-insulator-metal devices, and compete memory structures are combinatorially fabricated on multiple regions of a substrate, with each region having a different material and process condition for the current selector devices. The current selector devices are then characterized, and the data are compared to obtain the optimum materials and processes.
H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups
B08B 3/04 - Cleaning involving contact with liquid
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
C23C 14/22 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
According to various embodiments, a resistive-switching memory element and memory element array that uses a bipolar switching includes a select element comprising only a single diode that is not a Zener diode. The resistive-switching memory elements described herein can switch even when a switching voltage less than the breakdown voltage of the diode is applied in the reverse-bias direction of the diode. The memory elements are able to switch during the very brief period when a transient pulse voltage is visible to the memory element, and therefore can use a single diode per memory cell.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
G11C 17/06 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards using diode elements
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 13/02 - Digital stores characterised by the use of storage elements not covered by groups , , or using elements whose operation depends upon chemical change
G11C 11/36 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements
G11C 13/04 - Digital stores characterised by the use of storage elements not covered by groups , , or using optical elements
73.
THREE OR MORE RESISTIVE STATE RANDOM ACCESS MEMORY CELL
Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.
Provided are resistive random access memory (ReRAM) cells forming arrays and methods of operating such cells and arrays. The ReRAM cells of the same array may have the same structure, such as have the same bottom electrodes, top electrodes, and resistive switching layers. Yet, these cells may be operated in a different manner. For example, some ReRAM cells may be restively switched using lower switching voltages than other cells. The cells may also have different data retention characteristics. These differences may be achieved by using different forming operations for different cells or, more specifically, flowing forming currents in different directions for different cells. The resulting conductive paths formed within the resistive switching layers are believed to switch at or near different electrode interfaces, i.e., within a so called switching zone. In some embodiments, a switching zone of a ReRAM cell may be changed even after the initial formation.
Provided are methods of High Productivity Combinatorial testing of semiconductor substrates, each including multiple site isolated regions. Each site isolated region includes a titanium nitride structure as well as a hafnium oxide structure and/or a polysilicon structure. Each site isolated region is exposed to an etching solution that includes sulfuric acid, hydrogen peroxide, and hydrogen fluoride. The composition of the etching solution and/or etching conditions are varied among the site isolated regions to study effects of this variation on the etching selectivity of titanium nitride relative to hafnium oxide and/or polysilicon and on the etching rates. The concentration of sulfuric acid and/or hydrogen peroxide in the etching solution may be less than 7 % by volume each, while the concentration of hydrogen fluoride may be between 50 ppm and 200 ppm. In some embodiments, the temperature of the etching solution is maintained at between about 40C and 60C.
Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure.
Embodiments provided herein describe methods and systems for processing substrates. A plasma including radical species and charged species is generated. The charged species of the plasma are collected. A substrate is exposed to the radical species of the plasma. A layer is formed on the substrate after exposing the substrate to the radical species.
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers
78.
A MULTI-LEVEL MEMORY ARRAY HAVING RESISTIVE ELEMENTS FOR MULTI-BIT DATA STORAGE
A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
79.
Surface treatment methods and systems for substrate processing
Embodiments provided herein describe methods and systems for processing substrates. A plasma including radical species and charged species is generated. The charged species of the plasma are collected. A substrate is exposed to the radical species of the plasma. A layer is formed on the substrate after exposing the substrate to the radical species.
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/365 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and life and methods for forming the same. The nonvolatile memory device has a first layer on a substrate, a resistive switching layer on the first layer, and a second layer. The resistive switching layer is disposed between the first layer and the second layer and the resistive switching layer comprises a material having the same morphology as the top surface of the first layer. A method of forming a nonvolatile memory element in a ReRAM device includes forming a resistive switching layer on a first layer and forming a second layer, so that the resistive switching layer is disposed between the first layer and the second layer. The resistive switching layer comprises a material formed with the same morphology as the top surface of the first layer.
Methods for making conducting stacks includes forming a doped or alloyed silver layer sandwiched between two layers of transparent conductive oxide such as indium tin oxide (ITO). The doped silver or silver alloy layer can be thin, such as between 1. 5 to 20 nm and thus can be transparent. The doped silver or silver alloy can provide improved ductility property, allowing the conductive stack to be bendable. The transparent conductive oxide layers can also be thin, allowing the conductive stack can have improved ductility property.
B05D 5/12 - Processes for applying liquids or other fluent materials to surfaces to obtain special surface effects, finishes or structures to obtain a coating with specific electrical properties
82.
IMPROVED LOW EMISSIVITY COATING WITH OPTIMAL BASE LAYER MATERIAL AND LAYER STACK
A method for making low emissivity panels, including forming a base layer to promote a seed layer for a conductive silver layer. The base layer can be an amorphous layer or a nanocrystalline layer, which can facilitate zinc oxide seed layer growth, together with smoother surface and improved thermal stability. The base layer can include doped tin oxide, for example, tin oxide doped with Al, Ga, In, Mg, Ca, Sr, Sb, Bi, Ti, V, Y, Zr, Nb, Hf, Ta, or any combination thereof. The doped tin oxide base layer can influence the growth of (002) crystallographic orientation in zinc oxide, which in turn serves as a seed layer template for silver (111).
C03C 17/34 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
83.
Combinatorial processing using a remote plasma source
Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber, a remote plasma source, and a showerhead. Inert gas ports within the showerhead assembly can be used to alter the concentration and energy of reactive radical or reactive neutral species generated by the remote plasma source in different regions of the showerhead. This allows the showerhead to be used to apply a surface treatment to different regions of the surface of a substrate. Varying parameters such as the remote plasma parameters, the inert gas flows, pressure, and the like allow different regions of the substrate to be treated in a combinatorial manner.
C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
B44C 1/22 - Removing surface-material, e.g. by engraving, by etching
A spin deposition apparatus includes a deposition mask configured to be arranged proximate a target substrate. The deposition mask includes at least one fluid reservoir offset from a rotational axis of the deposition mask and configured to hold fluid for dispersal on a portion of a surface of the target substrate.
B05D 1/32 - Processes for applying liquids or other fluent materials using means for protecting parts of a surface not to be coated, e.g. using stencils, resists
85.
Dielectric doping using high productivity combinatorial methods
A combination of deposition processes can be used to evaluate layer properties using a combinatorial workflow. The processes can include a base ALD process and another process, such as a PVD process. The high productivity combinatorial technique can provide an evaluation of the material properties for given ALD base layer and PVD additional elements. An ALD process can then be developed to provide the desired layers, replacing the ALD and PVD combination.
Provided are semiconductor devices, such as resistive random access memory (ReRAM) cells, that include current limiting layers formed from doped metal oxides and/or nitrides. These current limiting layers may have resistivities of at least about 1 Ohm-cm. This resistivity level is maintained even when the layers are subjected to strong electrical fields and/or high temperature annealing. In some embodiments, the breakdown voltage of a current limiting layer may be at least about 8V. Some examples of such current limiting layers include titanium oxide doped with niobium, tin oxide doped with antimony, and zinc oxide doped with aluminum. Dopants and base materials may be deposited as separate sub-layers and then redistributed by annealing or may be co-deposited using reactive sputtering or co-sputtering. The high resistivity of the layers allows scaling down the size of the semiconductor devices including these layer while maintaining their performance.
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
87.
Embedded nonvolatile memory elements having resistive switching characteristics
Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.
G11C 11/21 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
88.
EMBEDDED NONVOLATILE MEMORY ELEMENTS HAVING RESISTIVE SWITCHING CHARACTERISTICS
Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
89.
Combinatorial approach for screening of ALD film stacks
In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H01L 21/365 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
Methods are described for forming CIGS absorber layers in TFPV devices with graded compositions and graded band gaps. Methods are described for utilizing Ag to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing Al to increase the band gap at the front surface of the absorber layer. Methods are described for utilizing at least one of Na, Mg, K, or Ca to increase the band gap at the front surface of the absorber layer.
A01N 43/42 - Biocides, pest repellants or attractants, or plant growth regulators containing heterocyclic compounds having rings with one nitrogen atom as the only ring hetero atom six-membered rings condensed with carbocyclic rings
91.
DEFECT ENHANCEMENT OF A SWITCHING LAYER IN A NONVOLATILE RESISTIVE MEMORY ELEMENT
Embodiments of the invention set forth a nonvolatile memory element with a novel variable resistance layer and methods of forming the same. The novel variable resistance layer includes a metal-rich host oxide that operates with a reduced switching voltage and current and requires significantly reduced forming voltage when manufactured. In some embodiments, the metal-rich host oxide is deposited using a modified atomic layer deposition (ALD) process. In other embodiments, the metal-rich host oxide is formed by depositing a metal-containing coupling layer on a host oxide and thermally processing both layers to create a metal-rich composite host oxide with a higher concentration of oxygen vacancies.
In some embodiments, the current invention discloses methods and apparatuses for making coated articles including a two step treatment process of a coated layer. The first step of the heat treatment involves a thermally assisted curing of the coated layer at a low temperature, which can strengthen the bond formation in the coated layer, leading to better layer stability during the subsequent heat treatment. The second step of the heat treatment involves annealing of the cured layer at a high temperature, which can control a porosity of the coated layer.
B05D 3/02 - Pretreatment of surfaces to which liquids or other fluent materials are to be appliedAfter-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials by baking
B05D 5/02 - Processes for applying liquids or other fluent materials to surfaces to obtain special surface effects, finishes or structures to obtain a matt or rough surface
C09C 3/12 - Treatment with organosilicon compounds
Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.
A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
Zinc oxide layer, including pure zinc oxide and doped zinc oxide, can be deposited with preferred crystal orientation and improved electrical conductivity by employing a seed layer comprising a metallic element. By selecting metallic elements that can easily crystallized at low temperature on glass substrates, together with possessing preferred crystal orientations and sizes, zinc oxide layer with preferred crystal orientation and large grain size can be formed, leading to potential optimization of transparent conductive oxide layer stacks.
B32B 17/06 - Layered products essentially comprising sheet glass, or fibres of glass, slag or the like comprising glass as the main or only constituent of a layer, next to another layer of a specific substance
96.
HPC optimization of contacts to optoelectronic devices
HPC techniques are applied to the screening and evaluating the materials, process parameters, process sequences, and post deposition treatment processes for the development of ohmic contact stacks for optoelectronic devices. Simple test structures are employed for initial screening of basic materials properties of candidate materials for each layer within the stack. The use of multiple site-isolated regions on a single substrate allows many material and/or process conditions to be evaluated in a timely and cost effective manner. Interactions between the layers as well as interactions with the substrate can be investigated in a straightforward manner.
Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
98.
ANTIREFLECTIVE COATINGS WITH CONTROLLABLE POROSITY AND DURABILITY PROPERTIES USING CONTROLLED EXPOSURE TO ALKALINE VAPOR
In some embodiments, the present invention discloses methods and apparatuses for making coated articles comprising exposing the coated layer to vapor-phase agents to modify its properties, such as the bonding and distribution of the coating mass. The coated layer is a porous solid layer, deposited via methods such as sol-gel, physical or chemical vapor deposition, aerosol deposition, or other methods capable of depositing a porous solid coating, with or without further processing such as curing or heat treatment.
H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
100.
Surface treatment to improve resistive-switching characteristics
This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.
H01L 47/00 - Bulk negative resistance effect devices, e.g. Gunn-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
