A picture processing device (100) is provided with an acquisition unit (101) for acquiring detection information relating to an XR device (1) equipped with a plurality of sensors (10a-10n), and a control unit (102) for controlling, on the basis of the detection information, the resolution or the frame rate of one or more pictures among a plurality of pictures obtained by the plurality of sensors (10a-10n) so as to inhibit an increase in power consumption of the XR device (1).
H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
H04N 23/63 - Control of cameras or camera modules by using electronic viewfinders
H04N 23/65 - Control of camera operation in relation to power supply
2.
ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD
An analog-to-digital (ADC) (20) comprises: a CCO-type first ADC that converts a time-integrated quantity of an input current into an upper M-bit first digital value and outputs the first digital value; and a second ADC that converts the difference between the time-integrated quantity of the input current and a time-integrated quantity of a current converted by the first ADC into a lower N-bit second digital value and outputs the second digital value. The first ADC includes: a first oscillator (21) including a first capacitor & switch array (21a) that time-integrates the input current, a first comparator (21b) that compares a voltage generated in the first capacitor with a threshold voltage, and a first switch that resets the charge accumulated in the first capacitor in accordance with the output of the first comparator (21b); and a counter (24) that counts the number of times the output of the first comparator (21b) is inverted, and outputs the counted result as a first digital value. The second ADC is a non-CCO-type ADC which differs from the CCO-type ADC.
H03M 1/52 - Input signal integrated with linear return to datum
H03M 1/14 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
A Doherty amplifier (100) comprises: an input terminal (PIN) to which a high-frequency signal is input; an output terminal (POUT) from which the high-frequency signal is output; a first carrier amplifier (151) provided in a first signal path from the input terminal (PIN) to the output terminal (POUT); a second carrier amplifier (161) provided, in the first signal path, on the output terminal (POUT) side relative to the first carrier amplifier (151); a first peak amplifier (171) provided in a second signal path from the input terminal (PIN) to the output terminal (POUT); and a second peak amplifier (181) provided, in the second signal path, on the output terminal (POUT) side relative to the first peak amplifier (171). The Doherty amplifier (100) further comprises: a temperature sensor (110) that detects the temperature of the Doherty amplifier (100); and a first amplifier gain adjustment circuit (190) that adjusts the power gain of at least one amplifier in accordance with a detection signal (Tdet) output from the temperature sensor (110).
A control device (100) comprises: camera input units (103a-103n) that acquire a plurality of videos output from sensors (10a-10n) which operate in synchronization on a fixed cycle; and a control unit (102) that reads the plurality of videos at different times.
H04N 23/45 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
This image output device (10) uses USB to output an image to which an endpoint is assigned, and comprises: an acquisition unit (for example, an image processing unit (11)) that acquires respective images from a plurality of imaging devices (30-32) via an interface different from USB; and a control unit (for example, a USB controller (15)) that executes control for outputting the respective images from the plurality of imaging devices (30-32) to a plurality of endpoints (EP0, EP2). The control unit outputs, to one endpoint (EP0) among the plurality of endpoints (EP0, EP2), a joined image (for example, an image (v5)) obtained by joining two or more images from two or more imaging devices among the plurality of imaging devices (30-32).
This gas detector comprises: a gas sensor element; a reference element that has been deactivated with regard to the gas; a control unit that controls an applied voltage or an applied current applied to the gas sensor element and the reference element; and a calculation unit that calculates the gas concentration from the respective output measurement results from the gas sensor element and the reference element. The control unit controls the applied voltage or the applied current on the basis of the output measurement result from the reference element.
G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon absorption of a fluidInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid
G01N 27/04 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
7.
REFERENCE VOLTAGE GENERATION CIRCUIT, LDO CIRCUIT, AND CONTROL METHOD
A reference voltage generation circuit (10) comprises a resistor (R11), a resistor (R12), a switch (SW1), a switch (SW2), a switch (SW3), a capacitor (C1), and a capacitor (Cref). The switch (SW1) and the switch (SW3) turn on, then the switch (SW3) turns off, and then the switch (SW1) turns off and the switch (SW2) turns on.
This selection device (100) is a selection device connected to a plurality of processors (for example, targets (210, 220, and 230)) and a debugger (for example, a host (400)) that executes debugging of the plurality of processors, the debugger being multidrop-connected to the plurality of processors, and comprises: a selection circuit (120) having a plurality of connection units (for example, connection terminals (121, 122, and 123)) connected to the plurality of processors on a one-to-one basis; and a switching circuit (170) that acquires number information indicating any of the connection destinations of the plurality of connection units, and causes the selection circuit (120) to output, to the debugger, only data input from a connection unit connected to the connection destination indicated by the number information among one or more pieces of data input from one or more connection units among the plurality of connection units.
This video signal processing device (100) comprises: an interrupt processing unit (101) that performs interrupt processing for acquiring a count value of a free-run counter (400) when a prescribed signal is generated; a delay time calculation unit (102) that calculates a delay time from the generation of the prescribed signal to the start of the interrupt processing on the basis of a count value of a prescribed counter (500) periodically reset in response to the generation of the prescribed signal; a signal generation timing calculation unit (103) that calculates a timing at which the prescribed signal is generated by subtracting the delay time from the count value of the free-run counter (400) acquired by the interrupt processing; and a period measurement unit (104) that measures the period of the prescribed signal by calculating the difference between the timing at which the current prescribed signal is generated and the timing at which the previous prescribed signal was generated.
A calibration support device (200) supports calibration for determining a correction amount corresponding to an actual distance to an object when correcting the distance to the object measured by a distance measurement device (100). The distance measurement device (100) comprises: a light-emitting unit (10) that emits light to the object; a light-receiving unit (20) that receives reflected light from the object that has reflected the light emitted by the light-emitting unit (10) ; and a distance calculation unit (40) that calculates a distance to the object based on the amount of the reflected light received by the light-receiving unit (20). The calibration support device (200) comprises: an acquisition unit (110) that acquires drive conditions for the distance measurement device (100); and a determination unit (120) that, based on the acquired drive conditions, determines the number of one or more dense arrangement ranges in which some correction points, among a plurality of correction points indicating positions to acquire data for determining a correction amount, are arranged more densely than in other ranges within the distance measurement range.
A fault injection circuit (100) comprises setting circuits (10a, 10b), an AND circuit (20), a monitoring circuit (30), and a stop circuit (40), which are configured from hardware. The setting circuits (10a, 10b) each configure the occurrence of the same fault injection. If the occurrence of fault injection is configured in both setting circuits (10a, 10b), the AND circuit (20) outputs a fault injection occurrence condition establishment signal which indicates establishment of a fault injection occurrence condition. The monitoring circuit (30) monitors whether the fault injection occurrence condition establishment signal has been output from the AND circuit (20) in a normal operation mode of a device under a fault injection test. If the fault injection occurrence condition establishment signal has been output from the AND circuit (20) when in the normal operation mode, the stop circuit (40) stops the fault injection into the device subjected to the test.
A method for driving a semiconductor device includes: setting a lower limit of a target resistance value of a nonvolatile resistive switching element; measuring a resistance value of the nonvolatile resistive switching element; determining whether the resistance value measured is below the lower limit of the target resistance value; and applying, when it is determined that the resistance value measured is below the lower limit of the target resistance value, a second high-resistance-setting voltage pulse and a first low-resistance-setting voltage pulse following the second high-resistance-setting voltage pulse to the nonvolatile resistive switching element. The second high-resistance-setting voltage pulse has second energy greater than first energy corresponding to a single application of the first high-resistance-setting voltage pulse, and applies a positive electric potential to a second electrode with respect to a first electrode.
This backlight control device (100) controls a backlight (300) used in a display device for displaying an image and comprises: a light emission amount calculation unit (110) that calculates, on the basis of image data for the image displayed by the display device, the light emission amount introduced to each region of a display surface by a plurality of light-emitting elements of the backlight (300); an adjustment unit (for example, a light emission amount peak level adjustment unit (131)) that adjusts the light emission amount of a first light-emitting element among the plurality of light-emitting elements on the basis of the light emission amounts of a plurality of second light-emitting elements surrounding the first light-emitting element; and an output unit (140) that outputs light emission amount information based on the adjusted light emission amount.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
G02F 1/133 - Constructional arrangementsOperation of liquid crystal cellsCircuit arrangements
G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
14.
SOLID-STATE IMAGING DEVICE, IMAGING DEVICE, AND DISTANCE-MEASURING IMAGING DEVICE
A solid-state imaging device (100a) comprises a pixel circuit (3) and a detection selection circuit (450). The pixel circuit (3) outputs a plurality of pixel signals. The detection selection circuit (450) has a detection circuit (420a) for generating the result of a comparison between a reference value and the level of one or more pixel signals among the plurality of pixel signals, and a sample-and-hold circuit (440a) having at least one capacitor. The sample-and-hold circuit (440a) has a holding control circuit (600a) that selects at least one pixel signal among the plurality of image signals and causes the at least one pixel signal to be held by the at least one capacitor.
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
This semiconductor device (1) which is provided with a vertical MOS transistor (10) comprises: a semiconductor layer (40); a plurality of gate trenches (17) that are formed in the semiconductor layer (40) and extend in a first direction; and a source electrode (51). The semiconductor layer (40) has a plurality of first recesses (100) that extend in the first direction at respective positions of the plurality of gate trenches (17) in a plan view. The source electrode (51) is configured by laminating a first conductive layer (51A) and a second conductive layer (51B). The upper surface of the first conductive layer (51A) has a plurality of second recesses (200) that extend in the first direction at positions included in the plurality of first recesses (100) in a plan view of the semiconductor device (1). The source electrode (51) additionally has a plurality of plugs (51D) that are formed between the first conductive layer (51A) and the second conductive layer (51B) and extend in the first direction, with the plugs (51D) being at least partially embedded in the plurality of second recesses (200), respectively.
A semiconductor module includes: a semiconductor device that includes n pads; and a mounting substrate that includes n lands corresponding one-to-one to the n pads. Each of the n pads is joined by solder bonding material to one of the n lands corresponding to the pad. When among the n pads, Pa denotes an area of a closest pad that is closest to a center of the semiconductor device and Pb denotes an area of a farthest pad that is farthest therefrom, and among the n lands, La denotes an area of a closest land corresponding to the closest pad and Lb denotes an area of a farthest land corresponding to the farthest pad, Pa/La is less than 1 and Pb/Lb is greater than 1, or Pa/La is greater than 1 and Pb/Lb is less than 1.
A level shift circuit includes: an input circuit that converts an input signal into a pair of complementary first signals, the input signal being generated using a first voltage source as a power source; a precharge circuit that outputs a pair of second signals from a first node and a second node, the pair of second signals corresponding to the pair of complementary first signals; and a precharge control circuit that outputs a pair of third signals and controls the precharge circuit, based on the pair of second signals. The input circuit includes a first phase alignment circuit that adjusts phases of the pair of complementary first signals to be substantially.
A hydrogen detection element (100) comprises: a hydrogen detection unit (50) provided with a sensitive layer (30), and with a first electrode layer (10) and a second electrode layer (20) which are laminated on the sensitive layer (30); and a water-repellent layer (40) composed of a self-assembled monolayer film. The second electrode layer (20) is laminated on the upper surface (31) of the sensitive layer (30). The first electrode layer (10) is laminated on the upper surface (31) of the sensitive layer (30) at a position different from the position of the second electrode layer (20) or on the lower surface of the sensitive layer (30). The water-repellent layer (40) covers the hydrogen detection unit (50) from above.
G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon absorption of a fluidInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid
A crystal oscillation circuit (30) comprises: a crystal oscillator (32); a FET (34b) having a gate (G) connected to one end of the crystal oscillator (32), a drain (D) connected to the other end of the crystal oscillator (32), and a source (S) to which a prescribed first DC potential (AVSS33; ground) is applied; a constant current source (34a) to which a prescribed second DC potential (DC power supply AVDD33) is applied; and a voltage-limiting circuit (34c) which is connected between an output terminal of the constant current source (34a) and the drain (D) and which limits the voltage of a signal appearing in the drain (D) so that the voltage does not exceed a prescribed value.
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
A semiconductor device includes: a semiconductor layer including a semiconductor substrate of a first conductivity type and a low-concentration impurity layer of the first conductivity type, the semiconductor substrate containing a first concentration of an impurity, the low-concentration impurity layer being in contact with a top surface of the semiconductor substrate and containing a second concentration of an impurity, the second concentration being lower than the first concentration; a first vertical metal-oxide-semiconductor (MOS) transistor and a second vertical MOS transistor that share the semiconductor substrate as a common drain region; and a first Schottky barrier diode that is connected in parallel with a body diode of the first vertical MOS transistor in a same forward direction, the low-concentration impurity layer serving as a cathode of the first Schottky barrier diode when the first conductivity type is n-type, and as an anode when the first conductivity type is p-type.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
21.
THREE-DIMENSIONAL SHAPE IDENTIFICATION METHOD, THREE-DIMENSIONAL SHAPE IDENTIFICATION DEVICE, AND PROGRAM
This three-dimensional shape identification method is executed by a computer, the three-dimensional shape identification method comprising: acquiring measurement data obtained due to a measurement device measuring a target object including a plurality of objects loaded in a prescribed space (S10); identifying a blind spot space produced by the plurality of objects in the prescribed space on the basis of the measurement data (S30); estimating one or more objects present in the blind spot space among the plurality of objects on the basis of the measurement data (S30); and identifying the three-dimensional shape of the target object on the basis of the measurement data and an estimation result for the one or more objects (S40).
This high-frequency power amplification device (1) is provided with a threshold voltage compensation circuit (201) connected to the gate of a power amplification transistor (102), and a voltage switching circuit (301). The voltage switching circuit (301) has a voltage switching transistor (303), a switching voltage terminal (302) connected to the gate and source of the voltage switching transistor (303), and a voltage adjustment circuit (305). When a voltage that turns off the voltage switching transistor (303) is applied to the switching voltage terminal (302), a first gate bias voltage is supplied to the gate of the power amplification transistor (102), and when a voltage that turns on the voltage switching transistor (303) is applied, a second gate bias voltage is supplied to the gate of the power amplification transistor (102).
A cutoff recovery device (10) is provided with: a prediction circuit (14) for predicting an amount of voltage drop of a power source (VDD) during power source recovery of a DSP (1 or 2) connected to the power source (VDD); and an impact assessment circuit (15) for assessing whether operation of a circuit in operation that is connected to the power source (VDD) will be impacted if a voltage drop of the predicted amount occurs, and determining an ON sequence for turning on a plurality of power switches (101-105 or 201-205) provided to a power supply line from the power source (VDD) to the DSP (1 or 2) on the basis of the result of this assessment.
G06F 1/26 - Power supply means, e.g. regulation thereof
H02J 1/00 - Circuit arrangements for dc mains or dc distribution networks
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A voltage measurement circuit includes: a first switched capacitor filter connected to a first battery cell included in a cell pack; a second switched capacitor filter connected to a second battery cell included in the cell pack; and a first amplifier shared by the first switched capacitor filter and the second switched capacitor filter. The first switched capacitor filter includes: a first switch group; a first capacitor; and a third switch group, the second switched capacitor filter includes: a second switch group; and a second capacitor; and a fourth switch group, the first switch group is electrically isolated from the third switch group via the first capacitor, and the second switch group is electrically isolated from the fourth switch group via the second capacitor.
A solid-state imaging device includes a sample-and-hold circuit. The sample-and-hold circuit includes: a first capacitor; a second capacitor; a first buffer having an output connected to an analog-to-digital (AD) conversion circuit; a first input switch disposed between a vertical signal line and the first capacitor; a second input switch disposed between the vertical signal line and the second capacitor; a first output switch disposed between the first capacitor and an input of the first buffer; and a second output switch disposed between the second capacitor and the input of the first buffer. In a plan view, the first output switch and the first buffer are adjacent to each other in a column direction of a pixel array, and the second output switch and the first buffer are adjacent to each other in the column direction of the pixel array.
A nitride semiconductor light-emitting element (100) is provided with an n-type cladding layer (104), an active layer (106), an electron blocking layer (108), a p-side guide layer (109), and a p-type cladding layer (110). Each of the electron blocking layer (108) and the p-side guide layer (109) contains a p-type impurity and Al. The electron blocking layer (108) has a first layer (108a), a second layer (108b), and a third layer (108c). The first layer (108a) includes a first position at which the concentration of the p-type impurity is greater than or equal to a first concentration and the Al composition ratio is maximized in the electron blocking layer (108). The Al composition ratio in the second layer (108b) is less than the Al composition ratio in the first layer (108a) and greater than or equal to the Al composition ratio in the third layer (108c). The concentration of the p-type impurity in the second layer (108b) is less than a second concentration, and the second concentration is less than the first concentration. The third layer (108c) has a region in which the concentration of the p-type impurity is greater than or equal to the second concentration and less than the first concentration.
H01S 5/343 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser
H01S 5/023 - Mount members, e.g. sub-mount members
H01S 5/22 - Structure or shape of the semiconductor body to guide the optical wave having a ridge or a stripe structure
H10H 20/825 - Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
27.
LIGHT-EMITTING DEVICE AND DISTANCE MEASURING DEVICE
This light-emitting device (100) includes: a light-emitting element (10); a drive circuit (20) which has a switch element connected in series to the light-emitting element (10) and drives the light-emitting element (10); and a control circuit (40) which controls the drive circuit (20). The control circuit (40) performs pulse control for causing the light-emitting element (10) to emit pulsed light and CW control for causing the light-emitting element (10) to emit CW light by controlling the current flowing through the switch element under the control of the drive circuit (20). The control circuit (40) changes the magnitude of the current flowing through the switch element between pulse control and CW control.
This semiconductor device (100) comprises: a substrate (101); a first nitride semiconductor layer (103) on the substrate (101); a second nitride semiconductor layer (104) on the first nitride semiconductor layer (103), the second nitride semiconductor layer (104) having a larger band gap than the first nitride semiconductor layer (103); a two-dimensional electron gas layer (105) in the vicinity of the boundary between the first nitride semiconductor layer (103) and the second nitride semiconductor layer (104); a p-type third nitride semiconductor layer (106) on the second nitride semiconductor layer (104); a gate electrode (303) on the third nitride semiconductor layer (106); a drain electrode (301); a p-type fourth nitride semiconductor layer (107) provided at a position, on the second nitride semiconductor layer (104), between the gate electrode (303) and the drain electrode (301); and an injection electrode (304) provided on the fourth nitride semiconductor layer (107) and supplied with an injection voltage (Vh) lower than a drain voltage (Vd) supplied to the drain electrode (301).
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 30/80 - FETs having rectifying junction gate electrodes
H10D 30/83 - FETs having PN junction gate electrodes
29.
BATTERY MONITORING DEVICE AND BATTERY MONITORING METHOD
A battery monitoring device (1) comprises n + 1 first terminals, two second terminals, a storage unit (12), and an impedance calculation unit (11), a multi-cell filter unit (100) is connected between n battery cells and the n + 1 first terminals, a single-cell filter unit (200) is connected between a shunt resistor (300) and the two second terminals, the storage unit (12) stores a multi-cell filter characteristic prepared in advance and a single-cell filter characteristic prepared in advance, and the impedance calculation unit (11) calculates an AC impedance in which components of the multi-cell filter characteristic and the single-cell filter characteristic are cancelled, on the basis of a voltage measured via the n + 1 first terminals, a current measured via the two second terminals, the multi-cell filter characteristic, and the single-cell filter characteristic.
A battery monitoring system (100) comprises: a drive control unit (23) that applies a first pulse current to a battery (B1) and applies a second pulse current in the direction opposite from the first pulse current to a battery (B2); a voltage measurement unit (20) that measures a first complex voltage of the battery (B1) and a second complex voltage of the battery (B2); a current measurement unit (21) that measures a first complex current flowing through the battery (B1) and a second complex current flowing through the battery (B2); an impedance computation unit (201) that measures a first complex impedance of the battery (B1) on the basis of the first complex current and the first complex voltage, and measures a second complex impedance of the battery (B2) on the basis of the second complex current and the second complex voltage; and an AC detection unit (22) that calculates a complex current flowing through a load (3) on the basis of the first complex voltage and the second complex voltage.
A drive measurement circuit (2) comprises a current measuring unit (21) that measures the current of a battery (B1) and the current of a battery (B2), a voltage measuring unit (20) that measures the voltage of the battery (B1) and the voltage of the battery (B2), an alternating current detecting unit (22) that, on the basis of the measurement results from the voltage measuring unit (20) and the measurement results from the current measuring unit (21), measures an AC voltage and an AC current corresponding to a measuring frequency and outputs the same to an MCU (200), and a drive control unit (23) that causes an AC current to flow to the battery (B1) and the battery (B2) by driving a plurality of switching elements (11, 12) so as to periodically change the state of movement of a current passing through an inductor (14) in accordance with the measurement frequency, wherein the drive control unit (23) repeats causing and not causing the AC current to flow to the battery (B1) and the battery (B2), and in the repetitions, switches the waveform of the initial pulse when the AC current starts to flow from among two or more types of waveforms.
G01R 31/389 - Measuring internal impedance, internal conductance or related variables
G01R 27/02 - Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
A semiconductor device (1) is provided with a vertical MOS transistor (10). The semiconductor device (1) comprises a low-concentration impurity layer (33), a body region (18) formed in the low-concentration impurity layer (33), and a plurality of gate trenches (17) formed from the upper surface of the low-concentration impurity layer (33) to a depth penetrating the body region (18). The body region (18) is provided with a central region (51) having a constant first depth from the upper surface of the low-concentration impurity layer (33), and a shallow bottom region (53) in which the depth from the upper surface of the low-concentration impurity layer (33) is shallower than the first depth. The plurality of gate trenches (17) include a plurality of central region gate trenches (17A) that penetrate at least a portion of the central region (51), and a plurality of shallow bottom region gate trenches (17B) that penetrate the shallow bottom region (53) and do not penetrate the central region (51).
A battery monitoring device (1) is provided with: a motor drive current frequency information acquisition unit (25) that acquires frequency information of the drive current of a motor (28), which is the load of a battery assembly (6); a control unit (9) that determines a measurement frequency on the basis of the frequency information; an AC superimposition unit (11) that supplies an AC current at the measurement frequency to the battery assembly (6); a voltage measurement unit (13) that measures the voltage of each of a plurality of batteries (5) through which the AC current flows; an AC superimposed current measurement unit (21) that measures the current value of the AC current; and an impedance calculation unit (23a) that measures the AC impedance of each of the plurality of batteries (5) on the basis of the voltage of each of the plurality of batteries (5) and the current value of the AC current.
A motor drive device is a sensorless device that detects zero-crossing of a counter electromotive voltage generated in a winding of a motor (100) for rotation control of the motor (100), and comprises: a detection unit (10) that determines whether a phase of a winding current flowing through the winding of the motor (100) is ahead of a phase of the counter electromotive voltage; and a waveform setting unit (20) that receives an acceleration command for the motor (100) if determined that the phase of the winding current is ahead of the phase of the counter electromotive voltage, and does not receive the acceleration command for the motor if determined that the phase of the winding current is behind the phase of the counter electromotive voltage.
A component-embedded substrate (1) is provided with: a first wiring layer (2); a second wiring layer (3); a sealing material (4) disposed between the first wiring layer (2) and the second wiring layer (3); and a semiconductor device (10) sealed by the sealing material (4). The thickness of the sealing material (4), from the first wiring layer (2) to a first main surface (10a) of the semiconductor device (10) in the thickness direction (Z-axis direction), is smaller at the outer periphery of the semiconductor device (10) than at the center of the semiconductor device (10) within the plane of the semiconductor device (10).
This conversion device (1) comprises: an acquisition unit (11) that acquires data which indicates the magnitude of a signal and in which additional information is embedded by a predetermined method; a saving unit (12) that saves the additional information embedded in the acquired data; a conversion unit (13) that performs a predetermined conversion process on the acquired data; and an embedding unit (14) that embeds the saved additional information in the data on which the predetermined conversion process has been performed.
H03M 7/30 - CompressionExpansionSuppression of unnecessary data, e.g. redundancy reduction
H04B 14/04 - Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation
H04L 7/00 - Arrangements for synchronising receiver with transmitter
37.
NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF
A nitride-based semiconductor light-emitting element includes: a substrate that is an example of a n-type nitride-based semiconductor including a group IV n-type impurity; and an n-side electrode in contact with the substrate. The substrate includes: a surface layer region in contact with the n-side electrode and including a halogen element; and an internal region located across the surface layer region from the n-side electrode. A peak concentration of the group IV n-type impurity in the surface layer region is at least 1.0×1021 cm−3. A peak concentration of the halogen element in the surface layer region is at least 10% of the peak concentration of the group IV n-type impurity in the surface layer region. A concentration of the group IV n-type impurity in the internal region is lower than a concentration of the group IV n-type impurity in the surface layer region.
H01S 5/343 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser
A hydrogen detection device includes: a bridge circuit including a first resistive element (hydrogen sensor), a second resistive element (reference element), a third resistive element (reference element), and a fourth resistive element (reference element). Each of the first to fourth resistive elements is provided on a semiconductor substrate and includes: first and second electrodes whose principal surfaces face each other; a metal oxide layer disposed in contact with the principal surfaces of the first and second electrodes; and insulating film and the like covering the second electrode and the like, and in at least the first resistive element among the first to fourth resistive elements, the insulating film and the like include an opening that is not covered by the insulating film and the like and through which an other surface of the second electrode opposite to the principal surface of the second electrode is exposed.
G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon absorption of a fluidInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
A semiconductor device (1) includes: a first conductivity type low-concentration impurity layer (33) formed on a first conductivity type semiconductor substrate (32); a second conductivity type body region (18) formed on the low-concentration impurity layer (33); a plurality of gate trenches (17) extending in a first direction that is parallel to the upper surface of the semiconductor substrate (32) and that is formed at equal intervals in a second direction parallel to the upper surface and orthogonal to the first direction; and a plurality of first conductivity type source regions (14) and a plurality of second conductivity type body contact regions (13), which are alternately formed in the first direction during a first period in each of the plurality of mesa portions (20) sandwiched between the plurality of gate trenches (17) in the second direction. Each upper surface of the plurality of mesa portions (20) has a plurality of first recessed portions (71) that are recessed in the first direction during a second period that is n (where n is an integer of 1 or more) times the first period, and at least a portion of the lower surface of the recessed portions are in contact with a body contact region (13) or the body region (18).
A DC-DC converter that controls output power of direct current (DC) by controlling on and off of a high-side switch, and the DC-DC converter includes: a controller that adjusts an off-time of the high-side switch for controlling the output power. In the DC-DC converter, the controller makes an on-time of the high-side switch inversely proportional to an input-output voltage difference that is a difference between an input voltage to the DC-DC converter and an output voltage from the DC-DC converter.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/15 - Arrangements for reducing ripples from DC input or output using active elements
A DC-DC converter that includes: a high-side switch; a low-side switch; an inductor; an output capacitor; and a controller. In the DC-DC converter, the controller includes: a pre-charge circuit that charges the output capacitor; a negative current detection circuit that outputs a negative current detection signal indicating that current flowing from the inductor to the low-side switch has reached a predetermined value; and a control circuit that performs a switching operation that alternately turns on the high-side switch and the low-side switch, and the control circuit starts the switching operation by turning on the low-side switch, and turns off the low-side switch after receiving the negative current detection signal.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device includes a low-concentration impurity layer provided on a semiconductor substrate, a body region provided in the low-concentration impurity layer, gate trenches extending in a first direction parallel to the top surface of the semiconductor substrate and arranged at equal intervals in a second direction orthogonal to the first direction, and source regions and body contact regions arranged alternately one by one at first intervals in the first direction in each of mesa portions sandwiched between the gate trenches in the second direction. The top surface of each of the mesa portions includes first recessed portions that are recessed at second intervals in the first direction and whose bottom surfaces are at least partially in contact with the body contact regions or the body region, the second intervals being n times the first intervals, where n is an integer greater than or equal to one.
A battery monitoring device includes: a signal generator for controlling a first measurement circuit connected to a first assembled battery and a second measurement circuit connected to a second assembled battery, the first assembled battery and the second assembled battery being obtained by dividing batteries connected in series; and an impedance calculator that calculates the alternating current impedance of each of the plurality of batteries, based on (i) the current value of current flowing through the first measurement circuit and the voltage value of each battery included in the first assembled battery and (ii) the current value of current flowing through the second measurement circuit and the voltage value of each battery included in the second assembled battery. The signal generator generates a control signal for turning on a first switch of the first measurement circuit and a second switch of the second measurement circuit in a mutually exclusive manner.
G01R 31/389 - Measuring internal impedance, internal conductance or related variables
G01R 31/374 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with means for correcting the measurement for temperature or ageing
G01R 31/3842 - Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
G01R 31/392 - Determining battery ageing or deterioration, e.g. state of health
44.
DISTANCE MEASURING DEVICE AND DISTANCE MEASURING METHOD
A distance measuring device includes: a light source that irradiates a predetermined range with irradiation light; a light receiver including a plurality of pixels; an image recognizer that obtains an image showing at least a part of the predetermined range, and detects a recognition target object, by performing image recognition on the obtained image; a drive controller that adjusts an irradiation condition of the irradiation light, based on a first output that each of one or more pixels outputs based on the reflected light of the irradiation light emitted under a predetermined irradiation condition, the one or more pixels corresponding to a region including the recognition target object; and a distance calculator that calculates the distance to the recognition target object, based on a second output that each of the plurality of pixels outputs based on the reflected light of the irradiation light emitted under the adjusted irradiation condition.
A battery monitoring device includes: a first temperature obtainer that obtains a first temperature that is an external temperature of a battery pack that includes a plurality of secondary batteries; a second temperature obtainer that obtains a second temperature that is an internal temperature of each of the plurality of secondary batteries; a third temperature obtainer that obtains a third temperature that includes temperature distribution information of the battery pack; and a determiner that compares the first temperature, the second temperature, and the third temperature and determines, for each of the first temperature, the second temperature, and the third temperature, whether an abnormality is present.
G01R 31/392 - Determining battery ageing or deterioration, e.g. state of health
G01R 31/36 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
G01R 31/374 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with means for correcting the measurement for temperature or ageing
G01R 31/3842 - Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
G01R 31/389 - Measuring internal impedance, internal conductance or related variables
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
46.
BATTERY MONITORING DEVICE AND BATTERY MONITORING METHOD
A battery monitoring device includes: a storage that stores relational data indicating a relationship between a state of a secondary battery and a resistance component that varies with the state of the secondary battery among a plurality of resistance components included in an impedance of the secondary battery; an impedance obtainer that obtains an impedance of a target secondary battery for monitoring; and an arithmetic processor that calculates, based on the impedance obtained by the impedance obtainer, a value of a resistance component that varies with a state of the target secondary battery for monitoring, to estimate the state of the target secondary battery for monitoring, based on the value of the resistance component and the relational data.
G01R 31/392 - Determining battery ageing or deterioration, e.g. state of health
G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
G01R 31/371 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with remote indication, e.g. on external chargers
G01R 31/374 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with means for correcting the measurement for temperature or ageing
G01R 31/389 - Measuring internal impedance, internal conductance or related variables
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
47.
SEMICONDUCTOR INTEGRATED CIRCUIT AND DATA TRANSFER METHOD
A semiconductor integrated circuit for scrambling data and transferring the data to a transfer destination circuit includes: a scrambler that generates a scramble key and scrambles the data using the scramble key to generate scrambled data, the scramble key having a Hamming weight of B/2 when B is an even number and having a Hamming weight of (B+1)/2 or (B−1)/2 when B is an odd number where B denotes a bus width of the data; and a transfer controller that transfers the scrambled data to the transfer destination circuit.
A memory system includes a memory controller and an external memory connected to the memory controller. The memory controller transmits, to the external memory: a read command or a write command; a data size; an address interval that is an interval between addresses of units of contiguous data of the data size; and a start address. The external memory reads or writes data based on the data size, the address interval, and the start address so as to perform access in accordance with the read command or the write command.
This imaging element comprises: a plurality of pixels arranged in a matrix; a plurality of first vertical signal lines that is provided corresponding to the columns of the plurality of pixels and that extends in the column direction; a pixel chip on which the plurality of pixels and the plurality of first vertical signal lines are arranged; one or more column circuit groups (40) including a plurality of column circuits (41) arranged along the row direction; a plurality of power supply lines (50) that is electrically connected to the plurality of column circuits (41) and that extends in the column direction; a logic chip (120) on which the one or more column circuit groups (40) and the plurality of power supply lines (50) are arranged and which is laminated with the pixel chip; and a plurality of first pads (11) that is electrically connected to the plurality of column circuits (41) via the plurality of power supply lines (50) and that is arranged along the row direction. A pitch (P1) at which the plurality of first pads (11) are arranged side by side is an integral multiple of a pitch (P2) at which the column circuits (41) are arranged side by side.
A ranging device (100) comprises: a light source (10) that emits irradiation light; a light reception unit (20) that has a plurality of pixels; a drive control unit (30) that controls the driving of the light source (10) and the plurality of pixels; and a distance calculation unit (50) that calculates the distance to an object (OBJ) on the basis of signals outputted by the plurality of pixels. The drive control unit (30): classifies the plurality of pixels into a plurality of groups each for exposing pixels therein at the same timing, the plurality of groups including a first group to which first pixels among the plurality of pixels belong and a second group to which second pixels adjacent to the first pixels among the plurality of pixels belong; drives the plurality of pixels such that, in the same frame, the timing of exposure based on emission of irradiation light differs between the plurality of groups; and drives the plurality of pixels such that, across consecutive frames, the timing of exposure based on emission of irradiation light alternates between the plurality of groups.
G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
G01C 3/06 - Use of electric means to obtain final indication
G01S 7/4861 - Circuits for detection, sampling, integration or read-out
51.
REFERENCE VOLTAGE GENERATION CIRCUIT, REFERENCE CURRENT GENERATION CIRCUIT, REFERENCE VOLTAGE GENERATION METHOD, AND REFERENCE CURRENT GENERATION METHOD
This reference voltage generation circuit (2) comprises: a bandgap reference voltage generation circuit (10) that generates a reference voltage (Vref) on the basis of the difference in current density between collector currents of NPN bipolar transistors (Q1 and Q2); and a current gain compensation current generation circuit (20) that generates first and second current gain compensation currents (a first current (i) and a second current (ii)) having the same value as a base current of the NPN bipolar transistors (Q1 and Q2). The first and second current gain compensation currents (the first current (i) and the second current (ii)) respectively flow only between a base terminal and an emitter terminal of the NPN bipolar transistors (Q1 and Q2).
A semiconductor device (1) comprises: a semiconductor layer (40) that includes a first region (A1) and a second region (A2) and that has an area bisected by the first region (A1) and the second region (A2); a transistor (10); and a transistor (20), wherein first gate wiring (114) surrounding a first source electrode (11) and second gate wiring (124) surrounding a second source electrode (21) are formed, the first gate wiring (114) and the second gate wiring (124) are formed such that the boundary (90C) between the first region (A1) and the second region (A2) is interposed therebetween, drain wiring (140) surrounds the first gate wiring (114) and the second gate wiring (124), and the drain wiring (140) is not formed between the first gate wiring (114) and the second gate wiring (124).
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
A semiconductor device (100) includes: a gate field plate (131) that is electrically connected to a gate electrode (130), extends in a direction from the gate electrode (130) toward a drain electrode (150), and covers the side surface of a p-type semiconductor layer (120) on the drain electrode side; and a source field plate (142) that is electrically connected to a source electrode (140), extends in a direction from the source electrode (140) toward the drain electrode (150), and covers the side surface of the gate field plate (131) on the drain electrode side. The source field plate (142) extends from the source electrode (140) to a position at least 2.5 μm closer to the drain electrode (150) from the side surface of the gate field plate (131) on the drain electrode side.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
54.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
Provided is a semiconductor device (1) comprising: a semiconductor laminate (20) having an electron transit layer (22) being a first nitride semiconductor layer and an electron supply layer (23) being a second nitride semiconductor layer located above the electron transit layer (22); a gate layer (40) being a p-type third nitride semiconductor layer located above a first region (20a) of the semiconductor laminate (20); a source electrode (70S) and a drain electrode (70D) located above a second region (20b) of the semiconductor laminate (20); and a gate electrode (70G) being a Schottky electrode located above the gate layer (40). The source electrode (70S), the drain electrode (70D), and the gate electrode (70G) include a TiAl alloy layer.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 30/83 - FETs having PN junction gate electrodes
55.
REFERENCE VOLTAGE GENERATION CIRCUIT AND REFERENCE VOLTAGE GENERATION METHOD
A reference voltage generation circuit (4) comprises: a transistor-characteristic voltage generation circuit (10) that comprises, inter alia, a transistor element group (NPN bipolar transistors (Q1 and Q2)) constituted by two types of transistor elements having different conduction current densities, and that generates a transistor-characteristic voltage (band gap reference voltage (Vbgr)); and a stress-compensation current generation circuit (20) that generates a stress-compensation current (Icompout) of which the direction and/or magnitude is changed on the basis of the direction and/or magnitude of stress applied to a semiconductor substrate. The transistor-characteristic voltage generation circuit (10) generates a voltage corresponding to the stress-compensation current by using a voltage drop caused by the stress-compensation current of a resistance element (R1a), and generates a reference voltage (Vref) by adding the voltage drop to or subtracting the voltage drop from the transistor-characteristic voltage.
This solid-state imaging device (10) comprises: a plurality of pixels (30) that are disposed in a two-dimensional shape; and a first light shielding body (60) and a second light shielding body (70) that are disposed at a boundary part (35) between adjacent pixels (30) and have a function of shielding light. Each of the plurality of pixels (30) has a photoelectric conversion unit (41) and an insulating film (50) formed on the photoelectric conversion unit (41). The first light shielding body (60) includes at least one among a first light-shielding wall (61) that is disposed in the insulating film (50) in the boundary part (35) and extends in a first direction intersecting a light-receiving surface (41a) of the photoelectric conversion unit (41), and a first light-shielding film (62) that extends in a second direction intersecting the first direction. The second light-shielding body (70) is disposed on the opposite side of the photoelectric conversion unit (41) with respect to the first light-shielding body (60) and is spaced apart from the first light-shielding body (60).
A wireless communication device according to the present invention is provided to one of a master device (200) that controls a battery (11a) and a slave device (100) that monitors the battery (11a). The wireless communication device comprises a memory unit that can store first firmware that is being applied and second firmware that has been acquired by wireless communication, a wireless communication testing control unit that performs a test of wireless communication with a wireless communication device that is provided to the other of the master device (200) and the slave device (100), and an OTA unit that controls the firmware that is applied. After the OTA unit has switched the firmware that is applied from the first firmware to the second firmware, the wireless communication testing control unit performs the wireless communication test, and when the wireless communication test is not successful, the OTA unit re-applies the first firmware.
A semiconductor device that is a square in a plan view, the semiconductor device including: a vertical MOS transistor; and a Schottky barrier diode in which the semiconductor layer functions as an anode or a cathode. The semiconductor device further includes: a first pad that is a portion of an upper surface of the semiconductor device; a second pad that is a portion of the upper surface; a third pad that is a portion of the upper surface; and a fourth pad that is a portion of the upper surface, the first pad to the fourth pad being circles each having an equal diameter. In the plan view, centers of the first pad and the third pad are located on one diagonal line of the semiconductor device, and centers of the second pad and the fourth pad are located on an other diagonal line of the semiconductor device.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
59.
WIRELESS COMMUNICATION DEVICE AND MONITORING SYSTEM
A wireless communication device includes a medium access control (MAC) portion having functions of a media link layer, a physical layer (PHY) portion having functions of physical layer, and an error correction circuit (ECC) portion that performs error-correction related processing on a passing signal. The ECC portion is connected between the MAC portion and PHY portion.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 1/1867 - Arrangements specially adapted for the transmitter end
H04W 4/48 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for in-vehicle communication
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
60.
WIRELESS COMMUNICATION DEVICE AND MONITORING SYSTEM
A wireless communication device includes: a first wireless communication subsystem including a first wireless communication circuit; a second wireless communication subsystem including a second wireless communication circuit; and a control system that controls the first wireless communication subsystem and the second wireless communication subsystem. The first wireless communication subsystem, the second wireless communication subsystem, and the control system are configured as a single semiconductor device.
A method for manufacturing a semiconductor laser element (1), wherein: a bar-shaped substrate (4) has a front surface (1f), a rear surface (1r), a first side surface (1a) perpendicular to a first direction parallel to at least a part of the front surface (1f), and a second side surface (1b); the bar-shaped substrate (4) has a plurality of waveguides (10w) extending in the first direction; the plurality of waveguides (10w) are arranged in a second direction perpendicular to the first direction; the semiconductor laser element (1) has a waveguide (10w), a part of each of the front surface (1f), the rear surface (1r), the first side surface (1a), and the second side surface (1b), a third side surface (1c), and a fourth side surface (1d). The method for manufacturing the semiconductor laser element (1) includes: a notch forming step of forming a plurality of notches (50) arranged along the first direction between two adjacent waveguides (10w) on the front surface (1f); and a dividing step of dividing the bar-shaped substrate (4) along the first direction. The third side surface (1c) and the fourth side surface (1d) are formed by the dividing step.
This nitride semiconductor device (1) comprises a power FET (11), an ESD protection FET (12), a diode (13), and a resistor element (14). A gate structure (50G) of the power FET (11) includes a p-type semiconductor layer (52G) and a gate electrode (54G) that is Schottky-connected to the p-type semiconductor layer (52G). An anode structure (50A) of the diode (13) includes a p-type semiconductor layer (52A). The gate structure (50G), a drain structure (51D) of the ESD protection FET (12), and the anode structure (50A) are electrically connected to each other. A source structure (50S) of the power FET (11), a source structure (51S) of the ESD protection FET (12), and a terminal structure (50R) of the resistor element (14) are electrically connected to each other. A gate structure (51G) of the ESD protection FET (12), a cathode structure (50K) of the diode (13), and a terminal structure (51R) of the resistor element (14) are electrically connected to each other.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
63.
MOTOR CONTROL DEVICE, MOTOR CONTROL SYSTEM, AND CONTROL METHOD
A motor control device (100) has an inverter circuit (20) and a control/drive circuit (30) that supplies a drive signal for controlling a motor (10) to each switch element constituting a plurality of switch element pairs of the inverter circuit (20). The control/drive circuit (30) performs control for supplying the drive signal to each switch element so as to alternately repeat, as deceleration control for reducing the rotational speed of the motor (10), an all-off mode in which all the switch elements are turned off and a short brake mode in which one switch element group among all the upper switch elements and all the lower switch elements is turned on and the other switch element group among all the upper switch elements and all the lower switch elements is turned off.
H02P 6/06 - Arrangements for speed regulation of a single motor wherein the motor speed is measured and compared with a given physical value so as to adjust the motor speed
H02P 6/08 - Arrangements for controlling the speed or torque of a single motor
64.
SEMICONDUCTOR STORAGE DEVICE AND MULTIPLY–ACCUMULATE OPERATION DEVICE
), ), connected in series between a bit line (BL) and a first source line (SL); a second resistance element (62n) and a second switch element (72n), which is controlled by the first word line (WL), connected in series between the bit line (BL) and a second source line (SLB); a third switch element (73p), which is controlled by a second word line (WLB), connected in series with the second resistance element (62n) between the bit line (BL) and the first source line (SL); and a fourth switch element (74n), which is controlled by the second word line (WLB), connected in series with the first resistance element (61p) between the bit line (BL) and the second source line (SLB).
An insulation resistance measurement device (20) comprising: a first series circuit that is connected between the negative electrode of a battery (1) and the ground, and that has a first resistor (21), a capacitor (22), and a first switch (23) connected in series; a second switch (25) that discharges the capacitor (22); a current detection circuit (24) that detects a current flowing through the first series circuit and outputs a current detection signal; and a control circuit (26) that controls the first switch (23) and the second switch (25), wherein the control circuit (26) calculates the resistance values of insulation resistances (101 and 102) on the basis of the current detection signal obtained when the first switch (23) is on and the second switch (25) is off.
A semiconductor device includes: a vertical metal-oxide semiconductor (MOS) transistor. In a plan view, an active region of the vertical MOS transistor includes unit cells repeatedly arranged within a plane of the active region, each unit cell is a hexagon having a perimeter defined along center positions of a width of a gate trench, in each unit cell, a shape of the body contact region exposed at the upper surface of a low-concentration impurity layer has a center that coincides with a center of the unit cell and rotational symmetry of 60° or less in a clockwise direction, and Lxm/3≤Lxr≤Lxm is satisfied, where Lxr μm denotes the width of the gate trench, and Lxm μm denotes a distance between parallel portions of the gate trench that face each other.
A nitride semiconductor device is a nitride semiconductor device including an active element and a passive element, and includes: a nitride semiconductor layer divided into an active region and an inactive region in a plan view; and a metal layer in contact with the nitride semiconductor layer in the inactive region. The active element is provided in the active region, and the passive element is provided in the inactive region. The metal layer includes a coherent state or a metamorphic state relative to the nitride semiconductor layer.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/60 - Impurity distributions or concentrations
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
A control system is included in each of sensors in a detection system that detects an object by using the sensors. The control system includes a counter, a first obtainer, a second obtainer, and a processing section. The counter generates an operation signal for causing a corresponding one of the sensors to operate in accordance with a counter value. The first obtainer obtains time information shared among the sensors. The second obtainer obtains the counter value of the counter at a time point when the first obtainer obtains the time information. Based on the time information obtained by the first obtainer and the counter value obtained by the second obtainer, the processing section performs adjustment processing for adjusting a timing at which an operation signal is generated.
This method for driving a semiconductor device (100) comprises: a high resistance state measurement step (S21) for measuring a resistance value (HR) of a nonvolatile variable resistance element (20) in a high resistance state or a semi-high resistance state; a low resistance voltage pulse application step (S14) for applying a low resistance voltage pulse to the nonvolatile variable resistance element (20); a high resistance state determination step (S20) for determining whether or not the resistance value (HR) obtained in the high resistance state measurement step (S21) is within a predetermined range of a reference resistance value (S(HR(i))); and a second high resistance voltage pulse application step (S13) for applying a second high resistance voltage pulse to the nonvolatile variable resistance element (20) when it is determined that the resistance value (HR) obtained in the high resistance state measurement step (S21) is not within the range of the reference resistance value (S(HR(i))).
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
A component built-in substrate (1) comprises: a first wiring layer (11) and a second wiring layer (21) that are parallel to each other; and a first semiconductor device (40) comprising a first vertical MOS transistor (60) and a second semiconductor device (40A) comprising a second vertical MOS transistor (60A), the first semiconductor device and the second semiconductor device being sealed between the first wiring layer (11) and the second wiring layer (21). In a cross-sectional view of the component built-in substrate (1), the first wiring layer (11), the first semiconductor device (40), the second semiconductor device (40A), and the second wiring layer (21) are laminated in the stated order. The component built-in substrate (1) further comprises a first resin (31) that seals the first semiconductor device (40), and a second resin (32) that seals the second semiconductor device (40A). The first resin (31) and the second resin (32) are discontinuous at the interface between the first resin (31) and the second resin (32).
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A semiconductor device (1) comprises: a first main surface (110); a second main surface (120); a vertical MOS transistor (10); a plurality of pads (111, 119) formed on the first main surface (110); and a metal layer (30) that is formed on the entire surface of the second main surface (120) and that functions as a drain terminal of the vertical MOS transistor (10), wherein: the plurality of pads (111, 119) only include one gate pad (119) functioning as the gate terminal of the vertical MOS transistor (10) and one or more source pads (111) functioning as source terminals of the vertical MOS transistor (10); and in plan view, the plurality of pads (111, 119) are in a point-symmetric relationship with the center of symmetry being a center point (91), which is the center of the semiconductor device (1), or in a line-symmetric relationship about a center line (90), which is a straight line that passes through the center point (91) and bisects the area of the semiconductor device (1).
An image encoding device (200) is provided with: a feature acquirer (240) that acquires a feature for each component; a ratio calculator (242) that calculates a feature ratio of a plurality of components according to the features thereof; a variance value acquirer (244) that acquires a variance value for one component; a flatness checker (246) that checks flatness according to the variance value; a target code amount controller (250) that determines a target code amount of data of each component according to the feature ratio and that corrects the target code amount determined according to the feature ratio according to the result of checking flatness; a frequency converter (210) that performs frequency conversion on the data of each component; a quantization processor (220) that quantizes the data of each component according to the target code amount; and an encoder (230) that encodes the data of each component.
A chip-size-package type semiconductor device includes a semiconductor layer, pads, and metal redistributions that are located above a top surface of the semiconductor layer and each of which is connected to one or more pads. The metal redistributions include first metal redistributions each of which includes a first portion and a second portion contained within the first portion in a plan view, the second portion being located above the first portion and having an area smaller than an area of the first portion in the plan view. Each of the first metal redistributions includes one or more line-shaped bends in a boundary portion between the first portion and the second portion on a surface of the first metal redistribution, the one or more line-shaped bends each having an interior angle of at least 180 degrees in a cross section of the first metal redistribution.
A delta sigma type ADC (1) is provided with a quantizer (30) operating at a prescribed sampling frequency (fs), an FIR filter (40) connected to the quantizer (30), and a DAC (50). A feedback path for the quantizer (30) is structured by the FIR filter (40) and the DAC (50). A reference signal for the DAC (50) is supplied from a reference signal source (60) chopping at a frequency lower than the prescribed sampling frequency (fs).
A scene determination device (1) comprises: a feature amount extraction unit (11) that extracts typical image feature amounts from a typical image group in which a scene to be determined appears; a correlation coefficient calculation unit (12) that calculates, from the typical image feature amounts, a correlation coefficient which indicates a correlation between the typical image feature amounts; a feature amount extraction unit (21) that extracts an input image feature amount from an input image; a distance calculation unit (22) that calculates, on the basis of the input image feature amount and the correlation coefficient, determination distance data indicating a difference between the feature of the input image and the feature of the typical image group; and a scene determination unit (23) that determines, on the basis of the determination distance data, a scene which appears in the input image.
This semiconductor device comprises: a substrate (101); a first nitride semiconductor layer (103) provided on the substrate (101); a second nitride semiconductor layer (104) provided on the first nitride semiconductor layer (103); a two-dimensional electron gas layer (105) provided in the vicinity of a boundary between the first nitride semiconductor layer (103) and the second nitride semiconductor layer (104); a source electrode (301) and a drain electrode (302) each electrically connected to the first nitride semiconductor layer (103); and a gate electrode (401) provided to be spaced apart from the source electrode (301) and the drain electrode (302). The device has an active region (701) on the substrate (101), and further comprises a first temperature detection resistor (601) for detecting a first temperature of the gate electrode (401) in the active region (701), and a second temperature detection resistor (602) for detecting a second temperature between the gate electrode (401) and the drain electrode (302) in the active region (701).
H10D 30/80 - FETs having rectifying junction gate electrodes
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 30/83 - FETs having PN junction gate electrodes
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
A semiconductor device (1) having a vertical MOS transistor (10) comprises: a source electrode (11); a source pad (111), which is a portion of the source electrode (11) exposed on the upper surface of the semiconductor device (1); a gate electrode (21); a low-concentration impurity layer (43) of a first conductivity type; a body region (18) of a second conductivity type formed in the low-concentration impurity layer (43), the second conductivity type being different from the first conductivity type; a trench (17) formed to a depth extending from the upper surface of the low-concentration impurity layer (43) through the body region (18) into a portion of the low-concentration impurity layer (43); a first conductor (15) embedded on the lower side inside the trench (17); and a second conductor (25) embedded on the upper side inside the trench (17). The first conductor (15) is connected to the source electrode (11). The second conductor (25) is connected to the gate electrode (21). The first conductor (15) has a portion connected to the source electrode (11) immediately below the source pad (111).
A variable power distributor (10) comprises a fixed power distributor (4) which is connected to an input terminal (1) and which outputs a high-frequency signal with power distributed at a ratio of N:1 (N is a real number of 1 or more) from a Port 1 and a Port 2, the Port 1 being connected to a first distribution output terminal (2), and a power amplifier (5) which is connected between the Port 2 and a second distribution output terminal (3), wherein: the maximum gain of the power amplifier (5) with respect to the high-frequency signal is greater than 10 x log (N) [dB]; when the input power to the input terminal (1) is equal to or less than a first switching power, the output power from the first distribution output terminal (2) is greater than or equal to the output power from the second distribution output terminal (3); and when the input power to the input terminal (1) is greater than the first switching power, the output power from the second distribution output terminal (3) is greater than the output power from the first distribution output terminal (2).
A sensor package includes: a chip including a surface on which the exposed portion of a sensor unit is provided; a substrate including a surface on which the chip is mounted; and a molded resin portion covering the surface of the substrate and the surface of the chip excluding the exposed portion. The molded resin portion includes an aperture positioned above the exposed portion. The chip includes a flat part positioned outside of the exposed portion on the surface of the chip. The edge of the aperture on the surface side of the chip is formed along the flat part.
G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon absorption of a fluidInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
A semiconductor light-emitting element includes a stacked structure including a semiconductor, the stacked structure having a first end face and a second end face facing each other and forming a resonator; and a protective film disposed on the first end face. The protective film includes a first protective film. The first protective film is an aluminum oxide film or an aluminum oxynitride film to which scandium is added.
A semiconductor laser element (1) comprises a semiconductor layered body (1S). The semiconductor layered body (1S) includes an n-type cladding layer (30) containing In, an active layer (42) containing In, a p-type cladding layer (50) containing In, and a contact layer (70). The semiconductor layered body (1S) has a first end surface (1F) and a second end surface (1R) constituting a resonator, a gain region into which a current is injected, and a window region (Rw) formed between the first end surface (1F) and the gain region. The p-type cladding layer (50) is doped with Mg, and Zn is diffused in the window region (Rw). When the Mg concentration in a portion of the p-type cladding layer (50) located in the gain region is represented by Na, the Mg concentration in a portion of the p-type cladding layer (50) located in the window region (Rw) is represented by Nw, and the Zn concentration in a portion of the p-type cladding layer (50) located in the window region (Rw) is represented by Nz, the relationships Na>10Nw and Nz>Nw are satisfied.
H01S 5/16 - Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface
H01S 5/323 - Structure or shape of the active regionMaterials used for the active region comprising PN junctions, e.g. hetero- or double- hetero-structures in AIIIBV compounds, e.g. AlGaAs-laser
A motor control device according to the present invention has a control drive circuit (30) that supplies a drive signal to an inverter (20) that drives a motor (10), a timepoint setting circuit (31) that sets a first timepoint and a second timepoint within a period before the motor (10) is started during which the control drive circuit (30) selects and energizes two of three phases of the motor (10), and a not-energized phase voltage detection circuit (32) that compares the voltage of the not-energized phase of the motor (10) at the first timepoint and the voltage of the not-energized phase of the motor (10) at the second timepoint.
A noise detection device includes: a DFT executor that performs a DFT on an input signal and outputs a transform result; a carrier wave detector that detects a carrier wave frequency bin in the transform result; a frequency corrector that performs a correction to reduce a difference between a center frequency of the carrier wave frequency bin and a frequency of the carrier wave; a phase calculator that calculates a phase of each signal component in a corrected transform result; a phase inversion unit that inverts an order of the phase of each signal component with respect to a center frequency of the carrier wave frequency bin in the corrected transform result; and an asymmetric component detector that detects, as noise, a signal component whose phase is asymmetric with respect to the carrier wave frequency bin in the corrected transform result.
A semiconductor light-emitting element includes: a substrate; an n-type clad layer above the substrate; an active layer above the n-type clad layer; and a p-type clad layer above the active layer. The active layer includes: a well layer; an n-side first barrier layer on an n-type clad layer side of the well layer; and a p-side barrier layer on a p-type clad layer side of the well layer. The p-side barrier layer comprises In. The n-side first barrier layer has an In composition ratio lower than an In composition ratio of the p-side barrier layer. The n-side first barrier layer has a band gap energy smaller than a band gap energy of the p-side barrier layer.
H01S 5/343 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser
85.
DISTANCE MEASUREMENT DEVICE AND DISTANCE MEASUREMENT METHOD
Provided is a distance measurement device (1) for measuring the distance to a target object using indirect TOF, wherein: during a light emission and exposure period, an exposure signal generation unit (112) outputs, to a pixel drive unit (12), a first exposure signal that drives a plurality of gates (33) to transfer a charge generated by a photoelectric conversion unit (31) to any of a plurality of charge storage units (32) during the period of a first exposure packet width; and during a background light adjustment period, the exposure signal generation unit (112) outputs, to the pixel drive unit (12), a second exposure signal that drives the plurality of gates (33) to transfer a charge generated by the photoelectric conversion unit (31) to any of the plurality of charge storage units (32) during the period of a second exposure packet width, which is different from the first exposure packet width.
A distance image imaging device (100) comprises: a light source (10) that emits irradiation light; a plurality of pixels (22) that receive reflected light that is the irradiation light reflected from an object; a drive control unit (23); and a signal processing unit (26) that calculates the distance to the object. Each pixel (22) includes a photoelectric conversion unit that converts the reflected light into a signal charge, a plurality of charge storage units that store signal charges, and a plurality of charge transfer gates that distribute and transfer the signal charges to the plurality of charge storage units. The drive control unit (23) controls the driving of the plurality of pixels (22) by dividing the plurality of pixels (22) into one or more groups in which the plurality of charge transfer gates are driven at the same timing. The drive control unit (23) has a first control mode in which the number of the one or more groups is a first number, and a second control mode in which the number of the one or more groups is a second number greater than the first number.
A distance image capturing device (100) that measures the distance to an object by an indirect time of flight (TOF) method comprises: a light source (10) that emits emitted light; pixels (22) that are exposed to incident light including reflected light resulting from the emitted light being reflected by the object; a drive control unit (23) that controls the driving of the light source (10) and the pixels (22) in any one of a plurality of modes that have mutually different emission and exposure timings; and an information processing unit (30) that assesses predetermined mode determination criteria to determine one mode from among the plurality of modes, and controls the drive control unit (23) to drive the light source (10) and the pixel (22) in the determined one mode.
A distance measuring device that outputs one or more distance information items each indicating a distance to a subject, the distance measuring device includes: a light source that emits illumination light including one or more bright portions; a light receiver that includes a pixel array in which pixels are arranged in a matrix; a distance information calculator that calculates, for each of the pixels, pixel distance information indicating a distance from the pixel to the subject when the light receiver receives reflected light that is the illumination light reflected off the subject; a distance information selector that selects one or more selective distance information items from among the pixel distance information items corresponding to the pixels; and an outputter that outputs the one or more distance information items, based on the one or more selective distance information items.
G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
G01S 7/481 - Constructional features, e.g. arrangements of optical elements
G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
G01S 7/4914 - Detector arrays, e.g. charge-transfer gates
G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
G01S 17/32 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
89.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: an electron transport layer; an electron supply layer provided above the electron transport layer and having a band gap greater than a band gap of the electron transport layer; a gate electrode provided above the electron supply layer; a contact layer embedded in recessed portions that penetrate through the electron supply layer, at positions between which the gate electrode is provided; a first insulating layer provided above a portion of the electron supply layer in which the gate electrode is not provided; and a second insulating layer provided above the first insulating layer, in contact with the contact layer, and not in contact with the gate electrode. A coefficient of linear thermal expansion of the second insulating layer is greater than a coefficient of linear thermal expansion of the electron supply layer.
H10D 64/00 - Electrodes of devices having potential barriers
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
A semiconductor device includes: a substrate; a channel layer; a nitride semiconductor layer that includes a barrier layer; a source electrode; a drain electrode; a gate electrode; a drain-side insulating layer; and a source-side insulating layer. The gate electrode includes a junction portion, a drain-side protruding portion, and a source-side protruding portion. The protrusion length of the source-side protruding portion is longer than the protrusion length of the drain-side protruding portion. The bottom surface of the source-side protruding portion includes a step. The height of an end portion of the bottom surface of the source-side protruding portion is greater than the height of an end portion of the bottom surface of the drain-side protruding portion.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 64/00 - Electrodes of devices having potential barriers
91.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes: a substrate; a channel layer; a nitride semiconductor layer that includes a barrier layer; a source electrode; a drain electrode; a gate electrode; and an insulating layer. The gate electrode includes a junction portion and a drain-side protruding portion. The insulating layer includes an in-situ Si3N4 film and an ex-situ Si3N4 film. At least one of the following is satisfied: (a) the halogen concentration of the in-situ Si3N4 film is lower than the halogen concentration of the ex-situ Si3N4 film; or (b) the interface oxygen concentration between the in-situ Si3N4 film and the nitride semiconductor layer is lower than the interface oxygen concentration between the ex-situ Si3N4 film and the in-situ Si3N4 film.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A semiconductor device includes: an electron transport layer; an electron supply layer provided above the electron transport layer; a gate electrode provided above the electron supply layer; a contact layer embedded in penetrating recessed portions that penetrate through the electron supply layer, at positions between which the gate electrode is provided; an electron-supply assisting layer that is an example of an n-type semiconductor layer provided in contact with the electron supply layer and the contact layer and not in contact with the gate electrode, the n-type semiconductor layer being made of an n-type semiconductor containing Si; an alloy layer provided above the electron-supply assisting layer and containing Si; a first insulating layer provided in contact with the gate electrode and not in contact with the contact layer; and at least one of a source electrode or a drain electrode provided above the alloy layer and the contact layer.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 64/60 - Electrodes characterised by their materials
A radio frequency amplifier includes: a transistor; an input line; an output line; and a shunt circuit that is connected between ground and the input line or the output line, wherein the shunt circuit includes: a first series resonant circuit that includes an inductor and a capacitor that are connected in series and has first resonant frequency f1; a second series resonant circuit that includes an inductor and a capacitor that are connected in series and has second resonant frequency f2 that is different from the first resonant frequency; and a resistor that is connected between a first connection point and a second connection point, the first connection point being a connection location between the inductor and the capacitor in the first series resonant circuit, the second connection point being a connection location between the inductor and the capacitor in the second series resonant circuit.
A semiconductor device includes: a semiconductor layer that includes a semiconductor substrate on a back face side and is divided into a first region, a second region, and a third region that do not overlap each other and are not dispersedly disposed in a plan view of the semiconductor device; a first vertical metal-oxide-semiconductor (MOS) transistor provided in the first region of the semiconductor layer; a second vertical MOS transistor provided in the second region of the semiconductor layer; and a drain pad connected to the semiconductor substrate, at a position within the third region in the plan view of the semiconductor device. In the plan view of the semiconductor device, the third region is interposed between the first region and the second region. In the plan view of the semiconductor device, an area of the first region is larger than an area of the second region.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H01L 23/00 - Details of semiconductor or other solid state devices
H10D 62/60 - Impurity distributions or concentrations
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
95.
NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
This nitride semiconductor device (1) comprises: a substrate (30); a semiconductor laminate (40) that includes a 2DEG (43); a source structure (50S), a drain structure (50D), and a gate structure (50G) for an FET (11); and an anode structure (50A) and a cathode structure (50K) for a diode (12). The gate structure (50G) includes a first p-type semiconductor layer (51G) and a first metal layer (55G). The anode structure (50A) includes a second p-type semiconductor layer (51A) and a second metal layer (55A). The second p-type semiconductor layer (51A) has the same layer configuration as the first p-type semiconductor layer (51G). The source structure (50S) is electrically connected to the anode structure (50A). The drain structure (50D) is electrically connected to the cathode structure (50K). The second metal layer (55A) is formed using a material which is different from that of the first metal layer (55G).
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
96.
VIDEO MONITORING DEVICE AND VIDEO MONITORING METHOD
A video monitoring device that monitors video data received from a video display device that receives a video signal from a camera and displays a video, the video monitoring device including: a video extractor that extracts, from the video data, color information of each pixel in an image indicated by the video data; a specific color difference operator that computes, for each pixel, difference information between a color indicated by the color information and a predetermined specific color; a histogram calculator that calculates a histogram by classifying the difference information computed for each pixel, the histogram having, for each difference interval, a frequency indicating the number of pixels belonging to the difference interval; and an anomaly detector that generates and outputs a signal indicating that the video data is anomalous, when a frequency of belonging to a predetermined difference interval in the histogram is at least a first threshold.
H04N 17/02 - Diagnosis, testing or measuring for television systems or their details for colour television signals
G06V 10/50 - Extraction of image or video features by performing operations within image blocksExtraction of image or video features by using histograms, e.g. histogram of oriented gradients [HoG]Extraction of image or video features by summing image-intensity valuesProjection analysis
G06V 10/56 - Extraction of image or video features relating to colour
G06V 10/60 - Extraction of image or video features relating to illumination properties, e.g. using a reflectance or lighting model
G06V 20/40 - ScenesScene-specific elements in video content
A radio frequency power amplifier includes a power amplification transistor and a gate bias circuit. The gate bias circuit includes a VHb terminal connected to a high voltage power supply for bias, a VLb terminal connected to a low voltage power supply for bias, an enable terminal that receives an enable signal, an enable transistor and a voltage dividing resistor that are connected in series and connected between the VHb terminal and the VLb terminal, a driver that outputs a voltage to a control terminal of the enable transistor, and a gate bias output terminal that outputs, as a gate bias voltage, a divided voltage generated by the voltage dividing resistor. When an OFF signal is received as the enable signal, the driver causes the enable transistor to operate in a first operating area that is not a cutoff region.
Provided is a semiconductor laser element (100) comprising a substrate (101), a semiconductor laminate (100S) disposed above the substrate (101), and a p-side electrode (113) disposed above the semiconductor laminate (100S) and in contact with the semiconductor laminate (100S), wherein the semiconductor laminate (100S) includes: an n-type cladding layer (102) that is a nitride semiconductor layer containing Al; an n-side guide layer (104) disposed above the n-type cladding layer (102); an active layer (105) disposed above the n-side guide layer (104); and a p-type cladding layer (110) that is disposed above the active layer (105) and is a nitride semiconductor layer containing Al, the composition ratio of Al in the n-type cladding layer (102) is greater than the composition ratio of Al in the p-type cladding layer (110), and the p-side electrode (113) is made of at least one of Ag, an Ag alloy, Al, or a translucent conductive film.
H01S 5/343 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser
This semiconductor laser element (100) is provided with: a substrate (101) which is formed of AlGaN; and a semiconductor multilayer body (100S) which is disposed above the substrate (101). The semiconductor multilayer body (100S) comprises: an n-type cladding layer (103) that is disposed above the substrate (101) and is formed of AlGaN; an n-side guide layer (104) that is disposed above the n-type cladding layer (103) and contains Al; an active layer (105) that is disposed above the n-side guide layer (104); and a p-type cladding layer (110) that is disposed above the active layer (105). The active layer (105) comprises a well layer (105b) and barrier layers (105a, 105c). The bandgap energy of the substrate (101) is greater than the bandgap energy of the n-side guide layer (104) and lower than the bandgap energy of the n-type cladding layer (103).
H01S 5/343 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser
H01S 5/22 - Structure or shape of the semiconductor body to guide the optical wave having a ridge or a stripe structure
This semiconductor device (1) comprises: a semiconductor layer (40) which has a semiconductor substrate (32) that has a first conductivity type and contains an impurity of a first concentration, and a low-concentration impurity layer (33) that is formed to be in contact with the upper surface of the semiconductor substrate (32), has the first conductivity type, and contains an impurity of a second concentration that is lower than the first concentration; a first vertical MOS transistor (10) and a second vertical MOS transistor (20) which use the semiconductor substrate (32) as a common drain region; and a first Schottky barrier diode (81) which uses the low-concentration impurity layer (33) as a cathode in a case where the first conductivity type is N-type, and uses the low-concentration impurity layer (33) as an anode in a case where the first conductivity type is P-type, the first Schottky barrier diode (81) being connected in parallel in the same forward direction with a body diode of the first vertical MOS transistor (10).
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
