A semiconductor device includes a vertical metal-oxide semiconductor (MOS) transistor that includes: first trenches provided from an upper surface of a low-concentration impurity layer and penetrating through a body region, and extending in a first direction; and second trenches provided from the upper surface of the low-concentration impurity layer and penetrating through the body region to a depth deeper than the depth of the first trenches, and extending in the first direction. The first trenches and the second trenches are alternately disposed in a second direction, first conductors connected to a gate electrode are provided inside the first trenches and in upper portions inside the second trenches, second conductors connected to the source electrode are provided in lower portions inside the second trenches, and a pitch between the second conductors is twice a pitch between the first conductors in the second direction.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/60 - Distribution ou concentrations d’impuretés
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
A multiply-accumulate operation device (30) comprises: a first current mirror circuit (41p); a second current mirror circuit (41n); an array (80) that is a collection (switch element groups (50-52)) of switch element groups which are provided in correspondence with each set among n sets of word lines (WL), and in which, in accordance with the signal state of a first word line (WL< i >) and a second word line (WLB< i >) of that set, a current flowing through a first bit line (31) is applied to a source line (33), and a current flowing through a second bit line (32) is applied to the source line (33); a constant current source (40) that maintains a constant sum of a first current (Ip) flowing through the first bit line (31) and a second current (In) flowing through the second bit line (32); and a calculation unit (44) that generates a result of a multiply-accumulate operation on the basis of the difference between the first current (Ip) and the second current (In).
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A solid-state imaging device includes: a pixel array in which a plurality of pixels are arranged in rows and columns; and a first power supply line. Each of the plurality of pixels includes a photoelectric converter, a floating diffusion, a capacitance accumulator, a first transfer transistor, an overflow transistor, a second transfer transistor, a first reset transistor, and an amplifier transistor. The solid-state imaging device further includes a resetter for resetting the floating diffusion and the capacitance accumulator at voltages different from each other.
H04N 25/59 - Commande de la gamme dynamique en commandant la quantité de charge stockable dans le pixel, p. ex. en modifiant le rapport de conversion de charge de la capacité du nœud flottant
H04N 25/63 - Traitement du bruit, p. ex. détection, correction, réduction ou élimination du bruit appliqué au courant d'obscurité
H04N 25/771 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des moyens de stockage autres que la diffusion flottante
H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N
A cell monitoring unit (100) is a cell monitoring unit for monitoring a battery cell (11), the cell monitoring unit comprising: a battery monitoring unit (110) for measuring the state of the battery cell (11); a power supply circuit (111); a second power supply circuit (120) for supplying lower power than the power supply circuit (111); and a radio communication unit (140) including a communication unit (146) for performing radio communication with an upper level system, a time setting circuit (147) for setting the start time and the stop time of the cell monitoring unit (100), and a time measurement unit (148) for measuring an elapsed time from the stop time. The power supply circuit (111) starts at the start time, supplies power to the battery monitoring unit (110) and the communication unit (146), and stops at the stop time, and the second power supply circuit (120) supplies power to the time measurement unit (148) during a period from the stop time to the subsequent start time.
G01R 31/396 - Acquisition ou traitement de données pour le test ou la surveillance d’éléments particuliers ou de groupes particuliers d’éléments dans une batterie
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
5.
VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE AND METHOD FOR DRIVING VARIABLE RESISTANCE NONVOLATILE STORAGE ELEMENT
A variable resistance nonvolatile storage device includes a memory cell and a heater thermally coupled to the memory cell, and the memory cell and the heater are independently operable. The memory cell includes a first electrode layer, a second electrode layer, and a variable resistance layer sandwiched between the first electrode layer and the second electrode layer, and the heater includes a heating element, and a third terminal and a fourth terminal each connected to the heating element.
A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:
A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:
Mc≥β−γ/β+γ×Mr
A semiconductor device includes: a filter circuit including: a resistor; a MOS capacitor; and a MOM capacitor stacked on at least one of the resistor or the MOS capacitor, wherein the following inequalities are satisfied:
Mc≥β−γ/β+γ×Mr
Mr≤√{square root over (1/2πftαβ)} [Math. 1]
where ft denotes a cutoff frequency of the filter circuit, Mr denotes a resistor area of a resistor-provided region in which the resistor is provided, Mc denotes a MOS capacitor area of a MOS capacitor-provided region in which the MOS capacitor is provided, α denotes a resistivity of the resistor, β denotes a MOS capacitance rate of the MOS capacitor, and γ denotes a MOM capacitance rate of the MOM capacitor.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H03H 11/12 - Réseaux sélectifs en fréquence à deux accès utilisant des amplificateurs avec contre-réaction
A semiconductor light-emitting device includes: a first semiconductor layer containing a first conductivity type nitride semiconductor; an active layer containing a nitride semiconductor including Ga or In; an electron barrier layer containing a nitride semiconductor including at least Al, and being of a second conductivity type; and a second semiconductor layer containing a second conductivity type nitride semiconductor. The electron barrier layer includes a region where an Al composition ratio increases monotonically toward the second semiconductor layer. A maximum impurity concentration position of the second conductivity type in the electron barrier layer is located between an interface on an active layer side of the electron barrier layer and an intermediate position between a maximum Al composition ratio position of the electron barrier layer in the region and an interface on an active layer side of the electron barrier layer.
H10H 20/825 - Matériaux des régions électroluminescentes comprenant uniquement des matériaux du groupe III-V, p. ex. GaP contenant de l’azote, p. ex. GaN
H10H 20/816 - Corps ayant des structures contrôlant le transport des charges, p. ex. couches semi-conductrices fortement dopées ou structures bloquant le courant
H10H 20/855 - Moyens de mise en forme du champ optique, p. ex. lentilles
8.
LASER DEVICE AND METHOD FOR CONTROLLING LASER DEVICE
This laser device (1) comprises: a semiconductor laser element (20) that emits first laser light (L1); a first temperature adjustment unit (51) that heats or cools the semiconductor laser element (20); and a control unit (80) that controls the amount of current supplied to the semiconductor laser element (20) and controls the first temperature adjustment unit (51) on the basis of a target temperature that is a control target for the temperature at an installation point of the semiconductor laser element (20). The target temperature for the semiconductor laser element (20) in an initial state is the temperature that requires heating of the semiconductor laser element (20) by means of the first temperature adjustment unit (51).
H01S 5/024 - Dispositions pour la gestion thermique
H01S 3/0941 - Procédés ou appareils pour l'excitation, p. ex. pompage utilisant le pompage optique par de la lumière cohérente produite par un laser à semi-conducteur, p. ex. par une diode laser
9.
SUBMOUNT, SEMICONDUCTOR LASER DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LASER DEVICE
A submount (2) comprises: a submount body (21); an Au layer (24) positioned above the submount body (21); an upper protective metal layer (25), which is an example of a metal layer positioned above the Au layer (24); and a solder layer (26) positioned above the upper protective metal layer (25). The Au layer (24) has an exposed region (24a) exposed from the upper protective metal layer (25), and the solder layer (26) is provided over the exposed region (24a) and the upper protective metal layer (25). The upper protective metal layer (25) has a plurality of protrusions (25a) protruding toward an end face of the submount body (21), each protrusion (25a) having a first portion (25a1) exposed from the solder layer (26) and a second portion (25a2) covered by the solder layer (26). The exposed region (24a) includes an inter-protrusion region (24a1) between two adjacent protrusions (25a). At least a part of the inter-protrusion region (24a1) is covered by the solder layer (26).
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
H01S 5/0237 - Fixation des puces laser sur des supports par soudage
A control system (100) comprises an influence determination circuit (13) and a control circuit (a CPU (11) and a system control circuit (14)). The influence determination circuit (13) determines whether or not the influence of power restoration of a target circuit (2) that is connected to a power supply (VDD) is permitted at least in an operation of a prescribed circuit (1) that is connected to the power supply (VDD). When the influence determination circuit (13) determines that the influence is not permitted, the control circuit changes operation states of: the prescribed circuit (1); and the target circuit (2) and/or a circuit other than the prescribed circuit (1) connected to the power supply (VDD).
G06F 1/28 - Surveillance, p. ex. détection des pannes d'alimentation par franchissement de seuils
G06F 1/30 - Moyens pour agir en cas de panne ou d'interruption d'alimentation
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
11.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
This semiconductor device (1) comprises: a channel layer (14); a barrier layer (16) that is provided above the channel layer (14) and has a larger band gap than the channel layer (14); a p-type semiconductor layer (18) provided above the barrier layer (16); a source electrode (32) and a drain electrode (34) between which the p-type semiconductor layer (18) is interposed; an i-type Al-containing layer (20) that is provided above the p-type semiconductor layer (18), has a larger band gap than the p-type semiconductor layer (18), and contains Al; an i-type Al-free layer (22) that is provided above the Al-containing layer (20) and does not contain Al; and a gate electrode (30) that is provided above the Al-free layer (22).
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
12.
SEMICONDUCTOR LASER DEVICE, LIGHT SOURCE MODULE, AND METHOD FOR MANUFACTURING LIGHT SOURCE MODULE
A semiconductor laser device (1) comprises: a semiconductor laser element (200) that emits laser light; and a lens unit (100) that has a cylindrical lens (110) and an installation surface, wherein the semiconductor laser element (200) has an active layer, the cylindrical lens (110) accepts incident laser light and changes the spread angle of the laser light in the fast-axis direction, the installation surface is fixed to an installation-bearing surface, the generatrix (115) of the cylindrical lens (110) is inclined with respect to a first reference plane of the installation-bearing surface, and the angle α between the generatrix (115) and the first reference plane satisfies 0° < |α| < 45°.
H01S 5/02326 - Dispositions pour le positionnement relatif des diodes laser et des composants optiques, p. ex. rainures dans le support pour fixer des fibres optiques ou des lentilles
H01S 5/02253 - Découplage de lumière utilisant des lentilles
A high frequency power amplifier (100) comprises a plurality of unit amplifiers (4) mounted on a semiconductor substrate (1). The plurality of unit amplifiers (4) each have: a high frequency transistor (12) which has a plurality of gate fingers (9), at least one drain finger (8), and a plurality of source fingers (7); a gate bus line (13) which is connected to one end of each of the plurality of gate fingers (9); a drain bus line (14) which is connected to one end of the at least one drain finger (8); a gate bias circuit (20) which is connected to the gate bus line (13); and a bias terminal (21) which supplies a voltage to the gate bias circuit (20). The voltages supplied to the respective bias terminals (21) of the plurality of unit amplifiers (4) are the same or different.
H03F 3/213 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
14.
DISTANCE IMAGE CAPTURING DEVICE, DISTANCE IMAGE CAPTURING METHOD, AND PROGRAM
A distance image capturing device (100) comprises: a light source (110); pixels (121); a drive control unit (130); a search unit (141); and a distance measurement unit (142). The light source (110) radiates irradiation light. The pixels (121) expose reflected light which is the irradiation light that has been reflected by an object (200). The drive control unit (130) causes the light source (110) to radiate irradiation light of one or a plurality of different amounts of light, and causes the pixels (121) to perform exposure. The search unit (141) determines one or a plurality of light amounts used for ranging from among the plurality of light amounts, on the basis of a plurality of distance images captured by controlling the drive control unit (130) so as to cause the light source (110) to radiate the irradiation light of the plurality of light amounts. The ranging unit (142) controls the drive control unit (130) so as to cause the light source (110) to radiate the irradiation light of one or a plurality of light amounts determined by the search unit (141), and performs ranging.
This motor drive device comprises: a position detection unit (10) that outputs a position detection signal by detecting a counter electromotive force generated in a motor winding during a non-energization period in which the motor winding is not energized; a current waveform control unit (20) that controls a current waveform including a non-energization period; an energization control unit (30) that controls energization to the motor winding on the basis of the current waveform; and a drive unit (40) that supplies a current to the motor winding according to the control of the energization control unit (30). The energization control unit (30) switches the energization phase of the motor (100) provided with the motor winding on the basis of the position detection signal. The current waveform control unit (20) adjusts the start timing of the non-energization period on the basis of the non-energization period.
H02P 6/182 - Dispositions de circuits pour détecter la position sans éléments séparés pour détecter la position utilisant la force contre-électromotrice dans les enroulements
16.
INTEGRATED CIRCUIT FOR DC-DC CONVERTER, DC-DC CONVERTER, AND CONTROL METHOD THEREFOR
This integrated circuit (20) for a DC-DC converter comprises: a high-side switching element (14); a low-side switching element (15); a control circuit (10) that controls the high-side switching element (14) and the low-side switching element (15) such that the output voltage of an inductor (L1) is constant; a p-type semiconductor substrate (21) that includes an n-well region (22) and a p-well region (23); and an electric potential control circuit (30). The low-side switching element (15) is a transistor that includes an n-type impurity region provided in the p-well region (23) as a source or a drain. If both the high-side switching element (14) and the low-side switching element (15) are non-conductive, the electric potential control circuit (30) supplies a first electric potential to the n-well region (22), and if one of the high-side switching element (14) and the low-side switching element (15) is conducting, the electric potential control circuit (30) supplies a second electric potential higher than the first electric potential to the n-well region (22).
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 89/00 - Aspects des dispositifs intégrés non couverts par les groupes
A high-frequency power amplifier (10) comprises an input terminal (1), a carrier amplifier (4), a peak amplifier (5), a composite point (8), and an output terminal (2). When A is the magnitude of a reflection coefficient with the peak amplifier (5) side being viewed from the composite point (8) while operation of the peak amplifier (5) is OFF, and θ is the phase of the reflection coefficient, the phase θ of the reflection coefficient at a first distortion frequency is θ <= arccos[-4×A/(3+A×A)] within the range of 0° or greater and less than 180°, or the phase θ of the reflection coefficient at a second distortion frequency is θ >= arccos[-4×A/(3+A×A)] within the range of -180° or greater and less than 0°.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
A main amplifier (1) and an auxiliary amplifier (2) of a Doherty amplifier are respectively constituted by epitaxial laminates (401 to 407) different from each other, transistors of the same size are respectively formed on the different epitaxial laminates, and, when the transistors are subjected to a class-C operation, the epitaxial laminate constituting the transistor having a higher gain is used for the auxiliary amplifier (2).
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
A semiconductor device (1) has a rectangular shape in which the side length in a first direction is equal to or greater than the side length in a second direction in plan view, the semiconductor device comprising: at positions that are included in a first region (A1), 2n+1 elliptical first source pads (111) of a first vertical MOS transistor (10), said source pads being arranged in a stripe pattern and extending in the second direction; and, at positions that are included in a second region (A2), 2n+1 elliptical second source pads (121) of a second vertical MOS transistor (20), said source pads being arranged in a stripe pattern and extending in the second direction, wherein a first source pad (111a) that is closest to a boundary line (90) between the first region (A1) and the second region (A2) among the 2n+1 first source pads (111) is longer than the other first source pads (111), and a second source pad (121a) that is closest to the boundary line (90) among the 2n+1 second source pads (121) is longer than the other second source pads (121).
This selection device (100) is connected to: a plurality of processors (for example, targets (210), (220), and (230)); and a debugger (for example, a host (400)) that executes debugging of the plurality of processors, the debugger being connected to the plurality of processors via a multi-drop connection. The selection device is provided with: a first holding circuit (for example, a first register (110)) that holds first identification information indicating any one of the plurality of processors; and a selection circuit (120) that outputs, to the debugger, among one or more pieces of data output from one or more processors among the plurality of processors, only the data output from one processor indicated by the first identification information.
A submount (7) comprises: an electrically insulating layer (70) having a first main surface (77), a second main surface (78) positioned on a back side of the first main surface (77), and a first recessed region (71) that is a region recessed with respect to the first main surface (77) or a region recessed with respect to the second main surface (78); and a first metal layer (metal layer (82)) that covers at least a portion of the first recessed region (71). The thickness of the first metal layer at a position facing the first recessed region (71) is greater than the depth of the first recessed region (71).
A semiconductor device has a shape of a rectangular in which the side length in a first direction is greater than or equal to the side length in a second direction in a plan view, and includes 2n+1 obround first source pads of a first vertical MOS transistor that are arranged in stripes at positions within a first area and extend in the second direction and 2n+1 obround second source pads of a second vertical MOS transistor that are arranged in stripes at positions within a second area and extend in the second direction.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
A semiconductor device includes: a semiconductor layer; a vertical metal-oxide semiconductor (MOS) transistor; a protective film; a first wiring electrode connected to a source electrode of the vertical MOS transistor; and a second wiring electrode connected to a gate electrode of the vertical MOS transistor. A first perimeter structure is provided in a perimeter portion of the first wiring electrode in the plan view of the semiconductor layer, the first perimeter structure protruding upward of the semiconductor device and including the source electrode, the protective film, and the first wiring electrode that are stacked in stated order. A second perimeter structure is provided in a perimeter portion of the second wiring electrode in the plan view of the semiconductor layer, the second perimeter structure protruding upward of the semiconductor device and including the gate electrode, the protective film, and the second wiring electrode that are stacked in stated order.
This decoupling capacitance element (100) comprises an n-type well region (11n) and a p-type well region (11p), power supply wiring (31) and ground wiring (32) extending in the X-axis direction, first n-type impurity regions (21n) and a first p-type impurity region (21p) formed in the n-type well region (11n), and second n-type impurity regions (22n) and a second p-type impurity region (22p) formed in the p-type well region (11p). The n-type well region (11n) and the p-type well region (11p) are positioned adjacent to each other in a region between the power supply wiring (31) and the ground wiring (32) in plan view. The power supply wiring (31) is electrically connected to the first n-type impurity regions (21n) and the second n-type impurity regions (22n), and the ground wiring (32) is electrically connected to the first p-type impurity region (21p) and the second p-type impurity region (22p).
A latch circuit device (10) comprises: a latch circuit (51) having an inverter (52) and an inverter (53) connected to each other in a positive feedback loop; and a power supply control circuit (20) for performing control for supplying a power supply voltage (VDD) to the latch circuit (51). The power supply control circuit (20) performs control such that the timing at which a power supply voltage (IVDD-IO2) is supplied to the inverter (52) is earlier than the timing at which a power supply voltage (IVDD-IO1) is supplied to the inverter (53).
x1-x1-xN (0≤x<1) as the main component. The p-side cladding layer (110) has a p-side cladding doped region that contains In. The In concentration in the p-side cladding doped region is 3×1017-1×1019cm-3.
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
H10H 20/816 - Corps ayant des structures contrôlant le transport des charges, p. ex. couches semi-conductrices fortement dopées ou structures bloquant le courant
H10H 20/825 - Matériaux des régions électroluminescentes comprenant uniquement des matériaux du groupe III-V, p. ex. GaP contenant de l’azote, p. ex. GaN
An optical sensor device (10) comprises: a substrate (20); an optical sensor element (30) disposed on one surface (20a) positioned on one side (positive direction of Z-axis) of the substrate (20); an adhesive material layer (100) that is disposed between the one surface (20a) and the optical sensor element (30) and that fixes the optical sensor element (30) to the substrate (20); and a light-transmitting member (50) that covers one side of the optical sensor element (30). The optical sensor element (30) is disposed in a hollow space formed by the substrate (20) and the light-transmitting member (50). The adhesive material layer (100) includes a plurality of adhesive materials (101) arranged regularly and separately from each other.
H10F 30/21 - Dispositifs individuels à semi-conducteurs sensibles au rayonnement dans lesquels le rayonnement commande le flux de courant à travers les dispositifs, p. ex. photodétecteurs les dispositifs ayant des barrières de potentiel, p. ex. phototransistors les dispositifs étant sensibles au rayonnement infrarouge, visible ou ultraviolet
A semiconductor module (100) comprises: a submount substrate (11); a LID (1) having a top plate (2) and a side wall (3); a semiconductor element (31); a plurality of electrode pads (23); an adhesive (51) for fixing the LID (1) and the submount substrate (11); and a frame body (41). The frame body (41) is sandwiched between the side wall (3) of the LID (1) and the submount substrate (11), and the frame body (41) extends in a manner covering the plurality of electrode pads (23) in a plan view.
H01L 23/10 - ConteneursScellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p. ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
29.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
A semiconductor device (1) comprises: a channel layer (14); a barrier layer (16) that is provided above the channel layer (14) and that has a band gap greater than that of the channel layer (14); a p-type semiconductor layer (18) provided above the barrier layer (16); a source electrode (32) and a drain electrode (34) provided so as to sandwich the p-type semiconductor layer (18) therebetween; a gate electrode (30) provided above the p-type semiconductor layer (18); and an i-type semiconductor layer (20) provided in contact with a side surface (18c) of the p-type semiconductor layer (18). The gate electrode (30) overlaps the p-type semiconductor layer (18) and the i-type semiconductor layer (20) in plan view.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
A control device (100) according to one aspect of the present disclosure comprises a first detection unit (110) that detects input of a first signal to a first terminal, a second detection unit (120) that detects input of a second signal to a second terminal that is different from the first terminal, and a control unit (130) that cold-starts a first processor (for example, a CPU (200)) when input of the first signal to the first terminal has been detected and input of the second signal to the second terminal is detected.
A semiconductor storage device (10) comprises: a memory cell array (24) divided into a plurality of sectors (20-23) to be sequentially accessed; and a power supply control circuit (30) that performs control for supplying a power supply voltage VDD to each of the plurality of sectors (20-23). When access is made to a first sector (for example, the sector (20)) from among the plurality of sectors (20-23), the power supply control circuit (30) performs control such that, to a second sector (for example, the sector (21)) to be accessed subsequently to the first sector, a first power supply voltage VDD necessary for the second sector to read and write data is supplied.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G11C 11/417 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation pour des cellules de mémoire du type à effet de champ
32.
INFORMATION PROCESSING METHOD, INFORMATION PROCESSING DEVICE, AND PROGRAM
An information processing method according to an aspect of the present disclosure: acquires (S110) image information indicating an image generated by an imaging device; performs first conversion (S130) of an image using a conversion table for correcting image distortion, which is dependent on a lens included in the imaging device, and image conversion based on a change in the roll angle of the imaging device; and performs second conversion (S140) for further converting the image subjected to the first conversion, on the basis of prescribed information.
A semiconductor laser device (10) is provided with: a submount (80) having a mounting surface (80a); a spacer (40) disposed on the mounting surface (80a); a semiconductor laser element (20) disposed above the spacer (40); and a bonding member (60) disposed between the mounting surface (80a) and the semiconductor laser element (20) and configured from a porous metal material that bonds the mounting surface (80a) and the semiconductor laser element (20). The semiconductor laser element (20) is provided with a bonding surface (30) facing the submount (80), and a semiconductor laminate (20S); the semiconductor laminate (20S) has a ridge (25R); the bonding surface (30) has a first region (31) that is a region facing the ridge (25R), and a second region (32) that is disposed along the first region (31); the bonding member (60) is bonded to the first region (31); and the spacer (40) is disposed at a position facing the second region (32).
H01S 5/024 - Dispositions pour la gestion thermique
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
A semiconductor laser device (10) comprises: a sub-mount (80) having a mounting surface (80a); a spacer (40) disposed on the mounting surface (80a); a semiconductor laser element (20) disposed above the spacer (40); and a junction member (60) that is disposed between the spacer (40) and the semiconductor laser element (20) and joins the spacer (40) and the semiconductor laser element (20). The semiconductor laser element (20) has a counter surface (20a) that faces the sub-mount (80). In a plan view of the mounting surface (80a), the spacer (40) is not present on the outer side of one end of the semiconductor laser element (20) in a first direction perpendicular to the resonance direction of the laser beam (L0), and the junction member (60) is disposed between one end of the semiconductor laser element (20) and one end of the spacer (40) in the first direction, and the counter surface (20a) is exposed from the junction member (60) at one end of the semiconductor laser element (20).
H01S 5/024 - Dispositions pour la gestion thermique
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
An image processing device (10) comprises: an image processing unit (11) that acquires, frame by frame, temporally continuous real-world images; a position information holding unit (12) that acquires, frame by frame, position information indicating the position at which the real-world images were captured; a virtual image memory (14) that acquires a virtual image created using a past real-world image N (N is an integer of 1 or more) frames prior to a current real-world image; a correction amount calculation unit (13) that calculates a correction amount for a positional deviation of the virtual image from the current real-world image on the basis of, among the position information acquired frame by frame, current position information indicating the position at which the current real-world image was captured and past position information indicating the position at which the past real-world image was captured; a correction unit (15) that corrects the positional deviation on the basis of the correction amount; and an output unit (16) that outputs the virtual image in which the positional deviation has been corrected.
A video transmission device (10) can be connected to a stage before a preexisting transmission device (30) without a function for compressing inputted video, and comprises: a reception unit (11) that receives a video signal; a video signal compression unit (12) that, if the video signal received by the reception unit (11) is a video signal exceeding the bandwidth of a video transmission path used by the preexisting transmission device (30), compresses the video signal; a compressed video information generation unit (13) that generates first compressed video information including a parameter which was used in the compression of the video signal by the video signal compression unit (12); and a transmission unit (14) that transmits the video signal compressed by the video signal compression unit (12) and the first compressed video information to the preexisting transmission device (30).
H04N 21/24 - Surveillance de procédés ou de ressources, p. ex. surveillance de la charge du serveur, de la bande passante disponible ou des requêtes effectuées sur la voie montante
37.
SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING ELEMENT
A semiconductor light-emitting element (10) comprises: a semiconductor laminate (10S); and a contact electrode (40) that is in contact with the semiconductor laminate (10S) and contains Ag as a main component. The contact electrode (40) has one or more recesses (D1) formed in the surface of the contact electrode (40), and on a straight line extending in a direction along the surface of the contact electrode (40), an average inter-recess distance defined by the average of the distances between two adjacent recesses (D1) among the one or more recesses (D1) is 0.11 μm or greater.
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
H10H 20/825 - Matériaux des régions électroluminescentes comprenant uniquement des matériaux du groupe III-V, p. ex. GaP contenant de l’azote, p. ex. GaN
H10H 20/831 - Électrodes caractérisées par leur forme
H10H 20/832 - Électrodes caractérisées par leurs matériaux
A semiconductor laser module includes a semiconductor laser chip, a first collimator element, and a package. The package includes: a body having a bottom and a top with an opening; a cap member; and a window member. The semiconductor laser chip has a light-emitting point for emitting laser light. The semiconductor laser chip is located on the bottom so as to emit the laser light in a direction parallel to the principal surface of the bottom. The laser light has a greater divergence angle along the first axis than a divergence angle along a second axis perpendicular to the first axis. The first collimator element includes a concave mirror surface. The mirror surface reflects the laser light toward the opening, and reduces the divergence angle of the laser light along the first axis.
H01S 5/02208 - SupportsBoîtiers caractérisés par la forme des boîtiers
H01S 5/02218 - Matériaux du boîtierMatériaux de remplissage du boîtier
H01S 5/02251 - Découplage de lumière utilisant des fibres optiques
H01S 5/02253 - Découplage de lumière utilisant des lentilles
H01S 5/02257 - Découplage de lumière utilisant des fenêtres optiques, p. ex. spécialement adaptées pour réfléchir de la lumière sur un détecteur à l’intérieur du boîtier
H01S 5/02325 - Composants intégrés mécaniquement aux éléments de montage ou aux micro-bancs optiques
H01S 5/024 - Dispositions pour la gestion thermique
H01S 5/40 - Agencement de plusieurs lasers à semi-conducteurs, non prévu dans les groupes
A semiconductor device that is a facedown mountable, chip-size-package type semiconductor device, the semiconductor device including: a semiconductor substrate; and a metal layer that is disposed on the semiconductor substrate and is exposed to outside. One or more marks are provided on an exposed surface of the metal layer. The one or more marks each include an outline portion defining an outline of the mark, and a central portion located inward of the outline portion. In a plan view of the exposed surface of the metal layer, the outline portion has a color different from at least one of a color of the central portion or a color of a base portion that is a portion of the exposed surface of the metal layer on which the one or more marks are not provided.
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
B23K 26/073 - Détermination de la configuration du spot laser
B23K 26/18 - Travail par rayon laser, p. ex. soudage, découpage ou perçage utilisant des couches absorbantes sur la pièce à travailler, p. ex. afin de marquer ou de protéger
B23K 26/40 - Enlèvement de matière en tenant compte des propriétés du matériau à enlever
B23K 101/00 - Objets fabriqués par brasage, soudage ou découpage
An impedance detection device includes: an obtainer that obtains measurement data items on at least one of a current or a voltage at I time points in a transient response when a predetermined current or voltage is supplied to a secondary cell; and a calculator that calculates internal impedance based on the measurement data items. The calculator includes: a first calculator that calculates I impedance data items by using the measurement data items; and a second calculator that calculates an element parameter of an equivalent circuit model of the secondary cell, based on the I impedance data items and an M-th degree equation in which the internal impedance is represented by a linear combination of a plurality of terms. The M-th degree equation is an equation that is based on a theoretical value and is according to the predetermined current or voltage.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge
G01R 31/367 - Logiciels à cet effet, p. ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
A Doherty amplifier (100) comprising a carrier amplifier (160) and a peak amplifier (170) comprises: a distributor (180) that distributes an input signal to the carrier amplifier (160) and the peak amplifier (170); a detection circuit (110) that is connected to the output, on the peak amplifier (170) side, of the distributor (180) and detects the power inputted to the peak amplifier (170); and an active bias circuit (120) that adjusts the gate bias of the carrier amplifier (160) or the peak amplifier (170) according to an output signal from the detection circuit (110).
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
H03F 3/68 - Combinaisons d'amplificateurs, p. ex. amplificateurs à plusieurs voies pour stéréophonie
42.
IMAGE SENSING DEVICE, IMAGE SENSING METHOD, AND RECORDING MEDIUM
An image sensing device includes: a 2D camera that generates a 2D image; a 3D camera that includes a light source and generates a depth image based on reflected light of light emitted by the light source; and an image recognizer that performs recognition on a subject included in the 2D image, using at least one of the 2D image or the depth image; and a camera controller that controls on and off of an operation of the 3D camera. The camera controller turns on the operation of the 3D camera based on a result of the recognition using the 2D image when the 3D camera is in a standby state, and the 3D camera enters the standby state when the camera controller turns off the operation of the 3D camera after turning on the operation.
H04N 13/254 - Générateurs de signaux d’images utilisant des caméras à images stéréoscopiques en combinaison avec des sources de rayonnement électromagnétique pour l’éclairage du sujet
H04N 23/45 - Caméras ou modules de caméras comprenant des capteurs d'images électroniquesLeur commande pour générer des signaux d'image à partir de plusieurs capteurs d'image de type différent ou fonctionnant dans des modes différents, p. ex. avec un capteur CMOS pour les images en mouvement en combinaison avec un dispositif à couplage de charge [CCD] pour les images fixes
H04N 23/61 - Commande des caméras ou des modules de caméras en fonction des objets reconnus
H04N 23/65 - Commande du fonctionnement de la caméra en fonction de l'alimentation électrique
H04N 23/67 - Commande de la mise au point basée sur les signaux électroniques du capteur d'image
43.
DISTANCE MEASUREMENT DEVICE AND OFFSET NOISE REMOVAL METHOD
This distance measurement device (10) comprises: a light source (11); a light reception unit (12); a drive control unit (13); a distance calculation unit (14) that calculates a distance value for the distance to a subject (20); and an offset noise removal unit (15) or the like that performs filtering on the distance value calculated by the distance calculation unit (14), thereby generating a distance image removed of offset noise. The offset noise removal unit (15) or the like counts the number of invalid values among the distance values of pixels positioned around a relevant pixel, and when the number of obtained invalid values exceeds a number threshold value, outputs the distance value of the relevant pixel by changing same to an invalid value.
G01S 17/10 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes à modulation d'impulsion interrompues
G01C 3/06 - Utilisation de moyens électriques pour obtenir une indication finale
G01S 17/89 - Systèmes lidar, spécialement adaptés pour des applications spécifiques pour la cartographie ou l'imagerie
44.
DISTANCE MEASUREMENT IMAGING DEVICE AND METHOD FOR DRIVING DISTANCE MEASUREMENT IMAGING DEVICE
A distance measurement imaging device (10) is for generating a distance image by using a TOF method, and comprises: a light source unit (11); an imaging unit (13); a drive circuit (14) that drives the imaging unit (13) to perform exposure in each of a plurality of continuous exposure periods; and a signal processing unit (15) that calculates and outputs the distance from the distance measurement imaging device (10) to a subject (5) on the basis of a signal generated by the imaging unit (13). The plurality of continuous exposure periods correspond to the distance measurement range of the distance measurement imaging device (10). In addition to the plurality of continuous exposure periods, the drive circuit (14) causes the imaging unit (13) to perform exposure in an additional exposure period in at least one of a timing that is earlier than the plurality of continuous exposure periods and a timing that is later than the plurality of continuous exposure periods, and a signal generated in the additional exposure period is added to or subtracted from a signal generated in any of the plurality of continuous exposure periods.
A sensor package (10 or 10A) comprises: a base material (20 or 20A) having a first surface (21) and a second surface (22) opposite to the first surface (21), and wiring (26); a chip (30) flip-chip connected to the first surface (21) of the base material; and an external conductor (60 or 60A) provided on the base material so as to be electrically connected to the wiring (26) of the base material. The chip (30) has a main surface (one main surface (31)) facing the first surface (21) of the base material, and a detection unit (100) provided on the main surface. The detection unit (100) is connected to the base material so as to be electrically connected to the wiring (26) of the base material. The base material has a through-hole (25) penetrating between the first surface (21) and the second surface (22).
This image compression device (1) comprises: an acquisition unit (10) that acquires MIPI image data in which respective images of a plurality of virtual channels are superimposed in units of lines constituting the images; an identification unit (20) that identifies, on the basis of identifiers added to each of a plurality of lines included in the MIPI image data, whether each of the plurality of lines is a line of an image of one of the plurality of virtual channels, and simultaneously outputs two or more identified lines of different virtual channel images; a buffer unit (30) that has a plurality of N-line buffers corresponding to the plurality of virtual channels, receives the two or more lines, and stores each of the two or more lines in an N-line buffer of the corresponding virtual channel on the basis of the identifiers added to each of the two or more lines; and a compression unit (50) that reads the data stored in the plurality of N-line buffers and compresses the respective images of the plurality of virtual channels.
H04N 19/436 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p. ex. la mise en œuvre de logiciels spécialisés utilisant des dispositions de calcul parallélisées
47.
SEMICONDUCTOR LASER DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LASER DEVICE
A semiconductor laser device (1) comprises: a semiconductor laser element (200) that emits laser light from a light emission end surface; and a lens unit (100) that has a cylindrical lens (110) and a first mounting surface. The semiconductor laser element (200) has an active layer. The cylindrical lens (110), when the laser light is incident thereon, reduces the divergence angle of the laser light in a fast-axis direction. The first mounting surface is fixed to a first mounted surface. In a plan view of the active layer, a bus (115) of the cylindrical lens (110) is inclined with respect to the first mounted surface.
A synchronization signal processing device (100) comprises a correction value control unit (10) and a synchronization generation unit (50). The correction value control unit (10) acquires an input synchronization signal that is a vertical synchronization signal for an input video, determines whether or not the cycle of the input synchronization signal is greater than or equal to a predetermined threshold value that is greater than the cycle corresponding to the refresh rate of an LCD panel (300) on which an output video is displayed, generates a set cycle on the basis of a cycle of 1/N times the input synchronization signal (N = integer 2 or greater) when it is determined that the cycle of the input synchronization signal is greater than or equal to the predetermined threshold value, and generates a set cycle on the basis of the cycle of the input synchronization signal when it is determined that the cycle of the input synchronization signal is less than the predetermined threshold value. The synchronization generation unit (50) generates an output synchronization signal that is a vertical synchronization signal of the output video on the basis of the set cycle.
H04N 5/05 - Circuits de synchronisation avec dispositions pour étendre la plage de synchronisation, p. ex. en utilisant la commutation entre différentes bases de temps
H04N 23/60 - Commande des caméras ou des modules de caméras
49.
DISTANCE MEASURING DEVICE AND METHOD FOR CALIBRATING DISTANCE MEASURING DEVICE
A distance measuring device (10) comprises a light source (11), a light receiving unit (12), a drive control unit (13) that drives the light source (11) and the light receiving unit (12), a depth calculating unit (14) that calculates a depth on the basis of the amount of light received by the light receiving unit (12), a distance calculating unit (15) that includes a correction value storage unit (15a) for holding a correction value, and that calculates a distance by correcting the depth on the basis of the correction value, and a calibration unit (16) that executes calibration for updating the correction value, wherein the calibration unit (16) includes: a pulse phase sweeping unit (16a) that controls the drive control unit (13) to change a phase, which is the time difference from when a light emission pulse is output until an exposure pulse is output, such that a plurality of different phases are sequentially generated; and a correction value calculating unit (16b) that calculates the correction value from the plurality of phases and the corresponding plurality of depths obtained by the depth calculating unit (14), and causes the correction value storage unit (15a) to hold the calculated correction value.
A motor drive device includes: an actual speed signal generator; a target speed signal generator; a speed comparator that compares an actual speed signal and a target speed signal; and a speed command generator that generates a speed command signal according to an output from the speed comparator. The speed command generator includes: a step width generator that generates, according to the output from the speed comparator, a step width signal indicating a step width including a size and a positive or negative sign that correspond to a magnitude of one of the actual speed or the target speed with respect to the other; an update signal generator that generates an update signal; and an accumulation calculator that adds the step width indicated by the step width signal to the speed command signal and outputs a resulting speed command signal, at a timing of the update signal.
H02P 6/17 - Dispositions de circuits pour détecter la position et pour l’obtention d’informations sur la vitesse
H02P 6/06 - Dispositions pour la régulation de la vitesse d'un seul moteur dans lesquelles la vitesse du moteur est mesurée et comparée à une grandeur physique donnée pour ajuster la vitesse du moteur
H02P 29/10 - Prévention de la survitesse ou la sous-vitesse
51.
INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM
An information processing device (100) comprises: an acquiring unit (110) that acquires a first video and a second video captured with a closer focal point than the first video; a rotating unit (120) that rotates the second video through 180 degrees; a detecting unit (130) that detects a first feature quantity from the first video and detects a second feature quantity from the second video rotated through 180 degrees; a calculating unit (140) that calculates a correlation between the first feature quantity and the second feature quantity; and a determining unit (150) that determines whether or not water droplets appear in the second video on the basis of the calculated correlation.
G01N 21/27 - CouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes en utilisant la détection photo-électrique
A drive measurement circuit (2) comprises: a current measurement unit (21) that measures the current of a first battery (B1) and the current of a second battery (B2); a voltage measurement unit (20) that measures the voltage of the first battery (B1) and the voltage of the second battery (B2); an AC detection unit (22) that receives a measurement instruction signal including information on a measurement frequency from a host system (200) that has a function of calculating the AC impedance, and measures an AC voltage and an AC current corresponding to the measurement frequency and outputs the AC voltage and the AC current to the host system (200) on the basis of the measurement result of the voltage measurement unit (20) and the measurement result of the current measurement unit (21); and a drive control unit (23) that drives a plurality of switching elements so as to periodically change the movement state of electrical energy via an inductor (14) in accordance with the measurement frequency.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 27/02 - Mesure de résistances, de réactances, d'impédances réelles ou complexes, ou autres caractéristiques bipolaires qui en dérivent, p. ex. constante de temps
A semiconductor integrated circuit device includes: standard cell rows each of which includes standard cells that are arranged in an X direction and a power supply wire that extends in the X direction and supplies power to the standard cells; strap power supply wires that extend in a Y direction; supplementary strap power supply wires that extend in the Y direction and are each connected to each of the power supply wires; and switch cells arranged at intersections between the strap power supply wires and the power supply wires. The standard cell rows include a standard cell row in which no switch cell is disposed at one or more positions corresponding to, among a plurality of standard cell columns, one or more standard cell columns other than standard cell columns located at both ends of the plurality of standard cell columns.
A hydrogen detection device (30) is provided with a hydrogen sensor element (100), a first reference element (100a), and a second reference element (100b) that are formed above one semiconductor substrate (102) and that are connected in series. Each of the hydrogen sensor element (100), the first reference element (100a), and the second reference element (100b) includes a layered body having an identical structure. The hydrogen sensor element (100) includes an opening (110) that exposes a secondary surface of the second electrode (106) facing a primary surface thereof to the outside without the secondary surface being covered by an insulating film (107c) or the like. The first reference element (100a) and the second reference element (100b) do not have an opening that exposes the secondary surface of the second electrode (106) facing the primary surface thereof to the outside. The first reference element (100a) and the second reference element (100b) have different lengths in the direction in which current flows.
G01N 27/04 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance
G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
55.
VIDEO-SIGNAL PROCESSING DEVICE AND VIDEO-SIGNAL PROCESSING METHOD
A video-signal processing device (10) comprises: an MIPI D-PHY (21) that receives a video signal output from an MIPI camera (5); a packet analysis unit (22) that determines whether the packet generated by the MIPI D-PHY (21) is payload data or embedded data; an embedded-data extraction unit (25) that extracts embedded data from the packet generated by the MIPI D-PHY (21); a video-input processing unit (23) that receives the payload data and the embedded data, performs video-signal processing and then, outputs the payload data and the embedded data; a frame memory (30); and a selection storage unit (24) that stores the payload data in a region of the frame memory (30) associated with the payload data and stores the embedded data in a region of the frame memory (30) associated with the embedded data, and the like.
H04N 23/60 - Commande des caméras ou des modules de caméras
H04N 7/18 - Systèmes de télévision en circuit fermé [CCTV], c.-à-d. systèmes dans lesquels le signal vidéo n'est pas diffusé
H04N 21/236 - Assemblage d'un flux multiplexé, p. ex. flux de transport, en combinant un flux vidéo avec d'autres contenus ou données additionnelles, p. ex. insertion d'une adresse universelle [URL] dans un flux vidéo, multiplexage de données de logiciel dans un flux vidéoRemultiplexage de flux multiplexésInsertion de bits de remplissage dans le flux multiplexé, p. ex. pour obtenir un débit constantAssemblage d'un flux élémentaire mis en paquets
H04N 21/434 - Désassemblage d'un flux multiplexé, p. ex. démultiplexage de flux audio et vidéo, extraction de données additionnelles d'un flux vidéoRemultiplexage de flux multiplexésExtraction ou traitement de SIDésassemblage d'un flux élémentaire mis en paquets
A nitride semiconductor light-emitting element emits light and includes an N-type cladding layer, an N-side optical guide layer, an active layer, an electron blocking layer, a P-type interlayer, a P-side optical guide layer, and a P-type cladding layer. Average band gap energy of the electron blocking layer is higher than average band gap energy of the P-type cladding layer. Average band gap energy of the P-type interlayer is higher than average band gap energy of the P-side optical guide layer, and is smaller than the average band gap energy of the electron blocking layer. An average impurity concentration of the P-type interlayer is lower than an average impurity concentration of the electron blocking layer, and is higher than an average impurity concentration of the P-side optical guide layer. A peak wavelength of the light is less than 400 nm.
H01S 5/32 - Structure ou forme de la région activeMatériaux pour la région active comprenant des jonctions PN, p. ex. hétérostructures ou doubles hétérostructures
H01S 5/323 - Structure ou forme de la région activeMatériaux pour la région active comprenant des jonctions PN, p. ex. hétérostructures ou doubles hétérostructures dans des composés AIIIBV, p. ex. laser AlGaAs
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
H10H 20/00 - Dispositifs individuels émetteurs de lumière à semi-conducteurs inorganiques ayant des barrières de potentiel, p. ex. diodes électroluminescentes [LED]
H10H 20/816 - Corps ayant des structures contrôlant le transport des charges, p. ex. couches semi-conductrices fortement dopées ou structures bloquant le courant
H10H 20/825 - Matériaux des régions électroluminescentes comprenant uniquement des matériaux du groupe III-V, p. ex. GaP contenant de l’azote, p. ex. GaN
57.
DISTANCE MEASURING DEVICE AND DISTANCE MEASURING METHOD
A distance measuring device includes: a light source unit that emits irradiation light; a light receiver including a pixel that generates a pixel signal based on incident light; a drive controller that controls driving of the light source unit and the light receiver; and a signal processor that derives a distance to a target object based on the pixel signal. The drive controller drives the light source unit and the pixel through a continuous wave (CW) time-of-flight (ToF) sequence and a pulse ToF sequence that are sequences for measuring a distance using mutually different types of indirect ToF methods. The signal processor derives the distance to the target object based on a first pixel signal generated by the pixel in the CW-ToF sequence and a second pixel signal generated by the pixel in the pulse ToF sequence.
G01S 7/4914 - Réseaux des détecteurs, p. ex. portes de transfert de charge
G01S 7/4915 - Mesure du temps de retard, p. ex. détails opérationnels pour les composants de pixelsMesure de la phase
G01S 17/10 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes à modulation d'impulsion interrompues
G01S 17/32 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées
A motor drive device includes: a target speed generator that generates a target speed signal indicating a target speed of a motor; an actual speed detector that generates an actual speed signal indicating an actual speed; and a driver that drives the motor to cause the actual speed indicated by the actual speed signal to approach the target speed indicated by the target speed signal. The target speed generator (i) generates an input speed signal based on an input command and a tentative speed signal higher than the actual speed signal at startup, and (ii) when the actual speed indicated by the actual speed signal at the startup is higher than a speed indicated by the input speed signal, outputs the tentative speed signal as the target speed signal.
H02P 1/16 - Dispositions de démarrage de moteurs électriques ou de convertisseurs dynamo-électriques pour faire démarrer des machines dynamo- électriques ou des convertisseurs dynamo-électriques
H02P 1/04 - Moyens de commande de la progression d'une séquence de démarrage en fonction du temps ou en fonction du courant, de la vitesse ou d'un autre paramètre du moteur
59.
POINT CLOUD DATA PROCESSING DEVICE, POINT CLOUD DATA PROCESSING METHOD, AND PROGRAM
A point cloud data processing device (100) comprises: a first ranging unit (130) that captures a first ranging image (11) using unstructured illumination (111); a second ranging unit (140) that captures a second ranging image (12) using structured illumination (112); an image processing unit (150) that generates a difference image (13) indicating the difference between the first ranging image (11) and the second ranging image (12); a point cloud converting unit (160) that, on the basis of the first ranging image (11) captured by the first ranging unit (130), performs point-cloud conversion of distance values included in the first ranging image (11) to generate first point cloud data (21); a correction data generating unit (170) that generates correction point cloud data on the basis of the difference image (13) generated by the image processing unit (150); and a point cloud correcting unit (180) that generates blended point cloud data (22) by correcting the first point cloud data (21) on the basis of the generated correction point cloud data.
A semiconductor device (100) is provided with: a semiconductor laminated structure (110) that contains a two-dimensional electron gas; a p-type first semiconductor layer (120) that is provided on the semiconductor laminated structure (110); and a drain electrode (160) that is in contact with the first semiconductor layer (120). The first semiconductor layer (120) includes a thick film part (122) and a thin film part (124) thinner than the thick film part (122). In the semiconductor laminated structure (110), a recessed part (112) is provided in a first region (101) contiguous to the thin film part (124) in plan view, and the drain electrode (160) is in contact with a side surface (112b) of the recessed part (112) and a side surface (124b) of the thin film part (124).
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
A semiconductor laser element (1) comprises: a semiconductor laminate (1S) that emits laser light and in which semiconductor layers are laminated, the semiconductor laminate (1S) having a ridge (50R); and a first p-side electrode (91) disposed over the semiconductor laminate (1S). The semiconductor laminate (1S) has an n-type cladding layer (30), an active layer (42), a p-type cladding layer (50), a p-type barrier relaxation layer (60), and a contact layer (70). The film thickness of the contact layer (70) is 0.1 μm or less, and the bandgap energy of the contact layer (70) is smaller than the energy corresponding to the peak wavelength of the laser light. The p-type barrier relaxation layer (60) has a first p-type barrier relaxation layer (60b) and a second p-type barrier relaxation layer (60t) disposed between the contact layer (70) and the first p-type barrier relaxation layer (60b). The second p-type barrier relaxation layer (60t) is an AlGaAs layer, and the bandgap energy of the second p-type barrier relaxation layer (60t) is greater than the energy corresponding to the peak wavelength.
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
H01S 5/323 - Structure ou forme de la région activeMatériaux pour la région active comprenant des jonctions PN, p. ex. hétérostructures ou doubles hétérostructures dans des composés AIIIBV, p. ex. laser AlGaAs
62.
SEMICONDUCTOR LASER ELEMENT AND METHOD FOR PRODUCING SEMICONDUCTOR LASER ELEMENT
A semiconductor laser element (1) having a plurality of light-emitting regions (1a), said semiconductor laser element (1) comprising a substrate (10), an N-side semiconductor layer (21) positioned above the substrate (10), a light-emitting layer (22) positioned above the N-side semiconductor layer (21), a P-side semiconductor layer (23) positioned above the light-emitting layer (22), a plurality of P-side contact layers (24) positioned above the P-side semiconductor layer (23) and provided for each of the plurality of light-emitting regions (1a), and a first p-electrode (41) provided for each of the plurality of P-side contact layers (24) so as to be in contact with each of the plurality of P-side contact layers (24), wherein one of at least two first p-electrodes (41) among the plurality of first p-electrodes (41) includes a first electrode material, and another of the at least two first p-electrodes (41) includes a second electrode material having a refractive index different from that of the first electrode material.
An imaging apparatus includes a substrate, a photoelectric converter provided in the substrate, a first transfer transistor connected to the photoelectric converter and including a first control terminal, and a second transfer transistor connected to the photoelectric converter and including a second control terminal. The photoelectric converter includes a first semiconductor region of a first conductivity type provided in the substrate. In a plan view of the substrate, each of the first control terminal and the second control terminal overlaps the first semiconductor region. The total of the overlapping area of the first control terminal and the first semiconductor region and the overlapping area of the second control terminal and the first semiconductor region is at least 20% of the area of the photoelectric converter.
H04N 25/705 - Pixels pour la mesure de la profondeur, p. ex. RGBZ
G01S 7/4865 - Mesure du temps de retard, p. ex. mesure du temps de vol ou de l'heure d'arrivée ou détermination de la position exacte d'un pic
H04N 25/59 - Commande de la gamme dynamique en commandant la quantité de charge stockable dans le pixel, p. ex. en modifiant le rapport de conversion de charge de la capacité du nœud flottant
H04N 25/76 - Capteurs adressés, p. ex. capteurs MOS ou CMOS
H10F 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément couvert par le groupe , p. ex. détecteurs de rayonnement comportant une matrice de photodiodes
H10F 39/18 - Capteurs d’images à semi-conducteurs d’oxyde de métal complémentaire [CMOS]Capteurs d’images à matrice de photodiodes
64.
IMAGING APPARATUS, DISTANCE MEASURING APPARATUS, AND CONTROL METHOD FOR IMAGING APPARATUS
An imaging apparatus includes: a first semiconductor layer; a unit cell that is provided in the first semiconductor layer and includes n pixels, where n is a natural number, and a charge accumulator in which charge generated in the n pixels accumulates; and a driving circuit. Each of the n pixels includes: a photoelectric converter; a first transfer transistor that includes a first control terminal; and a second transfer transistor that includes a second control terminal, and the driving circuit supplies a voltage corresponding to an operation mode selected from among a plurality of operation modes to the first semiconductor layer, the first control terminal, or the second control terminal.
H04N 23/667 - Changement de mode de fonctionnement de la caméra, p. ex. entre les modes photo et vidéo, sport et normal ou haute et basse résolutions
H04N 25/76 - Capteurs adressés, p. ex. capteurs MOS ou CMOS
H04N 25/771 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des moyens de stockage autres que la diffusion flottante
A chip-sized package type semiconductor device (1) comprises a semiconductor layer (40), a plurality of pads (50), and a plurality of metal rewirings (20) each connected to at least one of the pads (50) and located above the upper surface of the semiconductor layer (40). The plurality of metal rewirings (20) include a plurality of first metal rewirings (21): which comprise first parts (24A) and second parts (24B) located above the first parts (24A); and in which, in a plan view, the second parts (24B) are contained within the first parts (24A) and the area of the second parts (24B) is smaller than that of the first parts (24A). Each of the plurality of first metal rewirings (21) has, in a boundary region between the corresponding first part (24A) and second part (24B) on the surface of the first metal rewiring (21), at least one linear bending portion (25) having an interior angle greater than 180° in a cross section of the first metal rewiring (21).
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
This rendering display system (1) comprises a rendering display device (10) and a nonvolatile memory (20). The rendering display device (10) includes: a rendering processing unit (11) that performs rendering processing; a rendering-processing idle time detection unit (12) that detects an idle time generated in the rendering processing; and a firmware update processing unit (13) that updates firmware. The nonvolatile memory (20) has a first storage area (21) and a second storage area (22) that store the firmware. The rendering processing unit (11) acquires a program code from the first storage area (21) and performs rendering processing by executing the acquired program code. The firmware update processing unit (13) makes access for firmware update to the second storage area (22) on the basis of idle time information indicating the detected idle time.
A semiconductor module (1) comprises: a semiconductor device (100) provided with n-number of pads (101); and a mounting substrate (200) provided with n-number of lands (201) corresponding to the n-number of pads (101) in a one-to-one manner. Each of the n-number of pads (101) is joined to, among the n-number of lands (201), one land (201) corresponding to the pad (101) via a solder bonding material (301). When the area of a nearest pad (101a) that is nearest to the center of the semiconductor device (100) among the n-number of pads (101) is defined as Pa, the area of a farthest pad (101b) that is farthest from said center is defined as Pb, the area of a nearest land (201a) corresponding to the nearest pad (101a) among the n-number of lands (201) is defined as La, and the area of a farthest land (201b) corresponding to the farthest pad (101b) is defined as Lb, Pa/La is less than 1 and Pb/Lb is greater than 1, or Pa/La is greater than 1 and Pb/Lb is less than 1.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
A battery management system (5) for managing a battery pack (10) comprises: a plurality of monitoring circuits (100) for monitoring the battery pack (10); and a management circuit (200) that is connected to each of the plurality of monitoring circuits (100) by wireless communication and manages the battery pack (10). At least one of the plurality of monitoring circuits (100) and/or the management circuit (200) has a measurement circuit (215) for measuring time of flight (TOF) between the monitoring circuit (100) and the management circuit (200) by impulse response ultra wide band (IR-UWB) communication.
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
B60L 3/00 - Dispositifs électriques de sécurité sur véhicules propulsés électriquementContrôle des paramètres de fonctionnement, p. ex. de la vitesse, de la décélération ou de la consommation d’énergie
G01R 31/3835 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge ne faisant intervenir que des mesures de tension
G01R 31/396 - Acquisition ou traitement de données pour le test ou la surveillance d’éléments particuliers ou de groupes particuliers d’éléments dans une batterie
H02J 7/02 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries pour la charge des batteries par réseaux à courant alternatif au moyen de convertisseurs
A nitride semiconductor laser element (100) comprises: an n-type cladding layer (102); an active layer (105) disposed above the n-type cladding layer (102); a p-type cladding layer (110) disposed above the active layer (105) and having a ridge (110R) formed therein; a conductive oxide film (113) disposed above the p-type cladding layer (110) and translucent with respect to light of the excitation wavelength of the nitride semiconductor laser element (113); and a metal electrode (114) disposed above the conductive oxide film (113) and including a metal that has higher reflectance than palladium with respect to light of the excitation wavelength.
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
70.
HYDROGEN DETECTION ELEMENT AND METHOD FOR MANUFACTURING THE SAME
A hydrogen detection element includes: a first electrode that is planar; a second electrode that is planar, is disposed opposite to the first electrode, includes a principal surface covered by an insulating film (a protective film and a second insulating film), and includes a plurality of exposed portions that serve as a plurality of hydrogen gas inlets and are each provided by opening part of the insulating film on the principal surface; a metal oxide layer that is disposed between the first electrode and the second electrode; and a first terminal and a second terminal that are electrically connected to the second electrode at positions between which the plurality of exposed portions are arranged in plan view of the second electrode. When hydrogen gas is introduced to the plurality of exposed portions, resistance between the first terminal and the second terminal changes.
G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes
A semiconductor device includes: a semiconductor layer; a vertical metal-oxide semiconductor (MOS) transistor; a protective film; a first wiring electrode connected to a source electrode of the vertical MOS transistor; and a second wiring electrode connected to a gate electrode of the vertical MOS transistor. A first perimeter structure is provided in a perimeter portion of the first wiring electrode in the plan view of the semiconductor layer, the first perimeter structure protruding upward of the semiconductor device and including the source electrode, the protective film, and the first wiring electrode that are stacked in stated order. A second perimeter structure is provided in a perimeter portion of the second wiring electrode in the plan view of the semiconductor layer, the second perimeter structure protruding upward of the semiconductor device and including the gate electrode, the protective film, and the second wiring electrode that are stacked in stated order.
An object detection method that includes: obtaining a first image and a second image including pixels corresponding one to one to pixels of the first image; performing a first recognition process that recognizes a type of a first object included in the first image; performing a second recognition process that recognizes a position of a second object included in the second image; and when a first region based on the first object in the first image and a second region based on the second object in the second image overlap each other, detecting the first object and the second object as a same object.
G06V 10/26 - Segmentation de formes dans le champ d’imageDécoupage ou fusion d’éléments d’image visant à établir la région de motif, p. ex. techniques de regroupementDétection d’occlusion
G06V 10/70 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique
G06V 10/80 - Fusion, c.-à-d. combinaison des données de diverses sources au niveau du capteur, du prétraitement, de l’extraction des caractéristiques ou de la classification
G06V 10/98 - Détection ou correction d’erreurs, p. ex. en effectuant une deuxième exploration du motif ou par intervention humaineÉvaluation de la qualité des motifs acquis
A battery management system (5) for managing a battery pack (10) comprises: a monitoring circuit (100) which monitors the battery pack (10); and a management circuit (200) which is connected to the monitoring circuit (100) by wireless communication and manages the battery pack (10). Each of the monitoring circuit (100) and the management circuit (200) has a plurality of wireless communication units that use mutually different modulation schemes for wireless communication. The mutually different modulation schemes for wireless communication include a UWB (Ultra Wide Band) scheme.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
B60L 3/00 - Dispositifs électriques de sécurité sur véhicules propulsés électriquementContrôle des paramètres de fonctionnement, p. ex. de la vitesse, de la décélération ou de la consommation d’énergie
B60L 58/10 - Procédés ou agencements de circuits pour surveiller ou commander des batteries ou des piles à combustible, spécialement adaptés pour des véhicules électriques pour la surveillance et la commande des batteries
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
H01Q 21/06 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles
74.
SOLID-STATE LASER DEVICE AND METHOD FOR MANUFACTURING SOLID-STATE LASER DEVICE
A solid-state laser device (100) is provided with: a light-emitting element (140) that emits first light (L1); a laser crystal (150) that absorbs the first light (L1) and emits second light (L2); a nonlinear optical crystal (160) that absorbs the second light (L2) and emits third light (L3); a second selective transmission mirror (120) that is disposed between the laser crystal (150) and the nonlinear optical crystal (160) and transmits the second light (L2); and a third selective transmission mirror (130) that is disposed on the optical axis of the third light (L3) and transmits the third light (L3). A first selective transmission mirror (110) reflects the second light (L2), the second selective transmission mirror (120) reflects the third light (L3), and the third selective transmission mirror (130) reflects the second light (L2). The second selective transmission mirror (120) and the third selective transmission mirror (130) are spaced apart from the nonlinear optical crystal.
H01S 3/108 - Commande de l'intensité, de la fréquence, de la phase, de la polarisation ou de la direction du rayonnement, p. ex. commutation, ouverture de porte, modulation ou démodulation par commande de dispositifs placés dans la cavité utilisant des dispositifs optiques non linéaires, p. ex. produisant une diffusion par effet Brillouin ou Raman
G02F 1/37 - Optique non linéaire pour la génération de l'harmonique deux
The present invention includes a pixel array (110) in which a plurality of pixels (120) including a plurality of first pixels and a plurality of second pixels are disposed in a two-dimensional manner, in which each of the plurality of first pixels is exposed to reflected light (L2) of irradiation light (L1) reflected by a target (2) on the basis of an exposure signal at a timing interlocking with a light-emission signal and generates a signal for distance detection, each of the plurality of second pixels generates a signal for phase-difference detection on the basis of light incident from a region in which the reflected light is pupil-split, the pixel array (110) includes one or more phase-difference detection regions (220) in which two or more second pixels of the plurality of second pixels are aligned along one direction, and at least some of the plurality of first pixels are, in the pixel array (110), disposed at positions different from the one or more phase-difference detection regions (220) and closer to a center of the pixel array (110) than at least one phase-difference detection region (220) of the one or more phase-difference detection regions (220).
A current measurement-use semiconductor device (30) is for measuring the current which flows through a shunt resistor (4) provided in a measurement target device (3), and comprises: a first current measurement circuit (10) that measures the current flowing through the shunt resistor (4) by detecting voltage at both ends of the shunt resistor (4); and a second current measurement circuit (20) that has a coreless magnetic sensor (50) and measures the current flowing through the shunt resistor (4) by using the coreless magnetic sensor (50).
G01R 15/00 - Détails des dispositions pour procéder aux mesures des types prévus dans les groupes , ou
G01R 15/20 - Adaptations fournissant une isolation en tension ou en courant, p. ex. adaptations pour les réseaux à haute tension ou à courant fort utilisant des dispositifs galvano-magnétiques, p. ex. des dispositifs à effet Hall
G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
G01R 19/32 - Compensation des variations de température
G01R 35/02 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe des dispositifs auxiliaires, p. ex. des transformateurs pour appareils en fonction du rapport de transformation, de l'angle de phase ou de la puissance à l'utilisation
This imaging device is provided with: a plurality of pixels which each have a photoelectric conversion unit for converting incident light into an electric charge and which each generate a signal based on the electric charge; and a drive control unit that exposes the plurality of pixels. The drive control unit exposes the plurality of pixels so that the plurality of pixels generate: one or more first signals for representing a first signal value corresponding to an electric charge that is obtained by conversion by the photoelectric conversion unit during a period of an exposure pulse (A1) starting at a timing based on a light emission pulse (L); and one or more second signals for representing a second signal value corresponding to an electric charge that is obtained by conversion by the photoelectric conversion unit during a period of an exposure pulse (A2) starting at a timing based on the light emission pulse (L). The exposure pulse (A2) starts, on the basis of the light emission pulse (L), with a prescribed time difference from the start of the exposure pulse (A1). A pulse width (Tp1) of the exposure pulse (A1) and a pulse width (Tp2) of the exposure pulse (A2) are equal to each other, and are each shorter than a pulse width (TpL) of the light emission pulse (L).
A level shift circuit (10) comprises: an input circuit (12a) that converts one input signal generated by using a first voltage power supply (VDD_LV) as a power supply into a pair of complementary first signals (IN1 and N_IN1); a precharge circuit (14c) that outputs, from a first node (N_OUT) and a second node (OUT), a pair of second signals (N_OUT and OUT) corresponding to the complementary first signals (IN1 and N_IN1); a precharge control circuit (16a) that outputs a pair of third signals (OUT0 and N_OUT0) and controls the precharge circuit (14) on the basis of the second signals (N_OUT and OUT); and so forth, wherein the input circuit (12a) has a first phase matching circuit (13a) that matches the phases of the complementary first signals (IN1 and N_IN1).
An artificial intelligence processing device includes: a substrate; an operation circuit such as a multiply-accumulate operation circuit, which includes a first variable-resistance nonvolatile storage element and a second variable-resistance nonvolatile storage element that are provided on the substrate and have a same structure and each of which holds conductance; and a write circuit that rewrites the conductance of the first variable-resistance nonvolatile storage element by applying a first voltage pulse having a first voltage to the first variable-resistance nonvolatile storage element, and rewrites the conductance of the second variable-resistance nonvolatile storage element by applying a second voltage pulse having a second voltage to the second variable-resistance nonvolatile storage element, the second voltage being different from the first voltage.
G11C 27/00 - Mémoires analogiques électriques, p. ex. pour emmagasiner des valeurs instantanées
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
This method for driving a semiconductor device (100) includes: a determination step (S10) for determining a lower limit for a target resistance value of a nonvolatile variable-resistance element (20); a measurement step (S11) for measuring the resistance value of the nonvolatile variable-resistance element (20); a determination step (S13) for determining whether the measured resistance value is lower than the lower limit for the target resistance value; and an application step (S21 and S23) for applying a second high-resistance voltage pulse that has a second energy greater than a first energy corresponding to application of a single cycle of a first high-resistance voltage pulse and imparts a positive potential to a second electrode (22) with reference to a first electrode (21), and a first low-resistance voltage pulse that continues after the second high-resistance voltage pulse, to the nonvolatile variable-resistance element (20) when it is determined that the measured resistance value is lower than the lower limit for the target resistance value.
A semiconductor memory device includes: a first pull-down n-channel MOS transistor that includes: a drain connected to a word line; a source connected to a ground line; and a gate connected to a first node; a first series connection n-channel MOS transistor that includes: a drain connected to a power supply line; and a source connected to the first node; and a second series connection n-channel MOS transistor that includes: a drain connected to the first node; and a source connected to the ground line. The inverse-logic signal of a signal to be input to the gate of the second series connection n-channel MOS transistor is input to the gate of the first series connection n-channel MOS transistor.
A bandgap reference circuit includes: a diode characteristic element group; a dynamic element matching circuit that repeats, within a predetermined period, an operation of selecting, from the diode characteristic element group, a first diode characteristic element group including M diode characteristic elements connected in parallel and a second diode characteristic element group including N (≥M) diode characteristic elements connected in parallel, while changing a combination of the diode characteristic elements to be selected; a reference voltage generation circuit that generates a reference voltage based on a difference between a current density of current passing through the first diode characteristic element group and a current density of current passing through the second diode characteristic element group; and a second-order temperature coefficient adjustment circuit that adjusts a second-order temperature coefficient of the reference voltage generated.
G05F 3/30 - Régulateurs utilisant la différence entre les tensions base-émetteur de deux transistors bipolaires fonctionnant à des densités de courant différentes
83.
Semiconductor device and method for manufacturing semiconductor device
A semiconductor device includes: a Si substrate; a back electrode provided below the Si substrate; a SiC layer provided above the Si substrate; a nitride semiconductor layer provided above the SiC layer; a source electrode and a drain electrode provided above the nitride semiconductor layer; a gate electrode in contact with the nitride semiconductor layer; an intermediate layer provided in an opening that creates an opening in the SiC layer and the nitride semiconductor layer; a metal layer provided above the opening so as to cover the intermediate layer; and a conductor that is provided inside a through via that penetrates the intermediate layer and the Si substrate and is electrically connected with the back electrode and the metal layer. The intermediate layer is a metal nitride layer or a silicon oxide layer.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
A semiconductor device includes a semiconductor layer. The entire length of an outer peripheral side among outer peripheral sides of a first gate electrode region and the entire length of an outer peripheral side among outer peripheral sides of a first resistance element region match a portion of an outer peripheral side, among outer peripheral sides of the semiconductor layer, that is orthogonal to a border line and has the shortest distance to a first gate pad. Among four corner portions of an outer periphery of the first gate electrode region, only one corner portion is included in the outer peripheral sides of the first resistance element region, the only one corner portion having the shortest distance to the border line and the shortest distance to an outer peripheral side, among the outer peripheral sides of the semiconductor layer, that is orthogonal to the border line.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
H10D 64/60 - Électrodes caractérisées par leurs matériaux
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
A solid-state imaging device (1) is provided with a sample-and-hold circuit (10). The sample-and-hold circuit (10) is provided with: a first capacitor (11); a second capacitor (12); a first buffer (21) having an output connected to an AD conversion circuit (90); a first input switch (31) disposed between a vertical signal line (80) and the first capacitor (11); a second input switch (32) disposed between the vertical signal line (80) and the second capacitor (12); a first output switch (41) disposed between the first capacitor (11) and the input of the first buffer (21); and a second output switch (42) disposed between the second capacitor (12) and the input of the first buffer (21). In a plan view, the first output switch (41) and the first buffer (21) are adjacent to each other, and the second output switch (42) and the first buffer (21) are adjacent to each other in the column direction of a pixel array (70).
A battery pack includes: an assembled battery in which power storage devices are connected; a current application line for applying current to the assembled battery; voltage detection lines for detecting voltages of the power storage devices; and a battery monitoring device that measures internal impedances of the power storage devices via the current application line and the voltage detection lines. Each of the power storage devices includes an electrode assembly in which a positive electrode plate and a negative electrode plate are alternately stacked, and an electrode plate on one principal surface of the electrode assembly and an electrode plate on the other principal surface of the electrode assembly have the same polarity, the direction of current that flows through the positive electrode plate is an opposite direction of the direction of current that flows through the negative electrode plate, and each of the power storage devices is stacked.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
H01M 50/129 - Boîtiers primairesFourreaux ou enveloppes caractérisés par le matériau ayant une structure en couches comprenant au moins trois couches dont au moins deux couches de matériaux organiques uniquement
H01M 50/548 - Bornes caractérisées par la position des terminaux sur les cellules sur des côtés opposés de la cellule
H01M 50/55 - Bornes caractérisées par la position des terminaux sur les cellules sur le même côté de la cellule
H05K 9/00 - Blindage d'appareils ou de composants contre les champs électriques ou magnétiques
This semiconductor laser element (1) emits laser light, the semiconductor laser element (1) comprising: a semiconductor laminate (1S) in which semiconductor layers are laminated; and a first metal layer (71) that is disposed above the semiconductor laminate (1S) and contains Ag. The semiconductor laminate (1S) has a first end surface (1F) and a second end surface (1R) that are positioned at ends in a direction perpendicular to the lamination direction and constitute a resonator in which laser light resonates, and a current injection region (Ri) that is a region, into which a current is injected, of the upper surface of the semiconductor laminate (1S). The first metal layer (71) is disposed above the region between the current injection region (Ri) and the first end surface (1F) of the semiconductor laminate (1S).
A semiconductor device (1) is a chip-sized square semiconductor device (1) in plan view, the semiconductor device (1) comprising a semiconductor layer (40), a vertical MOS transistor (10) formed in the semiconductor layer (40), and a Schottky barrier diode (20) in which the semiconductor layer (40) functions as an anode or a cathode. The semiconductor device (1) furthermore comprises, on the upper surface thereof, a first pad (51), a second pad (52), a third pad (53), and a fourth pad (54). In plan view of the semiconductor device (1), the center of the first pad (51) and the center of the third pad (53) are positioned on one diagonal line of the semiconductor device (1), the center of the second pad (52) and the center of the fourth pad (54) are positioned on the other diagonal line of the semiconductor device (1), and the first pad (51), the second pad (52), the third pad (53), and the fourth pad (54) are circular and have the same diameter.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
A re-timer (a signal processing device) includes: a receiver that receives a signal; a transmitter that transmits the signal received by the receiver; and a controller. The receiver includes an equalizer circuit that compensates attenuation of the signal received. The transmitter includes a noise cancelling circuit that reduces noise included in a processed signal generated in the receiver. The controller: detects a threshold voltage of a transistor included in the re-timer; when the threshold voltage detected is lower than or equal to a predetermined voltage value, sets a current of the equalizer circuit to be lower than or equal to a predetermined current value and deactivates the noise cancelling circuit; and when the threshold voltage detected is higher than the predetermined voltage value, sets the current of the equalizer circuit to be higher than the predetermined current value and activates the noise cancelling circuit.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A cable includes a first retimer, a second retimer, and a coaxial line. Each of the first retimer and the second retimer includes: a differential-to-single-ended signal converter that receives an input of a differential signal and outputs a single-ended signal; and a single-ended-to-differential signal converter that receives an input of a single-ended signal and outputs a differential signal. The first retimer and the second retimer are connected via the coaxial line.
A hydrogen detection device (10) comprises a first resistance element (hydrogen sensor (100)), a second resistance element (reference element (100a)), a third resistance element (reference element (100b)), and a fourth resistance element (reference element (100c)) that constitute a bridge circuit. Each of the first to fourth resistance elements is formed on one semiconductor substrate (102), and has: a first electrode (103) and a second electrode (106), the principal surfaces of which are disposed mutually opposing; a metal oxide layer (104) disposed in contact with the principal surface of the first electrode (103) and the principal surface of the second electrode (106); and an insulating film (107b), or the like, covering the second electrode (106). On at least the first resistance element among the first to fourth resistance elements, the insulating film (107b), or the like, is formed with an opening (110) that exposes another surface that opposes the principal surface of the second electrode (106) without being covered by the insulating film (107b) or the like.
G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
92.
HYDROGEN DETECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME
A hydrogen detection device includes a bridge circuit including: a hydrogen sensor that is a first resistive element; a resistor that is a second resistive element; a reference element that is a third resistive element; and a resistor that is a fourth resistive element, and at least the hydrogen sensor and the reference element are provided on a single semiconductor chip. The hydrogen sensor includes a first electrode, a second electrode, a metal oxide layer, an insulating film, or the like, and the insulating film includes an opening through which part of the second electrode is exposed. The reference element includes a first electrode, a second electrode, a metal oxide layer, an insulating film, or the like, and the insulating film includes no opening through which part of the second electrode is exposed.
G01N 27/04 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance
G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes
An optical sensor package (10) comprises a substrate (20), an optical sensor device (30) mounted on the substrate (20), a resin frame (40) provided on the substrate (20) so as to surround the outer periphery of the optical sensor device (30), and a transparent plate (70) provided on the resin frame (40) so as to cover the optical sensor device (30) via a space. A plurality of recessed regions (50) are provided in a frame top surface (41) of the resin frame (40). When viewed from a direction perpendicular to the substrate (20), the transparent plate (70) is disposed such that the outer side (73) of the transparent plate (70) is positioned inside the outer side (43) of the resin frame (40), and the maximum distance (D1) between the outer side (73) of the transparent plate (70) and the outer side (43) of the resin frame (40), which are adjacent to each other, is equal to or less than the maximum length (L1) of the recessed regions (50).
A fixed object detector includes: a capturing device; a fixed-object area information obtainer (a dirt area information obtainer) that searches for a fixed object candidate that is a candidate for a fixed object appearing in a video captured by the capturing device, and obtains a fixed-object area information item indicating coordinates of the fixed object candidate in the video, the fixed object having a fixed relative position with respect to the capturing device; a storage that stores therein the fixed-object area information item obtained; and an observer that determines that the coordinates indicated by the fixed-object area information item to be coordinates of the fixed object in the video and outputs a determination result, the coordinates indicated by the fixed-object area information item matching coordinates indicated by a past fixed-object area information item stored in the storage in past.
A semiconductor device includes a substrate, a back-barrier layer, a channel layer that has a band gap smaller than a band gap of the back-barrier layer, a first barrier layer that has a band gap larger than the band gap of the channel layer, a second barrier layer that is provided to fill a first recessed portion and has a band gap larger than the band gap of the channel layer, a source electrode, a drain electrode, and a gate electrode. An In composition ratio of the first barrier layer is greater than or equal to 0 and less than an In composition ratio of the second barrier layer. An Al composition ratio of the first barrier layer is greater than or equal to an Al composition ratio of the second barrier layer.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/60 - Électrodes caractérisées par leurs matériaux
A ranging device (100) comprises: a light source (10) that emits light in a prescribed range; a light reception unit (20) that has a plurality of pixels for receiving reflected light resulting from the emitted light being reflected within the prescribed range; an image recognition unit (30) that acquires an image in which at least a portion of the prescribed range appears, and that detects a preset recognition target object (OBJ) by subjecting the acquired image to image recognition; a drive control unit (40) that, if the recognition target object (OBJ) is detected by the image recognition unit (30), adjusts an emission condition of the emitted light to be emitted by the light source (10), on the basis of first outputs that are respectively output by one or more pixels corresponding to a region of the recognition target object (OBJ) on the basis of the reflected light of the emitted light emitted under a prescribed emission condition; and a distance calculation unit (50) that calculates the distance to the recognition target object (OBJ) on the basis of second outputs that are respectively output by the plurality of pixels on the basis of the reflected light of the emitted light emitted under the adjusted emission condition.
A semiconductor device (1) includes a vertical MOS transistor (10) having a semiconductor substrate (32) of a first conductivity type containing an impurity of a first concentration, and a low-concentration impurity layer (33) of the first conductivity type formed in contact with the semiconductor substrate (32) and containing an impurity of a second concentration lower than the first concentration. In a plan view, an active region (112) of the vertical MOS transistor (10) is formed of unit cells repeatedly arranged in the plane of the active region (112). The unit cell has a hexagonal shape with the outer periphery at the center position of the width of a gate trench (17). In the unit cell, a body contact region (18a) is exposed on the upper surface of the low-concentration impurity layer (33) in a shape of which the center coincides with the center of the unit cell and that has a rotational symmetry of 60[°] or less in the clockwise direction. When the width of the gate trench (17) is Lxr [μm] and the distance between gate trenches (17) facing each other in parallel is Lxm [μm], the relationship Lxm/3 ≤ Lxr ≤ Lxm is satisfied.
A DC-DC converter (1) for controlling DC output power by controlling the on and off of a high-side switch (11) is provided with a control unit (2) for adjusting the off-time of the high-side switch (11) in order to control output power. The control unit (2) makes the on-time of the high-side switch (11) inversely proportional to an input output voltage difference (Ei-Eo) which is the difference between an input voltage (E1) to the DC-DC converter (1) and an output voltage (Eo) from the DC-DC converter (1).
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
A semiconductor device for high-frequency amplification includes a substrate; a first nitride semiconductor layer above the substrate; a two-dimensional electron gas layer; a second nitride semiconductor layer; and a source electrode, a drain electrode, and a gate electrode spaced apart from each other above the first nitride semiconductor layer. In a plan view, an active region with a two-dimensional electron gas layer includes a high-electron-mobility transistor and the resistor provided above the second nitride semiconductor layer. In the plan view, a non-active region includes a drain terminal and a gate terminal connected to the drain electrode or the gate electrode; and a first resistor terminal and a second resistor terminal connected to the resistor.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
A nitride semiconductor light-emitting element includes an N-type cladding layer, an N-side guide layer, an active layer, a P-type cladding layer, and a P-side guide layer (an upper P-side guide layer) and an electron blocking layer that are disposed between the active layer and the P-type cladding layer. The N-type cladding layer, the N-side guide layer, the P-side guide layer, the electron blocking layer, and the P-type cladding layer contains Al. The active layer includes an N-side barrier layer, a well layer disposed above the N-side barrier layer, and a P-side barrier layer disposed above the well layer. The average band gap energy of the P-side barrier layer is greater than the average band gap energy of the N-side barrier layer. A thickness of the P-side barrier layer is less than a thickness of the N-side barrier layer.
H10H 20/825 - Matériaux des régions électroluminescentes comprenant uniquement des matériaux du groupe III-V, p. ex. GaP contenant de l’azote, p. ex. GaN
H10H 20/816 - Corps ayant des structures contrôlant le transport des charges, p. ex. couches semi-conductrices fortement dopées ou structures bloquant le courant
H10H 20/832 - Électrodes caractérisées par leurs matériaux
