A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
2.
INVERTER CONTROL DEVICE AND AN INVERTER CONTROL METHOD
In inverter control of a motor, an inverter control method is provided that increases system efficiency in all speed ranges from low speed to high speed based on system efficiency. Specifically, the inverter control method of switching between overmodulation control and rectangular wave control, especially in the medium to high-speed range is provided, with taking system efficiency into consideration.
An n-type source region and an n-type drain region ND1 are formed in a semiconductor substrate. A gate electrode is formed via a gate insulating film on a portion of the semiconductor substrate located between the source region and the drain region. A p-type impurity region is: formed in a portion of the semiconductor substrate located under the drain region, under the gate electrode, and under the source region. An impurity concentration of the impurity region is higher than an impurity concentration of the semiconductor substrate. The impurity region is spaced apart from an upper surface of the semiconductor substrate.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
A read assist circuit is configured so as to be capable of switching validation/invalidation, and lowers a word line voltage applied to a word line in order to secure a static noise margin of a memory cell when being valid. An SNM detection circuit has a replica memory cell configured so as to make data retention ability lower than that of memory cell. The SNM detection circuit detects the static noise margin of the memory cell in a pseudo manner by using the replica memory and cell, switches the validation/invalidation of the read assist circuit depending on a detection result.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
H10B 10/00 - Static random access memory [SRAM] devices
5.
SEMICONDUCTOR DEVICE, MOTOR CONTROL SYSTEMS AND MOTOR CONTROL METHODS
In a method where a controller controls a motor via a semiconductor device, reduce power consumption while ensuring control accuracy. In the semiconductor device, the remaining step number control circuit obtains the first remaining step number by subtracting the number of steps that could be processed for FB (feedback) signal generation between the first CTE (carrier period event) and the next second CTE from the first next step number at the time of the first CTE occurrence. The total step number control circuit obtains the second total step number by adding the second next step number and the first remaining step number at the time of the second CTE occurrence. The output circuit generates the FB signal based on the second total step number.
A second semiconductor chip is mounted on a second die pad, and a first semiconductor chip and a third semiconductor chip are mounted on a first die pad spaced apart from the second die pad in a Y direction. The third semiconductor chip includes a transformer and is adjacent to the first semiconductor chip in an X direction. In plan view, a third side of the third semiconductor chip faces a first side of the first semiconductor chip, and a fourth side of the third semiconductor chip opposite the third side faces the second side of the second semiconductor chip. The first semiconductor chip and the third semiconductor chip are electrically connected with each other via a plurality of first wires. The second semiconductor chip and the third semiconductor chip are electrically connected with each other via a plurality of second wires.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 23/00 - Details of semiconductor or other solid state devices
A method of manufacturing a semiconductor device according to the present disclosure includes: stacking a WSi layer and a TEOS layer on a surface of a P-type polysilicon layer formed on an SiC substrate; patterning the stacked WSi layer and TEOS layer so as to leave a second stacked region corresponding to an anode of the temperature detection diode; performing a first mask process so that, on a surface of the p-type polysilicon layer, a first region corresponding to a cathode of the temperature detection diode is exposed; implanting n-type ions into the first region; performing a second mask process so that, on the surface of the p-type polysilicon layer, a formation region of the temperature detection diode is masked; and performing etching on an exposed polysilicon layer.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
Control the period during which voltage is applied to the drain to provide a reservoir computer with low power consumption. A reservoir computer is provided, comprising an FeFET with a drain connected to a sense circuit that applies a drain voltage and detects the drain current by converting it from analog to digital. The gate electrode is connected to a gate voltage generation circuit that inputs a gate voltage in the form of a triangular wave with peaks of positive and negative voltages. Additionally, it includes a first switch positioned between the sense circuit and the drain. The gate voltage generation circuit comprises a charge pump circuit for applying positive voltage, a charge pump circuit for applying negative voltage, a pulse generation circuit, and a Vref regulator.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
9.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A position of an upper surface of a lead-out portion of a gate electrode is higher than an upper surface of an active portion of the gate electrode. An insulating film has a first raised portion positioned on a side surface of the active portion of the gate electrode via a sidewall spacer and a second raised portion positioned on a side surface of the lead-out portion of the gate electrode via the sidewall spacer. An active portion of a field plate electrode is in contact with the first raised portion, and a position of an uppermost portion of the lead-out portion of the field plate electrode is lower than a position of an uppermost portion of the insulating film positioned over the upper surface of the lead-out portion of the gate electrode.
A clamp element 46 applies a fixed potential to a bit line BL at a time of a readout operation. A reference current source RCS generates a reference current Iref. An offset current source OCS1 is activated at a time of a readout operation for an OTP cell OTPC, and at a time of being activated, generates an offset current Iof1 to be subtracted from a cell current Icel. At the time of the readout operation for the OTP cell OTPC, the sense amplifier SA detects a magnitude relationship between the reference current Iref and a readout current Ird obtained by subtracting the offset current Iof1 from the cell current Icel.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
A semiconductor device comprising an n-type epitaxial layer, a plurality of p-type column regions formed in the epitaxial layer so as to be spaced apart from each other in a plan view, and a gate electrode formed between each of the plurality of p-type column regions. The plurality of p-type column region is formed in the epitaxial layer and is composed of first, second and third sub-column regions, which are arranged in order from the side closer to a main surface of the epitaxial layer EP. Additionally, a distance between a position of a maximum impurity concentration of the first sub-column region and a position of a maximum impurity concentration of the second sub-column region is smaller than a distance between the position of the maximum impurity concentration of the second sub-column region and a position of a maximum impurity concentration of the third sub-column region.
Semiconductor devices, systems and methods are described. A semiconductor device can include a driver configured to output a gate current to drive a power module. The semiconductor device can further include a buffer configured to buffer a reference voltage that is less than a supply voltage being provided to the driver. The semiconductor device can further include a controller configured to determine a gate voltage of the power module is equivalent to the reference voltage. The controller can, in response to determination that the gate voltage is equivalent to the reference voltage, disable the driver to cause the driver to stop providing the gate current to the power module and enable the buffer to supply the reference voltage to the power module.
Semiconductor devices, systems and methods are described. A semiconductor device can include a driver configured to output a gate current to drive a power module. The semiconductor device can further include a buffer configured to buffer a reference voltage that is less than a supply voltage being provided to the driver. The semiconductor device can further include a controller configured to determine a gate voltage of the power module is equivalent to the reference voltage. The controller can, in response to determination that the gate voltage is equivalent to the reference voltage, disable the driver to cause the driver to stop providing the gate current to the power module and enable the buffer to supply the reference voltage to the power module.
A built-in resistor electrically connecting a trench gate electrode and a gate pad is formed of a conductive film formed on a semiconductor substrate via an insulating film. Here, a film thickness of the insulating film is larger than a film thickness of an insulating film in a trench and is smaller than an insulating film which is a field oxide film.
H10D 84/60 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of BJTs
H10D 1/47 - Resistors having no potential barriers
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
Provided is a wide band gap semiconductor device having high robustness against misalignment between gate electrodes (trenches) and a punch-through stopper layer. A technical concept is to configure the planar shape of the punch-through stopper layer from a pattern having periodicity in each of the X and Y directions constituting the plane, on the premise that the trenches extending in the Y direction out of the X direction and the Y direction constituting the plane are arranged at predetermined intervals in the X direction.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
16.
MANUFACTURING METHOD OF A SEMICONDUCTOR WAFER AND A SEMICONDUCTOR WAFER
A semiconductor device capable of controlling the warpage of a semiconductor wafer is provided. A semiconductor wafer is provided in which a first semiconductor chip with a first trench arranged in a first direction and a second semiconductor chip with a second trench arranged in a second direction different from the first direction are alternately arranged laterally. In the semiconductor wafer, it is possible that a first semiconductor chip with a first trench arranged in a first direction and a second semiconductor chip with a second trench arranged in a second direction different from the first direction are alternately arranged longitudinally.
A semiconductor device includes a central processing unit (CPU), a memory, a test data input terminal that receive test data, a test group identification terminal that receive a test group identification signal, a test data input control unit that receives the test group identification signal through the test group identification terminal and generates a memory write enable signal for allowing the test data to be written into the memory based on the test group identification signal, and a memory write control circuit that generates test data write address and selects the test data received through the test data input terminal based on the memory write enable signal to transfer the test data selected and the test data write address to the memory, whereby a test with the test data in the memory is executed.
An information processing device is provided that synchronizes the progress of data transferring unit with the timing of processing by calculation processing unit. The information processing device comprises an external bus connecting unit for connecting data transferring unit, a local memory, and a command list processing unit to the external memory, the data transferring unit for transferring data, which are conditions for calculation stored in the external memory, to the local memory, the local memory for storing data and a list of commands, the command list processing unit for generating commands that cause the calculation processing unit to execute calculations, by reading the list of commands from the local memory while data is being transferred from the external memory to the local memory, and the calculation processing unit for executing calculations and processing data.
A semiconductor device includes an offset drain region and a p-type well. In a gate length direction of a gate electrode, a first distance between the offset drain region and a first portion of the p-type well is larger than a second distance between the offset drain region and a second portion of the p-type well. The semiconductor device includes an n-type semiconductor region formed in a portion of an epitaxial layer located between the offset drain region and a source region.
A semiconductor device has an interlayer insulation film made of antiferroelectric. The minimum value of a relative dielectric constant of the interlayer insulation film is less than 2.
A semiconductor device is provided. The semiconductor devices is connected to a power device. The semiconductor device includes a gate driver unit with a first circuit and a second circuit, a resistor unit connecting the gate of the power device and the gate driver unit, and a first control circuit connected to the gate driver unit. The first control circuit is configured to increase the resistance of the power device by issuing an instruction to reduce the slew rate of the power device to the first circuit during the turn-off of the power device.
The current control circuit switches the cutting control transistor to the on state with respect to the AND circuit, passing a current of a first current value through the electrical fuse, and using the heat generated by passing the first current value through the electrical fuse to start melting the cutting region of the electrical fuse; the current detection circuit detects a second current value that is smaller than the first current value and greater than 0 amperes; the current detection circuit outputs a low current detection signal to the detection signal processing circuit based on detecting the second current value; the detection signal processing circuit outputs a control signal to the AND circuit based on the low current detection signal, and the AND circuit switches the cutting control transistor to the off state based on the control signal, performing the cutting of the electrical fuse.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 21/66 - Testing or measuring during manufacture or treatment
23.
SEMICONDUCTOR DEVICE, BOOT PROGRAM EXECUTION METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM
A semiconductor device 1 includes a CPU 11, a DMA controller 12, a first memory 13, and a second memory 14. The CPU 11 executes an initialization program in the first memory 13 to write an interrupt program and interrupt jump instructions into the second memory 14. The DMA controller 12 starts a DMA transfer process of a boot program to the second memory 14 by overwriting the interrupt jump instructions. The CPU 11 starts an execution process of the boot program after a predetermined time has elapsed since a start of the DMA transfer process. The CPU 11 executes the interrupt jump instruction when an instruction execution address reaches an address of a DMA untransferred area. The CPU 11 executes the interrupt program at a jump destination to delay the execution process of the boot program.
G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
24.
WIRING METHOD FOR SEMICONDUCTOR CIRCUIT DEVICE, WIRING PROGRAM AND WIRING PROCESSING DEVICE
A wiring method of the semiconductor circuit device includes arranging a plurality of shield wiring candidates such that the plurality of shield wiring candidates adjacent to each other are arranged apart by a space for a wiring track, arranging a shield target wiring on at least one of wiring tracks between the plurality of shield wiring candidates adjacent to each other, and removing a shield wiring candidate which do not contribute as shield wiring to the shield target wiring arranged.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
25.
SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGING AND INVERTER SYSTEMS
The semiconductor device includes first, second and third semiconductor chips. Through non-contact communication between different potentials in the third semiconductor chip, signal transmission and reception occur between the first and second semiconductor chips. The first semiconductor chip comprises a first semiconductor substrate and a first active element. The first semiconductor substrate has a first main surface. The first active element is formed on the first main surface. The second semiconductor chip comprises a second semiconductor substrate and a second active element. The second semiconductor substrate has a second main surface. The second active element is formed on the second main surface. The third semiconductor chip comprises a third semiconductor substrate and a passive element. The third semiconductor substrate has a third main surface. The passive element is formed above the third main surface. Each of the first, second and third semiconductor substrates is formed of monocrystalline silicon.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
26.
SEMICONDUCTOR TEST APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
To provide a semiconductor test apparatus capable of improving the conductivity between a probe pin and an external terminal of a semiconductor device while suppressing the breakage of the probe pin. The semiconductor test apparatus comprises a socket base, a probe guide, and the probe pin. The socket base has a first surface and a second surface opposite the first surface in a first direction. A first opening penetrating the socket base along the first direction is provided. The probe guide is movably disposed within the first opening along the first direction. The probe guide has a first end that protrudes from the first surface when moved from the second surface to the first surface along the first direction, and a second end opposite the first end. A second opening penetrating the probe guide along the first direction is provided.
A semiconductor device includes a semiconductor substrate including a single crystal layer, a plurality of semiconductor elements formed on the single crystal layer, and an isolation film which is formed in the semiconductor substrate so as to surround each of the plurality of semiconductor elements in plan view and isolates the plurality of semiconductor elements from one another. The isolation film is made of an antiferroelectric. A minimum value of a relative dielectric constant of the isolation film is less than 2.
A semiconductor device can enhance ranging accuracy while satisfying communication standards. The baseband circuit BBC, during transmission, divides the original pulse signal into multiple divided pulse signals so that each frequency bandwidth falls within the frequency bandwidth range specified by the UWB communication standard and overlaps a common frequency range, and sequentially transmits them to the receiving terminal via the analog front-end circuit AFE at a predetermined transmission interval. On the other hand, the baseband circuit BBC, during reception, inputs multiple divided pulse signals sequentially received with a predetermined time difference, corrects the time difference as if they were received simultaneously, and further corrects the phase of the multiple divided pulse signals to be continuous in the common frequency range. Then, the baseband circuit BBC restores the original pulse signal by synthesizing the corrected multiple divided pulse signals.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
29.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND PRODUCT HISTORY MANAGEMENT METHOD FOR SEMICONDUCTOR DEVICE
A technique that not only suppresses cost increase but also enables traceability of semiconductor devices with high accuracy is demanded. By mapping positions of crystal defects, position information of the crystal defects on a wafer map is stored in a memory device. In each of a plurality of chip areas, a metal film is formed in a wiring layer located above a semiconductor element. In each of the plurality of chip areas, a surface morphology image of a specific area of the metal film is acquired. The position information of the crystal defects on the wafer map, a wafer identification number, position information of the plurality of chip areas, position information of the specific area in the chip area, and the surface morphology image for each of the plurality of chip areas are linked and stored in a memory device.
According to one embodiment, the semiconductor device includes: a semiconductor module including a semiconductor chip having a first surface and a second surface; and a lattice-shaped fin close to the second surface side of the semiconductor chip. The lattice-shaped fin includes a first lattice-shaped body and a second lattice-shaped body, the first lattice-shaped body including a plurality of first bars each having a bar shape extending in a first direction, and being spaced from each other in an arrangement direction, thereby forming a plurality of first trenches between the adjacent first bars, and the second lattice-shaped body including a plurality of second bars each having a bar shape extending in a second direction, and being spaced from each other in the arrangement direction, thereby forming a plurality of second trenches between the adjacent second bars. The first lattice-shaped body and the second lattice-shaped body are stacked in a stack direction.
To provide a semiconductor device that can be miniaturized. The semiconductor device includes a power transistor H_PN, L_PN that supplies current to a load, a current detection circuit that detects the current flowing through the power transistor H_PN, L_PN, a first detection current H_DI1, L_DI1 based on the current detected by the current detection circuit, a device control circuit that controls the current flowing through the power transistor H_PN, L_PN based on an input signal Inp, an overrange comparison circuit that outputs an overrange signal H_OV, L_OV when the voltage of the power transistor H_PN, L_PN exceeds a predetermined voltage,, and an abnormal signal generation circuit that outputs an abnormal signal indicating an overcurrent state of the power transistor based on a second detection current H_DI2, L_DI2 detected by the current detection circuit and the overrange signal H_OV, L_OV.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
32.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND PRODUCT HISTORY MANAGEMENT METHOD FOR SEMICONDUCTOR DEVICE
The technique capable of preventing cost increase and performing traceability of a semiconductor device with higher accuracy is demanded. In each of a plurality of chip regions, a multilayer wiring layer having a plurality of metal films in the uppermost-layer wiring layer is formed. In each of the plurality of chip regions, a surface morphology image of a specific area of the metal films is obtained. A wafer identification number, positional information of each of the plurality of chip regions, positional information of the specific area of each of the chip regions, and the surface morphology image for each of the plurality of chip regions are associated with one another, and these pieces of information are stored in the storage device.
A semiconductor device includes a memory array. In a plan view, the memory array has a memory cell region arranged at a center portion and dummy cell regions arranged at an outer circumferential portion. In the dummy cell regions, a dummy cell connected to a word line is arranged, the dummy cell has a transistor whose gate terminal is connected to the word line and to whose drain terminal a ground voltage is supplied. At a time of performing a reading operation of the memory cell, the transistor is made in a conductive state so that the ground voltage is supplied to the source lines.
An improved cell balancing is provided. Estimating a charge state of each battery cell at each time point based on a voltage of each cell coupled in series, calculating an integrated value of a current flowing through multiple battery cells during a period between each time point, estimating a maximum capacity of each battery cell based on its charge state at each time point and the integrated value of the current, determining a reference battery cell based on the maximum capacity and charge state of each battery cell, and discharging a battery cell other than the reference battery cell.
A semiconductor device includes a semiconductor substrate, a barrier metal layer, and a contact plug. The semiconductor substrate includes a metal silicide region. A contact trench is provided in the semiconductor substrate. The barrier metal layer is formed within the contact trench. The contact plug is formed on the barrier metal layer. The metal silicide region is in contact with the barrier metal layer and includes a first metal silicide region, a second metal silicide region, and a third metal silicide region. A first thickness of the first metal silicide region is smaller than a second thickness of the second metal silicide region and is smaller than a third thickness of the third metal silicide region.
After grinding a back surface of a semiconductor substrate SB such that a thickness of a central portion of the semiconductor substrate is less than a thickness of a peripheral portion of the semiconductor substrate, a metal film including a film made of silver or copper is formed on the back surface of the semiconductor substrate. Thereafter, a dicing tape is adhered to the back surface of the semiconductor substrate via the metal film. A base material layer of the dicing tape is made of polyvinyl chloride. Also, after separating the peripheral portion from the central portion and the dicing tape, the semiconductor substrate adhered to the dicing tape is diced. Thereafter, the semiconductor substrate adhered to the dicing tape is transported.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
37.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A write driver writes one of binary data into an OTP memory cell using a boost voltage or a regulator voltage. An OTP voltage select register causes the write driver to select one of two voltages. The trimming registers hold voltage setting values defining magnitudes of two voltages, respectively. An OTP voltage trimming step is a step of sequentially changing the voltage setting values in a high voltage direction while writing is performed into a plurality of OTP memory cells one by one using one of the two voltage setting values as a trimming target, until writing with the same voltage setting value succeeds in succession writing with the same voltage setting value is successively successful in N OTP memory cells.
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 17/02 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards using magnetic or inductive elements
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/44 - Indication or identification of errors, e.g. for repair
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
38.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a trench formed in a first main surface of a semiconductor chip, in which the trench has a portion extending in a first direction and a portion extending in a second direction different from the first direction in a continuous manner in plan view. The trench has a portion extending in a third direction different from the first direction and the second direction, in which the portion extending in the third direction is located between the portion extending in the first direction and the portion extending in the second direction in plan view, the portion extending in the first direction intersects the portion extending in the third direction at an obtuse angle, and the portion extending in the second direction intersects the portion extending in the third direction at an obtuse angle.
H10D 64/00 - Electrodes of devices having potential barriers
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A design system is provided for enhancing the utilization rate of hardware accelerators during the execution of a video pipeline. The design system disclosed herein is for designing a video pipeline, which, based on a pipeline graph, job information related to multiple jobs included in the pipeline graph, hardware accelerator information related to multiple hardware accelerators included in the pipeline graph, and optimization conditions, creates a list of candidate combinations of the assignment of multiple jobs to multiple hardware accelerators, the execution order of multiple jobs, and the execution timing of each of the multiple jobs. It comprises an optimization unit that creates the list of candidate combinations and a result output unit that outputs the list of candidate combinations created by the optimization unit to the user.
A semiconductor device is provided, the semiconductor device comprises a first battery module and a second battery module connected in series, the first battery module comprising a first controlling portion controlling a first cell group where a plurality of battery cells are connected in series; and a controller communicating with a device driven when receiving a power supply from the first and second battery modules, the second battery module comprising a second controlling portion controlling a second cell group where a plurality of battery cells are connected in series; and a first measuring circuit measuring a difference in a consumed electrical amount between the first battery module and the second battery module, and discharge starts from the plurality of battery cells included in the second cell group, based on the difference in the consumed electrical amount measured by the first measuring circuit.
A semiconductor device includes a semiconductor substrate having a first surface where a source terminal and a gate electrode of a vertical transistor are formed, and a second surface where a drain terminal of the vertical transistor is formed; a bonding region formed on an upper surface of a region where the source terminal is formed on the first surface side, to which a bonding wire for supplying current to the source terminal is connected; and a plurality of recesses formed in a region on the second surface, at least including the region facing the first surface where the bonding region is formed. An extending direction of an outer peripheral side of an opening of the plurality of recesses is set in a direction mismatched with an extending direction of a side of an element pattern formed on the first surface.
A semiconductor device includes an application allocation judgement unit and an application allocation control unit. The application allocation judgement unit compares CPU usage rate data and CPU usage rate threshold pattern data, thereby predicting a state in which the CPU usage rate exceeds a threshold value and generating an application allocation change request. The application allocation control unit changes an allocation destination of an application allocated to the CPU predicting that the CPU usage rate exceeds the threshold value based on the application allocation change request.
A first region of a die pad of a semiconductor device includes: a third region having a surface facing a surface of a semiconductor chip via a die bond material; and a fourth region having a surface facing the surface of the semiconductor chip via a sealing body without interposing the die bond material between the die pad and the semiconductor chip. The die pad includes a convex portion provided in the third region and protruding from a flat surface including an upper surface of the die pad toward the semiconductor chip. The sealing body includes a plurality of filler particles. A part of the plurality of filler particles is interposed between the surface of the semiconductor chip and the upper surface, which is located in the fourth region, of the die pad.
A semiconductor device includes a controller that, in an element that connects a collector of an IGBT, a drain of a MOSFET, and a cathode of a diode and connects an emitter of the IGBT, a source of the MOSFET, and an anode of the diode, controls a first gate that is a gate of the IGBT and a second gate that is a gate of the MOSFET, in which the controller controls the first gate in a state where the second gate is turned on.
H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
H02M 7/537 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
45.
SIMULATION APPARATUS, SIMULATION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM
A simulation apparatus includes a loop instruction sequence detector and an instruction computing section. The loop instruction sequence detector detects a loop instruction sequence included in a target program and generates a loop instruction sequence detection signal. When the loop instruction sequence detection signal is generated, the instruction computing section executes the loop instruction sequence once and generates a simulation elapsed time required for executing the loop instruction sequence a predetermined number of times.
A RAM stores a compensation value table in which a torque compensation value of each of discrete rotation angles that are discrete rotation angles of a motor is registered. A processor performs a step (a) of extracting a vibration component based on speed difference between a speed command value and a value of a rotation speed of the motor, and of calculating and deriving an update amount of each of the discrete rotation angles required for suppressing the vibration component. The processor further performs a step (b) of updating the compensation value table based on the update amount of each of the discrete rotation angles. The processor further performs a step (c) of calculating and deriving the torque compensation value of each any rotation angle of the motor by use of the compensation value table and a completion function, and of reflecting it to a motor control signal.
H02P 21/05 - Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation specially adapted for damping motor oscillations, e.g. for reducing hunting
F25B 31/02 - Compressor arrangements of motor-compressor units
H02P 21/22 - Current control, e.g. using a current control loop
H02P 27/12 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation pulsing by guiding the flux vector, current vector or voltage vector on a circle or a closed curve, e.g. for direct torque control
47.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An n-type impurity region is formed in a semiconductor substrate. A p-type well region and an n-type collector region are formed in the impurity region. An n-type emitter region and a p-type base region are formed in the well region. When a distance from a first junction surface to a second junction surface is Wb1, an impurity concentration of a part of the well region located under the first junction surface is Na1, a distance from a third junction surface to the base region is Wb2, and an impurity concentration of a part of the well region located between the third junction surface and the base region is Na2, the relationship (Na1×Wb1)≤(Na2×Wb2) is satisfied.
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
A semiconductor device includes a semiconductor substrate, a first interlayer dielectric film formed over the semiconductor substrate, a first wiring formed on the first interlayer dielectric film, a second interlayer dielectric film formed on the first interlayer dielectric film and including a first layer covering the first wiring and a second layer formed on the first layer, a first resistive film formed on the first layer and covered by the second layer, a first via plug formed in the first layer and electrically connecting the first wiring and the first resistive film, and a second via plug formed in the second interlayer dielectric film and electrically connected to the first wiring. The first resistive film contains silicon.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
49.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF INSPECTING SEMICONDUCTOR DEVICE, AND INSPECTION DEVICE
A method of manufacturing a semiconductor device includes preparing a semiconductor device and an inspection device. In the preparing, the semiconductor device has a semiconductor element, a plurality of pads electrically connected to the semiconductor element, and a plurality of bumps arranged on each pad. The inspection device includes a probe card having a plurality of probes, a first holding portion detachably holding the semiconductor device, a cleaning substrate cleaning the probes, and a second holding portion detachably holding the cleaning substrate. The first and second holding portions are movable relatively to the probe card.
A method of manufacturing a semiconductor device according to the present disclosure includes: introducing an impurity having a first conductivity type from an upper surface of a semiconductor substrate having the upper surface and a lower surface; forming a metal layer on the upper surface; introducing hydrogen from the lower surface and forming a first semiconductor layer; performing first heat treatment on the semiconductor substrate, and donating the hydrogen introduced into the first semiconductor layer; introducing from the lower surface an impurity of a second conductivity type opposite to the first conductivity type, and forming a second semiconductor layer at a position shallower than a position of the first semiconductor layer; and performing second heat treatment on the semiconductor substrate at a temperature higher than a temperature of the first heat treatment, and applying the second conductivity type to the second semiconductor layer.
A semiconductor device includes a semiconductor substrate and a multilayer wiring layer disposed on the semiconductor substrate. The semiconductor substrate includes, in plan view, a coil region and a peripheral region surrounding the coil region. The multilayer wiring layer includes a first coil, a second coil, a third coil, a fourth coil, and a metal film. The first coil and the second coil are formed in a first wiring layer being one of the plurality of wiring layers disposed on the coil region. The third coil and the fourth coil are formed in a second wiring layer being another one of the plurality of wiring layers disposed on the coil region. The second wiring layer is disposed above the first wiring layer. The third coil and the fourth coil are disposed so as to face the first coil and the second coil, respectively.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
A method of manufacturing a semiconductor device capable of detecting occurrence of a Hi-K disappearance is provided. The method of manufacturing a semiconductor device includes a step of manufacturing a test pattern including a reference resistance, a gate leakage resistance through which a gate leakage current flows and connected in series with the reference resistance, and a step of measuring a change in voltage at a connection node between the reference resistance and the gate leakage resistance caused by the flow of the gate leakage current.
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
53.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor substrate; an interlayer insulating film; a first and a second electrode pads; and a first and a second plating films. The semiconductor substrate has a first main surface and a second main surface opposite to the first main surface. The semiconductor substrate serves as an n-type drain region. The semiconductor substrate includes: an n-type source region; a p-type channel region adjacent to a side of the source region, the side being closer to the first main surface, and pn-bonded to the source region and the drain region; and a p-type well region and pn-bonded to the drain region. The interlayer insulating film is formed on the second main surface. The first electrode pad and the second electrode pad are formed on the interlayer insulating film and are electrically connected to the source region and the well region, respectively.
A semiconductor device includes a first semiconductor chip, a die attach film, a second semiconductor chip, and a resin molding member. The first semiconductor chip is attached to the second semiconductor chip via the die attach film. The second semiconductor chip includes an analog circuit, a bonding pad, and one or more deformed bonding pads serving as alignment marks of the first semiconductor chip. In plan view, the analog circuit is located inside an outer peripheral edge of the die attach film. The resin molding member seals the first semiconductor chip, the second semiconductor chip, and the die attach film.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
55.
PROGRAM, IMAGE PROCESSING METHOD, AND IMAGE PROCESSING DEVICE
An image processing device according to an embodiment includes: an image division unit dividing input image data into first division image data and second division image data having a predetermined overlap region with the first division image data according to a size of a kernel used for image processing; a reuse data determination unit determining first reuse data reused in performing the image processing to the second division image data among the first division image data; and a memory management unit, in a memory, storing first processed data of a first division image obtained by performing the image processing to the first division image data, in a region other than a region storing the first reuse data, and allocates a region storing the second division image data so as to be adjacent to the region storing the first reuse data.
A semiconductor device is provided, which includes a boundary member between an auxiliary element and a main surface of a semiconductor substrate to reduce the step of a protective film covering the auxiliary element. A semiconductor device is provided, comprising a semiconductor substrate having a first main surface having a first region, a second region, and a third region located between the first region and the second region in plan view, a transistor formed in the first region, an auxiliary element formed in the second region, a boundary member formed in the third region, and a protective film covering the auxiliary element and the boundary member. The height from the first main surface to the upper surface of the boundary member is lower than the height from the first main surface to the upper surface of the auxiliary element.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A protection cell has a first MISFET group composed of a plurality of first MISFETs and a second MISFET group composed of a plurality of second MISFETs. The first MISFET group and the second MISFET group are provided separately from each other. The first MISFET group is electrically connected to a first power wiring group and a first ground wiring group so as to electrically short-circuit them. The second MISFET group is electrically connected to a second power wiring group and a first ground wiring group so as to electrically short-circuit them. The first MISFET group overlaps with a part of the first power wiring group and a part of the first ground wiring group in a plan view.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
H01L 23/528 - Layout of the interconnection structure
58.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device is provided, the semiconductor device including: a first electrode; an N-type semiconductor layer arranged on the first electrode; a P-type semiconductor layer arranged on the N-type semiconductor layer; a first insulating layer surrounding and partitioning a first region in plan view, arranged on the P-type semiconductor layer; a second electrode arranged on the P-type semiconductor layer; a second insulating layer arranged on the first insulating layer surrounding and partitioning the first region in plan view on the second electrode; a metal plating layer arranged on the second electrode; a solder layer arranged on the metal plating layer; and a clip arranged on the solder layer, and the first region is a region where the clip is joined with the metal plating layer.
A first stacked structure and a first sidewall spacer are formed in a first region. A second stacked structure including a metal film is formed in a second region. In the first region, an epitaxial layer is formed on a semiconductor layer. The first sidewall spacer is removed. A first silicon oxide film is formed on a surface of the epitaxial layer exposed from a first insulating film. A thickness of each of the first insulating film and the first silicon oxide film is reduced by performing a cleaning treatment using an aqueous solution containing ammonia and an activator on each of the first insulating film and the first silicon oxide film. An extension region is formed in each of the semiconductor layer and the epitaxial layer by performing an ion implantation so as to pass through each of the first insulating film and the first silicon oxide film.
A radar system comprising a plurality of receivers, each receiver having its clock generator generating a clock signal with a sampling frequency for sampling a radar signal received on one or more receiving antennas and a plurality of delay estimation and compensation (DEC) blocks implemented within the corresponding plurality of receivers, wherein, each DEC block is configured to synchronise the clock generator of one receiver with every other receiver. A method in a radar comprising, generating a sync pulse in a first receiver in the plurality of receives, measuring a delay between the sync pulse and the clock signal in the first receiver, transmitting the sync pulse to other receivers in the plurality of receivers measuring a second delay between the sync pulse and the clock pulse in the other receivers and changing the frequency of the clock generator in the other receivers from the sampling frequency to first frequency for a first time duration.
A regulator includes a reference potential generation circuit that generates a reference potential serving as a reference for an intermediate potential and an intermediate potential lower than the intermediate potential, a differential amplifier to which the intermediate potential is supplied as a low potential side power supply and which amplifies a difference voltage between a feedback potential corresponding to the intermediate potential and the reference potential, and a transistor having a gate to which the amplified difference voltage is input, a drain connected to a ground potential via a constant current source or a resistor, and a source that generates the intermediate potential.
G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
62.
METHOD OF TRANSPORTING SEMICONDUCTOR DEVICE AND CARRIER TAPE
A method of transporting a semiconductor device includes: a step of placing a semiconductor device in a pocket portion, a step of attaching the cover tape to the carrier tape so as to cover the semiconductor device placed in the pocket portion, and a step of transporting the carrier tape containing the semiconductor device. Here, the pocket portion includes: a plurality of corner portions where a step section is formed, and a plurality of side portions located between these corner portions and having a first protruding portion and a second protruding portion formed thereon. Also, a width of a tip portion of the second protruding portion is smaller than a width of the tip portion of the first protruding portion. Furthermore, a protrusion amount of the second protruding portion from the side portion is larger than a protrusion amount of the first protruding portion from the side portion.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A communication device includes a communication control unit. The communication control unit includes a plurality of protocol processing units and a plurality of received data storage areas. A received message that is a CAN message received by the communication device is input into the plurality of protocol processing units. In a case where the destination of the received message is a virtual machine corresponding to the protocol processing unit itself, each protocol processing unit stores the payload of the received message in the received data storage area accessible from the destination virtual machine.
A semiconductor device includes a first resistor element. The first resistor element includes a first resistor, and a second resistor electrically connected in series to the first resistor. The first resistor and the second resistor are each made of a first material. One of a temperature coefficient of an electrical resistance value of the first resistor and a temperature coefficient of an electrical resistance value of the second resistor is a positive value. The other of the temperature coefficient of the electrical resistance value of the first resistor and the temperature coefficient of the electrical resistance value of the second resistor is a negative value.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/373 - Cooling facilitated by selection of materials for the device
A semiconductor device includes a variable-resistance memory cell array, a sense amplifier electrically connected to the variable-resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplification unit that amplifies a voltage at a sense node, a first clamp circuit having first and second NMOS transistors whose gate terminals are electrically connected, a second clamp circuit having third and fourth NMOS transistors whose gate terminals are electrically connected, a fifth NMOS transistor electrically connected to the variable-resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.
A semiconductor device includes a variable-resistance memory cell array, a sense amplifier electrically connected to the variable-resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplification unit that amplifies a voltage at a sense node, a first clamp circuit having first and second NMOS transistors whose gate terminals are electrically connected, a second clamp circuit having third and fourth NMOS transistors whose gate terminals are electrically connected, a fifth NMOS transistor electrically connected to the variable-resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.
The first and third NMOS transistors are connected in series between the sense node and the fifth NMOS transistor, and the second and fourth NMOS transistors are connected in series between the sense node and the sixth NMOS transistor.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
A semiconductor device includes: a first electric-current generator circuit generating a first electric current having a positive temperature coefficient and not having dependency on a first power-supply voltage; a second electric-current generator circuit generating a second electric current having a negative temperature coefficient and not having dependency on the first power-supply voltage; and a third electric-current generator circuit generating a third electric current neither having dependency on the temperature nor the first power-supply voltage, based on the first electric current and the second electric current.
A data transfer device that divides and transfers the transfer target data in a burst manner from a transmission-side device to a reception-side device includes a storage device and a control device that controls the storage device to store one piece of the input transfer target data, controls the storage device so that data transfer is performed at a set burst length as a data length of divided data when the one piece of the data is divided by a division number until a last part of the data is sensed, and when the last part of the data is sensed, controls the storage device to adjust the burst length so that a data length of the data coincides with a total of data lengths of data to be transferred, and to transfer the data at the adjusted burst length.
Improve the reliability of semiconductor device. The protective cell ESD1a comprises a group of MISFETS 1QA constituted by a plurality of n-type MISFETs 1Q, and a pair of MISFET groups 2QA constituted by a plurality of p-type MISFETs 2Q. The group of MISFETs 1QA and the pair of MISFET groups 2QA are electrically connected to the power wiring and the ground wiring, respectively, to electrically short-circuit them. The pair of MISFET groups 2QA outputs a signal to turn on a plurality of MISFETs 10 to each gate electrode of the plurality of MISFETs 1Q. The group of MISFETs 1QA is provided between the pair of MISFET groups 2QA.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A resist pattern having an opening portion that exposes a part of a conductive film located on a gate insulating film is formed on the conductive film. Next, an anisotropic etching treatment is performed using the resist pattern as a mask to selectively remove the conductive film exposed from the resist pattern and to form a gate pattern and a dummy gate pattern from the remaining conductive film. Next, an oblique ion implantation is performed using the resist pattern as a mask to form a p-type body region in a semiconductor substrate.
The method for transporting the semiconductor wafer involves the steps of preparing the non-contact chuck provided with an optical sensor and the semiconductor wafer having a first main surface, positioning the non-contact chuck so that the optical sensor and the first main surface face each other with a predetermined interval therebetween, measuring a first intensity, which is the intensity of a reflected light from the first main surface, by illuminating the first main surface with a light from the optical sensor before bringing the non-contact chuck close to the first main surface, bringing the non-contact chuck close to the first main surface and maintaining the semiconductor wafer in a non-contact state by blowing gas to the first main surface from the non-contact chuck, and disengaging the non-contact chuck from the semiconductor wafer by moving the non-contact chuck away from the first main surface.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A debugging system includes first and second semiconductor devices and a log analysis apparatus. Each of the first and second semiconductor devices executes software to generate a trace log, a first execution log, and a second execution log. The first semiconductor device transfers the trace log and the first execution log to the log analysis apparatus. The second semiconductor device transfers the trace log and the second execution log to the log analysis apparatus. The log analysis apparatus identifies the processing order of the first execution log and the second execution log based on time stamps given to the trace logs, the first execution log, and the second execution log transferred from the first and second semiconductor devices, and generates analysis data by combining the first and second execution logs according to the identified processing order. The analysis data is used for analyzing a cause of an error.
A semiconductor device includes: a field plate electrode formed in an inner portion of a trench through a first insulating film, the trench being formed in a semiconductor substrate; and a gate electrode formed over the field plate electrode through a second insulating film. The first insulating film includes a stacked film made of a first oxide film in contact with the semiconductor substrate and a second oxide film in contact with the field plate electrode, and an inclination of an upper surface of the first insulating film changes at a boundary between the first oxide film and the second oxide film.
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
73.
SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SEMICONDUCTOR DEVICE, AND PROGRAM
A Semiconductor device capable of performing efficient signal processing, to provide a control method and a program of the semiconductor device. The semiconductor device includes a first signal processing unit, a second signal processing unit, and a control unit. The control unit includes: a detection unit that detects the process amount of the second process in which the first signal processing unit or the second signal processing unit executes; a prediction unit that predicts the process amount of the second process to be executed next based on the process amount of the detected second process; and a distribution unit that distributes the first process to the first signal processing unit and the second signal processing unit according to the process amount of the predicted second process.
A semiconductor device includes, in a gate finger region, a gate potential trench formed on a main surface side of a semiconductor substrate, predetermined potential trenches formed so as to sandwich the gate potential trench on the main surface side of the semiconductor substrate, a drift region of a first conductivity type formed in a first region between the gate potential trench and the predetermined potential trench, and a well region of a second conductivity type, which is a region above the drift region and formed in a second region on a side of the predetermined potential trench opposite to a side where the gate potential trench is located.
The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Enhancing the performance of semiconductor devices by reducing the operating voltage of a ferroelectric memory equipped with a ferroelectric film. On a semiconductor substrate, forming a laminated body including a paraelectric film, which is an insulating film, and the ferroelectric film made of three or more layers of ferroelectric layers to on the insulating film, and forming a metal film and a gate electrode on the ferroelectric film. By discretely placing impurity particles between the ferroelectric layers that are in contact with each other, the crystallinity of the ferroelectric film is enhanced.
A plurality of wirings included in a wiring substrate includes: a plurality of first wirings for propagating a first clock signal and a first chip select signal to first and second memory devices mounted on a front surface; and a plurality of second wirings for propagating a second clock signal and a second chip select signal to third and fourth memory devices mounted on a back surface. The plurality of first wirings is provided in a wiring layer, which is closer to the front surface, of a plurality of wiring layers, and the plurality of second wirings is provided in a wiring layer, which is closer to the back surface, of the wiring layers.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
78.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a ferroelectric memory cell, and the ferroelectric memory cell includes a select transistor and a memory transistor. A gate dielectric film of the select transistor includes a ferroelectric film, and a gate dielectric film of the memory transistor includes a ferroelectric film.
A semiconductor device has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type differing from the first conductivity type in the first semiconductor layer; a third semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the second semiconductor layer; a fourth semiconductor layer of the first conductivity type on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type on the fourth semiconductor layer and having a higher impurity concentration than the fourth semiconductor layer; a sixth semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the third semiconductor layer; and a seventh semiconductor layer of the second conductivity type having the same impurity concentration distribution as the third semiconductor layer in a depth direction.
H01L 27/07 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
According to one embodiment, a semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a first conductive layer formed above the semiconductor substrate; and a second conductive layer formed on the upper surface of the first conductive layer, in which, when viewed from above, the second conductive layer is formed in a region inside an end edge of the first conductive layer, the thickness of the second conductive layer is larger than the thickness of the first conductive layer, the thermal conductivity of the second conductive layer is larger than the thermal conductivity of the first conductive layer, and the resistivity of the second conductive layer is smaller than the resistivity of the first conductive layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
A semiconductor device includes a semiconductor substrate, a first semiconductor region formed in the semiconductor substrate, a second semiconductor region surrounding the first semiconductor region in plan view, a first conductive layer formed on the first semiconductor region, a first electrode formed on the first conductive layer, a cathode region connected to the first electrode via the first conductive layer, a second conductive layer in contact with the first semiconductor region, a second electrode formed on the second conductive layer, and a first region disposed between a region in contact with the first conductive layer of the first semiconductor region and the cathode region in a direction along the upper surface of the semiconductor substrate, and the first region is in contact with a lower surface of the second conductive layer. A depth of the first region is greater than a depth of the cathode region.
On a lower layer side of a temperature sensing diode, trenches are periodically formed in a semiconductor substrate. A source field plate is arranged in the trenches via an insulating film. A P type diffusion layer is formed between adjacent trenches. The source field plate and the P type diffusion layer are connected to a source potential.
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
A semiconductor device includes a processor including a first register set and a second register set. In a first period, the processor selects the second register set as an active register set, and executes a first virtual machine by use of second context data. In a second period, the processor selects the first register set as the active register set, and executes a hypervisor by use of first context data. In the second period, the processor performs a processing of saving the second context data and a processing of reading third context data. In a third period, the processor selects the second register set as the active register set, and executes a second virtual machine by use of the third context data.
A semiconductor device with high performance is provided. A semiconductor device according to the present disclosure includes a semiconductor substrate having a plurality of trenches provided along a first direction, a field plate electrode having a plurality of recess portions and a plurality of thinning-out portions which are alternately disposed in the first direction, and being provided in the trench, an oxide film provided on the field plate electrode, and a gate electrode formed on the oxide film and disposed in each of the recess portions. In the adjacent trenches, the gate electrodes are disposed to be shifted in the first direction.
A semiconductor device includes a first terminal, an oscillation circuit that generates a first clock signal and a second clock signal, an AD conversion circuit, a correction circuit that corrects the digital signal obtained by the AD conversion circuit based on a correction data stored in a memory circuit and outputs the digital signal, an averaging circuit, a sampling circuit, a current generation circuit, and a superposition circuit, the correction data is generated based on an output of the sampling circuit when a dispersion current is superposed on a detection current, and is stored in the memory circuit.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
86.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor chip having a source electrode pad and mounted on a die pad via a die bonding material; a wire electrically connected with the source electrode pad of the semiconductor chip; and a sealing body sealing the semiconductor chip and the wire. The wire and the source electrode pad are made of different types of metals to each other. A wire bonding layer made of sintered metal is interposed between the source electrode pad and the wire. The wire is electrically connected with the source electrode pad via the wire bonding layer.
An interrupt reception unit receives an interrupt request. In response to a received interrupt request, an interrupt processing unit performs an interrupt process of a first priority or an interrupt process of a second priority having a lower priority than the first priority. An interrupt suppression control unit controls the number of interrupt processes of the second priority processed by the interrupt processing unit in a cycle time according to a suppression condition. The suppression condition is set on the basis of a cycle in which the interrupt process of the second priority occurs and the total number of the interrupt processes of the second priority occurring within a period corresponding to the cycle.
Since an electrode formed on an insulating film may be separated from the insulating film in a semiconductor device, the present invention makes it possible to prevent the separation of the electrode from the insulating film. A semiconductor device includes a semiconductor substrate, an insulating film, and an electrode. The insulating film is formed on the semiconductor substrate. The electrode is formed on the insulating film. The semiconductor device also includes an anchor member. The anchor member is in contact with the insulating film and the electrode, at an outer peripheral portion of the electrode.
A semiconductor device includes a semiconductor substrate, a first semiconductor region formed in the semiconductor substrate, a buried region formed in the semiconductor substrate, a second semiconductor region disposed over the buried region, a third semiconductor region disposed over the buried region, a drain region formed in the second semiconductor region, a source region formed in the third semiconductor region, and a gate electrode layer formed on an upper surface of the semiconductor substrate. The first semiconductor region includes a first region formed between the third semiconductor region and the buried region, and a second region formed between the second semiconductor region and the buried region. The semiconductor substrate, the first semiconductor region, and the second semiconductor region each have a first conductivity type. The buried region and the third semiconductor region each have a second conductivity type opposite the first conductivity type.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device including: a semiconductor chip mounted on a wiring substrate such that a main surface of the semiconductor chip faces a front surface of an insulating film of the wiring substrate; and a bump electrically connecting a land and an electrode pad. Here, in cross-sectional view, a center of the land is shifted in a direction from a center of an opening portion, which exposes a part of the land, of the insulating film toward a center of the semiconductor chip is provided.
A semiconductor device includes three types of cells as a plurality of logic gates. A first cell includes a p-type MOSFET having a first threshold voltage and an n-type MOSFET having a second threshold voltage. A second cell includes a p-type MOSFET having a third threshold voltage and an n-type MOSFET having a fourth threshold voltage. A third cell includes a p-type MOSFET having the third threshold voltage and an n-type MOSFET having the second threshold voltage. An absolute value of the first threshold voltage is higher than an absolute value of the third threshold voltage, and an absolute value of the second threshold voltage is higher than an absolute value of the fourth threshold voltage.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
92.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A pad is formed on an interlayer insulating film, and an insulating film is formed to cover the interlayer insulating film and the pad. An opening is formed in the insulating film to expose a part of the pad. In the opening, a nickel plating film is formed on the pad, a first gold plating film is formed on the nickel plating film, and a second gold plating film is formed on the first gold plating film. A phosphorus concentration of the nickel plating film is 2% by mass or more and 7% by mass or less.
H01L 23/00 - Details of semiconductor or other solid state devices
C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
C23C 18/32 - Coating with one of iron, cobalt or nickelCoating with mixtures of phosphorus or boron with one of these metals
C23C 18/44 - Coating with noble metals using reducing agents
A semiconductor device includes fuse circuits, and each of the fuse circuits includes fuse elements and cutting transistors. The fuse elements and the cutting transistors are arranged in a first direction of a first main surface of a semiconductor substrate, respectively, and each of the fuse elements is surrounded by each of deep trench isolation parts in plan view. In plan view, each of the cutting transistors is surrounded by each of power supply parts, and the power supply parts are integrally surrounded by the deep trench isolation part. The cutting transistors are formed in a well region, and each of the power supply parts has the same conductivity type as the well region and is formed in the well region.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
94.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An n-type drift region and a p-type well region are formed in a semiconductor substrate. An n-type first drain region and an n-type second drain region are formed in the n-type drift region, and an n-type source region and an n-type semiconductor region are formed in the p-type well region. An impurity concentration of the n-type semiconductor region is lower than an impurity concentration of the n-type source region. A gate electrode includes an n-type first gate electrode portion and an n-type second gate electrode portion extending in the Y direction, and a p-type gate connection portion connecting the first gate electrode portion and the second gate electrode portion. In plan view, the n-type source region is arranged between the first gate electrode portion and the second gate electrode portion.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a CPU configured to execute an instruction, a first register configured to store an address of the instruction currently being executed, a second register configured to store a return address when a function branch occurs, and a generation circuit configured to generate and output function branch information indicating an address of a function branch destination when the function branch occurs. The generation circuit is configured to determine whether or not the function branch has occurred based on values of the first register and the second register before and after instruction execution by the CPU, and, when determining that the function branch has occurred, output the value of the first register after the instruction execution by the CPU as the function branch information.
A semiconductor device includes an insulating film, and a polysilicon film formed on the insulating film. The semiconductor device includes, in plan view, a first region including a first semiconductor element formed of the polysilicon film, and a second region including a second semiconductor element. A first contact hole formed in the first region extends through the polysilicon film. An ohmic contact is formed between a metal embedded in the first contact hole and the polysilicon film on a side surface of the first contact hole.
A non-transitory computer readable medium stores a program for causing a co-simulation apparatus including a first simulator, a second simulator, a first communication path, and a second communication path to execute a co-simulation method. The first simulator stores first data in a first shared memory via the first communication path. In addition, the first simulator divides information related to a first address of the first shared memory in which the first data is stored into pieces of a size defined by an FMI standard, and transmits the pieces of information to the second simulator via the second communication path. The second simulator reads the first data stored in the shared memory by using the first address via the first communication path.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
A semiconductor device includes a dummy field structure in a non-element forming region. The dummy field structure includes a deep n-type well, an n-type well, a trench, a conductor layer, a first n-type semiconductor region, a second n-type semiconductor region, and a third n-type semiconductor region. The semiconductor device includes not only a first parasitic bipolar transistor but also a second parasitic bipolar transistor.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
An IGBT includes a first trench gate electrode extending in a first width direction, and a second trench gate electrode facing the first trench gate electrode. A first position range in the first width direction of a first channel region formed by the first trench gate electrode and a second position range in the first width direction of a second channel region formed by the second trench gate electrode differ from each other.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
100.
BATTERY MANAGEMENT SYSTEM, BATTERY MANAGEMENT METHOD, AND PROGRAM
The battery management system includes a first communication connection checking unit, a second communication connection checking unit, and an estimating unit. The first communication connection checking unit checks the communication state of the first communication connection that connects the microcontroller and the battery managing unit that obtains the cell voltage and the pack temperature. The second communication connection checking unit checks the communication state of the second communication connection that connects the microcontroller and the measuring unit that measures the pack voltage and pack current. The estimating unit estimates the charge/discharge information for controlling the charge/discharge of the battery based on the information that the microcontroller MC1 can be obtained, in accordance with the communication state of the first communication connection and the second communication connection.
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
