According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
According to one embodiment, a semiconductor device includes: a first well region of N-type and a second well region of P-type; a PMOS transistor provided in the first well region; and an NMOS transistor provided in the second well region. The PMOS transistor includes a first gate insulating layer and a first gate electrode. The NMOS transistor includes a second gate insulating layer and a second gate electrode. The first gate electrode includes a first semiconductor layer of P-type, a first insulating layer, and a first conductive layer. The second gate electrode includes a second semiconductor layer of N-type, a second insulating layer, and a second conductive layer. A film thickness of the first insulating layer is thicker than a film thickness of the second insulating layer.
H01L 23/528 - Layout of the interconnection structure
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
A memory system has a nonvolatile memory which comprises memory cells capable of storing 4-bit data of first to fourth bits by sixteen threshold regions including a first threshold region corresponding to an erased state and second to sixteenth threshold regions having higher voltage levels than a voltage level of the first threshold region corresponding to a written state; and a controller which causes the nonvolatile memory to execute a first program for writing data of the first bit and the second bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit and the fourth bit. The controller controls such that the threshold region is any threshold region of a seventeenth threshold region corresponding to an erased state and eighteenth to twentieth threshold regions having higher voltage levels than that of the seventeenth threshold region corresponding to a written state.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/26 - Sensing or reading circuitsData output circuits
H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
A semiconductor memory device comprising: circuitry configured to perform control to cause a channel of a first memory string including a first memory cell and a second memory cell connected in series to be in a floating state in which the channel is electrically insulated from a first bit line connected to a first end of the first memory string and a source line connected to a second end of the first memory string while applying a write voltage to a first word line connected to a gate of the first memory cell; and decrease a voltage of a second word line connected to a gate of the second memory cell from a first voltage that is less than the write voltage to a second voltage that is less than the first voltage after placing the channel of the first memory string into the floating state.
A semiconductor memory device according to an embodiment includes: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one; and a plurality of first plate-like portions that penetrate the stacked body in a stacking direction thereof and cross the stacked body in a first direction intersecting the stacking direction, the plurality of first plate-like portions being arranged along the first direction with a gap therebetween.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
According to an embodiment, a semiconductor memory devices includes a first memory string, a bit line, a source line, first and select gate lines, first to third word lines, and a control circuit. The first memory string includes a first selection transistor, first to third memory cells, and a second selection transistor. In a case where data is written to the first memory cell, the control circuit is configured to apply a first voltage to the bit line BL, apply a second voltage to the source line, apply a third voltage to the first select gate line, apply a fourth voltage to the second select gate line, apply a program voltage to the first word line, apply a fifth voltage to the second word line, and apply a sixth voltage to the third word line.
A memory system includes a nonvolatile memory including a plurality of blocks, and a controller. The controller manages a plurality of streams and allocates a first erased block for which a data erase operation has been completed among the plurality of blocks as a general-purpose block. In a case where use of a first stream among the plurality of streams is started, if two or more erased blocks for which the data erase operation has been completed are included in the plurality of blocks, the controller allocates a second erased block as the write destination block corresponding to the first stream, and if two or more erased blocks for which the data erase operation has been completed are not included in the plurality of blocks, sets the first erased block as the write destination block.
A semiconductor device comprises a control wiring connected to a gate of a first transistor, a second transistor including a first terminal and a second terminal, and a first gate having the control wiring, wherein the first terminal has a first voltage input thereto, wherein the first voltage is provided to turn on the first transistor, a third transistor including a third terminal and a fourth terminal, and a second gate, wherein the third terminal is connected to the second terminal, the fourth terminal controls a voltage of the control wiring, a fourth transistor including a fifth terminal and a sixth terminal, and a third gate, wherein the fourth transistor is turned on by a second control signal, and a capacitor configured to boost, by capacitive coupling, a second voltage output from the fourth terminal in a state in which the first transistor and the second transistor are turned on.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
10.
SEMICONDUCTOR DEVICE, METHOD FOR DESIGNING THE SAME, AND METHOD FOR MANUFACTURING THE SAME
According to an embodiment, a semiconductor device includes a first cell. The first cell includes, a first PMOS transistor, a second PMOS transistor arranged side by side with the first PMOS transistor, a first NMOS transistor, a second NMOS transistor arranged side by side with the first NMOS transistor, and a seventh interconnect not electrically coupled to the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A template according to the present embodiment includes a substrate, a light transmissive film, and a plurality of convex parts. The substrate has a first surface. The light transmissive film is provided on the first surface, has a second surface on a side opposite to the substrate, and has a composition different from the composition of the substrate. The plurality of convex parts are provided on the second surface and have different heights.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
A semiconductor storage device according to one embodiment includes a multi-layered body and a columnar body. The multi-layered body includes a plurality of gate electrode layers and a plurality of insulating layers.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A semiconductor storage device according to one embodiment includes a housing having a housing space, a board disposed in the housing space and having a first surface, and a semiconductor memory provided on the first surface.
According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A semiconductor storage device includes first and second stacks, and first to fourth semiconductor layers. The first stack includes first conductive layers and first insulating layers alternately stacked in a first direction. The first semiconductor layer extends through the first stack. The second semiconductor layer extends in a second direction above the first stack and connected to the first semiconductor layer. The second stack includes second conductive layers and second insulating layers alternately stacked in the first direction. The first and second stacks are arranged in a third direction. The third semiconductor layer extends through the second stack. The fourth semiconductor layer extends in the second direction above the second stack and connected to the third semiconductor layer. A third conductive layer is in contact with upper surfaces of the second and fourth semiconductor layers. The second and fourth semiconductor layers are separated from each other in the third direction.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A semiconductor storage device includes a first stacked region, a second stacked region, and a connection region arranged between the first and second stacked regions. In the connection region, one of a plurality of conductor layers in an upper stepped portion is connected to one of the plurality of conductor layers in the first stacked region via one of the plurality of conductor layers in a bridge portion.
H01L 23/528 - Layout of the interconnection structure
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality ofA memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.
According to one embodiment, a semiconductor device includes a substrate; a semiconductor chip provided on the substrate; a resin covering the semiconductor chip; and a metal film provided on the resin. The metal film includes a first metal layer provided on the resin, a second metal layer provided on the first metal layer, and a third metal layer provided on the second metal layer. The first metal layer and the second metal layer contain a same material, and a particle diameter of the second metal layer is smaller than a particle diameter of the first metal layer.
A device includes first-lines located in a first direction of a first insulator. The first lines are arrayed in a second direction and extend in a third direction. Second insulators are located on the first-lines, respectively. The width of each of the second insulators in the second direction in a face in contact with a corresponding first-line is smaller than the width of the corresponding first-line. Third insulators are located correspondingly on the first-lines, respectively, and each coat both side surfaces of an associated one of the second insulators. A fourth insulator is located on the third insulators. A fifth insulator is located on the fourth insulator. A first contact penetrates through the second to fifth insulators to be connected to the first-lines. A second line is located on the first contact. The first contact, or the second and fourth insulators are located in the first direction of the first-lines.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/528 - Layout of the interconnection structure
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
20.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In one embodiment, a semiconductor device includes a lower insulator, and a plurality of lower pads provided in the lower insulator. The device further includes an upper insulator provided on the lower insulator, and a plurality of upper pads provided on the plurality of lower pads in the upper insulator. Furthermore, a second pad that is included in the plurality of upper pads is disposed on a first pad that is included in the plurality of lower pads, and a structure of the second pad is different from a structure of the first pad.
H01L 23/00 - Details of semiconductor or other solid state devices
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
According to an embodiment, a semiconductor memory device includes a first chip which includes first and second memory cells, a second chip which includes third and fourth memory cells, and a third chip which includes a row decoder. In a first program operation of the first memory cell, the row decoder applies a first program voltage to the first word line. In a first program operation of the second memory cell, the row decoder applies a second program voltage higher than the first program voltage to the first word line. In a first program operation of the third memory cell, the row decoder applies a third program voltage to the first word line. In a first program operation of the fourth memory cell, the row decoder applies a fourth program voltage higher than the third program voltage to the first word line.
According to an embodiment, a semiconductor memory device includes a first chip, a second chip, and third chip. The first chip includes a first pillar including a first memory cell and a second memory cell coupled in series. The second chip includes a second pillar including a third memory cell and a fourth memory cell coupled in series. The third chip includes a row decoder to which a first word line, a second word line, and a third word line are coupled. The first word line is coupled to a gate of the first memory cell. The second word line is coupled to a gate of the third memory cell. The third word line is coupled to gates of the second memory cell and the fourth memory cell.
A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
In one embodiment, a semiconductor device includes a substrate, one or more first substrate pads provided on the substrate, and one or more first chips provided on the substrate and located in a first direction from the first substrate pads, each of the first chips including one or more first chip pads electrically connected to the first substrate pads. The device further includes one or more second substrate pads provided on the substrate, and one or more second chips provided on the first chips and located in a second direction from the second substrate pads, the second direction intersecting the first direction, each of the second chips including one or more second chip pads electrically connected to the second substrate pads. Moreover, each of the second chip pads is located to overlap with a highest first chip of the first chips in planar view.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
An etching method according to the present embodiment includes etching a structure from inside of a hole or a slit provided in the structure, using a chemical etching solution containing an acid and a polymer.
A semiconductor memory device according to the present embodiment includes a stacked body, a semiconductor layer, a first insulating film, a charge storage film, a second insulating film, a third insulating film, and an insulating portion. The stacked body is a stacked body in which an electrode layer and an insulating layer are alternately stacked in a first direction. The second insulating film is disposed between the stacked body and the charge storage film along the first direction. The third insulating film is disposed between the insulating layer and the second insulating film. The insulating portion is disposed in an end portion on a side of the third insulating film of the insulating layer, the insulating portion overlapping the electrode layer as viewed in the first direction. A density of the insulating portion differs from a density of the insulating layer.
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A memory system according to an embodiment includes a first board, a control circuit, and a semiconductor storage device. The semiconductor storage device includes a second board, a plurality of semiconductor memory chips, and a plurality of connection terminals. Each of the plurality of semiconductor memory chips includes only a plurality of first terminals for one channel configured of a predetermined number of terminals. The plurality of first terminals serve as terminals capable of transferring data signals or timing signals. The plurality of connection terminals include only a plurality of second terminals for one channel configured of the predetermined number of terminals. The plurality of second terminals serve as terminals capable of transferring the data signals or the timing signals.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
28.
SEMICONDUCTOR INTEGRATED CIRCUIT, RECEPTION DEVICE, AND MEMORY SYSTEM
According to one embodiment, a semiconductor integrated circuit includes: a comparator configured to execute comparison processing of differential analog signals; and a control circuit configured to determine values of a plurality of bits based on a result of the comparison processing of the comparator and generate a digital signal including the determined values of the plurality of bits, wherein the control circuit is configured to set an initial value for a first bit of a determination target among the plurality of bits, and if the determination of the first bit is not ended in a first period, set a first temporary value having a first value for the first bit.
A memory device includes a first conductor and a charge storage film extending along a first direction; a first semiconductor of a first conductive type; a second and third semiconductor each of a second conductive type; and a stack comprising a second conductor, a first insulator, and a third conductor sequentially stacked along the first direction and each extending along a second direction. The first conductor, the charge storage film, the first semiconductor, and the stack are arranged in this order along a third direction. The second semiconductor is in contact with the first semiconductor and the second conductor, between the second conductor or the first insulator and the charge storage film.
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Each of first, second, and third string has one end coupled to a first interconnect and another end coupled to a second interconnect. The first, second, and the third strings include first, second, and third memory cell transistor, respectively. A first power supply line is coupled to a gate of the first memory cell transistor via a first transistor and coupled to a gate of the second memory cell transistor via a second transistor. A second power supply line is coupled to a gate of the third memory cell transistor and applies a voltage different from that of the first power supply line during data erasing.
A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
A semiconductor memory device includes: conductive layers stacked in a stacking direction and including first conductive layers extending in a first direction over a semiconductor column region, a first terrace region, and a second terrace region, a second conductive layer including a terrace portion provided in the first terrace region, and a third conductive layer including a terrace portion provided in the second terrace region; a semiconductor column disposed in the semiconductor column region; a gate insulating film disposed between the conductive layers and the semiconductor column; and a first insulating member including a first insulating portion extending in the first direction in the first terrace region and a second insulating portion extending in the first direction in the second terrace region. The second insulating portion has a width in a second direction smaller than a width in the second direction of the first insulating portion.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
33.
MEMORY SYSTEM, HOST DEVICE AND METHOD FOR CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a controller of the memory system manages a plurality of zones using first information indicating (i) a correspondence between the zones and storage areas of a nonvolatile memory and (ii) a status of each of the zones. The status includes a first status indicating that data is written over an entire logical address range corresponding to a zone and a second status indicating that a zone is reset. In response to receiving a first command from a host device, the controller transmits to the host device a first list including information indicating a zone which is to be garbage collected. The zone is determined based on the first information.
A lithography simulation method according to the present embodiment includes acquiring a mask shape to be transferred from a mask substrate to a wafer substrate using a projection exposure apparatus. The lithography simulation method also includes acquiring a control point on a contour figure included in the mask shape, a function form of a polynomial parameterization, and an order of the function form. The lithography simulation method also includes Fourier-transforming the contour figure using the polynomial parameterization based on the control point, the function form, and the order to predict a resist pattern.
A memory system includes first and second memory chips, each including first and second pads, a phase adjustment circuit, and a control circuit. The first pads of the memory chips are commonly connected and the second pads of the memory chips are commonly connected. In response to a first command set for the first memory chip to read data and a second command set for the second memory chip to write data, the control circuit of the first memory chip reads and outputs a data signal through its first pad along with a timing signal output through its second pad, and concurrently therewith, the control circuit of the second memory chip receives the data through its first pad with reference to a timing signal received through its second pad and writes the data thereinto.
A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.
A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.
According to one embodiment, an interposer package disposed between a burn-in board and a test device package, includes: a first substrate having the same or substantially the same coefficient of expansion as a coefficient of expansion of the burn-in board; a second substrate having the same or substantially the same coefficient of expansion as a coefficient of expansion of the test device package; a first sheet contact inserted between the first substrate and the second substrate; and a case configured to seal the first substrate, the second substrate, and the first sheet contact. The first sheet contact is sandwiched between the first substrate and the second substrate, thereby electrically connecting the burn-in board and the test device packages to each other, and the first substrate, the second substrate, and the first sheet contact is sealed with the case applying a predetermined pressure, thereby maintaining the electrical connection.
A semiconductor manufacturing device is a semiconductor manufacturing device for connecting a semiconductor chip to a target object and includes a collet and a holder. The collet is formed of an elastic material and comes into contact with the semiconductor chip. The holder holds the collet. A recessed part into which the collet is inserted is formed at a front surface of the holder. A protrusion part is formed at a central part of a bottom surface of the recessed part, the amount of protrusion of the protrusion part being largest from the bottom surface of the recessed part relative to any other part of the bottom surface of the recessed part.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
40.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND PATTERN FORMING METHOD
A first hole pattern is transferred to a first hard mask layer to form a first hard mask pattern having a second hole pattern, a first spacer layer is formed on a side wall of the second hole pattern and the first hard mask pattern is removed to form a first spacer pattern being cylindrical and arranged at a position of the second hole pattern, a second spacer layer covering an upper surface of the second hard mask layer outside the first spacer pattern is formed, and a second spacer pattern having a third hole pattern is formed by removing the second spacer layer overlapping a first region consisting of a minimum distance connecting center points of the first spacer pattern, to form a fourth hole pattern including the second hole pattern included in the first spacer pattern and the third hole pattern included in the second spacer pattern.
A system includes a controller and a first memory chip associated with a first unique number and including a first set of pads coupled to the controller. The first memory chip is configured to receive a command from the controller through at least one pad of the first set of pads, the command including a target unique number and a target chip address, and the target chip address having a fewer number of bits than a number of bits of the target unique number, and to store the target chip address as a first chip address identifying the first memory chip, in response to the target unique number matching the first unique number.
According to one embodiment, a device includes: an operational amplifier including first and second input terminals and an output terminal, the operational amplifier that outputs a voltage; a first resistor including one end connected to the first input terminal and an other end connected to the output terminal; second resistors including one end connected to the first input terminal, the second resistors connected in series; switches each including one end connected to a first node between two adjacent resistors of the second resistors and an other end connected to a second node, the switches that receives a code; and a current source between the second node and a third node. A switch of the switches is turned on based on the code. The current source causes a current to flow from a part or all of the second resistors to the third node via the switch.
H03M 1/78 - Simultaneous conversion using ladder network
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
A semiconductor memory device includes memory block regions arranged in a first direction, a hook-up region arranged in the first direction with respect to memory block regions, and a wiring region extending in the first direction and arranged with memory block regions and the hook-up region in a second direction. Each of memory block regions includes memory strings extending in the first direction and arranged in the second direction and a first wiring extending in the second direction and connected to memory strings in common. The wiring region includes a second wiring extending in the first direction and connected to first wirings corresponding to memory block regions in common. The hook-up region includes a third wiring connected to the second wiring and a contact electrode extending in a third direction and connected to the third wiring.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
46.
TRANSISTOR, SEMICONDUCTOR MEMORY DEVICE, AND MANUFACTURING METHOD FOR TRANSISTOR
A transistor includes an upper electrode; a lower electrode; a gate electrode disposed between the upper electrode and the lower electrode; and a columnar portion penetrating the gate electrode and provided between the upper electrode and the lower electrode. The columnar portion includes a tubular gate insulating film and a semiconductor layer, the tubular gate insulating film disposed at a first distance away from the upper electrode and in contact with the gate electrode. The semiconductor layer is embedded in the tubular gate insulating film and between the gate insulating film and the upper electrode and in contact with the upper electrode.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10D 99/00 - Subject matter not provided for in other groups of this subclass
47.
CONTROLLER FOR CONTROLLING NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD OF CONTROLLING NON-VOLATILE SEMICONDUCTOR MEMORY
According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
According to one embodiment, a semiconductor circuit includes first to third first-conduction-type transistors, first and second second-conduction-type transistors and a constant current source. One end and another end of the first first-conduction-type transistor are respectively coupled to a first power supply node and a first node, and a gate end of the first first-conduction-type transistor is coupled to the first node via a resistor. One end and another end of the second first-conduction-type transistor are respectively coupled to the first power supply node and a second node, the second node is coupled to an output node, and a gate end of the second first-conduction-type transistor is coupled to the first node.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.
G11C 16/08 - Address circuitsDecodersWord-line control circuits
G11C 16/26 - Sensing or reading circuitsData output circuits
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
50.
SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device according to an embodiment includes a substrate, a transistor, a multi-layered body, a pillar, and a source line. The transistor is on the substrate. The multi-layered body includes a plurality of gate electrode layers and a plurality of insulating layers alternately stacked one by one in a first direction. The pillar includes an insulating core, a channel layer, and a memory film. The source line is between the multi-layered body and the substrate. The source line extends at least in a second direction. The pillar has a first end and a second end. The first end is in contact with the source line. The second end is on a side opposite to the first end in the first direction. A width of the first end in the second direction is larger than a width of the second end in the second direction.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
51.
METHOD OF CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY
According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
According to one embodiment, a chemical solution comprises a mixed acid including an inorganic acid, an oxidizing agent, a carboxylic acid, and water; and polyethyleneimine of a concentration in the chemical solution in a range of 0.05 wt % to 10 wt %.
A solid-state storage device is provided, which includes a controller and a non-volatile memory. The controller selects a first word line group from a plurality of word line groups obtained by classifying the word lines based on a read threshold voltage of each word line, and a representative word line corresponding to each word line group is set based on the read threshold voltage associated with each word line group. The controller uses the read threshold voltage of a first representative word line corresponding to the first word line group to read page data of the first representative word line. When the controller cannot correctly read the page data of the first representative word line using the read threshold voltage of the first representative word line, the controller updates the read threshold voltage of the first representative word line in the first word line group.
The semiconductor manufacturing apparatus according to the embodiment includes a processing tank that stores a processing solution for processing wafers and circulates the stored processing solution, a first belt conveyor arranged to extend vertically within the processing tank, a second belt conveyor arranged to extend vertically within the processing tank, and a drive controller that opens and closes the first and second belt conveyors to sandwich and support ends of the wafers, and controls the first and second belt conveyors to rotate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
A memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
A power supply circuit has a first node, a second node, a DC-DC converter that includes a switched capacitor, generates an output voltage based on an input voltage supplied from the first node, and outputs the output voltage from the second node, and a regulator that is connected in parallel to the DC-DC converter between the first node and the second node and controls an output current flowing to the second node based on a reference voltage lower than the input voltage.
H02M 1/14 - Arrangements for reducing ripples from DC input or output
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/08 - Address circuitsDecodersWord-line control circuits
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A semiconductor circuit includes: a first transistor connected between a first node configured to input an input voltage and a second node configured to output an output voltage; a cascode connection circuit including a plurality of second transistors connected in a cascode configuration between the first node and a third node set at a first voltage; a first capacitor connected between the second node and a fourth node of a first one of the plurality of second transistors; and a second capacitor connected between the first node and the fourth node, wherein a fifth node of the first second transistor is connected to a gate of the first transistor.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a charge storage layer between the semiconductor layer and the first gate electrode layer, the charge storage layer containing a first element, a second element, and oxygen, the first element being at least one element selected from the group consisting of hafnium and zirconium, and the second element being at least one element selected from the group consisting of nitrogen and aluminum; a first insulating layer between the charge storage layer and the first gate electrode layer; and a second insulating layer between the semiconductor layer and the first gate electrode layer, the second insulating layer containing silicon and nitrogen, the second insulating layer surrounding the charge storage layer in a cross section that being parallel to the first direction and including the charge storage layer.
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
A memory system includes a nonvolatile memory that stores a profile table and a memory controller that is configured to control the nonvolatile memory. The profile table includes a plurality of profile information items. The memory controller is configured to control the nonvolatile memory on the basis of first profile information among the plurality of profile information items in a first process among a plurality of processes that are executed during a startup sequence. The first profile information includes a parameter that is referred to when the first process is executed.
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i−th (i is a natural number in the range of 0 to N) word line, M (M
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
62.
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A semiconductor package according to one embodiment comprises a substrate. A semiconductor chip is provided on the substrate. A resin layer is configured to cover the semiconductor chip on the substrate. A metal film is configured to cover a surface and side surfaces of the resin layer. The metal film is a laminated film including first to fourth metal layers. The first metal layer is configured to cover the resin layer. The second metal layer includes a first metal material that is different from a material of the first metal layer. The third metal layer includes an alloy of the first metal material forming the second metal layer and a second metal material different from the first metal material. The fourth metal layer is configured to cover the second or third metal layer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Embodiments relate to decoding data read from a non-volatile storage device, including determining error candidates for the data based on component codes, determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate, determining whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate in response to implementing a suggested correction at one of the error candidates, and correcting errors in the data based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
A semiconductor memory device includes a semiconductor layer extending in a first direction, a conductive layer opposed to the semiconductor layer in a second direction intersecting with the first direction, an electric charge accumulating layer disposed between the semiconductor layer and the conductive layer, a first insulating layer disposed between the semiconductor layer and the electric charge accumulating layer, and a second insulating layer disposed between the conductive layer and the electric charge accumulating layer. The semiconductor layer includes at least one protrusion protruding in the second direction toward the electric charge accumulating layer. A position in the first direction of the protrusion is inside with respect to corner portions at both ends in the first direction of a surface opposed to the semiconductor layer in the electric charge accumulating layer.
According to one embodiment, a semiconductor device includes a first substrate; a semiconductor chip provided in a first region of a first face of the first substrate; and a first structure provided in a second region of the first face, wherein the first substrate includes: wiring embedded in the first substrate; a first conductor coupled to the semiconductor chip and the wiring and exposed on the first face; and a second conductor coupled to the first conductor via the wiring and exposed on a second face of the first substrate, a height of the first structure in a first direction perpendicular to the first face is greater than a height of the semiconductor chip in the first direction, in a case where the first face is taken as a reference.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
66.
MEMORY SYSTEM WITH SELECTIVE ACCESS TO FIRST AND SECOND MEMORIES
A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.
According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/08 - Address circuitsDecodersWord-line control circuits
According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
H04L 25/08 - Modifications for reducing interferenceModifications for reducing effects due to line faults
A semiconductor storage device includes: a printed circuit board; a nonvolatile memory disposed on the printed circuit board; a memory controller disposed on the printed circuit board and configured to operatively control nonvolatile memory; a capacitor disposed on the printed circuit board and configured to supply power to the nonvolatile memory and the memory controller; and at least one holder that holds the capacitor at an end portion of the printed circuit board. The holder includes a connecting portion connected to the end portion of the printed circuit board, and a pair of arm portions extending from the connecting portion toward an outside of the printed circuit board and configured to sandwich a body portion of the capacitor from both sides in a thickness direction of the printed circuit board.
A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table based on corrected data, determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data being corrected is read, and correct the first table based on the voltage difference.
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
71.
MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a controller of a memory system writes, in response to receiving from the host a write command specifying a logical address, data received from the host to a first write destination block. The controller manages a first list and first storage location information, the first list including a plurality of logical addresses corresponding respectively to write-uncompleted data, and the first storage location information indicating a storage location at a beginning of a write-uncompleted region in the first write destination block. In a case where a power loss has occurred without notice from the host, the controller writes the first list and the first storage location information to the nonvolatile memory using power from a capacitor.
According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/08 - Address circuitsDecodersWord-line control circuits
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
A semiconductor memory device comprises: a first pad receiving a first signal; a second pad receiving a second signal; a first memory cell array; a first sense amplifier connected to the first memory cell array; a first data register connected to the first sense amplifier and configured to store user data read from the first memory cell array; and a control circuit configured to execute an operation targeting the first memory cell array. The first memory cell array comprises a plurality of first memory strings. The first memory strings each comprise a plurality of first memory cell transistors. In a first mode of this semiconductor memory device, a command set instructing the operation is inputted via the first pad. In a second mode of this semiconductor memory device, the command set is inputted via the second pad.
According to one embodiment, a memory system includes a nonvolatile memory that includes memory cells. The nonvolatile memory outputs, to a memory controller, first hard bit data of the first bit, second hard bit data of the second bit, third hard bit data of the third bit, and fourth soft bit data related to the first bit, the second bit, and the third bit, in response to a first command set. The nonvolatile memory outputs, to the memory controller, the first hard bit data, the second hard bit data, the third hard bit data, first soft bit data related to the first bit, second soft bit data related to the second bit, and third soft bit data related to the third bit, in response to a second command set.
According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
A memory device includes a first memory cell and a second memory cell each corresponding to a first column address, a first sense amplifier unit, a first bit line connected between the first memory cell and the first sense amplifier unit, and a second bit line connected between the second memory cell and the first sense amplifier unit.
G11C 16/26 - Sensing or reading circuitsData output circuits
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
77.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes: a first bit line; a capacitor; and a first memory cell transistor and a second memory cell transistor that are coupled in series between the first bit line and the capacitor.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A nonvolatile semiconductor memory includes a first memory string, a first interconnect coupled to one end of the first memory string, a second interconnect coupled to another end of the first memory string, a first circuit configured to control the first interconnect in accordance with first data, and a second circuit coupled to the second interconnect, the second circuit including a current mirror circuit, and the second circuit being configured to output second data based on an amount of a current flowing through the second interconnect.
According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
80.
MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.
According to one embodiment, a method including supplying a liquid onto a substrate, solidifying the liquid on the substrate to form a solidified body, and melting the solidified body of the liquid on the substrate is provided. When solidifying the liquid, an internal pressure of the liquid on the substrate is varied.
B08B 7/00 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
An analysis system includes an analysis device; a first pipe including a first end portion, a second end portion, and a first location between the first end portion and the second end portion; a first valve between the second end portion and the analysis device; a gas supply source supplying purge gas; a second pipe including a third end portion connected to the first location, and a fourth end portion connected to the gas supply source; a second valve in the second pipe; a third pipe including a fifth end portion, a sixth end portion, and a second location between the fifth end portion and the sixth end portion; a third valve between the sixth end portion and the analysis device; a fourth pipe including a seventh end portion connected to the second location, and an eighth end portion connected to the gas supply source; and a fourth valve.
A semiconductor memory device includes first and second planes of memory cells, and a control circuit configured to perform a write operation on the memory cells to store first and second bits per memory cell, and to perform a first read operation using a first read voltage to read the first bits and a second read operation using second and third read voltages to read the second bits. In response to a first instruction, the control circuit performs the first and second read operations to read the first bits from the first plane and the second bits from the second plane, respectively. In response to a second read instruction, the control circuit performs the second and first read operations to read the second bits from the first plane and the first bits from the second plane, respectively.
According to one embodiment, a memory system includes a nonvolatile memory, a storage area, and a controller. The controller acquires a request from a submission queue included in a host, generates one or more commands to be executed by the nonvolatile memory in accordance with the request, and stores the commands to the storage area. The controller controls throttling of acquisition of requests from the submission queue in accordance with the number of commands in the storage area and the number of requests in the submission queue.
In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A memory system connectable to a host device includes a nonvolatile memory, a first circuit configured to generate a sequence of random number bits, and a processor configured to instruct the circuit to generate a sequence of random number bits having a first length, calculate a first value indicating randomness of the sequence, determine whether the first value exceeds a threshold value, upon determining that the first value exceeds the threshold value, generate a pseudo random number using the sequence, upon determining that the first value does not exceed the threshold value, instruct the first circuit to generate another sequence of random number bits having a second length greater than the first length, and generate a pseudo random number using said another sequence, and write or read data to or from the nonvolatile memory using the generated pseudo random number.
A memory system according to one embodiment includes a memory device and a memory controller. The memory device includes memory cells. The memory controller executes a tracking operation. In the tracking operation, the memory controller is configured to cause the memory device to execute a plurality of times of read operations using a plurality of read levels. In the tracking operation, the memory controller is further configured to set a first voltage difference between two adjacent read levels of the read levels in a fourth voltage range lower than a first voltage in a third voltage range and a second voltage difference between two adjacent read levels of the read levels in a fifth voltage range higher than the first voltage in the third voltage range. The first and second voltage differences are different from each other.
A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.
A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
91.
SELECTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME AND METHOD FOR FABRICATING SELECTOR AND SEMICONDUCTOR DEVICE
A selector includes a base material including carbon; and a dopant implanted into the base material. A method for fabricating a selector includes forming a carbon layer and implanting a dopant into the carbon layer. A semiconductor device includes a selector pattern including carbon as a base material and a dopant implanted through an ion implantation process; and a memory pattern disposed in an upper portion or a lower portion of the selector pattern.
According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving from a host a write request designating a first address for identifying data to be written, the controller encrypts the data with the first address and a first encryption key, and writes the encrypted data to the nonvolatile memory together with the first address. In response to receiving from the host a read request designating a physical address indicative of a physical storage location of the nonvolatile memory, the controller reads both the encrypted data and the first address from the nonvolatile memory on the basis of the physical address, and decrypts the read encrypted data with the first encryption key and the read first address.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
According to one embodiment, in response to receiving a read command from a host, a controller executes a command process of reading data from a nonvolatile memory. The controller executes an address translation process of translating a virtual address specified in the read command to a physical address for accessing a memory of the host. In the address translation process, the controller transmits an address translation request to the host. In response to receiving from the host a response indicating that obtainment of address translation information fails, the controller suspends the command process until the address translation information is obtained, and after the address translation information is obtained, resumes the command process.
A semiconductor memory device includes: a memory cell array including a plurality of bit lines, a source line, a plurality of NAND strings, a first and a second sub block, a first word line group included in the first sub block, a second word line group included in the second sub block, and a dummy word line located between the first and second sub blocks; and a control circuit capable of applying predetermined voltages to the first word line group, the second word line group, and the dummy word line. When a specific word line belonging to the first word line group is selected for the execution of a write operation, a voltage higher than voltages applied to an unselected word line belonging to the first word line group and the second word line group is applied to the dummy word line.
According to one embodiment, the polynomial ring vector inner product computation circuit computes an inner product between a first frequency domain polynomial ring vector and a second frequency domain polynomial ring vector, based on the first frequency domain polynomial ring vector obtained by preliminarily executing a process of multiplying each of one or more constant polynomials by 1/N and a process of applying the number theoretic transform to each of the one or more constant polynomials, and outputs a time domain polynomial obtained by applying inverse number theoretic transform to the computed inner product as an inner product between a first polynomial ring vector and a second polynomial ring vector.
A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H03M 13/01 - Coding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.
A method of storing data on a storage appliance with at least one non-volatile memory. The method comprising associating a first portion of a storage capacity of the at least one non-volatile memory to a first application of a plurality of applications, and associating a second portion of the storage capacity of the at least one non-volatile memory to a second application of the plurality of applications. The method also comprises receiving a request to write data associated with the first application to the at least one non-volatile memory and determining that the first portion does not have capacity to store the write data. Additionally, the method comprises requesting the second application to remove data stored in the second portion, reassociating a portion of the storage capacity of the second portion to the first portion, and storing the write data in the first portion.
Disclosed herein is a device and method for dynamically processing of a command within a storage system. This includes identifying a plurality of non-volatile memory storage locations of the storage system that have at least one operation parameter associated with the plurality of non-volatile memory storage locations. For each identified plurality of non-volatile memory storage locations, there is a determination whether a value of the at least one operation parameter exceeds a predetermined threshold value. That value is representative of operation effects of the storage system on a corresponding storage location of the identified plurality of non-volatile memory storage locations. During operation of the storage system, there is a throttling of execution of the command to access a storage location of the identified plurality of non-volatile memory storage locations that has the value determined to exceed the predetermined threshold value by a throttle amount determined to mitigate an effect of the value exceeding the predetermined threshold value.
G06F 3/06 - Digital input from, or digital output to, record carriers
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
An imaging device includes a stage holding a subject; a detector including a first pixel layer, an insulating layer, and a second pixel layer stacked on top of one another; an image formation optical member configured to form an image of imaging light transmitted through the subject; and an image processor configured to reconstruct an image of the subject based on a detection intensity of the imaging light. The first pixel layer includes first linear pixels having linear light receiving surfaces extending in a first direction, and the first linear pixels are arranged with equal intervals from one another in a direction orthogonal to the first direction. The second pixel layer includes second linear pixels having linear light receiving surfaces extending in a second direction, and the second linear pixels are arranged with equal intervals from one another in a direction orthogonal to the second direction.
