The adjustable gain amplifier comprises an amplifier transistor comprising a control terminal and a controllable path. The adjustable gain amplifier also comprises a variable impedance circuit, which is configured to provide a variable impedance in dependence on a gain adjustment information. The load path of the amplifier transistor and the variable impedance circuit are circuited in series between a first supply potential feed and a second supply potential feed. The adjustable gain amplifier also comprises an active feedback circuit configured to stabilize a load path bias voltage of the amplifier transistor. The adjustable gain amplifier can be used in an automated test equipment.
An apparatus for wireless testing of a plurality of transmit paths of an electronic device capable of varying a preferred direction of beam of a test signal of the electronic device comprising a test interface, a test generator, a test module, and an analysis module. The test interface for being connected to the electronic device is configured to transmit data to the electronic device and to receive data from the electronic device. The test generator drives the electronic device through the test interface to vary the preferred direction of beam. Further, the test module determines a plurality of transmit values of a transmit parameter wirelessly based on the test signal received from the electronic device by using at least one static antenna of the test module for receiving the test signal. Each transmit value of the transmit parameter is associated with a different preferred direction of beam. The analysis module provides an assessment of the plurality of transmit paths of the electronic device based on the plurality of transmit values.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
3.
OPTIMIZED AUTOMATED TEST EQUIPMENT MULTI-PATH RECEIVER CONCEPT
A multi-path receiver (300) for automated test equipment (100), the multi-path receiver comprising an input (302) for receiving low-power signals as well as high-power signals, the high-power signals having a higher signal amplitude than the low-power signals; an output (304) for outputting a received signal; a first path (308a) for transmitting a received high-power signal from the input (302) to the output (304); a second path (308b) for transmitting a received low-power signal from the input (302) to the output (304), the second path comprising an amplifier (310); a first switch (306a) for switching a received high-power signal to the first path (308a) and for switching a received low-power signal to the second path (308b); and a high-power amplifier (312) connected between the input (302) and the first switch (306a) for amplifying the received signal independent of its input power before it is switched with the first or second path (308a;b).
An apparatus for providing a modulated bitstream in dependence on a modulation content comprises a mapper configured to selectively provide a carrier bitstream portion or an inverted carrier bitstream portion in dependence on a binary value of the modulation content bitstream representing the modulation content, to obtain the modulated bitstream.
APPARATUS AND METHOD FOR COMBINING ELECTRICAL OR ELECTRONIC COMPONENTS; APPARATUS AND METHOD FOR PROVIDING A COMBINATION INFORMATION; APPARATUS AND METHOD FOR DETERMINING A SEQUENCE OF COMBINATIONS AND COMPUTER PROGRAM
An apparatus for combining electrical or electronic components based on a digital input signal which can take a plurality of values out of a range of values, so as to generate an analog quantity corresponding to the digital input signal comprises a combination generator and a component combiner. The combination generator is adapted to supply, in dependence on the input signal, a control signal describing a sequence of combinations of electrical or electronic components. For a given value of the digital input signal, at least two different combinations of electrical or electronic components associated with the given value are available. At least one of the combinations includes at least two electrical or electronic components having different nominal values. The combination generator is configured to provide the control signal such that, in response to the given value, the control signal describes, in the course of time, a plurality of different combinations of electrical or electronic components. The component combiner comprises a plurality of electrical or electronic components, at least two of which electrical or electronic components comprise different nominal values. The component combiner is adapted to select, in dependence on the control signal, the different sets of the electrical or electronic components to be combined from the plurality of electrical or electronic components.
H03M 3/04 - Differential modulation with several bits
H03M 7/00 - Conversion of a code where information is represented by a given sequence or number of digits to a code where the same information is represented by a different sequence or number of digits
6.
METHOD AND APPARATUS FOR DETERMINING RELEVANCE VALUES FOR A DETECTION OF A FAULT ON A CHIP AND FOR DETERMINING A FAULT PROBABILITY OF A LOCATION ON A CHIP
A method is described for determining relevance values (R(i,m)), each relevance value representing a relevance of a combination ((i,m)) of an input node (i) of a first number (I) of input nodes with a measurement node (m) of a second number (M) of measurement nodes for a detection of a fault on a chip, the method comprising: applying a third number (K) of tests at the first number (I) of input nodes, wherein each test (k) of the third number (K) of tests defines for each input node (i) a test input choice (U(k,i)); measuring for each test (Jc) of the third plurality (K) of tests a signal at each of the second number (M) of measurement nodes to obtain for each measurement node (m) of the second number (M) of measurement nodes a third number (K) of measurement values, wherein each measurement value (Y(k,m)) is associated to the test (k) it was measured for and to each measurement node (m) it was measured at; and determining the relevance values (R(i,m)), wherein each relevance value is calculated based on a correlation between the third number (K) of test input choices (U(k,i)) defined for the input node (i) of the respective combination and the third number (K) of measurement values (Y(k,m)) associated to the measurement node (m) of the respective combination (i,m).
An apparatus (190) for determining a compensation parameter for compensating a signal level change of a test signal, wherein the signal level change is caused by a propagation of the test signal along a signal path (102), comprises a test signal generator (110) and a test signal analyzer (120). The test signal generator is configured to provide the test signal and couple it into the signal path. The test signal analyzer is configured to analyze a reflection of the test signal and configured to determine the compensation parameter based on the analysis of the reflected test signal. The analysis of the reflected test signal is based on determining a signal level of the reflected test signal.
In one embodiment, a test system has a set of test electronics for testing a device under test (DUT). The test system also has at least one test electronics to DUT interface having a zero insertion force (ZIF) connector. Each ZIF connector has a ZIF connector to DUT clamping mechanism configured to i) apply a first orthogonal force to a probe card that interfaces with a DUT, by pressing the ZIF connector against the probe card, and simultaneously ii) exert at least one second orthogonal force on the probe card, the at least one second orthogonal force being opposite in direction to the first orthogonal force.
G01R 31/26 - Testing of individual semiconductor devices
H01L 21/66 - Testing or measuring during manufacture or treatment
9.
RE-CONFIGURABLE TEST CIRCUIT, METHOD FOR OPERATING AN AUTOMATED TEST EQUIPMENT, APPARATUS, METHOD AND COMPUTER PROGRAM FOR SETTING UP AN AUTOMATED TEST EQUIPMENT
A re-configurable test circuit for use in an automated test equipment comprises a test circuit, a test processor and a programmable logic device. The pin electronics circuit is configured to interface the re-configurable test circuit with a device under test. The test processor comprises a timing circuit configured to provide one or more adjustable-timing signals having an adjustable timing. The programmable logic device is configured to implement a state machine, a state sequence of which is dependent on one or more input signals received from the pin electronics circuit, to provide an output signal, which is dependent on a current or previous state of the state machine, to the pin electronics circuit in response to the one or more signals received from the pin electronics circuit. The test processor is coupled to the programmable logic device to provide at least one of the one or more adjustable-timing signals to the programmable logic device to define a timing of the programmable logic device.
An apparatus for determining a position in a bit sequence in a digital stream of data of a reference time, wherein a plurality of transitions in the bit sequence comprise a time information each, comprising a bit number determiner and a position determiner. The bit number determiner is configured to assign a bit number to a reference bit in the bit sequence on the basis of a time information of a transition associated with the reference bit and the position determiner is configured to determine the position in the bit sequence at the reference time on the basis of a plurality of reference bits with bit numbers and a direction of the respectively associated transition.
A test arrangement (400) comprises an interface (401) for a device under test (404), the interface (401) comprising an impedance matching circuit (402) comprising a resistance (R) and an inductance (L) connected in parallel.
A method for processing a full-rate input signal (un,...,un+R) having a first clock rate (f1) and for providing a full-rate output signal (Yn,..., Yn+R) in dependence on the full-rate input signal (un,..., un+R), the method comprising deserializing the full-rate input signal (un,..., un+R-1) to obtain a sub-rate input signal (Un) comprising a plurality of subsequent values of the full-rate input signal, such that the sub-rate input signal has a second clock rate (f2) being a fraction of the first clock rate (f1), updating a sub-rate internal state of a sub-rate finite state machine in dependence on a previous sub-rate internal state (zn) and the sub-rate input signal (Un) at the second clock rate (f2), providing a sub-rate output signal (Yn) in dependence on the previous or updated sub-rate internal state (zn; zn+R), the sub-rate output signal comprising a plurality of output values (Yn,..., Yn+R-1), and serializing the sub-rate output signal (Yn) comprising the plurality of output values (Yn,..., Yn+R-1) to obtain a serialized output signal having the first clock rate (f1) and having values equal to the full-rate output signal.
An embodiment of a state machine (200) for generating a pseudo-random word stream, each word of the word stream comprising a plurality of subsequent bits of a pseudorandom bit sequence comprises a plurality of clock registers (210) and a feedback circuit (230) coupled to the registers (210) and adapted to provide a plurality of feedback signals to the registers (230) based on a feedback function and a plurality of register output signals of the registers (210), wherein the state machine (200) is configured such that a first word defined by the plurality of register output signals comprises a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals comprises a second set of subsequent bits of a pseudo-random bit stream.
A test system (100) for testing a signal path (102) comprises a test signal generator (110) and a signal processing means (140). The test signal generator (110) comprises a modulator (120) and a phase-locked loop (130), wherein the phase-locked loop (130) of the test signal generator (110) is configured to provide a test signal and couple it into the signal path (102) under test. The modulator (120) of the test signal generator (110) is configured to enable a phase modulation of the test signal. The signal processing means (140) is configured to receive and process the test signal, wherein the signal path (102) under test extends from the phase-locked loop (130) of the test signal generator (110) to the signal processing means (140). A method for testing a signal path comprises the steps of generating a test signal by a test signal generator, coupling the test signal into the signal path, receiving the test signal by the signal processing means and assessing the test signal received.
METHOD OF SHARING A TEST RESOURCE AT A PLURALITY OF TEST SITES, AUTOMATED TEST EQUIPMENT, HANDLER FOR LOADING AND UNLOADING DEVICES TO BE TESTED AND TEST SYSTEM
A method of sharing a test resource (112) at a plurality of test sites (102-108) executes respective test flows at the plurality of test sites (102-108) with an offset in time, the respective test flows (116-122) accessing the test resource 112 at a predetermined position (116b-122b) in the test flow.
A signal distribution structure for distributing a signal to a plurality of devices comprises a first signal guiding structure comprising a first characteristic impedance. The signal distribution structure also comprises a node, wherein the first signal guiding structure is coupled to the node. The signal distribution structure comprises a second signal guiding structure comprising one or more transmission lines. The one or more transmission lines of the second signal guiding structure are coupled between the node and a plurality of device connections. The second signal guiding structure comprises, side-viewed from the node, a second characteristic impedance which is lower than the first characteristic impedance. The signal guiding structure also comprises a matching element connected to the node.
A data processing unit comprises a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or strobe signal and at least one data extraction unit, coupled to the time information provider and configured to select data from a sequence of data samples of a data signal depending on the digitized clock or strobe time information.
In one embodiment, a method for testing a plurality of singulated semiconductor die involves 1) placing each of the singulated semiconductor die on a surface of a die carrier, 2) mating an array of electrical contactors with the plurality of singulated semiconductor die, and then 3) performing electrical tests on the plurality of singulated semiconductor die, via the array of electrical contactors.
For determining a minimum/maximum of a plurality of binary values a bit position in the plurality of binary values is determined subsequent to which all bit values are the same. From the plurality of binary values those binary values are selected the bit values of which at the bit position determined in the preceding step and all subsequent positions, if any, comprises a predetermined value. The preceding steps are then repeated until only one binary value remains which is provided as the minimum or maximum.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
20.
A HIGH CURRENT TRANSMISSION LINE AND A METHOD FOR TRANSMITTING HIGH CURRENTS
A high current transmission line for guiding a current (I) along a current path comprises a first, a second and a third conducting layer (110, 120, 130) and a first and a second isolating layer (210, 220). The first, second and third conducting layers (110, 120, 130) are arranged as a layer stack such that the second conducting layer (120) is arranged between the first and third conducting layers (110, 130). The first isolating layer is arranged between the first conducting layer (110) and the second conducting layer (120) and the second isolating layer (220) is arranged between the second and third conducting layer (120, 130).
An apparatus for estimating data relating to a time difference between two events comprises a delay line 100 having a plurality of stages (101, 102, 103, 104). Each stage has a delay difference between a first delay in a first part and a second delay in a second part. This delay difference is measured by a phase arbiter (105) in each stage, which outputs an indication signal indicating whether the first event of two events in the first part precedes or succeeds a second event of the two events in the second part. A summation device (200) is provided for summing over the indication signals of the plurality of stages to obtain a sum value (201). The sum value indicates a time difference estimate.
A manipulator for positioning a test head has a manipulator frame (3) having disposed thereon the test head (2), as well as a plurality of supporting feet (4). Each supporting foot has a supporting-foot plate (7), a height adjustment means for the supporting-foot plate (7), a base plate (9) and a bearing disposed between the base plate (9) and the supporting-foot plate (7) for low-friction horizontal shifting of the supporting-foot plate (7) relative to the base plate (9).
F16M 7/00 - Details of attaching or adjusting engine beds, frames, or supporting-legs on foundation or baseAttaching non-moving engine parts, e.g. cylinder blocks
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G01R 1/04 - HousingsSupporting membersArrangements of terminals
A distributed system has a plurality of nodes and a central unit couplable to the plurality of nodes via a communication interface having multicast capabilities. In order to manage resources on the nodes, the nodes receive a first message including an identifier and a request to allocate required resources to the identifier from the central unit. The nodes allocate required resources accordingly and receive a second message including the identifier and resource configuration information defining how to configure the allocated resources. The allocated resources are configured accordingly and, upon receipt of a third message including the identifier, the configured resources are utilized.
A repetitive bit value pattern associated to a predetermined bit position of a sequence of data words (2), the data words comprising two or more bits in a bit order, a bit position describing a position within the bit order being indicative of a value represented by the bit at the bit position, can be determined from program loop information, the program loop information comprising a program expression for determining an updated data word of the sequence of data words (2). Using the predetermined bit position, a sequence length value (8) associated to the predetermined bit position is determined. The program expression is evaluated (6) for a number of loop iterations indicated by the sequence length value (8), to obtain updated bit values associated to the predetermined bit position. The repetitive bit value pattern is determined using the updated bit values of the number of loop iterations.
In an embodiment, there is disclosed a clamp, having a housing; a latch member extending from within the housing, and the latch member translatable along a displacement axis; an actuator mounted to the housing and operatively associated with the latch member to translate the latch member along the displacement axis; and a nonlinear biasing member operatively associated with the latch member and the housing, and the nonlinear biasing member positioned to bias the latch member toward a retracted position. Other embodiments are also disclosed.
G01R 31/01 - Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass productionTesting objects at points as they pass through a testing station
26.
A TRANSMIT/RECEIVE UNIT, AND METHODS AND APPARATUS FOR TRANSMITTING SIGNALS BETWEEN TRANSMIT/RECEIVE UNITS
In one embodiment, apparatus for transmitting and receiving data includes a transmission line network having at least three input/output terminals; at least three transmit/receive units, respectively coupled to the at least three input/output terminals; and a control system. The control system is configured to, depending on a desired direction of data flow over the transmission line network, i) dynamically place each of the transmit/receive units in a transmit mode or a receive mode, and ii) dynamically enable and disable an active termination of each transmit/receive unit. Methods for using this and other related apparatus to transmit and receive data over a transmission line network are also disclosed.
H04J 3/16 - Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
27.
SYSTEM, METHOD AND COMPUTER PROGRAM FOR DETECTING AN ELECTROSTATIC DISCHARGE EVENT
A system (100) for detecting an electrostatic discharge event with respect to a device (110) to be monitored comprises a current measurement device (140) configured to measure a current flowing via a power supply connection (120) connecting the device to be monitored with the power supply to obtain a current measurement signal representing the current or a current component. Alternatively, a current flowing through a protective earth connection (180) connecting the device to be monitored with the protective earth is measured to obtain the measurement signal. The system comprises an electrostatic discharge event detector configured to detect an electrostatic discharge event in response to a pulse of the current measurement signal. The system may optionally comprise data processing of current measurement signals or values.
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
28.
METHODS AND APPARATUS THAT SELECTIVELY USE OR BYPASS A REMOTE PIN ELECTRONICS BLOCK TO TEST AT LEAST ONE DEVICE UNDER TEST
In one embodiment, apparatus for testing at least one device under test (DUT) includes a tester input/output (I/O) node, a DUT I/O node, a remote pin electronics block, a bypass circuit, and a control system. The remote pin electronics block provides a test function and is coupled between the tester I/O node and the DUT I/O node. The bypass circuit is coupled between the tester I/O node and the DUT I/O node and provides a signal bypass path between the tester I/O node and the DUT I/O node. The signal bypass path bypasses the test function provided by the remote pin electronics block. The control system is configured to enable and disable the bypass circuit. Methods for using this and other related apparatus to test one or more DUTs are also disclosed.
In accordance with one embodiment of the invention, a system is provided that comprises a first terminal for receiving an input testing signal during operations; a plurality of input/output terminals coupled with the first terminal; wherein the input/output terminals are configured to parallel output respective output testing signals during parallel output operation; wherein the input/output terminals are configured to parallel input testing response signals during parallel input operation from devices under test; and wherein each of the input/output terminals is electrically isolated during operation from the remaining plurality of input/output terminals.
An environmental variable of a scan chain is set to a value believed to cause a hold time fault, and a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is the scan chain's length. The number of possible hold time faults in the scan chain is determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at the scan chain's output, and ii) a clock cycle when the at least one bit actually causes a transition at the scan chain's output. If there is a value of the environmental variable at which the scan chain operates correctly, the location(s) of hold time faults can be determined.
In accordance with one embodiment of the invention, a method and apparatus are provided for obtaining test data from multiples devices under test. This could be accomplished in accordance with one embodiment by outputting from a testing device a test signal for input in parallel to at least two devices under test; inputting in parallel to the testing device at least two response signals, each response signal produced by one of the at least two devices under test; storing the response signals received in parallel in a storage device; and serially outputting the response signals from the storage device.
In accordance with one embodiment of the invention, a method and apparatus are provided for testing a wafer while the wafer is disposed in a wafer carrier. The test results can be utilized to adjust the manufacturing process and thereby increase processing yield.
B65G 49/07 - Conveying systems characterised by their application for specified purposes not otherwise provided for for fragile or damageable materials or articles for semiconductor wafers
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
33.
CHIP TESTER, METHOD FOR PROVIDING TIMING INFORMATION, TEST FIXTURE SET, APPARATUS FOR POST-PROCESSING PROPAGATION DELAY INFORMATION, METHOD FOR POST-PROCESSING DELAY INFORMATION, CHIP TEST SET UP AND METHOD FOR TESTING DEVICES UNDER TEST
A chip tester for testing at least two devices under test connected to the chip tester comprises a timing calculator for generating a timing information for the Channels of the chip tester. The timing calculator is adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from the first Channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first Channel port of the chip tester to the second terminal of the second device under test. The timing calculator is adapted to provide a timing information for a second Channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information. The Channel module configurator is adapted to configure the second Channel of the chip tester on the basis of the timing information.
A chip tester (110) for testing a plurality of devices under test (130,132) comprises an input (140) for connection to a common line (142), a bias source (152) for biasing the common line and a controller (160). The controller is adapted to control a provision of a first signal (166) for a first DUT and a provision of a second signal (168) for a second DUT, to control the first DUT and the second DUT such that, in a measurement phase, the effect of an electrical characteristic of the first DUT to the DC state at the input is distinguishable from the effect of an electrical characteristic of the second DUT to the DC state at the input. A measurement unit (144) is adapted to measure a DC state at the input in the measurement phase. A diagnosis unit (150) is adapted to decide whether an open-line failure is present with respect to the first DUT on the basis of the measured DC state at the input.
An apparatus for obtaining a time-domain-reflection response-information comprises a signal driver adapted to apply two pulses of different pulse lengths to a TDR port in order to excite a first TDR response signal corresponding to a first pulse and a second TDR response signal corresponding to a second pulse. The apparatus comprises a timing determinator adapted to provide a timing Information on the basis of a first instance in time when the first TDR response signal crosses a threshold value and on the basis of a second instance in time when the second TDR response signal crosses the threshold value. The apparatus comprises a TDR response information calculator adapted to calculate an information about a TDR response on the basis of the timing information.
In accordance with one embodiment of the invention, a method of singulated die testing can be implemented. This can be implemented by obtaining a wafer and singulating the dies into individual die pieces. The singulated dies can be arranged in a separated testing arrangement and can even combine dies from multiple wafers as part of the combined arrangement. Then, testing can be implemented on the combined test arrangement.
There is disclosed apparatus for routing signals between at least one PCB within a test head and a socket card assembly. In an embodiment, the apparatus may include at least one flexible circuit electrically connecting first and second sides of the PCB and the socket card assembly with one another, and the flexible circuit having a defined shape configured to interface with the socket card assembly and the PCB along substantially perpendicular planes. Methods of routing signals between at least one PCB within a test head and a socket card assembly are disclosed. In one embodiment, a method may include electrically connecting first and second sides of the PCB and the socket card assembly with one another at least on flexible circuit having a defined shape configured to interface with the socket card assembly and the PCB along substantially perpendicular planes. Other embodiments are also disclosed.
As a scan pattern is shifted out of a scan chain, the scan pattern is evaluated in real-time for the existence of a logic condition. A reference to a portion of the scan pattern that is currently being evaluated is maintained. Upon identifying the existence of the logic condition when the reference has a predetermined relationship to a stored value, the stored value is overwritten using the reference. The stored value is then used to estimate the position of a stuck-at defect in the scan chain.
A tester for testing a device under test comprises a first channel unit and a second channel unit. The first channel unit comprises a corresponding first pin connection for a signal from a device under test, a corresponding first test processor adapted to process, at least partially, data obtained from the first pin connection, and a corresponding first memory coupled with the first test processor and adapted to store data provided by the first test processor. The first channel unit is adapted to transfer at least a part of the data obtained from the first pin connection to the second channel unit as transfer data. The second channel unit comprises a corresponding second test processor adapted to process, at least partly, the transfer data from the first channel unit.
A signal processing device (100), preferably an undersampling ADC using coherent sampling, is presented for processing a signal (102) , the signal processing device (100) comprising a comparator unit (105) for comparing the signal (102) with a reference signal (106), a generation unit (105, 130) for generating digital result signals (110) indicative of the result of the comparing, an evaluation unit (112) for determining transition times of the digital result signals (110), and an output signal calculation unit (115) adapted for calculating essentially uniformly spaced output signals (116).
A test module (206) for a test apparatus (200) for testing a device under test (201 ), the test module (206) being adapted for performing a specific test function and comprising a universal section (213) adapted to provide test resources being unspecific with regard to the test function of the test module (206), the universal section (213) comprising a control interface (204) adapted to be connected to a central control device (202) of the test apparatus (200), and comprising a specific section (214) to be coupled to the universal section (213) and adapted to provide test resources being specific with regard to the test function of the test module (206), the specific section (214) comprising a device under test interface (205) adapted to be connected to the device under test (201 ).
An asynchronous sigma delta digital to analog converter (100) for converting a digital input signal (u⏧k]) into an analog output signal (f(t)), the digital to analog converter (100) comprising an asynchronous sigma delta modulator (120) comprising a low pass filter (104) and a comparator (106) and being supplied with the digital input signal (u⏧k]), and a clock sample unit (108) adapted to sample a signal (x(t)) processed by the comparator (106) based on a clock signal (fb), thereby generating the analog output signal (f(t)).
A signal processing device (100) for processing a repetitive signal (102), the signal processing device (100) comprising a determining unit (103) for determining a number of points of time for undersampling the repetitive signal (102), a comparator unit (105) for comparing, at the number of points of time, the repetitive signal (102) with a reference signal (106), a generation unit (105) for generating digital result signals (110) indicative of the result of the comparing, and an evaluation unit (112) for determining transition times of the digital result signals (110).
A device (203) for processing test data, the device (203) comprising a data input interface (204) adapted for receiving primary test data indicative of a test carried out for testing a device under test (202), the primary test data being provided in a primary format, a processing unit (205) adapted for generating secondary test data in a secondary format by transforming, by carrying out a coordinate transformation, the primary test data from the primary format into the secondary format, and a data output interface (206) adapted for providing the secondary test data in the secondary format for storing the secondary test data in a plurality of storage units (207a to 207c).
A device (100) for processing data adapted for being converted between an analog format and a digital format, the device (100) comprising a scrambling unit (101) adapted for scrambling the data based on at least a part of the data to thereby decorrelate the data in the analog format with respect to the data in the digital format.
A signal processing device (100) comprising an adjustment unit (103) for adjusting a time duration of each of a plurality of signals (101, 110) individually in accordance with an amplitude of the respective signal (101, 110) to thereby generate calibrated signals (104, 111), and a combining unit (120) for combining the calibrated signals (104, 111).
A time-to-digital converter (110) comprising at least one chain of delay elements (126.1,..., 126.N), wherein a status of said chain of delay elements (126.1,..., 126.N) represents a digital signal relating to a time interval to be converted, wherein said time- to-digital converter (110) comprises means (156) for providing trigger signals (154) having statistically equally distributed variable positions relative to a pulse forwarded in said chain of delay elements (126.1,..., 126.N), means (130) for capturing said status of said chain of delay elements (126.1,..., 126.N) in response to said calibration trigger signals (154), wherein said status depends on delay times of said delay elements (126.1,..., 126.N), means for determining an actual contribution of at least some of said delay elements (126.1,..., 126.N) to an overall delay of said chain of delay elements (126.1,..., 126.N) on the basis of occurrences of pulse positions in response to said calibration trigger signals (154), and means (164) for taking into account said actual contribution of at least some of said delay elements (126.1,..., 126.N) when converting said time interval into said digital signal (168).
A test system (100) for performing tests on devices under test (DUTs) (180) includes a storage device (140) storing test data (120) for performing the tests on the DUTs (180), a shared processor (110) for generating the test data (120), storing the test data (120) in the storage device (140) and generating a test control signal (125) including one or more test instructions for executing the tests, and, for each DUT (180), a dedicated processor (160) configured to receive a test control signal (125) from the shared processor (110), and in response to the test control signal (125), transfer the test data (120) for one of the test instructions to the DUT (180) to execute that test instruction and verify the completion of that test instruction.
A time-to-digital converter (210) comprising at least one chain of delay elements (226.1, 226.2,...), wherein a status of said chain of delay elements (226.1, 226.2,...) represents a digital signal relating to a time interval (t1) to be converted, wherein said time-to-digital converter (210) comprising means (270) for injecting a calibration pulse (t3-t2) of known position and/or known duration in time into said chain of delay elements (226.1, 226.2,...), wherein a first status of said chain of delay elements (226.1, 226.2,...) being expected in response to said calibration pulse (t3-t2), said time-to-digital converter (210) further comprising means for capturing (288, 290) said actual status of said chain of delay elements (226.1, 226.2,...) in response to said calibration pulse (t3-t2), means (281) for calculating a deviation between said expected first status and said actual status, and means (266) for taking into account said deviation when converting said time (t1) interval to said digital signal.
A self-repair system (130) provides resource failure tolerance using an interconnection network (140) that provides interconnection information identifying connections between system resources (110), redundant resources (115) and ports (120) that are connectable to consumers of the system resources (110). A controller (150) identifies both defective system resources (110) and the affected ports (120) connected to the defective system resources (110) from the interconnection network (140). The controller (150) further identifies compatible resources from the system resources (110) and redundant resources (115) that are capable of replacing the defective system resources (110) for each of the affected ports (120) from the interconnection network (140). The controller (150) determines a respective cost associated with each of the compatible resources, and in response to the determined costs, selects at least one of the compatible resources as a replacement resource for each of the defective system resources (110). The controller (150) further configures the interconnection network (140) to connect the replacement resources to the affected ports (120) instead of the defective system resources (110).
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
52.
TESTING DEVICES UNDER TEST BY AN AUTOMATIC TEST APPARATUS HAVING A MULTISITE PROBE CARD
Automated tester apparatus (10) for testing devices (W) includes a probe card (5) to establish contact (30) with the devices under test (W) under the control of prober modules. The probe card (5) is a multisite probe card including a plurality of sites exposed to site malfunctioning. The apparatus includes: - a malfunction detection module for checking malfunctioning of the sites in the multisite probe card (5), - a control module (1000) configured, if at least one site in the multisite probe card (5) is found to be malfunctioning, for continuing testing by using sites of the probe card (5) that are correctly operating. Continuing testing typically includes: - i) re-testing a set of devices that were already tested by using the site in the probe card (5) found to be malfunctioning; and - ii) testing at least one new set of devices in a lot of devices under test (W) not previously tested.
An apparatus (100) for estimating a duration of a test of a device under test (204) to be performed by a test device (200), the apparatus (100) comprising an input unit (101) adapted for receiving test information indicative of the test to be performed, and a processing unit (102) adapted to estimate the duration of the test of the device under test (204) performed by the test device (200) based on the received test information and based on a model characterizing the test.
A signal processing device (102) comprising a plurality of processing stages (106 to 108), each of the plurality of processing stages (106 to 108) being adapted for applying an input signal to each of at least one item under examination (109) to be coupled to a respective one of the plurality of processing stages (106 to 108), and at least one signal reconditioning unit (116), each of the at least one signal reconditioning unit (116) being adapted for reconditioning the input signal in a signal path between a preceding one of the plurality of processing stages (106) and a subsequent one of the plurality of processing stages (107).
A device (100) for processing data, the device (100) comprising a detection unit (101) adapted for detecting primary data indicative of an environment (102) of a user, a recognition unit (103) adapted for analyzing the detected primary data so as to recognize secondary data assigned to the primary data, and a presentation unit (104) adapted for presenting the secondary data to the user so that the assignment of the secondary data to the primary data is perceivable for the user.
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