An interconnect substrate includes a first interconnect layer, an insulating layer formed on the interconnect layer and containing a filler, a via hole penetrating the insulating layer and reaching an upper surface of the first interconnect layer, and a second interconnect layer filling the via hole and electrically connected to the first interconnect layer, wherein the insulating layer includes a first layer covering the first interconnect layer and a second layer laminated on, and thinner than, the first layer, an amount of the filler in the second layer being smaller than in the first layer, an inner surface of the via hole being inclined relative to a direction perpendicular to the upper surface, an angle of the inner surface of the via hole in the first layer with respect to the upper surface being larger than an angle of the inner surface of the via hole in the second layer.
A wiring board includes a layered structure and a waveguide. The layered structure include multiple insulating layers that are laminated. The waveguide is formed inside the layered structure. The waveguide includes a pair of conductive layers, and multiple conductive pillars. The pair of the conductive layers face each other in a lamination direction of the insulating layers. The multiple conductive pillars are arranged in two rows along a propagation direction of electromagnetic waves between the pair of the conductive layers, and connects the pair of the conductive layers. The respective conductive pillars include multiple connection pads and a via. The connection pads are laminated between the pair of the conductive layers. The via connects the connection pads of adjacent layers, and has a cross-section perpendicular to the lamination direction in a rectangular shape.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
A lead frame has inner leads arranged in a first direction, and each inner lead includes a first main surface parallel to the first direction, an end surface connecting to the first main surface, a first side surface connecting to the first main surface and to the end surface, and a second side surface connected to the first main surface and to the first side surface. In a plan view perpendicular to the first main surface, an angle between a first imaginary straight line including a first line of intersection between the first main surface and the end surface, and a second imaginary straight line including a second line of intersection between the first main surface and the second side surface, is less than 90 degrees on a side of each inner lead.
A wiring board includes a first interconnect structure including a first interconnect layer and a first insulating layer, a second interconnect structure, including a second interconnect layer and a second insulating layer, and laminated on one side of the first interconnect structure, and a third interconnect structure, including a third interconnect layer and a third insulating layer, and laminated on the other side of the first interconnect structure. The second interconnect layer has an interconnect density higher than those of the first and the third interconnect layers. The first insulating layer has a through hole penetrating the first insulating layer, and an electronic component electrically connected to the second interconnect layer is disposed inside the through hole. An embedding resin covering the electronic component is provided inside the through hole, and extends to cover the first insulating layer and fills in between the first and second insulating layers.
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A substrate fixing device includes a ceramic base plate, a ceramic electrostatic chuck having a mounting surface on which a target object to be adsorbed is mounted, and an adhesion layer bonding the base plate and the electrostatic chuck.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
6.
INTERCONNECT SUBSTRATE AND METHOD OF MAKING INTERCONNECT SUBSTRATE
An interconnect substrate includes a first interconnect layer having a surface, the surface including a first region and a second region, an adhesion enhancing film covering the second region, an insulating layer formed on the adhesion enhancing film, a via hole formed through the insulating layer and the adhesion enhancing film to reach the first region, and a second interconnect layer formed on the insulating layer and in contact with the first region through the via hole, wherein a roughness of the first region is higher than a roughness of the second region.
A wiring board includes a core board, a first interconnect structure, a second interconnect structure, and a through-hole. The core board includes an interconnect layer that is formed on an upper surface and a lower surface of a substrate. The first interconnect structure includes an interconnect layer and an insulating layer that are layered on the core board. The second interconnect structure includes an interconnect layer and an insulating layer that are layered on the core board. The through-hole penetrates the insulating layer of the second interconnect structure and the substrate of the core board to a pad that is contained in the interconnect layer of the core board or penetrates the insulating layer of the second interconnect structure, the substrate of the core board, and the insulating layer of the first interconnect structure to a pad that is contained in the interconnect layer of the first interconnect structure.
An optical waveguide device includes a substrate, a first waveguide disposed on or in the substrate, and a second waveguide disposed on a first surface of the substrate, wherein the second waveguide includes a core and a cladding covering the core, wherein throughout an entirety of a predetermined region, a portion of the core overlaps the first waveguide when viewed from a direction normal to the first surface, in wherein the predetermined region, the core has a bottom surface in contact with the first surface and a convex surface connected to the bottom surface, and wherein the core includes a portion whose thickness gradually decreases from a widthwise center to widthwise ends in a transverse cross-sectional view.
A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate, a first semiconductor element mounted on an upper surface of the first substrate and an upper surface of the second substrate so as to extend across the first substrate and the second substrate, a second semiconductor element mounted on the upper surface of the second substrate, and a third semiconductor element mounted on a lower surface of the second substrate. The third semiconductor element overlaps the second semiconductor element in plan view.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A semiconductor device includes a semiconductor element provided on a wiring board including a first signal pad, and a pair of first ground pads spaced apart from the first signal pad, arranged so as to sandwich the first signal pad and oppose each other in a plan view. The semiconductor element includes a second signal pad, and a pair of second ground pads spaced apart from the second signal pad and sandwiching the second signal pad and oppose each other. The second signal pad includes a first bump electrically connected to the first signal pad through a first bonding part. The pair of second ground pads includes second and third bumps. The third bump is closer to the second signal pad than the second bump, and at least the second bump is electrically connected to each of the pair of first ground pads through a second bonding part.
A heat storage device includes a ceramic part having a closed space therein, a latent heat storage provided inside the closed space, an electric heater provided inside the ceramic part and configured to heat the latent heat storage, a heat insulating member covering the ceramic part, and a power supply part configured to supply electric power to the electric heater.
A stacked wiring substrate includes a first wiring substrate and a second wiring substrate mounted on the first wiring substrate. The first wiring substrate includes a first wiring layer, a first insulating layer covering the first wiring layer, a second wiring layer stacked on an upper surface of the first insulating layer and electrically connected to the first wiring layer, a second insulating layer stacked on the upper surface of the first insulating layer and covering the second wiring layer, and a first electrode pad stacked on an upper surface of the second insulating layer and electrically connected to the second wiring layer. The second wiring substrate includes a wiring structure having a higher wiring density than the first wiring substrate, and a second electrode pad connected to the first electrode pad. The second insulating layer is thinner than the first insulating layer.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A wiring board includes a first wiring structure and a second wiring structure. The first wiring structure includes: a mounting surface for a semiconductor element; and a back surface on an opposite side of the mounting surface. The second wiring structure is formed on the back surface of the first wiring structure. The first wiring structure further includes thin film layers, a cavity, an electronic component, and a filling resin layer. The thin film layers include laminated wiring layers and laminated insulating layers. The cavity is formed by cutting out at least one of the insulating layers of the thin film layers in a direction toward the mounting surface. The electronic component is located in the cavity. The filling resin layer fills the cavity, and further covers the electronic component.
A wiring board includes a first insulating layer, a first interconnect layer formed on the first insulating layer, a second insulating layer formed on the first interconnect layer, an opening penetrating the second insulating layer and exposing an upper surface of the first interconnect layer, and a second interconnect layer that is an outermost interconnect layer disposed inside the opening and electrically connected to the first interconnect layer.
A wiring board includes a first wiring structure and a second wiring structure. The first wiring structure includes a mounting surface for a semiconductor element and a back surface on an opposite side of the mounting surface. The second wiring structure is formed on the back surface of the first wiring structure. The second wiring structure includes a reinforcing insulating layer, a cavity, an electronic component, and a filled resin layer. The reinforcing insulating layer is formed on the back surface of the first wiring structure. The cavity is formed by cutting off the reinforcing insulating layer in a direction toward the back surface of the first wiring structure. The electronic component is arranged in the cavity. The filled resin layer is filled in the cavity and covers the electronic component.
A semiconductor device includes a wiring substrate and a semiconductor element. The wiring substrate includes an insulating layer and a wiring layer. The semiconductor element includes a first electrode and is fixed to the wiring substrate with the first electrode facing the wiring substrate. The wiring layer includes a first wiring pattern on a surface of the insulating layer on the opposite side from the semiconductor element. The wiring layer further includes a first via interconnect. The first via interconnect is formed of a sintering material of metal and fills in a first through hole piercing through the first wiring pattern and the insulating layer to expose the first electrode. The first via interconnect electrically connects the first wiring pattern and the first electrode.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A wiring substrate includes an insulating layer and a protruding electrode. The insulating layer has a recess formed in the upper surface of the insulating layer. The protruding electrode is partly buried in the insulating layer to protrude in the recess. The width of the protruding electrode is constant in a sectional view of the protruding electrode. The upper surface of the protruding electrode is positioned lower than the upper surface of the insulating layer.
A semiconductor apparatus includes three or more semiconductor devices connected in parallel with each other and an interconnect substrate arranged on the semiconductor devices, wherein the semiconductor devices have respective control electrodes and are switched by a voltage applied to the control electrodes, wherein the interconnect substrate includes an insulating layer and a first interconnect pattern arranged on an opposite side of the insulating layer from the semiconductor devices and connecting the control electrodes of the semiconductor devices, wherein the first interconnect pattern includes a same number of interconnects of equal length as the semiconductor devices, and a voltage input point configured to receive a voltage applied to the control electrodes via the interconnects of equal length, and wherein the control electrodes of the semiconductor devices are connected to the voltage input point only by the interconnects of equal length, which extend in different directions from the voltage input point.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A wiring substrate includes a first wiring layer, a first insulating layer, and a second wiring layer. The first insulating layer covers the first wiring layer. The second wiring layer is formed on an upper surface of the first insulating layer and is electrically connected to the first wiring layer. The upper surface of the first insulating layer includes a first roughened surface, and a second roughened surface having a greater roughness than the first roughened surface. The second roughened surface includes a wrinkle pattern resulting from buckling. A volume percent of the first wiring layer located in a first region that overlaps the first roughened surface in plan view is greater than a volume percent of the first wiring layer located in a second region that overlaps the second roughened surface in plan view.
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
20.
LEAD FRAME, SEMICONDUCTOR DEVICE, AND LEAD FRAME MANUFACTURING METHOD
A lead frame includes a lead, a connection portion, and a plating film. The lead includes an upper surface and a lower surface, and a width of the upper surface is larger than a width of the lower surface. The connection portion is arranged on the upper surface and serves as a connection portion for a semiconductor element. The plating film covers a surface of the lead.
A wiring board includes an insulating layer and a connection terminal that is formed on a surface of the insulating layer. The connection terminal includes a metal pad that is embedded in the insulating layer and a plated layer that covers an end face of the pad that is exposed on the surface of the insulating layer. The end face of the pad is depressed in a concave surface form to a position lower than the surface of the insulating layer and a surface of the plated layer on a side opposite to a surface making contact with the end face of the pad is depressed in the concave surface form toward the end face.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
A latent heat storage unit includes a ceramic part made of a polycrystalline body and having a closed space formed therein and a metal part provided in the closed space and containing boron, wherein a melting point of the metal part is 1100° C. or higher.
A latent heat storage unit includes a ceramic part made of a polycrystalline body and having a closed space formed therein and a metal part provided in the closed space and containing 50% or more silicon by mass.
A wiring substrate includes a first wiring layer, a first insulating layer covering the first wiring layer, a second wiring layer formed on the first insulating layer and connected to the first wiring layer, a second insulating layer formed on the first insulating layer, and a third wiring layer formed on the second insulating layer and connected to the second wiring layer. The second wiring layer includes a first connection pad connectable to a first electronic component, and a wiring pattern connected to the third wiring layer. The second insulating layer includes an open portion extending through the second insulating layer in a thickness-wise direction and exposing the first connection pad and part of the first insulating layer. The third wiring layer includes a second connection pad connectable to a second electronic component. The first wiring layer includes wiring that electrically connects the first and second connection pads.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
An electrostatic chuck includes a first base body, a first adhesive layer, a second base body stacked on the first base body with the first adhesive layer interposed therebetween, and an electrostatic electrode embedded in the second base body. The first base body is made of aluminum oxide ceramics. The second base body is made of aluminum oxide ceramics with a higher purity of aluminum oxide than that of the first base body.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A substrate fixing device includes a base plate, an adhesive layer provided on the base plate, a heat insulating layer provided on the adhesive layer, and an electrostatic chuck provided on the heat insulating layer. The electrostatic chuck includes a base and an electrostatic electrode provided in the base, and the heat insulating layer has a lower thermal conductivity than the base and the adhesive layer.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
An optical module includes a first cladding layer formed on a substrate, a first groove extending through the first cladding layer in a thickness direction, and a second cladding layer formed on the first cladding layer. The optical module further includes a second groove extending through the first cladding layer and the second cladding layer in the thickness direction, a silicon photonics component mounted on the first cladding layer, and a single-mode fiber fitted into the second groove. The silicon photonics component includes a main body and an optical axis located below the main body. The lower surface of the main body is in contact with the upper surface of the first cladding layer. The optical axis is retained within the first groove. A circumferential surface of the single-mode fiber is in contact with a bottom surface of the second groove and a wall surface of the second groove.
A leadframe includes a die pad having a surface that includes a region for mounting a semiconductor chip, and a flat film and a roughened film on the surface of the die pad. In a plan view, the flat film is along and outside the outer edge of the region and the roughened film is inside and outside the flat film. The roughened film includes a roughened plating film and a plating film on the roughened plating film. The plating film follows the shape of the roughened plating film to have a roughened surface. The flat film has a flatter surface than the roughened film, and includes a first metal film formed of the same material as the roughened plating film and a second metal film on the first metal film. The second metal film is an alloy film including metals of the roughened plating film and the plating film.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A terminal structure includes a first wiring layer, an insulation layer covering the first wiring layer, an opening extending through the insulation layer, via wiring formed in the opening, a second wiring layer electrically connected to the via wiring on the insulation layer, a protective metal layer formed on the second wiring layer, a solder layer formed on the protective metal layer, and an intermetallic compound layer formed between the protective metal layer and the solder layer. The protective metal layer includes a projection projecting further outward from a side surface of the second wiring layer. The intermetallic compound layer covers only the upper surface of the protective metal layer. The solder layer covers only an upper surface of the intermetallic compound layer and exposes the side surfaces of the intermetallic compound layer, the protective metal layer, and the second wiring layer.
A wiring board includes a first insulating layer provided on an interconnect layer, a second insulating layer provided on the first insulating layer, a first opening formed in the first insulating layer and reaching the interconnect layer, a second opening formed in the second insulating layer and having a lower end connected to an upper end of the first opening, a third opening formed in the second insulating layer and having a lower end connected to an upper end of the second opening, and a connection terminal formed inside the first, second, and the third openings, and making contact with an upper surface of the interconnect layer. The lower end diameter of the second opening is equal to the upper end diameter of the first opening, and the lower end diameter of the third opening is larger than the upper end diameter of the second opening.
A wiring substrate includes a metallic plate, a first through-hole, an insulating layer, a second through-hole, a wiring layer, and feedthrough wiring. The first through-hole is formed in the metallic plate. The insulating layer covers both surfaces of the metallic plate and an inner wall surface of the first through-hole. The second through-hole is formed on an inner side of the insulating layer in the first through-hole. The wiring layer is laminated on the insulating layer on both surface sides of the metallic plate. The feedthrough wiring is formed in the second through-hole, and connects the wiring layer disposed on both surface sides of the metallic plate. The metallic plate includes a bent portion that is bent in a bottomed box shape and that forms a space on one of the surface sides of the metallic plate.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
32.
WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
A wiring board includes an insulating layer, a connection terminal, and a wiring structure. The insulating layer includes a first surface and a second surface on an opposite side of the first surface, and includes an opening portion that is formed so as to penetrate through the first surface and the second surface. The connection terminal is arranged in the opening portion. The wiring structure is connected to the connection terminal. The connection terminal includes a pad that is formed in the opening portion and that has a bottom surface located on a same plane as the second surface of the insulating layer, and a surface treatment layer that covers the pad. The pad protrudes from the first surface of the insulating layer, and the surface treatment layer forms a gap between the surface treatment layer and an inner wall surface of the opening portion.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
An optical waveguide device includes a first cladding layer, a core layer disposed on the first cladding layer and forming cores, and a second cladding layer disposed on the first cladding layer and selectively covering the core layer, wherein a first region not covered by the second cladding layer is provided on the first cladding layer, wherein the cores include signal cores, one end of which is disposed in the first region, for inputting or outputting signal light, and an inspection core, both ends of which are exposed at an outer perimeter surface of the optical waveguide device, for inputting or outputting inspection light, and wherein the inspection core is made of a same material as the signal cores, and a cross-sectional shape of the inspection core in a short-hand direction is identical to a cross-sectional shape of each of the signal cores in a short-hand direction.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
34.
CERAMIC SUBSTRATE, METHOD OF MANUFACTURING THE SAME, ELECTROSTATIC CHUCK, SUBSTRATE FIXING DEVICE, AND SEMICONDUCTOR DEVICE PACKAGE
A ceramic substrate includes a base, and a conductor pattern incorporated in the base. The base is a ceramic, and the conductor pattern includes, as a main component, a solid solution of a body-centered cubic lattice structure in which nickel and manganese are solid solved in tungsten, a solid solution of a body-centered cubic lattice structure in which nickel and niobium are solid solved in tungsten, or a solid solution of a body-centered cubic lattice structure in which nickel and indium are solid solved in tungsten.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
C04B 35/10 - Shaped ceramic products characterised by their compositionCeramic compositionsProcessing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxides based on aluminium oxide
C04B 41/00 - After-treatment of mortars, concrete, artificial stone or ceramicsTreatment of natural stone
An optical waveguide device includes an interconnect substrate, a first cladding layer disposed on the interconnect substrate, a core layer disposed on the first cladding layer, a second cladding layer disposed on the first cladding layer and selectively covering the core layer, and one or more elevated supports disposed on the first cladding layer and apart from the core layer, wherein one longitudinal-direction end of the core layer and the elevated supports are situated in a component mounting region exposed from the second cladding layer, and wherein the elevated supports are made of a same material as the core layer and have a same thickness as the core layer.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/42 - Coupling light guides with opto-electronic elements
An optical waveguide device includes an optical waveguide substrate, and an optical semiconductor element including a silicon waveguide and mounted on the optical waveguide substrate. The optical waveguide substrate includes a substrate, a first cladding layer formed on the substrate, a first core layer formed on the first cladding layer, and a second cladding layer formed on the first cladding layer and the first core layer. The silicon waveguide includes a second core layer optically coupled to the first core layer, and the optical semiconductor element is fixed to the substrate by the second cladding layer.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
37.
OPTICAL WAVEGUIDE DEVICE AND METHOD OF MAKING THE SAME
An optical waveguide device includes an optical waveguide substrate including a first cladding layer disposed on a support, a core layer disposed on the first cladding layer, and a second cladding layer selectively covering the core layer, and a silicon photonic chip including a silicon substrate and a silicon waveguide disposed on one side of the silicon substrate, wherein part or all of a thickness of one end of the silicon waveguide is embedded in the core layer exposed from the second cladding layer, wherein a thickness of the core layer in a place covered with the silicon substrate is less than that of the core layer in a place not covered with the silicon substrate, and wherein a width of the core layer at a point of contact with the silicon substrate is wider than that of the core layer in a place covered with the second cladding layer.
G02B 6/036 - Optical fibres with cladding core or cladding comprising multiple layers
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
38.
OPTICAL WAVEGUIDE MOUNTED SUBSTRATE AND METHOD OF MAKING THE SAME
An optical waveguide mounted substrate includes an interconnect substrate having a recess that opens on a first surface thereof, and an optical waveguide device including: an optical waveguide substrate including a support and a core layer disposed on the support; and a silicon photonic chip including a silicon substrate and a silicon waveguide disposed on the silicon substrate, the silicon waveguide being optically coupled with the core layer, wherein the optical waveguide substrate is mounted on the interconnect substrate such that the core layer faces away from the recess and at least a part of a thickness of the support is situated inside the recess.
A wiring board has a built-in post wall waveguide having a region surrounded by two mutually opposing conductors and first and second post walls connecting the two conductors and serving as a transmission path for electromagnetic waves. The conductors oppose each other with insulating layers interposed therebetween. The first post wall has first columnar portions, formed by a laminate of via interconnects penetrating the insulating layers, arranged at predetermined intervals in a first direction in which the electromagnetic waves are transmitted. The second post wall has second columnar portions similar to the first columnar portions. In a cross sectional view taken in a second direction perpendicular to the first direction, an interval between adjacent via interconnects in one of the insulating layers not in contact with the conductor is wider than an interval between adjacent via interconnects in two of the insulating layers in contact with the two conductors, respectively.
A lead frame includes a die pad having an upper surface and a lower surface, and a curved part disposed outside the die pad in a bottom view, and having one end connected to an outer edge of the die pad. The curved part has a groove that opens toward the lower surface of the die pad, and the curved part is curved toward the upper surface of the die pad at the groove.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
A semiconductor device includes a wiring substrate, a semiconductor chip, and a sealing resin. The semiconductor chip is mounted on the wiring substrate. The sealing resin is filled in a gap between the wiring substrate and the semiconductor chip and extends to an upper surface of the semiconductor chip. The semiconductor chip includes a groove that is formed in an outer peripheral area that is located around a circumference of a predetermined area disposed on the upper surface of the semiconductor chip and that includes a peripheral edge of the upper surface of the semiconductor chip, and that captures an extending portion of the sealing resin extends.
A wiring substrate includes a first wiring layer, an insulation layer covering a side surface of the first wiring layer and exposing part of the first wiring layer, and a second wiring layer formed on the first wiring layer exposed from the insulation layer. The insulation layer includes a resin and a filler. The insulation layer includes an upper surface having a structure in which the filler is exposed from the resin. The second wiring layer includes a first metal film, covering the upper surface of the insulation layer and the wiring layer exposed from the insulation layer, and a metal layer, formed above the first metal film. The first metal film is formed from a CuNiTi alloy and has a Ni content rate of 5 wt % or greater and 30 wt % or less and a Ti content rate of 5 wt % or greater and 15 wt % or less.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
43.
OPTICAL WAVEGUIDE DEVICE AND MANUFACTURING METHOD THEREOF
An optical waveguide device includes a substrate, a first cladding layer disposed on the substrate, a core layer disposed on the first cladding layer, and a recess formed in the core layer along a longitudinal direction of the core layer and opened on a first surface of the core layer facing away from the first cladding layer.
A semiconductor device includes a wiring substrate, a semiconductor chip including conductive pillars, and a conductive bonding material. The wiring substrate includes electrode pads and via lands electrically connected to each other at a surface of the wiring substrate. A through hole and a cut continuous with the through hole are formed in each electrode pad. In a plan view perpendicular to the surface, the cut of a first electrode pad extends toward a space between a second electrode pad and a third electrode pad adjacent to each other and adjacent to the first electrode pad, a first via land and a second via land adjacent to each other and adjacent to the first electrode pad, or a fourth electrode pad and a third via land adjacent to each other and adjacent to the first electrode pad. The conductive bonding material bonds the electrode pads and the conductive pillars.
A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipating plate arranged above the semiconductor element, and an encapsulation resin that encapsulates the semiconductor element and fills a space between the wiring substrate and the heat dissipating plate and a space between the semiconductor element and the heat dissipating plate. The heat dissipating plate includes a main body arranged overlapping the semiconductor element in plan view, and a lead projecting outward from the main body. The lead is thinner than the main body. The lead includes an upper surface covered by the encapsulation resin, and an outer side surface located at an outer edge of the semiconductor device and exposed from an outer side surface of the encapsulation resin. The main body includes an upper surface exposed from an outer surface of the encapsulation resin.
H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
A substrate fixing device includes a base plate, a heating portion provided on the base plate, a metal layer provided on the heating portion, and an electrostatic chuck provided on the metal layer. In the substrate fixing device, the metal layer is made of the same material as the base plate.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
47.
WAVEGUIDE SUBSTRATE AND METHOD OF MAKING WAVEGUIDE SUBSTRATE
A waveguide substrate includes a core substrate through which first through holes and second through holes are formed, a first conductive layer covering an inner wall of the first through holes and both sides of the core substrate, a second conductive layer covering an inner wall of the second through holes and both sides of the core substrate, a first filler material filling a space surrounded by the first conductive layer inside the first through holes, a second filler material filling a space surrounded by the second conductive layer inside the second through holes, and third conductive layers disposed on respective sides of the core substrate, the third conductive layers overlapping the first and second through holes in a plan view, and the third conductive layers being electrically connected to the first and second conductive layers, wherein the second conductive layer overlaps the first through holes in the plan view.
A wiring substrate includes: a wiring layer; an insulating layer that is laminated on the wiring layer; an opening portion that passes through the insulating layer to the wiring layer; and an electric conductor film that is formed at the opening portion of the insulating layer. A surface of the insulating layer includes a smoothed portion that is not covered by the electric conductor film, and a roughened portion that includes an inner wall surface of the opening portion covered by the electric conductor film and that have surface roughness that is greater than surface roughness of the smoothed portion.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A wiring board includes a wiring layer, an insulating layer, an oxide thin film, a seed layer, and a conductive layer. The insulating layer is laminated on the wiring layer and includes an opening portion that penetrates until the wiring layer. The oxide thin film is formed on a surface of the insulating layer including an inner wall surface of the opening portion. The seed layer is made of metal and that is laminated on the oxide thin film at a position of the opening portion. The conductive layer is formed on the seed layer. The oxide thin film is a thin film that has a thickness of 1 to 100 angstroms and covers a surface of the insulating layer including the inner wall surface of the opening portion and a surface of the wiring layer exposed from a bottom portion of the opening portion.
H05K 3/14 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material
A wiring board includes an insulating layer covering upper and side surfaces of a first interconnect layer, a via hole penetrating the insulating layer and reaching the first interconnect layer, a second interconnect layer filling the via hole and extending on the insulating layer, and a cavity provided in the first interconnect layer, communicating with the via hole and extending outside than a lower end of an inner side surface of the via hole in a plan view. The second interconnect layer includes a first seed layer provided on the insulating layer, a second seed layer continuously covering upper and inner side surfaces of the first seed layer, the inner side surface of the via hole, and surfaces of the insulating layer and the first interconnect layer exposed inside the cavity, and an electrolytic plating layer provided on the second seed layer thicker than the first seed layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
A wiring board includes an insulating layer, first and second pads provided on the insulating layer and including a first surface in contact with the insulating layer, a second surface opposite to the first surface, and a side surface connecting the first and second surfaces, respectively, and a protective insulating layer provided above the insulating layer. The first and second pads have a portion exposed inside an opening in the protective insulating layer. The first pad has a portion opposing the second pad without the protective insulating layer interposed between the first and second pads. A region of the second surface of the first and second pads exposed from the protective insulating layer is covered with a plating layer. A region of the side surface of the first and second pads exposed from the protective insulating layer is exposed from the plating layer.
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
An evaporator includes a first metal layer having a first inner surface and a first outer surface, a second metal layer having a second inner surface bonded to the first inner surface and a second outer surface, and a porous body provided between the first outer surface and the second outer surface. The porous body includes first bottomed holes provided in the first inner surface, second bottomed holes provided in the second inner surface, a fine pore, a first groove portion provided in the first inner surface, and a second groove portion provided in the second inner surface. The first groove portion and the second groove portion are provided not to overlap each other in a plan view. The first outer surface and the second outer surface serve as an outer surface of the evaporator.
F28D 15/02 - Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls in which the medium condenses and evaporates, e.g. heat-pipes
F28D 15/04 - Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls in which the medium condenses and evaporates, e.g. heat-pipes with tubes having a capillary structure
A substrate fixing device includes a base plate having a first surface in which a plurality of first bottomed holes are formed, an electrostatic chuck mounted on the first surface of the base plate and having a second surface facing the first surface, the second surface being formed therein with a plurality of second bottomed holes each connected to each of the first bottomed holes, and a plurality of fixing members each fit into one first bottomed hole and one second bottomed hole.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A myoelectric sensor includes a wearable portion configured to be worn on a living body and deformable in response to deformation of the living body, an electrode sheet disposed on a surface of the wearable portion, and fixing members configured to fix the electrode sheet to the surface, wherein the electrode sheet includes a plurality of bioelectrode units, and interconnect members each electrically connecting two bioelectrode units among the plurality of bioelectrode units, wherein the interconnect members are located between the wearable portion and the fixing members, and the fixing members press the interconnect members to the surface.
A wiring substrate includes a first insulation layer, a first wiring layer including a pad formed on an upper surface of the first insulation layer, a second insulation layer formed on the upper surface of the first insulation layer to cover the first wiring layer, a first hole extending through the second insulation layer in a thickness-wise direction and partially exposing an upper surface of the pad, a second hole formed in the second insulation layer to be continuous with the first hole and widening a bottom opening of the first hole and entirely exposing a side surface of the pad in a thickness-wise direction, a via wiring filling the first hole and the second hole, and a second wiring layer formed on an upper surface of the second insulation layer integrally with the via wiring. The second hole partially exposes the upper surface of the first insulation layer.
An interconnect substrate includes an insulating layer, an electrode disposed on the insulating layer and having a first surface not covered with the insulating layer, and an external connection terminal disposed on the first surface of the electrode, wherein the electrode has a recess in the first surface, wherein the external connection terminal includes a first conductor filling the recess and a second conductor disposed on the first conductor, and a melting point of the first conductor is higher than a melting point of the second conductor, and wherein a metal material of the electrode is different from a metal material of the first conductor.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
An optical connection structure includes a first silicon photonic chip having a first lateral surface, a second silicon photonic chip having a second lateral surface that faces the first lateral surface, and an optical waveguide disposed astride a gap between the first silicon photonic chip and the second silicon photonic chip. The first silicon photonic chip includes a first silicon substrate and a first silicon waveguide disposed over the first silicon substrate. The second silicon photonic chip includes a second silicon substrate and a second silicon waveguide disposed over the second silicon substrate. The optical waveguide includes a first cladding filling a space between the first lateral surface and the second lateral surface, a core disposed on the first cladding and covering one end of the first silicon waveguide and one end of the second silicon waveguide, and a cladding covering the core.
An interconnect substrate includes an interconnect layer, an insulating layer covering the interconnect layer, an electrode disposed on an upper surface of the interconnect layer and protruding from an upper surface of the insulating layer, and a groove formed in the upper surface of the insulating layer around the electrode, wherein the electrode includes a first portion whose side surface is covered with the insulating layer, a second portion whose entire side surface is located outside the insulating layer, the second portion being partially located inside the groove and partially protruding above the upper surface of the insulating layer, and a metal layer covering both an upper surface of the second portion and the entire side surface of the second portion.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
An electronic apparatus includes a lead frame, a wiring board, and a sealing resin. The wiring board mounts an electronic component boded to the lead frame. The sealing resin seals the lead frame, the electronic component, and the wiring board. The lead frame includes a first surface bonded to the electronic component and a second surface located opposite to the first surface and exposed from the sealing resin. The wiring board includes an insulating base material, a wiring layer formed on a first surface of the insulating base material, and an adhesive layer laminated on a second surface of the insulating base material on an opposite side of the first surface and including a second surface to which the electronic component is bonded. The first surface of the insulating base material and the second surface of the adhesive layer are covered by the sealing resin.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
An electronic apparatus includes a first metal layer, a component mounting substrate, a second metal layer, and sealing resin. The first metal layer includes a first mounting portion and a second mounting portion. The component mounting substrate includes an electronic component mounted on the first mounting portion. The second metal layer is arranged on the first metal layer such that the second metal layer and the second mounting portion sandwich a driving component. The sealing resin fills a space between the first metal layer and the second metal layer, covers the component mounting substrate, and seals the electronic component and the driving component. The first metal layer includes a terminal portion that protrudes from the first mounting portion toward the second metal layer. The second metal layer includes a wire portion that comes into contact with the terminal portion and connects the second metal layer to the first mounting portion.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A wiring board includes a first interconnect layer, an insulating layer covering the first interconnect layer, a via interconnect penetrating the insulating layer, and a second interconnect layer provided on an upper surface of the insulating layer and electrically connected to the first interconnect layer through the via interconnect. The via interconnect includes a first seed layer that covers an inner wall surface of a via hole penetrating the insulating layer, and an upper surface of the first interconnect layer exposed inside the via hole, and a first electrolytic plating layer provided on the first seed layer. The second interconnect layer includes a second seed layer provided on the upper surface of the insulating layer and on an upper surface of the first electrolytic plating layer, and a second electrolytic plating layer provided on the second seed layer.
H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
An optical connector includes a holding member to which a waveguide member is fixed. The waveguide member includes a first clad layer having a longitudinal direction and a first surface, a core layer provided on the first surface, a second clad layer provided on the first surface and covering the core layer, and first and second contact layers provided on the first surface, sandwiching the core layer in a cross sectional view perpendicular to the longitudinal direction and exposed from the second clad layer. The first contact layer includes a second surface making contact with the first surface, and a third surface opposite to the second surface, and the second contact layer includes a fourth surface making contact with the first surface, and a fifth surface opposite to the second surface. The first clad layer includes sixth and seventh surfaces forming obtuse angles with the first surface.
A wiring substrate includes a first wiring layer, an insulation layer covering the first wiring layer, a first through hole extending through the insulation layer and exposing part of the upper surface of the first wiring layer, and a second through hole arranged adjacent to the first through hole. The second through hole extends through the insulation layer in the thickness-wise direction and exposes part of the upper surface of the first wiring layer. A bottom portion of the first through hole is in communication with a bottom portion of the second through hole through a communication hole. A via wiring fills the first through hole, the second through hole, and the communication hole. A second wiring layer is formed integrally with the via wiring on the insulation layer.
A tray mounted on an electrostatic chuck includes an accommodation recess configured to accommodate a substrate, a bottom plate portion placed on the electrostatic chuck, a coating film layer made of a material different from the bottom plate portion and formed on an upper surface of the bottom plate portion, and an opening portion penetrating the coating film layer in a thickness direction. The accommodation recess includes an inner side surface of the opening portion and an upper surface of the bottom plate portion exposed from the opening portion. The coating film layer has a multilayer structure including a first coating film having higher plasma resistance than the bottom plate portion and a second coating film laminated on an upper surface of the first coating film and having higher plasma resistance than the first coating film. The first coating film is thicker than the second coating film.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
65.
INTERCONNECT SUBSTRATE AND METHOD OF MAKING THE SAME
A method of making an interconnect substrate includes forming a first insulating layer containing a filler and covering a first interconnect layer, forming a via hole in the first insulating layer by laser processing, the via hole exposing the first interconnect layer, performing a heat treatment, plasma processing, and a desmear process in this order with respect to the first insulating layer, and forming, after the desmear process, a second interconnect layer including both an interconnect pattern formed on an upper surface of the first insulating layer and a via interconnect formed in the via hole.
A wiring substrate includes a metal layer, a resin layer, and a wiring structure. The resin layer is laminated on the metal layer. The wiring structure includes a wiring layer and an insulating layer that are laminated on the resin layer, and in which the wiring layer is located by being brought into contact with the resin layer.
A semiconductor device includes a laminate including a semiconductor element, an insulating substrate on a first surface of the semiconductor element, an interconnect on the insulating substrate, and an interconnect member on a second surface of the semiconductor element. The interconnect is electrically connected to a first electrode in the first surface of the semiconductor element through a through hole in the insulating substrate. The interconnect member is electrically connected to a second electrode in the second surface of the semiconductor element. The semiconductor device further includes first and second elastic terminals holding the laminate therebetween. The first terminal includes a bulge that engages with a depression in the interconnect. The second terminal contacts the interconnect member. The semiconductor device further includes a fixing member fixing the first terminal and the second terminal while electrically isolating the first terminal and the second terminal from each other.
A heat conductor includes a base including a forest of carbon nanotubes, a first solder layer on a first surface of the base, and a second solder layer on a second surface of the base opposite from the first surface. The second solder layer is electrically connected to the first solder layer via the carbon nanotubes.
A stem includes a base member and a block member. The base member includes a main body portion and a columnar portion that rises from one surface of the main body portion. The block member incudes a device mounting surface, on which a semiconductor device is able to be mounted, and is fixed to the one surface of the main body portion in a state in which the block member is pressed against the columnar portion.
A cap housing includes a tubular part, and a top plate, extending from one end toward a center axis of the tubular part, and having an opening. The top plate includes an annular first surface facing the opening, an annular second surface continuous with the first surface and perpendicular to the center axis, and an annular third surface continuous with the second surface and inclined from the second surface. The third surface is inclined from the second surface so as to separate farther away from a center of the tubular part in a direction along the center axis as the third surface approaches the tubular part. A second size of the second surface on a straight line perpendicular to the center axis and passing through the center axis is smaller than or equal to a first size of the first surface in a direction along the center axis.
An evaporator includes a first metal layer having a first inner surface and a first outer surface, a second metal layer having a second inner surface and a second outer surface, and a porous body provided between the first outer surface and the second outer surface. The porous body includes a first bottomed hole provided in the first inner surface, a second bottomed hole provided in the second inner surface, a first fine pore, wherein the first bottomed hole and the second bottomed hole partially communicate with each other through the first fine pore, a first groove portion provided in the first inner surface and configured to communicate with the first bottomed hole, and a second groove portion provided in the second inner surface and configured to communicate with the second bottomed hole. The first outer surface and the second outer surface serve as an outer surface of the evaporator.
F28D 15/02 - Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls in which the medium condenses and evaporates, e.g. heat-pipes
F28D 15/04 - Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls in which the medium condenses and evaporates, e.g. heat-pipes with tubes having a capillary structure
A heat spreader includes a metal substrate and a plating layer covering a surface of the metal substrate. Multiple depressions and multiple projections are alternately arranged in the surface of the metal substrate covered by the plating layer.
A biological information measurement device includes a sensor unit and a controller. The sensor unit includes an N number of measurement portions. N is a natural number of 3 or greater. The controller acquires an N number of output signals from the measurement portions in a given acquisition order. The controller outputs a shutdown signal having a first level to the measurement portions in accordance with the acquisition order of the output signals. The controller outputs the shutdown signal having a second level to the measurement portions in response to acquisition of a corresponding output signal. When the controller outputs the first-level shutdown signal to the measurement portion having an ordinal number of i in the acquisition order, where i is a natural number of 1 or greater, the controller also outputs the first-level shutdown signal to the measurement portion having an ordinal number of (i+1) in the acquisition order.
A substrate fixing device includes a base plate having a first bonding surface, an electrostatic chuck having a substrate placement surface on which a substrate is placed and a second bonding surface provided on a side opposite to the substrate placement surface, and configured to attract and hold the substrate, and an adhesive layer configured to bond the first bonding surface of the base plate and the second bonding surface of the electrostatic chuck. The electrostatic chuck includes a recess provided in the second bonding surface, an electronic component accommodated in the recess, and a layer having a filling portion configured to fill the recess and a protruding portion protruding from the recess and having a tip end in contact with the first bonding surface.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A semiconductor device includes a first inorganic insulating layer, a metal post embedded in the first inorganic insulating layer, a semiconductor chip mounting part stacked on the first inorganic insulating layer, and a second inorganic insulating layer. The metal post has first and second end faces that are exposed in the first and second opposite surfaces, respectively, of the first inorganic insulating layer. The semiconductor chip mounting part has first and second opposite surfaces and a side surface connecting the first and second opposite surfaces of the semiconductor chip mounting part. The first surface of the semiconductor chip mounting part contacts the second surface of the first inorganic insulating layer. The second inorganic insulating layer covers the entirety of the second surface and the entirety of the side surface of the semiconductor chip mounting part. The second inorganic insulating layer is continuous with the first inorganic insulating layer.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A temperature adjusting member includes a base body, an insulator substrate including a built-in heat-generating element and an opening portion through which a part of the heat-generating element is exposed, an electric wire connected to the heat-generating element through the opening portion, and an adhesive layer bonding the base body and the insulator substrate. The base body includes a through-hole connecting to the opening portion, through which the electric wire passes. The adhesive layer has a first part between the base body and the insulator substrate, and a second part filling the through-hole.
H05B 3/32 - Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible heating conductor mounted on insulators on a metallic frame
77.
WIRING BOARD ASSEMBLY, WIRING BOARD, AND WIRING BOARD MANUFACTURING METHOD
A wiring board assembly includes a wiring structure and an insulating layer. The insulating layer covers a surface of the wiring structure and includes a slit that exposes a predetermined region on the surface of the wiring structure. An edge portion of the outermost insulating layer corresponding to the edge portion of the slit meanders in a wave-like manner.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A myoelectric sensor array includes a plurality of myoelectric sensors, and a plurality of wiring members each electrically connecting corresponding two adjacent myoelectric sensors among the plurality of myoelectric sensors, wherein each of the plurality of the myoelectric sensors includes a substrate, a pair of myoelectric electrodes provided on the substrate, and a signal processing circuit electrically connected to the pair of myoelectric electrodes and at least one of the wiring members.
An electrostatic chuck includes a base body, and an electrostatic electrode embedded in the base body. The base body is a ceramic. The electrostatic electrode has TixOy, which is an oxide of titanium, as a main component, and an atomic ratio y/x is less than 1.7.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A wiring substrate includes a first insulating layer, a first wiring layer that is provided on the first insulating layer, and a thin film layer that is provided on one of surfaces of the first insulating layer and that includes a second insulating layer that is different from the first insulating layer and a second wiring layer. The thin film layer includes a first pad and a second pad that are provided on an opposite surface of a surface that faces the first insulating layer, a first via that is electrically connected to the first pad, and a second via that is electrically connected to the second pad. The first wiring layer includes thicker than the second wiring layer, and includes a transmission wiring that electrically connects between the first via and the second via.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A substrate with optical waveguide includes an interconnect substrate and an optical waveguide formed on the interconnect substrate, wherein the optical waveguide includes a first cladding layer, a first protrusion formed on the first cladding layer, the first protrusion having an upper surface and an inclined surface connected to, and sloping relative to, the upper surface, a first metal film formed at least on the inclined surface, a core layer formed on the first cladding layer such as to cover part of the first metal film, and a second cladding layer formed on the first cladding layer such as to cover the core layer, wherein in plan view, a perimeter of a first surface region constituted by both the upper surface and the inclined surface does not have a corner where two lines meet, except for a part thereof where the inclined surface meets the first cladding layer.
A connection structural body includes a first connection terminal, a second connection terminal facing the first connection terminal, and a bonding member bonding the first connection terminal and the second connection terminal. The bonding member includes an intermetallic compound layer that is formed by a roughened-surface metal film, structured by deposits of metal piled over one another such that a large number of pores are formed, and a solder layer that is disposed in the pores.
A wiring substrate includes a wiring layer, a protective insulation layer covering the wiring layer, an opening extending through the protective insulation layer and partially exposing an upper surface of the wiring layer, a first plating layer formed inside the opening on the wiring layer that is exposed in the opening, a gap extending between a side surface of the first plating layer and a wall surface of the opening, and a second plating layer entirely covering a surface of the first plating layer in the opening of the protective insulation layer. The first plating layer is formed from nickel or a nickel alloy. The second plating layer is formed from a metal having a higher resistance to oxidation than the metal forming the first plating layer. The second plating layer entirely covers a side surface of the first plating layer that is exposed in the gap.
A wiring board includes a first interconnect structure including a first interconnect layer and a first insulating layer, and a second interconnect structure, including a second interconnect layer and a second insulating layer, and disposed on the first interconnect structure. Interconnect width and spacing of the second interconnect layer are smaller than those of the first interconnect layer. The first insulating layer covers a side surface of the first interconnect layer and exposes an upper surface of the first interconnect layer. The second insulating layer covers the upper surface of the first interconnect layer and an upper surface of the first insulating layer. The first insulating layer and the second insulating layer include a filler. An average grain diameter and a maximum grain diameter of the filler included in the second insulating layer are smaller than those of the filler included in the first insulating layer.
A wiring board includes a first interconnect layer, a first insulating layer covering the first interconnect layer, a second interconnect layer including an interconnect pattern formed on an upper surface of the first insulating layer, and a via interconnect penetrating the first insulating layer and electrically connecting the interconnect pattern and the first interconnect layer, and a second insulating layer laminated on the first insulating layer. The second insulating layer includes a first insulating film laminated on the upper surface of the first insulating layer, and a second insulating film laminated on an upper surface of the first insulating film. The interconnect pattern has a recess in an upper surface thereof located at a position on the via interconnect. The first insulating film covers upper and side surfaces of the interconnect pattern, and fills the recess. The upper surface of the first insulating film is flatter than the interconnect pattern.
An interconnect substrate includes an insulating layer, a dispersion layer, and an interconnect layer, the insulating layer, the dispersion layer, and the interconnect layer being laminated together, wherein the dispersion layer includes a main material and one or more fillers dispersed in the main material, the one or more fillers forming a unique dispersion pattern, and wherein the unique dispersion pattern is identifiable by image recognition from outside of the interconnect substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
An interconnect substrate includes alternately stacked pads and insulating layers, and via interconnects extending through respective ones of the insulating layers, the via interconnects and the pads being alternately stacked in a vertical direction, the pads being electrically connected to each other via the via interconnects, wherein the pads include a first pad disposed on an uppermost one of the insulating layers and electrically connectable to a semiconductor chip, the first pad being an uppermost layer pad, a second pad disposed on a second uppermost one of the insulating layers, and a third pad disposed on a third uppermost one of the insulating layers, and wherein the uppermost one of the insulating layers located between the first pad and the second pad is thicker the second uppermost one of the insulating layers located between the second pad and the third pad.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A substrate fixing device includes a base plate, a heat-generating part provided on the base plate via an adhesive layer, and an electrostatic chuck provided on the heat-generating part and configured to adsorb and hold a target object. The heat-generating part includes a first insulating layer having a first surface and a second surface opposite to the first surface, the first surface being in contact with the electrostatic chuck, a heat-generating element arranged on the second surface of the first insulating layer, and a second insulating layer stacked on the second surface of the first insulating layer and covering the heat-generating element. A through-hole penetrating through the base plate, the adhesive layer, and the second insulating layer and exposing a part of the heat-generating element is provided. A glass transition temperature of the second insulating layer is higher than a glass transition temperature of the first insulating layer.
A laminated wiring board includes a plurality of first wiring boards laminated on one another, a first insulating resin layer disposed between two adjacent first wiring boards among the plurality of first wiring boards, and a second insulating resin layer configured to cover side surfaces of the plurality of first wiring boards.
A laminated wiring board includes a first wiring board, a plurality of second wiring boards disposed side by side and laminated on the first wiring board, a third wiring board laminated on the plurality of second wiring boards, a first insulating resin layer disposed between the first wiring board and the plurality of second wiring boards, and a second insulating resin layer disposed between the plurality of second wiring boards and the third wiring board.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A semiconductor device includes a lower substrate, a first wiring pattern disposed on the lower substrate with a current input terminal, a semiconductor element mounted on the lower substrate with a first electrode electrically connected to the first wiring pattern and a second electrode opposed to the first wiring pattern, an upper substrate disposed on the second electrode, via wirings extending through the upper substrate and connected to the second electrode, a second wiring pattern disposed on the upper substrate and electrically connected to the second electrode via the via wirings, and a current output terminal. The second wiring pattern is electrically connected to the current output terminal and extends from the second electrode toward the current output terminal in plan view. Among the via wirings, first via wirings closest to the current output terminal are larger than second via wirings adjacent to the first via wirings in plan view.
A substrate fixing device includes a base plate, a ceramic plate fixed to the base plate and configured to adsorb a substrate by electrostatic force, and an adhesive layer bonding the base plate and the ceramic plate. The adhesive layer includes a plurality of linear heat transfer bodies arranged adjacent to each other such that a longitudinal direction of each linear heat transfer body is along a stack direction of the ceramic plate and the base plate, and a resin filled between adjacent heat transfer bodies of the heat transfer bodies and bonded to the ceramic plate and the base plate.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A substrate fixing device includes a base plate, a ceramic plate bonded to the base plate via an adhesive layer and configured to adsorb a substrate by electrostatic force, a thermal conduction member arranged in only a central region, which overlaps a central portion of the ceramic plate in a plan view, or in only an outer circumferential region, which overlaps an outer circumferential portion of the ceramic plate in a plan view of at least one of an adhesive surface of the ceramic plate, an adhesive surface of the base plate, or an inside of the adhesive layer, the thermal conduction member having thermal conductivity in a stack direction of the base plate and the ceramic plate member higher than thermal conductivity in a plane direction perpendicular to the stack direction.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A substrate fixing device includes a base plate, a ceramic plate, and a thermal conduction member. The ceramic plate is bonded to the base plate via an adhesive layer, and has an electrode embedded therein for generating heat, and configured to adsorb a substrate by electrostatic force. The thermal conduction member is arranged in at least one of an adhesive surface of the ceramic plate, an adhesive surface of the base plate, and an inside of the adhesive layer, and having thermal conductivity in a stack direction of the base plate and the ceramic plate higher than thermal conductivity in a plane direction perpendicular to the stack direction.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
95.
WIRING BOARD, SEMICONDUCTOR DEVICE, AND WIRING BOARD MANUFACTURING METHOD
A wiring board includes a first wiring layer, an insulating layer that is arranged on the first wiring layer, and a second wiring layer that is arranged on the insulating layer. The first wiring layer includes a first plain layer, an opening that penetrates through the first plain layer, and a reinforcing pad that is arranged in the opening. The second wiring layer includes a second plain layer. The insulating layer includes a reinforcing via that connects the reinforcing pad and the second plain layer.
H05K 3/20 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
A latent heat storage includes a ceramic part, formed of a polycrystalline material, and including a closed space famed therein, and a metal part provided inside the closed space, and including aluminum.
A substrate includes a heat conduction member including a plurality of carbon nanotubes, a first resin layer provided on first ends of the plurality of carbon nanotubes, and a second resin layer provided on second ends of the plurality of carbon nanotubes, the second ends being opposite the first ends, a first metal layer laminated on the first resin layer, and a second metal layer laminated on the second resin layer, wherein neither the first resin layer nor the second resin layer contains a filler, and wherein spaces between the first ends of the plurality of carbon nanotubes are filled with a resin constituting the first resin layer, and spaces between the second ends of the plurality of carbon nanotubes are filled with a resin constituting the second resin layer.
B32B 3/20 - Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shapeLayered products comprising a layer having particular features of form characterised by a discontinuous layer, i.e. apertured or formed of separate pieces of material characterised by an internal layer formed of separate pieces of material of hollow pieces, e.g. tubesLayered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar shapeLayered products comprising a layer having particular features of form characterised by a discontinuous layer, i.e. apertured or formed of separate pieces of material characterised by an internal layer formed of separate pieces of material of pieces with channels or cavities
B32B 15/08 - Layered products essentially comprising metal comprising metal as the main or only constituent of a layer, next to another layer of a specific substance of synthetic resin
A heat conductor includes a first resin layer and a second resin layer each free of a filler, multiple carbon nanotubes extending between the first resin layer and the second resin layer, a first heat transfer layer, and a second heat transfer layer. The first heat transfer layer is on the first resin layer on the side opposite from the carbon nanotubes and has a thermal conductivity higher than the thermal conductivity of the first resin layer. The second heat transfer layer is on the second resin layer on the side opposite from the carbon nanotubes and has a thermal conductivity higher than the thermal conductivity of the second resin layer. The carbon nanotubes have respective first end portions embedded in first resin constituting the first resin layer and have respective second end portions embedded in second resin constituting the second resin layer.
A latent heat storage includes a ceramic part, formed of a polycrystalline material, and including a closed space famed therein, and a metal part provided inside the closed space, and including copper.
A ceramic substrate includes a base body and an electrical conductor pattern embedded in the base body. The base body is a ceramic. The electrical conductor pattern has, as a main component, a solid solution having a body-centered cubic lattice structure in which cobalt and iron are solid-dissolved in tungsten, a solid solution in a body-centered cubic lattice structure in which cobalt and silicon are solid-dissolved in tungsten, a solid solution having a body-centered cubic lattice structure in which cobalt and manganese are solid-dissolved in tungsten, or a solid solution having a body-centered cubic lattice structure in which cobalt and nickel are solid-dissolved in tungsten.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
