Deposit and cure, on a first heat transfer component, a porous organo-silicate material. Fill connected porosity of the deposited and cured porous organo-silicate material with a thermally conductive material. Bond the porous organo-silicate material having the filled connected porosity to a second heat transfer component.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A device includes a photonics chip and a flexible waveguide having a first end connected to the photonics chip and a second end opposite the first end, in which the second end of the flexible waveguide includes a first portion connected to a ferrule module and a second portion connected to the ferrule module. The second portion is stacked vertically over the first portion in the ferrule module.
A semiconductor device includes a metal line (227) having a longitudinal break therein to provide a first portion and a second portion. A first extended via contacts an end of the first portion at a sidewall of the first extended via. A second extended via is offset from the first extended via and contacts an end of the second portion at a sidewall of the second extended via. The first extended via and the second extended via define a space therebetween, and a zero track skip (224) is disposed within the space.
xxxx and the fluorinated gas in the reactor, and a separation component for removing silicon tetrafluoride from a gaseous mixture formed in the reactor. A process of semiconductor manufacturing includes defluorinating exhaust gas using the process. A system for semiconductor manufacturing includes a set of components for carrying out the process.
The present invention provides a semiconductor structure (10). The semiconductor structure (10) includes a first area (810) having a back-end-of-line (BEOL) region that includes a first set of vias (301/302); a metal level (M1) with one metal line (311/312/313) above the first set of vias (301/302); and a second set of vias (321) above the metal level (M1); and a second area (820) having a metal stub (350), where a bottom surface of the metal stub (350) is substantially aligned with a bottom surface of the first set of vias (301/302) and a top surface of the metal stub (350) is substantially aligned with either a top surface of the one metal line (311/312/313) of the metal level (M1) or a top surface of the second set of vias (321), and where the metal stub (350) has a horizontal width that is at least 10 times larger than a width of the one metal line (311/312/313). A method of forming the semiconductor structure (10) is also provided.
A semiconductor integrated circuit (IC) device includes a bottom wire level, a top wire level, a first region with a first vertical dimension between the bottom wire level and the top wire level, and a second region with a second vertical dimension between the bottom wire level and the top wire level that is less than the first vertical dimension. The discrepancy in the vertical dimensions between wiring levels in different regions of the semiconductor IC device may provide desired or optimized capacitance and/or resistance metrics therein and may increase overall semiconductor integrated circuit (IC) device performance.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A method for serving by a distributed communication system a vehicle traveling from an origin to a destination. The distributed communication system comprises an initial set of computer systems. The method comprises: predicting a route of the vehicle from a current location of the vehicle to the destination. Resource information may be used for selecting from the initial set of computer systems a set of computer systems that can provide machine learning based content to the vehicle along the route. A subset of one or more computer systems of the set of computer systems may be selected for generating a predicted content. A generation of the predicted content may be offloaded to the subset of computer systems. Content delivery computer systems of the initial set of computer systems may be controlled to deliver the generated content to the vehicle in accordance with the specific set of space-time points.
Automated on-demand occupant environment modulation in a data center, including: identifying, by a computing device operatively coupled to one or more computing devices in a data center, based on data from one or more sensors, a location of an individual in the data center; and modifying, by the computing device, one or more environmental parameters at the location, including modifying operation of the one or more computing devices in the data center based on the location of the individual in the data center relative to the one or more computing devices.
A semiconductor integrated circuit (IC) device includes a first source/drain region that is connected to a second source/drain region by one or more active channels, a backside dielectric plug that is connected to the second source/drain region, and a faux channel that is connected to the first source/drain region and that is connected to the backside dielectric plug. The backside dielectric plug adequately electrically isolates the faux channel from the second source/drain region. The fabrication of the backside dielectric plug may be utilized to modify transistors within a first region of the semiconductor IC device relative to transistors within a second region semiconductor IC device.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A semiconductor device includes a wafer having a frontside, a backside, and front end of line (FEOL) devices arranged on the frontside. The semiconductor device includes a first dielectric material coupled to the frontside and including frontside wiring electrically connected to the FEOL devices. The semiconductor device includes a second dielectric material coupled to the backside and including backside wiring electrically connected to the FEOL devices. The semiconductor device includes a first and second vias extending through the first dielectric material and electrically connected with the backside wiring such that a first power delivery pathway delivers power to a first FEOL device through the first via and the backside wiring and a second power delivery pathway delivers power to a second FEOL device through the second via and the backside wiring. The first power delivery pathway is shorter than the second power delivery pathway.
Mechanisms are provided for dynamically generating workspaces and provisioning them with datasets. The mechanisms store datasets in a data vault for provisioning to dynamically generated workspaces associated with users. The dynamically generated workspaces are computer environments through which the users can perform operations on the one or more datasets. The mechanisms receive a request, from a user, for access to a specified dataset, and retrieve a data usage agreement (DUA) corresponding to a pairing of the user with the specified dataset. The DUA specifies a level of obfuscation to be applied to the specified dataset when provisioning a workspace associated with the user, with the specified dataset. The mechanisms dynamically generate, on-demand, the workspace associated with the user based on the retrieved DUA. The mechanisms also automatically provision, on-demand, the dynamically generated workspace with a version of the specified dataset corresponding to the level of obfuscation specified in the DUA.
A semiconductor device includes an electrically conductive contact embedded in a region of dielectric material. The electrically conductive contact has an uppermost surface that includes a recess and a depression. The recess is recessed a first depth relative to an uppermost surface of the region of dielectric material, and the depression recessed a second depth relative to the uppermost surface of the region of dielectric material. The second depth greater than the first depth. The semiconductor device further includes a region of fill material formed in the recess and the depression of the uppermost surface of the electrically conductive contact. The fill material includes an intermetallic alloy. The intermetallic alloy may be an alloy of copper and one or more of gold, palladium, cobalt, tin, or nickel.
A semiconductor device includes a diode, the diode includes a first frontside contact over a first source/drain region, a first backside contact, and a first placeholder connected to a bottom surface of the first source/drain region.
A nanosheet semiconductor structure including a logic device region comprising logic devices having backside contact structures embedded in a backside dielectric layer, and a passive device region including passive devices on a continuous silicon substrate, where a height of the backside dielectric layer in the logic device region is substantially equal to a height of the continuous silicon substrate in the passive device region.
A semiconductor structure includes a device layer including a device region with a plurality of devices and a pre-charging circuit; a front side wiring layer, located on a front side of the device layer, and including at least signal wiring connected to the device region; a supply voltage line coupled to the device region; and a back side wiring layer, located on a back side of the device layer. The back side wiring layer includes a virtual power rail coupled to the pre-charging circuit and a transient line capacitively but not conductively coupled to the virtual power rail and coupled to the device region. The pre-charging circuit is configured to cause the virtual power rail to experience a voltage differential from a supply voltage applied to the supply voltage line responsive to a pulse on the transient line.
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a deep trench via in a single diffusion break region; a frontside metal wire conductively connected to a top surface of the deep trench via; and a backside metal wire conductively connected to a bottom surface of the deep trench via, where the frontside metal wire and the backside metal wire are parallel to each other and perpendicular to the deep trench via. A method of forming the same is also provided.
A semiconductor device that includes a thermoelectric cooling structure at a hybrid bonding interface between two semiconductor dies is provided. Thermoelectric cooling structures that are formed at a hybrid bonding interface of two semiconductor dies can lead to enhanced thermal conductance, targeted thermal management, mitigated thermal expansion mismatch, extend operational reliability and/or provide integrated thermal management solutions.
A semiconductor structure includes a gate structure disposed between a first vertical field- effect transistor and a second vertical field-effect transistor, a first liner layer disposed on the gate structure and a sidewall of the first vertical field-effect transistor and the second vertical field- effect transistor, a second liner layer disposed on the gate structure and a sidewall of the second vertical field-effect transistor, a backside gate contact between opposing sidewalls of the first liner layer and the second liner layer and having a first surface disposed on the gate structure, and a backside metal via disposed on a second surface of the backside gate contact. The first surface of the backside gate contact has a first width and the second surface of the backside gate contact has a second width greater than the first width.
A computer-implemented method, according to one approach, is for refactoring a number of source code blocks. The computer-implemented method includes evaluating the source code blocks and identifying dependent and exclusive ones of the source code blocks. The exclusive source code blocks are automatically refactored and options outlining how the dependent source code blocks can be refactored are generated. Moreover, the generated options are transmitted to a user. In response to receiving a selection of one or more of the options from the user, the dependent source code blocks are refactored as outlined in the selected one or more options. Furthermore, the refactored exclusive source code blocks and refactored dependent source code blocks are combined to form an updated application and corresponding updated service.
A load adaptive process is provided for noise impact on function testing of circuit design logic cells. The process includes obtaining multiple noise tolerance data curves for different potential capacitive loads on a logic cell. The process includes performing noise impact on function testing of an instance of the logic cell within the circuit design. The performing includes selecting, based on a capacitive load of the logic cell instance of the circuit design, a noise tolerance data curve of the multiple curves, and determining whether the logic cell instance fails noise impact on function testing based on comparing a noise pulse at the logic cell instance to the selected noise tolerance data curve. Further, the process includes initiating, based on the logic cell instance of the circuit design failing the noise impact on function testing, one or more actions to facilitate addressing the failing of the logic cell instance.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
21.
INDUCTOR-CAPACITOR CIRCUIT STRUCTURE AT HYBRID BONDING INTERFACE
A structure is provided that includes an inductor-capacitor (L-C) circuit that is connected at a hybrid bonding interface. Notably, the L-C circuit includes a top portion and a bottom portion that are connected together at the hybrid bonding interface. The L-C circuit can be used as a monitoring device that can detect and transmit data related to at least one of temperature, strain and humidity at the hybrid bonding interface.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
There are processing methods and resulting structures for providing three-transistor (3T) footprint stacked SRAMs. An SRAM bit cell includes a first inverter positioned at a first obtuse corner of a parallelogram. The first inverter includes a first pull-up transistor (PU) vertically stacked over a first pull-down transistor (PD) . The SRAM bit cell includes a second inverter positioned at a second obtuse corner of the parallelogram. The second inverter includes a second PU vertically stacked over a second PD. A first pass-gate (PG) is positioned at a first acute corner of the parallelogram and a second PG is positioned at a second acute corner of the parallelogram.
Embodiments are disclosed for a semiconductor device and a method for fabrication. The device includes a first gate, having a top FET that is disposed above a bottom FET, and in electrical contact with a top source /drain epitaxial (S/D epi) and a back end of line (BEOL) interconnect. Additionally, the device includes the bottom FET. The bottom FET is in electrical contact with a bottom S/D epi. Further, a shallow backside contact is in electrical contact with the bottom S/D epi. Additionally, the device includes a deep via that is in electrical contact with the BEOL interconnect and the shallow backside contact. The deep via and the shallow backside contact provide a conductive path between the BEOL interconnect and the bottom S/D epi.
An apparatus for bonding a first substrate to a second substrate includes a heatable mounting stage configured to accommodate a first semiconductor substrate on an upward-facing surface and a first stack of semiconductor materials on the first semiconductor substrate; a heatable bond head configured to accommodate a second semiconductor substrate on a downward-facing surface and a second stack of semiconductor materials on the second semiconductor substrate; and a collet disposed on the downward-facing surface of the heatable bond head and configured to receive the second semiconductor substrate and the second stack of semiconductor materials. The heatable bond head is configured to have a vacuum applied thereto to deformably accommodate the second semiconductor substate and the second stack of semiconductor materials against the collet. The heatable bond head is configured to be pressed against the heatable mounting stage to bond the semiconductor materials.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
25.
INCREASING RESOURCE UTILIZATION IN CLOUD COMPUTING CLUSTERS
A computer-implemented method for provisioning cloud computing clusters includes receiving a request to create a cloud computing cluster, the cloud computing cluster comprising a clustered filesystem and a requested number of processing nodes and attached storage devices associated with the cloud computing cluster and initiating an initialization process for a single processing node and a corresponding attached storage device responsive to receiving the request to create the cloud computing cluster. The method may also include, previous to completion of the initialization process, requesting and receiving an IP address for the single processing node and a device ID for the corresponding attached storage device from one or more cloud infrastructure controllers and configuring the clustered filesystem and a corresponding WAN cache using the received IP address and the received device ID. A system and computer program product corresponding to the above method are also disclosed herein.
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
Analog memory-based activation function for an artificial neural network can be provided. An apparatus can include at least two non-volatile memory devices connected in parallel such that the current can flow through one of the two non-volatile memory devices depending on the voltage level driving the current. To control which branch an input current flows through, each of the two non-volatile memory devices can be connected to a circuit element that can function as a switch, for example, a diode such as a semiconductor diode, a transistor, or another circuit element. Such apparatus can implement an analog memory-based activation function, for example, for an analog memory-based artificial neural network.
A chip and cooler assembly includes an active or passive interposer (114) that has a front side and a back side. Integrated circuit chips (102, 112) are mounted onto the back side of the interposer (114). Each of the chips (102, 112) has a front side that is attached to the interposer (114) and a back side that faces away from the interposer (114). Gaps (108) separate the chips (102, 112). The assembly also includes a frame (300) that is fitted into the gaps (108) between the chips (102, 112). The frame (300) is CTE-matched to the chips (102, 112). The frame (300) and the chips (102, 112) define a back side surface. A cooler module (200) is attached to the back side surface. The cooler module (200) is CTE-matched to the chips (102, 112). The cooler module (200) includes a microchannel cooler (202) that is disposed directly against the back sides of the chips and a manifold (204, 206) that is attached to the microchannel cooler (202) opposite the chips (102, 112). The manifold (204, 206) is CTE-matched to the microchannel cooler (202).
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
A computer-implemented method, computer system, and computer program product is provided. The computer-implemented method includes selecting, using a first attribute of a first object, the first object in a first volumetric video. The method also includes selecting, using a second attribute of a second object, the second object in a second volumetric video, where the first attribute and the second attribute satisfy an aggregation rule. The method also includes generating an aggregated volumetric video from the first volumetric video and the second volumetric video, where the generating of the aggregated video comprises rendering the first object and the second object simultaneously in the aggregated volumetric video based on the aggregation rule.
A memory device including a trench to a first electrically conductive structure; a first electrode of a conformal electrically conductive material contained within the trench in electrical communication with the first electrically conductive structure and is present on sidewalls of the trench; a switching layer is present in the trench on the first electrode and extends outside the trench; and a second electrode present on the switching layer overfilling the trench. The memory device also includes a contact positioned on a portion of the second electrode that is overfilling the trench to provide that the contact is horizontally offset from the first electrode that is present in the trench.
DNS request obfuscation includes generating decoy domain name system (DNS) requests for obfuscating DNS request activity being handled by a private DNS server for an organization, and sending the decoy DNS requests to external DNS server (s) for resolution, receiving a DNS request seeking a DNS lookup for a client device, obfuscating the DNS request by sending, to an external DNS server of the external DNS server (s), the DNS request interspersed with at least some of the generated decoy DNS requests sent to the external DNS server, receiving, from the external DNS server, a DNS response to the sent DNS request, and providing the DNS response to a source of the DNS request.
An End of Data Set (EOD) including a High Resolution Tape Directory (HRTD) is written at a position next to a last written user data set on a tape. When appending a new user data set, the new user data set is written starting from a position next to an end longitudinal position (LPOS) of the EOD to generate an overwritten EOD.
A semiconductor structure is provided that includes a resistive random access memory located on a surface of a bitline (28) that is embedded in a shallow trench isolation structure (12). The structure can further include a source line (SL) that is present above the bitline (28) or embedded in the shallow trench isolation structure (12).
A connection system comprises a printed circuit board. The printed circuit board comprises a top face and a bottom face. The printed circuit board also comprises a first edge that is normal to the top face and bottom face. The printed circuit board also comprises a second edge that is normal to the top face and bottom face. The first edge face and second edge face intersect at an angle that is not a straight angle. The connection system also comprises a coplanar card-edge socket on the printed circuit board. The socket comprises a top section that interfaces with the top face of the printed circuit board along the first and second edge faces of the printed circuit board. The socked also comprises a bottom section that interfaces with the bottom face of the printed circuit board along the first and second edge faces of the printed circuit board.
A complementary field effect transistor (CFET) device is formed on a semiconductor substrate. The CFET device has a first transistor that is under a second transistor. A filled gate cut is directly adjacent to the sidewall of the gate of the CFET device. The first dielectric material in the gate cut is adjacent to the first transistor. The second dielectric material in the gate cut is adjacent to the second transistor. The two dielectric materials in the gate cut are selected to improve the electrical performance of each of the NFET and the PFET in the CFET device. The first dielectric material can apply a compressive stress to the channels of the first transistor when the first transistor is a PFET to improve the electrical performance of the PFET. When the second transistor is an NFET, the second dielectric material applies a tensile stress to NFET to improve NFET performance.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
A node of the computing environment obtains an exclusive fetch request of a cache line shared by, at least, the node and a manager node of the computing environment. The exclusive fetch request includes a state indication regarding processing of the exclusive fetch request by the manager node. The node processes the exclusive fetch request, based on the state indication included with the exclusive fetch request regarding processing of the exclusive fetch request by the manager node.
A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
Systems and methods for performing layer normalization are described. A circuit can receive a sequence of input data across a plurality of clock cycles, where the sequence of input data represents a portion of an input vector. The circuit can determine a plurality of sums and a plurality of sums of squares corresponding to the sequence of input data. The circuit can determine, based on the plurality of sums of squares, a first scalar representing an inverse square-root of a variance of vector elements in the input vector. The circuit can determine a second scalar representing a negation of a product of the first scalar and a mean of the vector elements in the input vector. The circuit can determine, based on the first scalar, the second scalar and the received sequence of input data, an output vector that is a normalization of the input vector.
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G06N 3/04 - Architecture, e.g. interconnection topology
Unloading shared resources is described. A shared library correlation table (SLCT) is generated in a mock resource. During a close function, selecting an entry in the SLCT is selected for reducing a reference count of the selected entry in the SLCT, a status of the selected entry based on the reference count is verified, and an associated container of the selected entry is removed from memory when the status of the selected entry indicates the associated container is not a shared resource, thereby avoiding segmentation faults.
A semiconductor structure including a one-transistor one-capacitor (ITIR) device is provided that includes an embedded resistive random access memory (ReRAM) having a width larger than 1 gate pitch, that is present in a frontside or the backside of the structure, a frontside contact structure electrically connected to a source region of the transistor of the 1T1R device and a backside contact structure electrically connected to a drain region of the transistor of the 1T1R device.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
40.
IMPROVED CONTACT STRUCTURE FOR POWER DELIVERY ON SEMICONDUCTOR DEVICE
A semiconductor structure with improved backside metal contacts includes a plurality of source/drain regions within a field effect transistor. A backside metal contact is electrically connected to at least one source/drain region of the plurality of source/drain regions. The backside metal contact includes a first taper profile. The semiconductor structure further includes a backside power rail electrically connected to the at least one source/drain region through the backside metal contact. The backside power rail includes a second taper profile that is different from the first taper profile.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A method for restoring a mapper of a processor core includes saving first information in a staging latch. The first information represents a newly dispatched first instruction of the processor core and is saved in an entry latch of a save-and-restore buffer. In response to reception of a flush command of the processor core, the restoration of the mapper is begun with the first information from the staging latch without waiting for a comparison of a flush tag of the flush command with the entry latch of the save-and-restore buffer. A processor core configured to perform the method described above is also provided. A processor core is also provided that includes a dispatch, a mapper, a save-and-restore buffer that includes entry latches and is connected to the mapper via at least one pipeline, and a register disposed in the at least one pipeline.
A semiconductor structure is presented having a first field effect transistor (FET) including a first device layer, a second FET including a second device layer, where the first device layer has a stepped portion with respect to the second device layer, and an electrical connection between a gate of the first FET and a gate of the second FET at the stepped portion of the first device layer. The first FET is stacked over the second FET. The second device layer is larger than the first device layer. The gate of the first FET is positioned above the first device layer having a stepped portion.
Facilitating peer-to-peer cloud computing resource sharing utilizing a permissioned distributed ledger is provided. A request by a computational resource consumer for additional computational resources from a computational resource provider via a peer-to-peer decentralized network is detected. A computational resource exchange environment is generated to transfer the additional computational resources from the computational resource provider to the computational resource consumer in response to validating that the computational resource consumer is authorized to consume the additional computational resources and that the computational resource provider is authorized to transfer the additional computational resources to the computational resource consumer via the peer-to-peer decentralized network. The additional computational resources are transferred from the computational resource provider to the computational resource consumer for consumption via the computational resource exchange environment. The additional computational resources provided by the computational resource provider and the consumption of the additional computational resources by the computational resource consumer are anonymized.
Provided are a computer program product, system, and method for managing access to tape cartridges at a tape archival service provider. A determination is made as to whether a non-volatile memory of the tape cartridge stores a key encryption key comprising an encrypted user encryption key associated with a user. In response to determining that the non-volatile memory of the tape cartridge stores the key encryption key, the key encryption key is decrypted to produce the user encryption key. The user encryption key, resulting from the decrypting, is provided to an encryption engine of the tape drive to encrypt plain-text data read from the tape medium in the tape cartridge with the user encryption key to return to a read request.
A semiconductor structure includes a first metallization layer having a first plurality of metal containing lines, and a second metallization layer located above the first metallization layer. The second metallization layer includes a second plurality of metal containing lines. A first group of the second plurality of metal containing lines is disposed within the first metallization layer. The first group of the second plurality of metal containing lines is isolated from the first metallization layer by a dielectric barrier layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
46.
STACKED AND NON-STACKED TRANSISTORS WITH DOUBLE-SIDED INTERCONNECTS
A semiconductor structure is provided that includes a stacked transistor including at least one transistor stacked over another transistor and a non-stacked transistor integrated on a same wafer. Both the stacked transistor and the non-stacked transistor include frontside and backside interconnects.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
47.
FIXED ASYMMETRY COMPENSATION FOR MULTIPLY AND ACCUMULATE OPERATIONS
Systems and methods for compensating multiply and accumulate (MAC) operations are described. A processor can send an input vector to a first portion of a memory device. The first portion can store synaptic weights of a trained artificial neural network (ANN). The processor can read a first result of a MAC operation performed on the input vector and the synaptic weights stored in the first portion. The processor can send an inverse of the input vector to a second portion of the memory device. The processor can read a second result of a MAC operation performed on the inverse of the input vector and an inverse of synaptic weights stored in the second portion. The processor can combine the first result and the second result to generate a final result. The final result can be a compensated version of the first result.
An electronic device includes a first electrode, a second electrode, and a memory component configured to store a resistive state. The memory component includes a layered region arranged in direct contact with the first electrode and a bulk region arranged in direct contact with the second electrode. The layered region includes a plurality of first layers made of a first material and a plurality of second layers made of a second material alternatingly arranged with one another. The first material is a phase-change material and the second material is a non-phase-change material. The bulk region is a continuous mass made of a third material that is different than the first material and the second material, and the bulk region is in direct contact with at least two of the first layers and at least one of the second layers of the layered region.
A method, computer system, and a computer program product for private audio communication in a conference call is provided. The present invention may include receiving a mute request from a first participant in a conference call. The present invention may also include muting the first participant in the conference call. The present invention may further include capturing an audio from the muted first participant. The present invention may include transmitting the captured audio to a second participant in the conference call over a private communication channel.
One or more systems, devices, and/or methods of fabrication provided herein relate to adjacent buried power rail for stacked field-effect transistor architecture. A semiconductor device can comprise a first transistor stacked on a second transistor, wherein the first transistor is offset laterally from the second transistor, and a first buried power rail and a second buried power rail, wherein the first buried power rail is coupled to the first transistor and the second buried power rail is coupled to the second transistor.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 23/528 - Layout of the interconnection structure
51.
SCALABLE SWITCH CAPACITOR COMPUTATION CORES FOR ACCURATE AND EFFICIENT DEEP LEARNING INFERENCE
An apparatus comprising: a first plurality of inputs representing an activation input vector; a second plurality of inputs representing a weight input vector; an analog multiplier-and-accumulator to generate a first analog voltage representing a first multiply-and-accumulate result for the said first inputs and the second inputs; a voltage multiplier that takes the said first analog voltage and produces a second analog voltage representing a second multiply-and-accumulate result by multiplying at least one scaling factor to the first analog voltage; an analog to digital converter configured to convert the said second analog voltage multiply-and-accumulate result into a digital signal using a limited-precision operation during a neural network inference operation; and a hardware controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result, or a software controller configured to determine the at least one scaling factor based on the first multiply-and-accumulate result.
A computer-implemented method for validating ownership of a digital asset is disclosed. The computer-implemented method includes transmitting a public key for encrypting a digital asset to an owner of the digital asset responsive to receiving a request for the public key. The computer-implemented method further includes receiving from the owner of the digital asset, an encrypted digital asset and a first liveness hash, wherein the digital asset is encrypted using the public key, and the first liveness hash is generated based, at least in part, on the digital asset in an unencrypted form and a first nonce. The computer-implemented method further includes determining whether the first liveness hash is valid. The computer-implemented method further includes generating in response to determining that the first liveness hash is valid, a digital asset record, wherein the digital asset record includes the encrypted digital asset and the first liveness hash.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
53.
INTELLIGENT REUSABLE PACKAGING AMELIORATION FOR COGNITIVE SHIPMENTS
An embodiment for ameliorating reusable packaging for cognitive commerce shipments is provided. The embodiment may include receiving information relating to a product to be shipped in a reusable package and historical sensor data obtained from a knowledge corpus. The embodiment may also include predicting a size of the reusable package in which to ship the product. The embodiment may further include identifying a required level of inflation of an array of balloons in the reusable package. The embodiment may also include inflating a plurality of balloons in the array of balloons consistent with the required level of inflation. The embodiment may further include in response to determining the product does not require additional protection, deflating each inflated balloon in the array of balloons upon delivery of the product to the final destination.
B65D 81/05 - Containers, packaging elements, or packages, for contents presenting particular transport or storage problems, or adapted to be used for non-packaging purposes after removal of contents specially adapted to protect contents from mechanical damage maintaining contents at spaced relation from package walls, or from other contents
It discloses an (or an array of) magnetic tunneling junction (MTJ) pillars, each with a magnetic free layer (160) (containing a fast-switching material like aluminum or a metal like gallium), a magnetic reference layer (124), and a tunnel barrier layer (150) separating the two magnetic layers. A chromium-containing diffusion barrier layer (181) disposed between the magnetic free layer (160) and tunnel barrier layer (150) prevents aluminum (or gallium) diffusion from the magnetic free layer into a tunnel barrier layer of the MTJ pillar. Devices using and methods of making the fast-switching MTJ (s) are also disclosed. It enables devices with reduced resistance area (RA). Using a AlMnGe alloy to make the magnetic free layer with a tetragonal crystalline structure and a lower magnetic moment that supports higher magnetic orientation switching speeds is provided.
A semiconductor structure is provided that includes a backside bitline connected to a dynamic random access memory (DRAM) cell that includes a plurality of field effect transistors (FETs) and a plurality of DRAM capacitors that are present in a frontside of the structure.
A microelectronic structure including a first stacked FET device that includes a first bottom FET device and a first upper FET device. The first bottom FET device include a plurality of first bottom channel layers, and the first upper FET device includes a plurality of first upper channel layers. A bottom gate that surrounds the plurality of first bottom channel layers and an upper gate that surrounds the plurality of first upper channel layers. A gate protrusion that extends downwards from the backside of the upper gate to connected to the bottom gate. The gate protrusion partially overlaps with a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps with an upper gate cut region of the first upper stacked FET device.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A method, computer program product, and computer system are provided for container cross-cluster capacity scaling. The method includes broadcasting local capacity information of capacity availability or capacity requirement for the local cluster and receiving broadcasts from each of one or more other clusters providing capacity information including capacity availability or capacity requirements. The method may map the received capacity information with the local capacity information and may determine a suitable cross-cluster capacity sharing when a capacity requirement of the local cluster maps to a capacity availability of another cluster or when a capacity availability of the local cluster maps to a capacity requirement of another cluster. The method may coordinate the deallocation of a node from the cluster having the capacity availability and reallocation of the node to the cluster having the capacity requirement.
A circuit comprises a first pulse-width modulator configured to generate a first pulse based on a first input, a second pulse-width modulator configured to generate a second pulse based on a second input, a first differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor, and a second differential circuit comprising a first transistor, a second transistor, a first resistor, and a second resistor. A gate of the first transistor of the first differential circuit and a gate of the second transistor of the first differential circuit, and a gate of the first transistor of the second differential circuit and a gate of the second transistor of the second differential circuit are configured to be controlled by the first and second pulse width modulators based on the first input and the second input.
A non-volatile memory apparatus includes a first hydrogen reservoir, which is electrically conductive; a charge of hydrogen, which is captured in the first hydrogen reservoir; a dielectric layer that has a first side that is adjacent to the first hydrogen reservoir and a second side that is opposite from the first hydrogen reservoir; a second hydrogen reservoir that is adjacent to the second side of the dielectric layer, is electrically conductive, and has a side that is opposite from the dielectric layer; and a piezoelectric layer that is adjacent to the side of the second hydrogen reservoir and that has a side that is opposite from the second hydrogen reservoir.
A device structure for a phase-change memory device is disclosed. The device structure includes a top electrode, a phase-change material that is recessed between two layers of resistive liner material, and a conductive material. The conductive material contacts the sidewall of the top electrode, the sidewall of the phase-change material, and a portion of a top surface and a bottom surface of each of the two layers of the resistive liner material. The device structure includes a heater contacting a bottom electrode and the bottom layer of the resistive liner material. The heater is in a first bilayer dielectric. A second bilayer dielectric is under the top electrode.
Managing battery cells in a battery pack circuit for reducing stored energy can include a plurality of battery packs electrically connected in a circuit in a battery system to provide a system output voltage. Each of the battery packs include a plurality of battery cells connected in an electrically conductive circuit, and each of the battery packs generate a pack output voltage collectively resulting in the system output voltage. In response to detecting when a cell of the plurality of battery cells of a battery pack of the battery packs approaches a threshold of a thermal state related to battery capacity, discharging electrical capacity of remaining cells in the battery pack thereby reducing available energy in the battery pack.
A technique for threat response associated with an endpoint detection and response (EDR) system. The system uses a combination of automated observable detection, threat intelligence enrichment, graph analysis, and supervised machine learning to machine-predict analyst behavior in classifying (as 'true' or 'false' positives) the EDR alerts, and to support either (i) automated suppression of those alerts that the system classifies with sufficient confidence as either true or false, or (ii) for those alerts than cannot be so classified, the providing of recommendations to analysts to facilitate their activities. Auto-detection of observables for graph-based feature detection, together with the automated disposition of alerts where possible greatly reduces overall analyst workload for the EDR system. Further, and even where a machine-based prediction does not have sufficient confidence to enable bypassing the analyst, the system provides the analyst with additional context and enrichment to facilitate expedited (or at least more efficient) alert handling.
An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
64.
STACKED FIELD EFFECT TRANSISTOR STRUCTURE WITH INDEPENDENT GATE CONTROL BETWEEN TOP AND BOTTOM GATES
A semiconductor device includes a first transistor and a first gate electrically coupled to the first transistor. A second transistor is positioned on top of the first transistor. A second gate is electrically coupled to the second transistor. A dielectric isolation layer is positioned between the first gate and the second gate. A first conductive contact is electrically coupled to the first gate. A second conductive contact is electrically coupled to the second gate. A control of the first gate through the first conductive contact is independent of a control of the second gate through the second conductive contact.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
65.
MULTIMODAL MACHINE LEARNING FOR GENERATING THREE-DIMENSIONAL AUDIO
Methods and systems use one or more machine learning models to automatically generate three-dimensional sound. A multimodal content item is accessed by a computing device. Three-dimensional sound is automatically generated by the computing device using the one or more machine learning models based on the multimodal content item.
An integrated circuit structure includes a power supply rail formed in a backside of a semiconductor wafer. The integrated circuit structure also includes a frontside BEOL wire layer connected to the power supply rail through a gate, wherein the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer. A method of forming an integrated circuit structure includes forming a power supply rail in a backside of a semiconductor wafer, forming a gate in the semiconductor wafer, and forming a frontside BEOL wire layer connected to the power supply rail through the gate. Again, the gate is of a type to be powered off by a power supply coupled through the gate from the power supply rail to the first frontside BEOL wire layer.
A semiconductor structure is provided including a backside source/drain contact structure that contacts a source/drain region of a transistor and overlaps a portion of a tri-layered bottom dielectric isolation structure that is located on a backside of the transistor. The presence of the tri-layered bottom dielectric isolation structure prevents shorting between the gate structure of the transistor and the backside source/drain contact structure, and thus improves process margin.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
According to an aspect, a computer-implemented method for performing distributed communication operations includes receiving a request, by a first computing system, to perform a distributed communication operation and obtaining, by the first computing system, a tree structure for performing the distributed communication operation, wherein the first computing system is a root node of the tree structure. The method also includes creating, by the first computing system, a message having header information and a payload for the distributed communication operation and transmitting, by the first computing system, a portion of the message to each child node of the first computing system, wherein the portion transmitted to each child node is unique.
Embodiments of present invention provide a magnetic tunnel junction (MTJ) structure. The MTJ structure includes a MTJ stack, the MTJ stack including a tunnel barrier layer on a reference layer and a free layer on the tunnel barrier layer, wherein the free layer includes multiple sub free layers, the multiple sub free layers being multiple ferromagnetic strips placed parallel to each other on the tunnel barrier layer, the multiple ferromagnetic strips having respective first ends connected to a first electrode and respective second ends connected to a second electrode. A method of forming the MTJ structure is also provided.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
Systems, methods and/or computer program products predictively automating configurations of modular service zones servicing physical assets, maximizing reuse of service zone (s) and optimizing time for servicing a plurality of physical assets. Digital twin models of physical assets are classified, and arranged into workflows for the service zones, sequencing services performed on physical assets arriving at service centers and preparing service zones based on types of services requested, the estimated time of arrival and similarities between classifications of different digital twins of physical assets. Based on sequences of the workflow, arrival times of physical assets and overlap between parts, tools, machines, etc., within various service zones, service center coordinates robotic systems to arrange service zones in a manner that minimizes waiting time between services, maximizes the number of physical assets repaired within a period of time and reduces rearrangement of service zones between the services provided to different physical assets.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
71.
DNN TRAINING ALGORITHM WITH DYNAMICALLY COMPUTED ZERO-REFERENCE.
A computer implemented method includes performing a gradient update for a stochastic gradient descent (SGD) of a deep neural network (DNN) using a first set of hidden weights stored in a first matrix comprising a Resistive Processing Unit (RPU) crossbar array. A second matrix comprising a second set of hidden weights is stored in a digital medium. A third matrix comprising a set of reference values is computed upon a transfer cycle of the first set of weights from the first matrix to the second matrix, accounting for a sign-change (chopper). The third matrix is stored in the digital medium. A third set of weights is updated for the DNN from the second matrix when a threshold is reached for the second set of weights, in a fourth matrix comprising a RPU crossbar array.
In an approach to improve write transducers a write transducer for recording data on a magnetic media is disclosed. The write transducer comprises a first pole piece. The write transducer further comprises a second pole piece. The first pole piece and the second pole piece are arranged in such a way, that a write gap is formed between the first pole piece and the second pole piece. A longitudinal axis is defined between opposite ends of the write gap. A length of the write gap along the longitudinal axis varies in the direction transverse to the longitudinal axis.
A computer-implemented method for grouping devices in a massive multiple-input and multiple-output (MIMO) -based cellular network includes determining movement states of end devices in a cell of the massive MIMO-based cellular network, estimating payload requirements of the end devices, and grouping the end devices in a group based on the determined movement states and the estimated payload requirements.
Embodiments of present invention provide a method of forming a phase change memory device. The method includes forming a bottom electrode on a supporting structure; forming a first blanket dielectric layer, a phase-change material layer, a second blanket dielectric layer, and a hard mask sequentially on top of the bottom electrode; forming an inner spacer in an opening in the hard mask to modify the opening; extending the opening into the second blanket dielectric layer to create an extended opening; filling the extended opening with a heating element; etching the second blanket dielectric layer, the phase-change material layer, and the first blanket dielectric layer respectively into a second dielectric layer, a phase-change element, and a first dielectric layer; forming a conductive liner surrounding the phase-change element; and forming a top electrode on top of the heating element. A structure formed thereby is also provided.
A computer implemented method for manipulating an image comprising pixels. A group of processor units creates editable text having changeable text attributes from text in the image. The group of processor units forms a text layer for the image with the editable text created from the text in the image, wherein the editable text is located in text positions in the text layer corresponding to positions of the text in the image. The group of processor units creates a set of editable shapes having changeable shape attributes, wherein the set of editable shapes correspond to a set of shapes in the image. The group of processor units forms a shape layer for the image with the set of editable shapes. The set of editable shapes have a set of shape positions in the shape layer that correspond to a set of positions of the set of shapes in the image.
A structure of a circuitry substrate for securing an area from tampering is disclosed. The structure includes a circuitry substrate with at least one of a top tamper enclosure and a bottom tamper enclosure covering a component in a protected area of the circuitry substrate. The top and bottom tamper enclosures are adhesively bonded to a surface of the circuitry substrate, and a tear initiation site is added to a side of the perimeter of circuitry substrate bordering the protected area that includes at least one tamper enclosure, such that the tear initiation site is located and configured to enable propagation of a delamination of at least one internal layer of the circuitry substrate and a severing of a security circuit when a removal force is applied to the at least one of the top tamper enclosure and the bottom tamper enclosure.
Methods, systems (126), and computer program products for domain adaptive speech recognition using artificial intelligence are provided herein. A computer-implemented method includes generating a set of language data candidates, each language data candidate comprising one or more graphemes, by processing a sequence of phonemes related to input speech data using an artificial intelligence-based data conversion model (104) (302); determining, for a target pair of phonemes and graphemes, a subset of graphemes from the set of language data candidates (304); generating a first speech recognition output by processing the subset of graphemes using at least one biasing language model (108) and an artificial intelligence-based speech recognition model (306); generating a second speech recognition output by replacing at least a portion of the subset of graphemes in the first speech recognition output with at least one of the graphemes from the target pair (308); and performing automated actions based on the second speech recognition output (310).
A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and/or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and/or multi-cycle violations using a rules-based approach.
A system, method, and computer program product perform audio-visual inspection at a surface of a liquid over machinery that is operating under the surface. The audio-visual inspection includes each of feeding surface wave movements into a neural network, feeding bubble formation pattern into the neural network, feeding bubble dimensions into the neural network, and feeding underwater acoustic information to the neural network. The system, method, and computer program product further identify, using the neural network, a statistical anomaly from the audio-visual inspection indicating an anomaly of the performance of the machinery.
Identifying an indistinct entity within an image can include generating by an image filter multiple gradients, each of which corresponds to one of a plurality of pixels of an image captured by an imager. The image can be searched for a likely repeating pattern. Responsive to detecting, based on the multiple gradients, a likely repeating pattern within the image, data structures can be generated, the data structures comprising a set of probabilistically weighted feature vectors corresponding to the likely repeating pattern. A machine learning model can classify each of the set of probabilistically weighted feature vectors. An identity of the likely repeating pattern can be output, the identity based on the machine learning model classifications of the probabilistically weighted feature vectors.
A semiconductor device includes backside power rails located between N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor space; and backside local signal lines located between the backside power rails.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source/drain (S/D) epi regions, a top FET including a plurality of top S/D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S/D epi region of the plurality of bottom S/D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN).
Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.
Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.
The present specification describes a computer-implemented method. A first comparison test is executed to determine whether an unknown object is of a first sub-class of a class of objects. Responsive to determining that the unknown object is not of the first sub-class, it is determined whether the unknown object is an instance of a second sub-class by determining whether there are additional sub-classes other than the first sub-class and a second sub-class. Responsive to determining that there are additional sub-classes, the second code fragment executes while refraining from assuming the unknown object is of a particular sub-class.
A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. Accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.
A vertical-transport field-effect transistor (VTFET) is on a wafer. The VTFET has a first width. The first width is a contacted poly pitch (CPP). A bottom source/drain region of the VTFET extends at least the first width from the VTFET. A contact from a frontside of the VTFET is connected to the bottom source/drain region.
A semiconductor structure includes a first source-drain region; a second source-drain region; at least one channel region coupling the first and second source-drain regions; and a gate adjacent the at least one channel region. A bottom dielectric isolation region is located inward of the gate. First and second bottom silicon regions are respectively located inward of the first and second source-drain regions. A back side contact projects through the second bottom silicon region into the second source-drain region.
Embodiments are disclosed for a three-terminal spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device. The three-terminal SOT MRAM device includes a first type field effect transistor (FET) that drives an SOT line. Additionally, the first type FET includes a write gate in electrical contact with a write wordline (WWL). Further, the device also includes a second type FET in electrical contact with a magnetic tunnel junction (MTJ). Also, the second type FET comprises a read gate in electrical contact with a read wordline (RWL). Additionally, the first type FET is disposed above the second type FET. Further, the three-terminal SOT MRAM device provides a density of three contacted poly pitch (CPP) per two cells.
A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device can implement a FinFet-based input/output (I/O) device in the first region. A second semiconductor device excluding a gate dielectric is on the second region. The second semiconductor device can implement a nanosheet-based logic device in the second region.
A magnetic random access memory (MRAM) apparatus includes a magnetic tunnel junction (MTJ) stack; a spin-orbit-torque (SOT) layer that underlies the MTJ stack; and a dielectric pillar that underlies the SOT layer and the MTJ stack. The SOT layer has a stepped profile.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
A hybrid bonded semiconductor structure includes a first substrate and a second substrate each having an interface joined in a hybrid bond. Each substrate has a die portion and a crackstop structure adjacent the die portion. One or more voids in the first substrate and the second substrate are formed in or about a portion of a periphery of each crackstop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unified void with airgaps across the hybrid bond interface.
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer
An example operation may include one or more of invoking, via an operating system, execution of a plurality of software programs having a first mode of operation that causes the plurality of software programs to operate in a first resource consuming mode, monitoring physical resources of a computing device that are consumed by the plurality of software programs, determining to reduce or allow expanded consumption of the physical resources of the computing device by the plurality of software programs based on the monitored physical resources, and in response to the determination, switching from a first mode of operation of a software program from among the plurality of software programs and to a second mode of operation of the software program that causes the software program to operate in a second resource consuming mode that consumes either less or more physical resources than the first resource consuming mode.
A magnetoresistive random access memory (MRAM) structure is provided. The MRAM structure includes a chiral spin-orbit-torque (SOT) metal bottom electrode (18) under the magnetic free layer (26) where the chiral SOT metal bottom electrode (18) is surrounded by a via dielectric material structure (24). The chiral SOT metal bottom electrode (18) enables a charge current direction, a spin current direction and a spin polarization direction to be in the same direction which is perpendicular to a horizontal surface of the chiral SOT metal bottom electrode (18).
A computer implemented method, apparatus, system, and computer program product manages updates to images. A computer system determines shared layers present between the images selected for update management. The images comprise executable code that are run to create containers. The computer system detects a change in a shared layer in the shared layers for an image in the images. The computer system updates the shared layer in the shared layers in a set of the images having the shared layer in response to detecting the change to the shared layer for the image. According to other illustrative embodiments, a computer system and a computer program product for managing updates to images are provided.
In an approach for enhancing an experience of a user listening to and/or watching an audio-visual content by modifying future audio and/or video frames of the audio-visual content, a processor captures a set of sensor data from an IoT device worn by the first user. A processor analyzes the set of sensor data to generate one or more connotations by converting the emotion using an emotional vector analytics technique and a supervised machine learning technique. A processor scores the one or more connotations on a basis of similarity between the emotion exhibited by the first user and an emotion expected to be provoked by a second user. A processor determines whether a score of the one or more connotations exceeds a pre-configured threshold level. Responsive to determining the score does not exceed the pre-configured threshold level, a processor generates a suggestion for the producer of the audio-visual content.
H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
98.
MIRROR WRITE CONSISTENCY CHECK POLICY FOR LOGICAL VOLUME MANAGER SYSTEMS
Improving the runtime and discovery recovery performance for cloud-based logical volume management systems when performing mirror write operations. A mirror write consistency check (MWCC) policy that incorporates aspects of Active MWCC policies and Passive MWCC policies are utilized to more efficiently ensure that data is properly mirrored from a first copy of a logical volume to the second copy of a logical volume (as well as to potentially multiple other copies of the logical volume).
An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.
An embodiment includes analyzing text content of a user query to identify via natural language processing (NLP) a query topic. The embodiment maps the query topic to a topic cluster at a node of a hierarchical model of a text database. The embodiment generates query demand data indicative of demand for the topic cluster based on user queries. The embodiment identifies the topic cluster as a topic-cache candidate based on the query demand data. The embodiment compares an amount of memory required for storing text associated with the first topic cluster to available cache memory. The embodiment caches the text of the topic cluster candidate upon determining that there is sufficient available cache memory space.
patents