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2025
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Invention
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Heterogeneous hybrid bonding. A semiconductor device includes an electrically conductive contact ... |
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Invention
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Dynamic workspace creation with automated obfuscation as a computing service. Mechanisms are prov... |
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Invention
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Floating node in integrated circuit. A semiconductor structure includes a device layer including ... |
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Invention
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Load adaptive noise tolerance testing of circuit design. A load adaptive process is provided for ... |
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Invention
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3-transistor footprint stacked sram. There are processing methods and resulting structures for pr... |
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Invention
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Vertical field-effect transistor with backside gate contact. A semiconductor structure includes a... |
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Invention
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Code block refactoring enabling co-existence of source code and updated code. A computer-implemen... |
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Invention
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Channel disconnection by backside dielectric plug. A semiconductor integrated circuit (IC) device... |
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Invention
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Thermoelectric cooling structure at hybrid bonding interface. A semiconductor device that include... |
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Invention
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Backside power delivery in 3d die. A semiconductor device includes a wafer having a frontside, a ... |
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Invention
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Backside to frontside connection among different metal tracks. Embodiments of present invention p... |
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Invention
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Inductor-capacitor circuit structure at hybrid bonding interface. A structure is provided that in... |
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Invention
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Self aligned backside contacts compatible with passive devices. A nanosheet semiconductor structu... |
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Invention
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Diode formation with backside power delivery network. A semiconductor device includes a diode, th... |
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2023
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Invention
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Increasing resource utilization in cloud computing clusters. A computer-implemented method for pr... |
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Invention
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Top contact on resistive random access memory. A memory device including a trench to a first elec... |
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Invention
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Retaining high resolution tape directory in overwritten end of data set. An End of Data Set (EOD)... |
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Invention
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Resistive random access memory on buried bitline. A semiconductor structure is provided that incl... |
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Invention
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Negative capacitance for ferroelectric capacitive memory cell. A capacitive memory cell includes ... |
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Invention
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Hardware for parallel layer-norm compute. Systems and methods for performing layer normalization ... |
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Invention
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Semiconductor structure with backside metallization layers. A semiconductor structure includes a ... |
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Invention
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Stacked and non-stacked transistors with double-sided interconnects. A semiconductor structure is... |
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Invention
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Private audio communication in a conference call. A method, computer system, and a computer progr... |
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Invention
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Personalized aggregation of volumetric videos. A computer-implemented method, computer system, an... |
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Invention
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Dns request obfuscation. DNS request obfuscation includes generating decoy domain name system (DN... |
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Invention
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Thermal expansion matched chip module with integrated liquid cooling. A chip and cooler assembly ... |
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Invention
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Invalidity protection for shared cache lines. A node of the computing environment obtains an excl... |
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Invention
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Scalable switch capacitor computation cores for accurate and efficient deep learning inference. A... |
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Invention
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Stacked cmos devices with two dielectric materials in a gate cut. A complementary field effect tr... |
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Invention
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Improved contact structure for power delivery on semiconductor device. A semiconductor structure ... |
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Invention
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Embedded reram with backside contact. A semiconductor structure including a one-transistor one-ca... |
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Invention
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Managing access to tape cartridges at tape archival service provider. Provided are a computer pro... |
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Invention
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Unloading interdependent shared libraries. Unloading shared resources is described. A shared libr... |
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Invention
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Facilitating peer-to-peer cloud computing resource sharing utilizing a permissioned distributed l... |
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Invention
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Phase-change memory cell with mixed-material switchable region. An electronic device includes a f... |
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Invention
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Fast mapper restore for flush in processor. A method for restoring a mapper of a processor core i... |
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Invention
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Latch cross couple for stacked and stepped fet. A semiconductor structure is presented having a f... |
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Invention
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Method to validate ownership and authentication of a digital asset. A computer-implemented method... |
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Invention
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Non-volatile memory-based activation function. Analog memory-based activation function for an art... |
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Invention
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Adjacent buried power rail for stacked field-effect transistor architecture. One or more systems,... |
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Invention
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Intelligent reusable packaging amelioration for cognitive shipments. An embodiment for ameliorati... |
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Invention
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Container cross-cluster capacity scaling. A method, computer program product, and computer system... |
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Invention
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Coplanar card-edge connector. A connection system comprises a printed circuit board. The printed ... |
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Invention
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Stacked fet with extremely small cell height. A microelectronic structure including a first stack... |
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Invention
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Fet dram with backside bitline. A semiconductor structure is provided that includes a backside bi... |
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Invention
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Analog memory-based complex multiply-accumulate (macc) compute engine. A circuit comprises a firs... |
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Invention
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Fixed asymmetry compensation for multiply and accumulate operations. Systems and methods for comp... |
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Invention
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Structures and processes for void-free hybrid bonding. An apparatus for bonding a first substrate... |
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Invention
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Fast switching mram having aluminum-manganese-germanium free layer combined with chromium diffusi... |
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Invention
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Backside contacts for stacked field effect transistors. Embodiments are disclosed for a semicondu... |
