Abstract

A substrate structure includes a first substrate and a second substrate. The first substrate includes a first glass plate and at least one first conductive via penetrating the first glass plate. The second substrate includes a second glass plate and at least one second conductive via penetrating the second glass plate. The second substrate is connected to the first substrate. The second glass plate is bonded to the first glass plate through chemical bonding force and defines a chemical bonding contact surface with the first glass substrate. The at least one second conductive via is bonded to the at least one first conductive via through metal diffusion and defines at least one metal bonding contact surface with the at least one first conductive via.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/15 - Ceramic or glass substrates

Abstract

A substrate structure including a first substrate and a second substrate is provided. The first substrate includes a first core layer and a first conductor. The second substrate includes a second core layer and a second conductor. There is a metal diffusion bonding interface between the first conductor and the second conductor. There is a covalent bonding interface between the first core layer and the second core layer.

IPC Classes  ?

• H05K 1/14 - Structural association of two or more printed circuits
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A circuit board and a method of manufacturing the same are provided. The circuit board includes two circuit substrates and a conductive layer. The circuit substrates are stacked on each other, while each of the circuit substrates includes an insulation substrate and a conductive via which is disposed inside the insulation substrate. Two opposite sides of the insulation substrate are connected to each other through the conductive via. The conductive layer is disposed between the conductive vias, and the conductive vias are electrically connected to each other through the conductive layer which includes the nanoporous structure.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/03 - Use of materials for the substrate
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

A substrate structure includes an inorganic substrate, an adhesion promotion layer (APL), an electroless nickel-phosphor layer, and a conductive material. The inorganic substrate has an upper surface, a lower surface, and at least one through hole. The APL is disposed on the upper surface, the lower surface, and an inner wall of the at least one through hole. The electroless nickel-phosphor layer is disposed on a portion of the APL. The conductive material is disposed on the electroless nickel-phosphor layer and fills the at least one through hole to define at least one first conductive circuit on the upper surface, at least one second conductive circuit on the lower surface and at least one conductive through hole located within the at least one through hole and electrically connected to the at least one first conductive circuit and the at least one second conductive circuit.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/495 - Lead-frames
• H01L 29/34 - Semiconductor bodies having polished or roughened surface the imperfections being on the surface

Abstract

A manufacturing method of a circuit carrier includes the following. A fine redistribution structure is formed on a temporary substrate. A build-up package substrate is provided. The build-up package substrate includes a substrate, a first build-up circuit structure, and a second build-up circuit structure. The first build-up circuit structure is disposed on a top surface of the substrate. The second build-up circuit structure is disposed on a bottom surface of the substrate. The fine redistribution structure is bonded on the build-up package substrate. The fine redistribution structure is directly attached on the first build-up circuit structure. A line width and a line spacing of the fine redistribution structure are smaller than a line width and a line spacing of the first build-up circuit structure. At least one conductive through hole is formed to penetrate the fine redistribution structure and a portion of the first build-up circuit structure.

IPC Classes  ?

• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits

Abstract

A substrate structure includes a substrate and a vertical conductive connector. The substrate includes a material with a heat resistance temperature of 300° C. or greater. The vertical conductive connector penetrates through the substrate. The vertical conductive connector has a bonding structure extending toward the substrate. A manufacturing method of the substrate structure is also provided.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
• H05K 3/42 - Plated through-holes

Abstract

A probe card includes an adapter plate, a guide plate and a plurality of probes. The guide plate incudes a first guide plate portion, a second guide plate portion and a capacitor structure. The probes include at least one first ground probe, at least one second ground probe and a plurality of power probes. The first ground probe penetrates through the first guide plate portion and is connected to the capacitor structure and the adapter plate. The second ground probe and the power probes penetrate through the first guide plate portion, the capacitor structure and the second guide plate portion and are connected to the adapter plate. The first ground probe is used to provide voltage to the capacitive structure to generate a potential difference. The power probes draw current through the capacitor structure and form a current loop with the second ground probe.

IPC Classes  ?

• G01R 1/073 - Multiple probes

Abstract

A probe card includes an adapter plate, a guide plate, a plurality of probes, at least one capacitor and a conductive layer. The adapter plate includes at least one power pad and at least one ground pad. The guide plate is disposed between the adapter plate and a device under test. The probes penetrate through the guide plate and are electrically connected to the adapter plate. The probes include at least one power probe and at least one ground probe. The power probe is electrically connected to the power pad, and the ground probe is electrically connected to the ground pad. The capacitor is located on at least a portion of the power probe. The conductive layer is connected to the guide plate. The capacitor connects the power probe and the ground probe in series through the conductive layer to form a current loop.

IPC Classes  ?

• G01R 1/073 - Multiple probes

Abstract

A substrate structure and a cutting method thereof are provided. The cutting method includes the following steps. A first substrate structure is provided, wherein the first substrate structure includes a glass substrate and a redistribution layer disposed on the glass substrate. A laser process is performed on the glass substrate to form a modified region on the glass substrate. A wet etching process is performed on the modified region of the glass substrate to remove the modified region and form a plurality of second substrate structures.

IPC Classes  ?

• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• C03C 15/00 - Surface treatment of glass, not in the form of fibres or filaments, by etching
• C03C 23/00 - Other surface treatment of glass not in the form of fibres or filaments
• H05K 1/03 - Use of materials for the substrate

Abstract

A package substrate includes a core layer, at least one functional component, at least one spacer, a filler, a first and a second build-up structures. The core layer has at least one opening and multiple conductive through vias. The functional component is disposed in the openings. The spacer is disposed on the functional component. The filler is filled in the opening, covering the functional component and spacer, and completely filling the gap between the opening, the functional component and the spacer. The first build-up structure is disposed on a first surface of the core layer and a third surface of the filler, and electrically connected to the functional component and the conductive through vias. The second build-up structure is disposed on a second surface of the core layer and a fourth surface of the filler, contacts the spacer and electrically connected to the conductive through vias.

IPC Classes  ?

• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates

Abstract

A package structure includes a package substrate, an application specific integrated circuit (ASIC), a plurality of optoelectronic assemblies, and a plurality of organic interposers. The ASIC is disposed on the package substrate and electrically connected to the package substrate. The optoelectronic assemblies are separately disposed on the package substrate and surround the ASIC. Each of the plurality of optoelectronic assemblies includes an electronic integrated circuit (EIC), a photonic integrated circuit (PIC), and a plurality of hybrid bonding pads. The EIC is bonded to the PIC through the plurality of hybrid bonding pads. The plurality of organic interposers are separately disposed on the package substrate and surround the ASIC. The optoelectronic assemblies are electrically connected to the package substrate through the plurality of organic interposers.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

A package structure includes a package substrate, a system on a chip (SoC), at least one input/output circuit, multiple optoelectronic assemblies and an organic interposer. The SoC is disposed on the package substrate and includes a central processing unit (CPU), a graphics processing unit (GPU) and a memory. The input/output circuit is disposed on the package substrate. The optoelectronic assemblies are separately disposed on the package substrate and surround the SoC and the input/output circuit. The organic interposer is disposed on the package substrate. The SoC, the input/output circuit and the optoelectronic assemblies are electrically connected to the package substrate through the organic interposers.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

A package structure includes a package substrate, an organic interposer and an electronic unit. The package substrate includes a plurality of first pads. The organic interposer is disposed on the package substrate and includes a plurality of second pads. The second pads are directly connected to the first pads to electrically connected the organic interposer to the package substrate. At least one of each of the first pads and each of the second pads includes a pad portion and a plurality of contact portions connecting the pad portion. A first extension direction of the pad portion is different from a second extension direction of the contact portions. The electronic unit is disposed on the organic interposer, wherein the electronic unit is electrically connected to the package substrate through the organic interposer.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

A chip package structure includes a first chip, a second chip, a plurality of first hybrid bonding pads, a first insulating layer, a first patterned conductive layer, a second patterned conductive layer, and a plurality of first conductive via structures and second conductive via The first chip is electrically connected to the second chip through a plurality of first 5 structures. through silicon vias. The first chip is bonded onto the second chip through the first hybrid bonding pads. The first insulating layer covers the first and the second chips. The first and the second patterned conductive layers are respectively disposed on a first upper surface and a first lower surface of the first insulating layer. The first conductive via structures are electrically connected to the first and the second patterned conductive layers. The second conductive via structures are electrically connected to the first chip and the first patterned conductive layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A connector and a manufacturing method thereof. The connector includes at least one circuit substrate, at least one contact and a first elastic body. The at least one circuit substrate has a first surface. The at least one contact includes a fixed part and a first contact part that are connected to each other. The fixed part is disposed on the at least one circuit substrate. The first contact part protrudes out of the first surface and covers a part of the first surface. The first elastic body is disposed on the first surface and is electrically insulated. At least a part of the first elastic body is located between the first contact part and the first surface.

IPC Classes  ?

• H01R 12/71 - Coupling devices for rigid printing circuits or like structures

Abstract

An electronic packaging structure including a first circuit structure and a second circuit structure is provided. An electronic component is disposed between the first circuit structure and the second circuit structure. At least one of the first circuit structure and the second circuit structure (for example, the second circuit structure) has a cavity. The electronic component is embedded in the cavity, and may be encapsulated between the first circuit structure and the second circuit structure.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 25/03 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes

Abstract

A circuit board structure includes a core, a wiring layer and a buried passive component. The wiring layer and the buried passive component are disposed on the core, and the buried passive component is electrically connected to the wiring layer. The buried passive component includes a first spiral metal layer, a second spiral metal layer and a dielectric interlayer. The first spiral metal layer is intertwined with the second spiral metal layer. The dielectric interlayer is disposed between the first spiral metal layer and the second spiral metal layer. The first spiral metal layer and the second spiral metal layer are spaced apart by the dielectric interlayer at least in the core.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits

Abstract

A manufacturing method of the circuit board includes the following. The third substrate has an opening and includes a first, a second and a third dielectric layers. The opening penetrates the first and the second dielectric layers, and the opening is fully filled with the third dielectric layer. The first, the second and the third substrates are press-fitted so that the second substrate is located between the first and the third substrates. Multiple conductive structures are formed so that the first, the second and the third substrates are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate. The conductive via structure is electrically connected to the first and the third substrates to define a signal path. The ground path surrounds the signal path.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/42 - Plated through-holes

Abstract

A manufacturing method of the package carrier includes the following steps. A circuit substrate having a through via is provided. A heat-conducting material layer coving the inner wall of the through via is electroplated on the circuit substrate. A first build-up structure and a second build-up structure are respectively formed on two opposite sides of the circuit substrate. Parts of the first build-up structure, the circuit substrate, the heat-conducting material layer and the second build-up structure are removed to expose the remaining heat-conducting material layer, so as to define a heat-conducting element and form a circuit structure layer including a notch portion. The heat-conducting element includes a first heat-conducting portion and a second heat-conducting portion vertically connected to the first heat-conducting portion. The notch portion exposes the first heat-conducting portion, and an outer surface of the second heat-conducting portion is aligned with a side surface of the circuit structure layer.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/498 - Leads on insulating substrates
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/42 - Plated through-holes
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A circuit carrier includes at least one wiring layer and a capacitive element. The capacitive element is disposed in at least one dielectric layer of the wiring layer. The capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least one second finger. The first finger and the second finger extend from opposite sides of the plate, respectively.

IPC Classes  ?

• H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• H01G 4/012 - Form of non-self-supporting electrodes
• H01G 4/30 - Stacked capacitors
• H05K 1/02 - Printed circuits Details
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

An electronic package module including a circuit substrate, an electronic component disposed on the circuit substrate and a molding compound is provided. The molding compound encapsulates the circuit substrate and the electronic component. The circuit substrate includes a first circuit layer and a first insulation layer covering on the first circuit layer. The first insulation layer has a boundary surface where a second circuit layer is disposed. A second insulation layer covers a part of the second circuit layer while the insulation layer bares a region surrounding the perimeter of the boundary surface. The molding compound directly contacts the region and the second insulation layer.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A circuit board structure includes a core layer, at least one electroplating metal layer, at least one dielectric layer and at least one conductive metal layer. The core layer includes at least one dielectric portion and at least one metal portion. The electroplating metal layer is disposed on at least one of a first surface and a second surface of the core layer, exposing a portion of at least one of the first surface and the second surface and at least connecting the at least one metal part. The dielectric layer is disposed on at least one of the first surface and the second surface and on the electroplating metal layer. The dielectric layer has at least one opening exposing a portion of the electroplating metal layer. The conductive metal layer is disposed in the opening of the dielectric layer and is correspondingly connected to the electroplating metal layer.

IPC Classes  ?

• H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
• H05K 1/09 - Use of materials for the metallic pattern
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/02 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
• H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

Abstract

A circuit board device includes a transition region that includes a first conductive layer at a first level, a second conductive layer at a second level, and conductive vias. The first conductive layer includes a pad connected to the solderless connector, a transmission line, and a first reference layer. The transmission line includes first and second segments. A second width of the second segment is the same as or less than a first width of the first segment. The first reference layer has a first anti-pad region for the pad and the transmission line disposed therein. In a plan view, the first anti-pad region surrounding the pad is completely located within a second anti-pad region of a second reference layer of the second conductive layer. The conductive vias are disposed between the first and second conductive layers and surround the pad.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits Details

Abstract

A circuit board structure and a manufacturing method thereof. Circuit board structure includes first circuit board, second circuit board, conductive coil, magnetic body and molding compound. First circuit board has first side surface and first cavity located on first side surface. Second circuit board has second side surface facing first side surface and being spaced apart from first side surface. Conductive coil is in a spiral shape and includes first coil pattern and second coil pattern. First coil pattern is disposed in first circuit board. Second coil pattern is disposed in second circuit board. First coil pattern is electrically connected to second coil pattern. Magnetic body is filled in first cavity of first circuit board. Conductive coil surrounds at least a part of magnetic body. Molding compound is filled in a gap between first side surface and second side surface.

IPC Classes  ?

• H05K 1/14 - Structural association of two or more printed circuits
• H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• H05K 3/36 - Assembling printed circuits with other printed circuits

Abstract

A circuit board structure including a first circuit board, a second circuit board, a conductive coil and a first molding compound and a manufacturing method thereof. The first circuit board has a first side surface. The second circuit board has a second side surface facing the first side surface and being spaced apart from the first side surface. The conductive coil is in a spiral shape and includes a first coil pattern and a second coil pattern. The first coil pattern is disposed in the first circuit board. The second coil pattern is disposed in the second circuit board. The first coil pattern is electrically connected to the second coil pattern. The first molding compound is magnetic and filled in a gap located between the first side surface and the second side surface. The conductive coil surrounds at least a part of the first molding compound.

IPC Classes  ?

• H05K 1/14 - Structural association of two or more printed circuits
• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

A co-packaged structure for optics and electrics includes a substrate, an optical module and an electrical connection layer. The optical module includes a carrier and an optical transceiver unit. The carrier is mounted on the substrate. The optical module is mounted on the carrier. The electrical connection layer is mounted on the substrate, and the carrier is electrically connected with a circuitry on the substrate through the electrical connection layer. A plurality of fiber accommodation through hole are formed on the substrate and correspond to the optical transceiver unit.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

A substrate structure and a cutting method thereof are provided. The cutting method includes the following steps. A first substrate structure is provided, wherein the first substrate structure includes a glass substrate and a redistribution layer disposed on the glass substrate. A laser process is performed on the glass substrate to form a modified region on the glass substrate. A wet etching process is performed on the modified region of the glass substrate to remove the modified region and form a plurality of second substrate structures.

IPC Classes  ?

• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• C03C 15/00 - Surface treatment of glass, not in the form of fibres or filaments, by etching
• C03C 23/00 - Other surface treatment of glass not in the form of fibres or filaments
• H05K 1/03 - Use of materials for the substrate

Abstract

An inspection system and an inspection method of a bare circuit board are provided. The inspection system is used for inspecting a bare circuit board. The bare circuit board includes a chip pad and an antenna. The inspection system includes an adapter board, a test device and a measure device. The adapter board includes a chip and a contact structure. The chip is electrically connected to the contact structure. The contact structure touches the chip pad so that the chip is electrically connected to the chip pad. The test device includes a transceiver antenna. The test device and the bare circuit board separate. The measure device is electrically connected to the chip or the transceiver antenna.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

The present invention includes an aluminum board, an electromagnet core, and a coil. The aluminum board includes a first surface, a second surface opposite to the first surface, and multiple through vias in communication with the first surface and the second surface. The electromagnet core is mounted on the first surface, and the through vias are located on two opposite sides of the electromagnet core. The coil is mounted through the through vias to wrap around the electromagnet core. An inside wall of each of the through vias forms an anodic aluminum oxide (AAO) by an anodizing process. The present invention is able to decrease via size of a conductive through via of a vertically embedded inductor. This allows through vias to be more densely formed on a board, and thus increases an amount of the coil wrapped around the electromagnetic core and increases inductance of the inductor.

IPC Classes  ?

• H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• H01F 17/00 - Fixed inductances of the signal type
• H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A manufacturing method of a circuit board structure includes the following steps. A first sub-circuit board having an upper surface and a lower surface opposite to each other and including at least one conductive through hole is provided. A second sub-circuit board including at least one conductive through hole is provided on the upper surface of the first sub-circuit board. A third sub-circuit board including at least one conductive through hole is provided on the lower surface of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are laminated so that at least two of their conductive through holes are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/03 - Use of materials for the substrate
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

A carrier board includes a substrate having a first substrate surface, a second substrate surface, and a substrate hole that penetrates the first substrate surface and the second substrate surface; a magnet sheath disposed in the substrate hole to cover a hole boundary of the substrate hole, and including a first magnetic surface, a second magnetic surface, and an inner periphery that interconnects the first magnetic surface and the second magnetic surface; a first dielectric isolation layer and a second dielectric isolation layer respectively having outer surfaces facing away from the substrate; and a conductive metal layer covering the inner periphery of the magnet sheath and extending to overlie the outer surfaces of the first dielectric isolation layer and the second dielectric isolation layer.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 1/03 - Use of materials for the substrate
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A manufacturing method of the circuit board includes the following steps. A metal layer, a first substrate, a second substrate, and a third substrate are laminated. Multiple blind holes and a through hole are formed. A conductive material layer is formed, which covers the metal layer, the conductive layer of the third substrate, and an inner wall of the through hole, and fills the blind holes to define multiple conductive holes. The conductive material layer, the metal layer, and the conductive layer are patterned to form a first external circuit layer located on the first substrate and electrically connected to the conductive pillars, and a second external circuit layer located on the insulating layer and electrically connected to the conductive holes, and define a conductive through hole structure connecting the first external circuit layer and the second external circuit layer and located in the through hole.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H05K 1/02 - Printed circuits Details
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/42 - Plated through-holes
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

Disclosed is a package structure including a circuit board, a co-packaged optics (CPO) substrate, an application specific integrated circuit (ASIC) assembly, a glass interposer, an electronic integrated circuit (EIC) assembly, a photonic integrated circuit (PIC) assembly, and an optical fiber assembly. The CPO substrate is configured on the circuit board, and the ASIC assembly is configured on the CPO substrate. The glass interposer is configured on the CPO substrate and includes an upper surface, a lower surface, a cavity, and at least one through glass via (TGV). The EIC assembly is configured on the upper surface of the glass interposer and electrically connected to the glass interposer. The PIC assembly is configured in the cavity of the glass interposer and electrically connected to the glass interposer. The optical fiber assembly is configured on the lower surface of the glass interposer and optically connected to the PIC assembly.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes a line portion, a first insulating layer, and a conductive terminal. The first insulating layer is disposed on the line portion. The conductive terminal is disposed on the first insulating layer and embedded in the first insulating layer to be electrically connected with the line portion. The conductive terminal includes a first portion, a second portion, and a third portion. The first portion protrudes from a surface of the first insulating layer. The second portion is embedded in the first insulating layer and connected to the first portion. The third portion is disposed between the line portion and the second portion. A width of the second portion is greater than a width of the third portion.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits

Abstract

A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits Details
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A chip package structure includes a package carrier, a plurality of chips, a bridge and a plurality of solder balls or C4 bumps. The package carrier includes a plurality of carrier pads. The chips are arranged side by side on the package carrier. Each of the chips includes a plurality of first pads and a plurality of second pads. The bridge is located between the chips and the package carrier and includes a plurality of bridge pads. Each of the first pads is hybrid bonded with each of the bridge pads to form a hybrid bonding pad, so that the chips are electrically connected to each other through the bridge. The solder balls are located between the package carrier and the chips. The second pads of each of the chips are electrically connected to the carrier pads of the package carrier through the solder balls.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

A circuit board structure includes a build-up structure, a graphene layer disposed on the build-up structure, and at least one conductive pillar disposed on the graphene layer, the graphene layer includes an oxidized area not covered by the at least one conductive pillar and a non-oxidized area covered by the at least one conductive pillar, and the at least one conductive pillar is electrically connected to the build-up structure via the non-oxidized area.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

An anti-diffusion substrate structure includes a substrate, a substrate circuit layer, and a chip. The substrate has multiple through holes. Within each of the through holes includes a first metal layer and an anti-diffusion layer plated on the first metal layer. The anti-diffusion layer is an Electroless Palladium Immersion Gold (EPIG) layer or an Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) layer. The substrate circuit layer is mounted on the substrate and extended on the anti-diffusion layer within each of the through holes. The substrate circuit layer is made of a second metal layer, and a composition of the second metal layer is different from a composition of the first metal layer. The chip is electrically connected to the substrate circuit layer. The anti-diffusion layer is able to better prevent material of the first metal layer from migrating or diffusing to the second metal layer.

IPC Classes  ?

• C23C 18/42 - Coating with noble metals
• C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
• C23C 18/32 - Coating with one of iron, cobalt or nickelCoating with mixtures of phosphorus or boron with one of these metals
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A vapor chamber structure includes a first flexible substrate, a second flexible substrate, a spacer, a flexible sealing member, and a working fluid. The first flexible substrate includes a first organic material layer, a first copper foil layer, and a first capillary structure layer. The second flexible substrate includes a second organic material layer, a second copper foil layer, and a second capillary structure layer. The first copper foil layer, the first capillary structure layer, the spacer, the second copper foil layer, and the second capillary structure layer are retracted by a distance relative to the first and second organic material layers to form a space. The first and second organic material layers and the flexible sealing member define a sealed chamber. The working fluid is disposed in the sealed chamber and located among the first and second capillary structure layers and grooves of the spacer.

IPC Classes  ?

• F28D 15/04 - Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls in which the medium condenses and evaporates, e.g. heat-pipes with tubes having a capillary structure
• F28D 15/02 - Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls in which the medium condenses and evaporates, e.g. heat-pipes
• F28F 3/10 - Arrangement for sealing the margins
• F28F 21/08 - Constructions of heat-exchange apparatus characterised by the selection of particular materials of metal

Abstract

A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01P 3/08 - MicrostripsStrip lines

Abstract

A transmission line device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.

IPC Classes  ?

• H01P 3/08 - MicrostripsStrip lines
• H05K 1/02 - Printed circuits Details

Abstract

A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

The present disclosure provides a circuit board including a first circuit layer, a dielectric layer on the first circuit layer, and a seed layer on the dielectric layer and directly contacting the first circuit layer, in which a top surface of the seed layer includes a levelled portion. The circuit board also includes a second circuit layer on the levelled portion of the seed layer, in which a grain boundary density of the second circuit layer is lower than that of a portion of the seed layer directly contacting the first circuit layer.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A circuit board structure is provided. The circuit board structure includes a via hole, a conductive layer, and an alternate stacking of a plurality of circuit layers and a plurality of insulating layers. The via hole penetrates through the plurality of circuit layers and the plurality of insulating layers. The lateral ends of the plurality of insulating layers form the sidewall of the via hole. The conductive layer is conformally disposed within the via hole. The conductive layer exposes the first region of the sidewall and covers the second region of the sidewall. The sidewall extends in the longitudinal direction of the via hole and has no misalignments in the radial direction.

IPC Classes  ?

• H05K 3/42 - Plated through-holes
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

The present disclosure provides a circuit board with an embedded chip, which includes a dielectric layer, a first circuit layer, a chip, a conductive connector, and an insulating protection layer. The first circuit layer includes at least one first trace in the dielectric layer. The chip is in the dielectric layer and adjacent to the first trace, where the chip includes a plurality of chip pads at an upper surface of the chip. The conductive connector is on the upper surface of the chip and on the first circuit layer, where a lower surface of the conductive connector contacts at least one chip pad of the chip pads and an upper surface of the first trace. The insulating protection layer is on the chip, the first circuit layer, and the conductive connector, where the insulating protection layer contacts the upper surface of the chip.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

This disclosure provides a circuit board assembly and a manufacturing method thereof. The circuit board assembly includes circuit board, embedded chip, heat dissipation assembly and temperature switch structure. The temperature switch structure includes a first metal layer and a second metal layer stacked on each other. The first metal layer of the temperature switch structure is electrically connected to the circuit board and is thermally coupled to the embedded chip. A thermal expansion coefficient of the first metal layer is different from a thermal expansion coefficient of the second metal layer so that the temperature switch structure is deformed in response to a temperature change of the embedded chip to be in contact with or spaced apart from the second electrically conductive contact of the heat dissipation assembly.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01H 37/04 - BasesHousingsMountings
• H01H 37/52 - Thermally-sensitive members actuated due to deflection of bimetallic element
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H05K 1/03 - Use of materials for the substrate
• H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor

Abstract

A manufacturing method for circuit board structure includes steps of providing a carrier, forming a first build-up layer including a plurality of first circuits, forming a second build-up layer including a plurality of second circuits on a side of the first build-up layer located away from the carrier, attaching a side of the second build-up layer located away from the first build-up layer to a core layer, and removing the carrier from the first build-up layer, where the first circuits are finer than the second circuits.

IPC Classes  ?

• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

An integrated circuit (IC) package structure includes a chip, a redistribution layer (RDL) structure, a molding compound structure and an electromagnetic interference (EMI) shielding structure. The RDL structure is formed on the chip and electrically connected thereto. The molding compound layer is provided on outer surfaces of the chip and the RDL structure. The EMI shielding structure is provided on outer surfaces of the molding compound structure. The molding compound structure layer provided on outer surfaces of the chip and the RDL structure provide protection and reinforcement to multiple faces of the IC package structure; and the EMI shielding structure provided on outer surfaces of the molding compound structure provides EMI protection to multiple faces of the chip and the RDL structure.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A multi-layered resonator circuit structure and a multi-layered filter circuit structure. The multi-layered resonator circuit structure includes a multi-layered substrate, a plurality of resonators and a plurality of conductive components. The multi-layered substrate has a top surface, a bottom surface, and a ground layer. The top surface and the bottom surface face away from each other. The ground layer is located between the top surface and the bottom surface. A part of the plurality of resonators is/are disposed on the top surface. Another part of the plurality of resonators is/are disposed on the bottom surface. The plurality of conductive components is located in the multi-layered substrate. The plurality of resonators is electrically connected to the ground layer, respectively, via the plurality of conductive components.

IPC Classes  ?

• H01P 1/203 - Strip line filters
• H01P 3/08 - MicrostripsStrip lines

Abstract

A circuit board assembly is provided and includes a first circuit board, a second circuit board and a first connecting module. The first connecting module includes a first connecting wire, a first connector and a second connector. The first circuit board includes a first processor, and the second circuit board includes a second processor. One end of the first connector is connected to one end of the first connecting wire, and the other end of the first connector is connected to the first circuit board. One end of the second connector is connected to the other end of the first connecting wire, and the other end of the second connector is connected to the second circuit board. The first connector is adjacent to the first processor, and the second connector is adjacent to the second processor.

IPC Classes  ?

• H05K 1/14 - Structural association of two or more printed circuits
• H01R 12/79 - Coupling devices for flexible printed circuits, flat or ribbon cables or like structures connecting to rigid printed circuits or like structures
• H05K 1/02 - Printed circuits Details

Abstract

The present disclosure provides a printed circuit board and a method thereof. The printed circuit board has a first substrate, at least one first trace layer and at least one second trace layer. The first substrate has a first surface and a second surface. The first surface and the second surface are corresponding to each other along an axis. The first trace layer is formed on the first surface and/or the second surface of the first substrate. The first trace layer has at least one first trace and at least one first gap beside the first trace by etching. The second trace layer is formed on the first trace layer. The second trace layer has at least one second trace and at least one second gap beside the second trace by etching.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 1/09 - Use of materials for the metallic pattern
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/26 - Cleaning or polishing of the conductive pattern
• H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A package structure includes a circuit board, a package substrate, an electronic/photonic assembly, a film redistribution layer, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on the circuit board and electrically connected to the circuit board. The electronic/photonic assembly includes an ASIC assembly, an EIC assembly, and a PIC assembly. The EIC assembly and the PIC assembly are stacked and disposed on the package substrate and electrically connected to the package substrate via the film redistribution layer. An orthographic projection of the EIC assembly on the film redistribution layer is overlapped with an orthographic projection of the PIC assembly on the film redistribution layer. The heat dissipation assembly is disposed on the electronic/photonic assembly. The optical fiber assembly is disposed on the package substrate and optically connected to the PIC assembly.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
• H01L 23/38 - Cooling arrangements using the Peltier effect
• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

A package structure includes a circuit board, a package substrate, a fine metal L/S RDL-substrate, an electronic assembly, a photonic assembly, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on and electrically connected to the circuit board. The fine metal L/S RDL-substrate is disposed on and electrically connected to the package substrate. The electronic assembly includes an application specific integrated circuit (ASIC) assembly, an electronic integrated circuit (EIC) assembly, and a photonic integrated circuit (PIC) assembly which are respectively disposed on the fine metal L/S RDL-substrate and electrically connected to the package substrate by the fine metal L/S RDL-substrate. The heat dissipation assembly is disposed on the electronic assembly. The optical fiber assembly is disposed on the package substrate and electrically connected to the package substrate and the PIC assembly. A packaging method of the VCSEL array chip is presented.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01S 5/42 - Arrays of surface emitting lasers

Abstract

A manufacturing method of a package structure includes: forming a redistribution layer on a top surface of a glass substrate; forming a protective layer on the top surface of the glass substrate; cutting the glass substrate and the protective layer such that the glass substrate has a cutting edge, in which a crack is formed in the cutting edge of the glass substrate; and heating the protective layer such that a portion of the protective layer flows towards a bottom surface of the glass substrate to cover the cutting edge of the glass substrate and fill the crack in the cutting edge of the glass substrate.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings

Abstract

Provided is a manufacturing method of circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The third substrate has an opening and includes a first dielectric layer. The opening penetrates the third substrate, and the first dielectric layer fills the opening. Multiple conductive structures are formed so that the first substrate, the second substrate, the third substrate, and the fourth substrate are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate. The conductive via structure is electrically connected to the first substrate and the fourth substrate to define a signal path, and the ground path surrounds the signal path.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• H05K 3/24 - Reinforcing of the conductive pattern
• H05K 3/42 - Plated through-holes
• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

A method for manufacturing a circuit board includes providing a composite material film including a metal film and a polymeric film, disposing a dielectric layer on the polymeric film to form a stacked structure, forming a circuit layer with a contact pad on a substrate, bonding the stacked structure onto the substrate and the circuit layer, and forming a first opening extending through the metal film to form a patterned metal film. The dielectric layer directly contacts the substrate and entirely covers the circuit layer. The method further includes plasma etching the dielectric layer with the patterned metal film as a mask to form a second opening in the dielectric layer and expose the contact pad in the second opening, removing the composite material film, and depositing a conductive material in the second opening to form a conductive blind hole electrically connected to the contact pad.

IPC Classes  ?

• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Abstract

An electronic packaging structure including a first circuit structure, a second circuit structure and at least one electronic device is provided. The bottom side of the first circuit structure has at least one cavity. The first circuit structure is disposed on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic device is disposed on the second circuit structure. The electronic device is disposed corresponding to the cavity of the first circuit structure.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/66 - High-frequency adaptations
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 1/02 - Printed circuits Details

Abstract

The present invention provides an etching device which comprises an oxygen supplier, so that the etching device of the present invention can etch copper gently by means of the dissolved oxygen in the etching solution to accurately control the etching degree so as to fulfill the stricter requirements of microcircuit manufacturing. The present invention further provides an etching method. Finally, the etching waste solution of the present invention can be recycled to further ameliorate the environmental pollution and reduce the production cost, so the present invention is widely applicable in integrated circuit packaging.

IPC Classes  ?

• C09K 13/04 - Etching, surface-brightening or pickling compositions containing an inorganic acid
• C23F 1/18 - Acidic compositions for etching copper or alloys thereof

Abstract

An electronic packaging structure including a first circuit structure, a second circuit structure and at least one electronic device is provided. The first circuit structure includes a bottom conductive plate having at least one cavity. The first circuit structure is disposed on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic device is disposed on the second circuit structure. The electronic device is disposed corresponding to the cavity of the first circuit structure.

IPC Classes  ?

• H01L 23/552 - Protection against radiation, e.g. light
• H01L 23/66 - High-frequency adaptations
• H01L 21/52 - Mounting semiconductor bodies in containers
• H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or

Abstract

The present disclosure provides a circuit board and its manufacturing method. The circuit board includes a first circuit layer, a first conductive post, and a second circuit layer. The first circuit layer includes a first pad and a first seed layer covering a sidewall of the first pad. The first conductive post is on the first pad and directly connected to the first pad. The second circuit layer includes a second pad and a second seed layer covering a sidewall of the second pad. The second pad is on a first connecting end of the first conductive post. The first connecting end is embedded in the second pad, and the second pad is connected to and directly contacts the first connecting end. The first seed layer and the second seed layer do not extend on a sidewall of the first conductive post.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 1/02 - Printed circuits Details

Abstract

An electronic device including a light-emitting element, an IC chip, a substrate, an optical waveguide layer, and an optical signal outlet is provided. The IC chip is configured to control the light-emitting element to emit an optical signal. The light-emitting element is disposed on a first surface of the substrate, and the IC chip is disposed on a second surface of the substrate. The optical waveguide layer is disposed on the first surface of the substrate, and the optical waveguide layer includes a core layer, a cladding layer, and a metal layer. The metal layer is disposed on at least a portion of an interface between the core layer and the cladding layer. The optical signal outlet corresponds to the light-emitting element, and the optical signal reaches the optical signal outlet after being transmitted in the core layer.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water

Abstract

A connector includes a substrate, a coverlay and a spring contact. The substrate has a first surface, a second surface opposite to the first surface and a conductive through hole extending between the first and second surfaces. The coverlay is disposed on the first surface and includes a first opening. The spring contact includes an anchor member, a rising member and a pin. The anchor member is disposed between the substrate and the coverlay. The rising member extends from the anchor member and through the first opening in a direction away from the substrate. A first portion of the rising member is in the first opening, and a second portion of the rising member is out of the first opening. The pin extends from the anchor member to an inside of the conductive through hole, and is electrically connected to the conductive through hole.

IPC Classes  ?

• H01R 13/17 - Pins, blades or sockets having separate spring member for producing or increasing contact pressure the spring member being on the pin
• H01R 12/70 - Coupling devices

Abstract

A circuit board includes a conductive metal layer, at least one insulating layer, at least one thermally conductive insulating layer and a heat dissipation element. The conductive metal layer is mainly used to transmit electronic signals. The insulating layer is connected to the conductive metal layer. The thermally conductive insulating layer is sandwiched between the conductive metal layer and the insulating layer, and thermally contacts the conductive metal layer, and is used for thermally conducting the heat of the conductive metal layer. The heat dissipation element is in thermal contact with the thermally conductive insulating layer, and is used to conduct the heat of the thermally conductive insulating layer to the outside through a heat dissipation channel.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

An electronic circuit assembly includes an interposer substrate, a wiring substrate, an electrical connective part and an electronic component. The interposer substrate with a first coefficient of thermal expansion (CTE) includes a first surface, a second surface opposite to the first surface, and a first side surface connecting to the first surface and the second surface. The wiring substrate with a second CTE is disposed below the second surface. The first CTE is lower than the second CTE. The electrical connective part is disposed in the interposer substrate and extends to the first side surface. The electronic component is attached to the first side surface and is electrically connected to the electrical connective part.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
• H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits

Abstract

An electronic package structure and manufacturing method thereof. The electronic package structure includes a circuit board, an interposer, a chip, a circuit structure, and a coaxial conductive element. The interposer is disposed on the circuit board. The interposer has a through groove. The chip is disposed in the through groove and located on the circuit board to electrically connect with the circuit board. The circuit structure is disposed on the interposer. The coaxial conductive element penetrates the interposer to electrically connect the circuit structure and the circuit board. The coaxial conductive element includes a first conductive structure, a second conductive structure, and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is disposed between the first conductive structure and the second conductive structure.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/66 - High-frequency adaptations
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H05K 1/14 - Structural association of two or more printed circuits
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

An electronic package structure and its manufacturing method are provided. The electronic package structure includes an interposer, a circuit board, a chip, and a circuit structure. The interposer includes an interposer substrate and a coaxial conductive element located in the interposer substrate. The interposer substrate includes a cavity. The coaxial conductive element includes a first conductive structure, a second conductive structure surrounding the first conductive structure, and a first insulation structure. The first insulation structure is disposed between the first and second conductive structures. The circuit board is disposed on a lower surface of the interposer substrate and electrically connected to the coaxial conductive element. The chip is disposed in the cavity and located on the circuit board, so as to be electrically connected to the circuit board. The circuit structure is disposed on an upper surface of the interposer substrate and electrically connected to the coaxial conductive element.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/66 - High-frequency adaptations
• H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or

Abstract

Provided is a circuit board structure including a substrate, a loop-wrapping ground layer, an insulating structure, a first build-up layer, a top wiring layer, a bottom wiring layer, a first conductive via, and a plurality of second conductive vias. The aforementioned structure defines a signal transmitting structure. An equivalent circuit of the signal transmitting structure at least includes a first equivalent circuit, a second equivalent circuit, a third equivalent circuit and a fourth equivalent circuit, which correspond to different uniform transmitting sections respectively. The first equivalent circuit, the second equivalent circuit, the third equivalent circuit and the fourth equivalent circuit are connected in series with each other according to an ABCD transmission matrix series connection principle.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

A circuit board, including a first dielectric material, a second dielectric material, a third dielectric material, a fourth dielectric material, a first external circuit layer, a second external circuit layer, a conductive structure, a first conductive via, and multiple second conductive vias, is provided. The first conductive via at least passes through the first dielectric material and the fourth dielectric material, and is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias pass through the first dielectric material, the second dielectric material, the third dielectric material, and a part of the conductive structure, and surround the first conductive via. The second conductive vias are electrically connected to the first external circuit layer, the conductive structure, and the second external circuit layer to define a ground path, and the ground path surrounds the signal path.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 1/02 - Printed circuits Details
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits

Abstract

A circuit board structure includes a substrate, a first build-up structure layer, first and second external circuit layers, at least one first conductive via, and second conductive vias. The first build-up structure layer is disposed on a first circuit layer of the substrate. The first external circuit layer is disposed on the first build-up structure layer. The second external circuit layer is disposed on a second circuit layer and a portion of a third dielectric layer of the substrate. The first conductive via is electrically connected to the first external circuit layer and the second external circuit layer to define a signal path. The second conductive vias surround the first conductive via, and the first external circuit layer, the second conductive vias, the first circuit layer, the outer conductive layer, and the second external circuit layer define a first ground path. The first ground path surrounds the signal path.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits Details

Abstract

A bare circuit board is provided, in which the bare circuit board includes a substrate, an antenna, a chip pad, a ground pattern and a trace. The substrate includes a surface. The antenna and the chip pad are formed on the substrate. The ground pattern is formed on the surface. The trace is formed on the surface and isn't connected to the ground pattern. A measuring gap is formed between the trace and an edge of the ground pattern, and the trace includes a first end and a second end. The first end is electrically connected to the chip pad, whereas the second end is electrically connected to the antenna. The bare circuit board is adapted to transmit a signal. The width of the measuring gap is smaller than a quarter of an equivalent wavelength of the signal.

IPC Classes  ?

• H01Q 1/48 - Earthing meansEarth screensCounterpoises
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A method of a circuit signal enhancement of a circuit board comprises the following steps: forming a first substrate body with a first signal transmission circuit layer and a second substrate body with a second signal transmission circuit layer; forming a first signal enhancement circuit layer and a second signal enhancement circuit layer on the first substrate body and the second substrate body; forming a third substrate body with a third signal transmission circuit layer and a fourth substrate body with a fourth signal transmission circuit layer on the carrier; separating the third substrate body and the fourth substrate body from the carrier; combining the first signal transmission circuit layer and the third signal transmission circuit layer through the first signal enhancement circuit layer; and combining the second signal transmission circuit layer and the fourth signal transmission circuit layer through the second signal enhancement circuit layer.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details

Abstract

A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

IPC Classes  ?

• H05K 3/24 - Reinforcing of the conductive pattern
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/15 - Ceramic or glass substrates
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A printed circuit board stack structure includes a first printed circuit board, a second printed circuit board, and a filling glue layer. The first printed circuit board has at least one overflow groove, and includes first pads and a retaining wall surrounding the first pads. The second printed circuit board is disposed on the first printed circuit board, and includes second pads and conductive pillars located on some of the second pads. The conductive pillars are respectively connected to some of the first pads to electrically connect the second printed circuit board to the first printed circuit board. The filling glue layer fills between the first and the second printed circuit boards, and covers the first pads, the second pads, and the conductive pillars. The retaining wall blocks the filling glue layer so that a portion of the filling glue layer is accommodated in the overflow groove.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/14 - Structural association of two or more printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/42 - Plated through-holes

Abstract

A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.

IPC Classes  ?

• H01L 33/54 - Encapsulations having a particular shape
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A circuit board structure includes a circuit substrate, a first circuit layer, and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is aligned with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate and electrically connected to the conductive structure. A line width of the first circuit layer is less than or equal to 1/4 of a line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and electrically connected to the first circuit layer.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits Details
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

The invention discloses a glass carrier having a protection structure, comprising a glass body and a protection layer. The glass body has a top surface, a bottom surface, and a lateral surface. The protection layer covers the lateral surface of the glass body. The protection layer is a hard material with a stiffness coefficient higher than a stiffness coefficient of the glass body. The invention further discloses a manufacturing method of a glass carrier having a protection structure, comprising the following steps: covering the protection layer around the lateral surface of the glass body, wherein the protection layer is the hard material with the stiffness coefficient higher than the stiffness coefficient of the glass body.

IPC Classes  ?

• C03C 17/00 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating
• C03C 17/22 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with other inorganic material
• C03C 17/42 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating of an organic material and at least one non-metal coating
• H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• H01L 23/15 - Ceramic or glass substrates
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H05K 1/03 - Use of materials for the substrate

Abstract

A light-emitting diode package structure includes a heat dissipation substrate, a redistribution layer, and multiple light-emitting diodes. The heat dissipation substrate includes multiple copper blocks and a heat-conducting material layer. The copper blocks penetrate the heat-conducting material layer. The redistribution layer is disposed on the heat dissipation substrate and electrically connected to the copper blocks. The light-emitting diodes are disposed on the redistribution layer and are electrically connected to the redistribution layer. A side of the light-emitting diodes away from the redistribution layer is not in contact with any component.

IPC Classes  ?

• H01L 33/64 - Heat extraction or cooling elements
• H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers
• H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
• H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls

Abstract

A light-emitting diode package includes a redistribution layer, a light-emitting diode, a first dielectric layer, a plurality of wavelength conversion structures, and a transparent encapsulant. The light-emitting diode is disposed on and electrically connected to the redistribution layer. The light-emitting diode includes a first light-emitting diode, a second light-emitting diode, and a third light-emitting diode. The first dielectric layer is disposed on the redistribution layer and covers the light-emitting diode. The wavelength conversion structures are disposed on the first dielectric layer and respectively in contact with the second light-emitting diode and the third light-emitting diode. The transparent encapsulant is disposed on the first dielectric layer and covers the plurality of wavelength conversion structures. In addition, a manufacturing method of the light-emitting diode package is provided.

IPC Classes  ?

• H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A circuit board includes an insulation part, a support layer disposed on the insulation part, a metal case disposed in the insulation part, a heat-exchanging fluid distributed within the enclosed space, and a first porous material distributed within the enclosed space. The metal case is thermally coupled to the support layer and includes a first inner surface, a second inner surface opposite to the first inner surface and positioned between the first inner surface and the support layer, a third inner surface connecting the first inner surface and the second inner surface, and an enclosed space surrounded by the first inner surface, the second inner surface and the third inner surface. The first porous material is disposed on the first inner surface.

IPC Classes  ?

• H05K 1/00 - Printed circuits
• H05K 1/02 - Printed circuits Details

Abstract

A flexible circuit board and a manufacturing method thereof are provided. The flexible circuit board includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material and a Young's modulus of the insulating layers is between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.

IPC Classes  ?

• H05K 1/03 - Use of materials for the substrate
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A chip packaging structure and a manufacturing method thereof are provided. The chip packaging structure includes a substrate, at least one first chip, an adhesive material, a redistribution circuit structure, and multiple second chips. The substrate has a first surface, a second surface opposite to the first surface, and at least one cavity. The at least one first chip is disposed in the at least one cavity. The adhesive material is disposed in the at least one cavity and located between the substrate and the at least one first chip. The redistribution circuit structure is disposed on the first surface of the substrate, and is electrically connected to the at least one first chip. The second chips are disposed on the redistribution circuit structure, and are electrically connected to the redistribution circuit structure.

IPC Classes  ?

• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 23/495 - Lead-frames
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole, a first annular retaining wall, and a second annular retaining wall. The conductive through hole penetrates through the third dielectric layer, a second dielectric layer, and the fourth dielectric layer. The conductive through hole is electrically connected to the first external circuit layer and the second external circuit layer. The first annular retaining wall is disposed in the third dielectric layer, surrounds the conductive through hole, and is electrically connected to the first external circuit layer and the first inner circuit layer. The second annular retaining wall is disposed in the fourth dielectric layer, surrounds the conductive through hole, and connects to the second external circuit layer and the second inner circuit layer electrically.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits Details
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole electrically connected to the first and second external circuit layers, a first annular retaining wall surrounding the conductive through hole, and a second annular retaining wall surrounding the conductive through hole. The first annular retaining wall is electrically connected to the first external circuit layer and a first inner circuit layer. The second annular retaining wall is electrically connected to the second external circuit layer and a second inner circuit layer. A first ground circuit, the first annular retaining wall, and the first inner circuit layer define a first ground path surrounding a first signal circuit. A second ground circuit, the second annular retaining wall, and the second inner circuit layer define a second ground path surrounding a second signal circuit.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01L 23/498 - Leads on insulating substrates
• H05K 1/14 - Structural association of two or more printed circuits

Abstract

A circuit board structure includes a first dielectric layer, first and second inner circuit layers, a conductive connection layer, a second dielectric layer, two third dielectric layers, third and fourth inner circuit layers, two conductive through vias, first and second annular retaining walls, two fourth dielectric layers, first and second external circuit layers, and third and fourth annular retaining walls. The conductive through vias penetrate the third and second dielectric layers and electrically connect the third and fourth inner circuit layers. The first and second annular retaining walls surround the conductive through vias and electrically connect the third and first and the fourth and second inner circuit layers. The third and fourth annular retaining walls are respectively disposed in the fourth dielectric layers and electrically connect the first external circuit layer and the third inner circuit layer and the second external circuit layer and the fourth inner circuit layer.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details

Abstract

A circuit carrier includes a substrate, a first build-up circuit structure, a second build-up circuit structure, a fine redistribution structure and at least one conductive through hole. The substrate has a top surface and a bottom surface opposite to each other. The first build-up circuit structure is disposed on the top surface of the substrate and electrically connected to the substrate. The second build-up circuit structure is disposed on the bottom surface of the substrate and electrically connected to the substrate. The fine redistribution structure is directly attached on the first build-up circuit structure, wherein a line width and a line spacing of the fine redistribution structure are smaller than those of the first build-up circuit structure. The conductive through hole penetrates the fine redistribution structure and a portion of the first build-up circuit structure and is electrically connected to the fine redistribution structure and the first build-up circuit structure.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits Details
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

An electroplating apparatus includes an anode and a cathode, a power supply, a regulating plate, and a controller. The power supply is electrically connected to the anode and the cathode. The regulating plate is disposed between the anode and the cathode. The regulating plate includes an insulation grid plate and a plurality of wires. The controller is electrically connected to the plurality of wires to control a state of an electromagnetic field around the plurality of wires. An electroplating method is also provided.

IPC Classes  ?

• C25D 5/00 - Electroplating characterised by the processPretreatment or after-treatment of workpieces
• C25D 21/12 - Process control or regulation
• H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

Abstract

An electroplating apparatus including an anode and a cathode, a power supply, and a regulating plate is provided. The power supply is electrically connected to the anode and the cathode. The regulating plate is arranged between the anode and the cathode. The regulating plate includes an insulating grid plate and a plurality of magnetic components. The plurality of magnetic components are uniformly and randomly arranged on the insulating grid plate. An electroplating method is also provided.

IPC Classes  ?

• C25D 5/00 - Electroplating characterised by the processPretreatment or after-treatment of workpieces
• C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating

Abstract

A circuit board assembly is provided and includes a first circuit board, a second circuit board and a first connecting module. The first connecting module includes a first connecting wire, a first connector and a second connector. The first circuit board includes a first processor, and the second circuit board includes a second processor. One end of the first connector is connected to one end of the first connecting wire, and the other end of the first connector is connected to the first circuit board. One end of the second connector is connected to the other end of the first connecting wire, and the other end of the second connector is connected to the second circuit board. The first connector is adjacent to the first processor, and the second connector is adjacent to the second processor.

IPC Classes  ?

• H05K 1/14 - Structural association of two or more printed circuits
• H05K 1/02 - Printed circuits Details
• H01R 12/79 - Coupling devices for flexible printed circuits, flat or ribbon cables or like structures connecting to rigid printed circuits or like structures

Abstract

A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 33/56 - Materials, e.g. epoxy or silicone resin
• H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls

Abstract

A packaging method includes steps of: forming first and second wiring layers electrically connected to each other on two opposite surfaces of a substrate; then configuring mother substrate interconnecting bumps on the first wiring layer and along perimeter of a daughter substrate unit, and then cutting along the perimeter of the daughter substrate unit to expose lateral faces of the mother substrate interconnecting bumps and configuring solder materials thereon; then configuring first and second chips on the first and the second wiring layers to form electrical interconnection between the two chips. A package structure enables interconnecting two chips through one single daughter substrate unit with its wiring layers directly connecting with lateral face contacts of the mother carrier substrate through the mother substrate interconnecting bumps. Hence, area of the daughter substrate unit is reduced; lengths of the interconnection paths are shortened, and qualities of communication and space utilization are enhanced.

IPC Classes  ?

• H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/498 - Leads on insulating substrates
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A circuit board, comprising a multi-layer circuit board, a first conductive circuit, a first circuit layer, an adhesion promoter layer, a second conductive circuit, and a second circuit layer. The multi-layer circuit board comprises an inner circuit and an opening. The opening exposes the inner circuit. The first conductive circuit is disposed in the opening and on the inner circuit. The first circuit layer is disposed on the first conductive circuit in the opening and lower than the depth of the opening. The adhesion promoter layer is disposed in the opening and on the surface of the multi-layer circuit board and connected to the first conductive circuit. The second conductive circuit is disposed on the adhesion promoter layer and on the first circuit layer in the opening. The second circuit layer is disposed on the second conductive circuit in the opening and on the second conductive circuit.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits Details
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

A vapor chamber structure includes a thermally conductive shell, a capillary structure layer, and a working fluid. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion and the second thermally conductive portion are a thermally conductive plate that is integrally formed, and the thermally conductive shell is formed by folding the thermally conductive plate in half and then sealing the thermally conductive plate. The first thermally conductive portion has at least one first cavity, the second thermally conductive portion has at least one second cavity. At least one sealed chamber is defined between the thermally conductive plate, the first cavity and the second cavity. A pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.

IPC Classes  ?

• F28D 15/04 - Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls in which the medium condenses and evaporates, e.g. heat-pipes with tubes having a capillary structure
• F28D 15/02 - Heat-exchange apparatus with the intermediate heat-transfer medium in closed tubes passing into or through the conduit walls in which the medium condenses and evaporates, e.g. heat-pipes
• F28F 3/10 - Arrangement for sealing the margins
• B23P 15/26 - Making specific metal objects by operations not covered by a single other subclass or a group in this subclass heat exchangers
• F28F 21/08 - Constructions of heat-exchange apparatus characterised by the selection of particular materials of metal

Abstract

A substrate is manufactured by drilling a chip containing groove in a composite inner layer circuit structure, having a component connecting end of a circuit layer protruding from a mounting side wall in the chip containing groove, mounting a chip component in the chip containing groove, and connecting the surface bonding pad to the component connecting end. The chip component in the present invention penetrates at least two circuit layers, and the surface bonding pad is bonded to the component connecting end of the circuit layer directly, reducing the occupied area of the chip component in each one of the circuit layers, and increasing the area for circuit disposing and the possible amount of chip components that may be mounted in the substrate.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 3/02 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
• H05K 3/42 - Plated through-holes
• H05K 3/00 - Apparatus or processes for manufacturing printed circuits

Abstract

A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, at least one second build-up circuit layer, at least one conductive through hole, and a fine redistribution layer (RDL). The embedded block is fixed in a through cavity of the dielectric substrate. The electronic component is disposed in an opening of the embedded block. The first build-up circuit layer is disposed on a top surface of the dielectric substrate and electrically connected with the electronic component. The second build-up circuit layer is disposed on a bottom surface of the dielectric substrate and covers the embedded block. The conductive through hole is disposed in a via of the embedded block and electrically connects the first and the second build-up circuit layers. The fine RDL is disposed on and electrically connected to the first build-up circuit layer.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/02 - Printed circuits Details

Abstract

An inspection apparatus used for inspecting a bare circuit board is provided, where the bare circuit board includes an antenna. The inspection apparatus includes a holding stage, a probing device, and a measurement device. The holding stage can hold the bare circuit board. The measurement device is electrically connected to the probing device and electrically connected to the antenna via the probing device. The measurement device can input a first testing signal to the antenna. The antenna can input a second testing signal to the measurement device after receiving the first testing signal. The measurement device can measure the antenna according to the second testing signal, where the first testing signal and the second testing signal both pass through no active component.

IPC Classes  ?

• G01R 29/08 - Measuring electromagnetic field characteristics

Abstract

A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, and at least one second build-up circuit layer. The dielectric substrate includes a through cavity penetrating the dielectric substrate. The embedded block is fixed in the through cavity. The embedded block includes a first through hole and a second through hole. The electronic component is disposed in the through hole of the embedded block. The first build-up circuit layer is disposed on the top surface of the dielectric substrate and covers the embedded block. The second build-up circuit layer is disposed on the bottom surface of the dielectric substrate and covers the embedded block.

IPC Classes  ?

• H05K 1/18 - Printed circuits structurally associated with non-printed electric components
• H05K 1/02 - Printed circuits Details
• H05K 1/09 - Use of materials for the metallic pattern
• H05K 1/03 - Use of materials for the substrate
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

A circuit board includes a substrate, a build-up circuit structure, a graphene oxide layer, a graphene layer, and an insulating material layer. The build-up circuit structure is disposed on the substrate, including at least one inner circuit, at least one dielectric layer, an outer circuit, and multiple conductive vias. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. The conductive vias penetrate the dielectric layer and electrically connect the inner circuit and the outer circuit. The graphene oxide layer and the graphene layer are disposed on the build-up circuit structure at an interval. The graphene oxide layer and the graphene layer are respectively disposed in correspondence to the dielectric layer and the outer circuit. The insulating material layer is disposed on the graphene oxide layer and the graphene layer. The insulating material layer has an opening, which exposes the graphene layer.

IPC Classes  ?

• H05K 3/46 - Manufacturing multi-layer circuits
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

An interlayer connective structure is suitable for being formed in a wiring board, in which the wiring board includes two traces and an insulation part between the traces. The insulation part has a through hole. The interlayer connective structure located in the through hole is connected to the traces. The interlayer connective structure includes a column and a pair of protuberant parts. The protuberant parts are located at two ends of the through hole respectively and connected to the column and the traces. The protuberant parts stick out from the outer surfaces of the traces respectively. Each of the protuberant parts has a convex curved surface, in which the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/42 - Plated through-holes
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer, and a connection structure layer. The redistribution structure layer has a first and second surface, and includes an inner and outer dielectric layer, first connecting pads, and chip pads. A bottom surface of each first connecting pad is aligned with the first surface, and the chip pads are protruded from and located on the second surface. The build-up circuit structure layer includes second connecting pads. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer and includes a substrate and conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads via the conductive paste pillars, respectively. A top surface of each conductive paste pillar is aligned with the first surface of the redistribution structure layer.

IPC Classes  ?

• H01R 12/52 - Fixed connections for rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/24 - Reinforcing of the conductive pattern
• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits