Abstract

A circuit board structure and a manufacturing method thereof are provided. The circuit board structure includes a ceramic board, a thick circuit layer formed on the ceramic board, and a thin circuit layer that is formed on the ceramic board. The thick circuit layer has a thickness being greater than or equal to 200 μm, and the thin circuit layer has a thickness being within a range from 1 μm to 150 μm. The thin circuit layer includes a sputtering layout segment connected to the ceramic board and an electroplating layer that is connected to the sputtering layout segment. The material of the electroplating layer is different from that of the sputtering layout segment.

IPC Classes  ?

• H05K 3/42 - Plated through-holes
• H05K 1/03 - Use of materials for the substrate
• H05K 3/46 - Manufacturing multi-layer circuits

Abstract

An optical package structure includes a substrate, an optical chip disposed on the substrate, a ring-shaped supporting layer disposed on the optical chip, a light-permeable layer disposed on the ring-shaped supporting layer, and an encapsulant formed on the substrate. The optical chip has a pressure channel arranged therein. Two ends of the pressure channel are respectively arranged on an outer surface of the optical chip and are respectively located at two opposite sides of the ring-shaped supporting layer. The light-permeable layer, the ring-shaped supporting layer, and the optical chip are embedded in the encapsulant and jointly define an air chamber that is in fluid communication with the pressure channel. The encapsulant encloses the pressure channel, and the air chamber is enclosed.

IPC Classes  ?

• H01L 31/0203 - Containers; Encapsulations
• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details

Abstract

A metal-ceramic substrate having double brazing layers and a method for manufacturing the same are provided. The metal-ceramic substrate includes a ceramic substrate layer, a conductive metal layer, and an active metal layer disposed between the ceramic substrate layer and the conductive metal layer. The active metal layer includes a first brazing layer formed from a first active metal solder and an organic dispersion medium, and a second brazing layer formed from a second active metal solder and another organic dispersion medium. The first active metal solder includes silver, copper, and a first active metal. Based on a total weight of the first active metal solder being 100 wt %, an amount of the silver ranges from 10 wt % to 60 wt %. The second active metal solder includes copper and a second active metal, but is without silver.

IPC Classes  ?

• C04B 37/02 - Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles
• B23K 35/02 - Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
• B23K 35/30 - Selection of soldering or welding materials proper with the principal constituent melting at less than 1550°C
• B23K 103/00 - Materials to be soldered, welded or cut

Abstract

An active metal brazing substrate and a method for manufacturing the same are provided. The active metal brazing substrate includes a ceramic substrate layer, an active metal layer, and a conductive metal layer. The active metal layer is disposed between the ceramic substrate layer and the conductive metal layer. The active metal layer is formed from an active metal solder and an organic dispersion medium. The active metal solder includes silver, copper, and an active metal. Based on a total weight of the active metal solder being 100 wt %, an amount of the silver ranges from 10 wt % to 60 wt %. A tensile strength of the active metal brazing substrate ranges from 165 N/cm to 270 N/cm.

IPC Classes  ?

• B32B 9/04 - Layered products essentially comprising a particular substance not covered by groups comprising such substance as the main or only constituent of a layer, next to another layer of a specific substance
• B23K 35/02 - Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
• B23K 35/30 - Selection of soldering or welding materials proper with the principal constituent melting at less than 1550°C
• B32B 37/06 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the heating method
• B32B 37/24 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer not being coherent before laminating, e.g. made up from granular material sprinkled onto a substrate
• H01L 23/373 - Cooling facilitated by selection of materials for the device

Abstract

A package structure includes a board, an inner metal layer, a metal piece, and a buffering conductor. The inner metal layer is disposed on an inner side of the board and includes a connection region. The metal piece has a first segment being spaced apart from and facing toward the connection region. The first segment and the connection segment have uneven surfaces that are complement in shape with each other and that have a gap there-between. The buffering conductor is arranged in the gap, and connects the first segment and the connection segment to be jointly formed as an expansion joint. The buffering conductor has a coefficient of thermal expansion (CTE) that is less than a CTE of the inner metal layer and that is less than a CTE of the metal piece.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/373 - Cooling facilitated by selection of materials for the device

Abstract

A method for reducing warpage occurred to a substrate during a packaging process includes attaching a plurality of dies to an upper surface of the substrate; attaching an adhesive material having a first curing temperature to a lower surface of the substrate; applying a liquid-packaging material having a second curing temperature to surroundings of the dies; heating the substrate, the adhesive material, and the liquid-packaging material to a heating temperature not less than the first curing temperature and the second curing temperature; and cooling the substrate, the adhesive material, and the liquid-packaging material to a room temperature. When being cooled to the room temperature, the liquid-packaging material applies an upper-surface shrinkage stress to the upper surface of the substrate, the adhesive material applies a lower-surface shrinkage stress to the lower surface of the substrate, and the lower-surface shrinkage stress is substantially equal to the upper-surface shrinkage stress.

IPC Classes  ?

• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A semiconductor package structure includes a conductive substrate, a chip, a plurality of conductive spacers, a lead frame, and an encapsulant that covers the above components. The conductive substrate has a chip-bonding surface and a heat-dissipation surface that is opposite to the chip-bonding surface. The chip is disposed on the chip-bonding surface of the conductive substrate, and has a plurality of connection pads arranged away from the conductive substrate. The conductive spacers are respectively disposed on the connection pads, and ends of the conductive spacers are arranged away from the conductive substrate and are coplanar with each other. The lead frame is connected to the ends of the conductive spacers in a flip-chip manner, and has an exposed surface. The heat-dissipation surface and the exposed surface are exposed from the encapsulant.

IPC Classes  ?

• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/495 - Lead-frames
• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass

Abstract

A power component submount includes a ceramic substrate, a sputtering layer formed on the ceramic substrate, a conductive block formed on the sputtering layer, and three electroless plating layers that are sequentially stacked on the conductive block. The sputtering layer includes an electroplating portion. The conductive block is formed on the electroplating portion, and bottoms of the three electroless plating layers are connected to the ceramic substrate. Materials of the three electroless plating layers are gold, palladium, and gold, respectively; or, materials of the three electroless plating layers are nickel, palladium, and gold, respectively. One of the three electroless plating layers arranged away from the conductive block is provided for allowing a power component to be mounted thereon.

IPC Classes  ?

• H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
• C23C 14/18 - Metallic material, boron or silicon on other inorganic substrates
• C23C 14/58 - After-treatment
• C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
• C23C 18/32 - Coating with one of iron, cobalt or nickelCoating with mixtures of phosphorus or boron with one of these metals
• C23C 18/42 - Coating with noble metals
• C23C 28/02 - Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups , or by combinations of methods provided for in subclasses and only coatings of metallic material
• C25D 5/02 - Electroplating of selected surface areas
• C25D 5/54 - Electroplating of non-metallic surfaces
• H05K 1/03 - Use of materials for the substrate

Abstract

An image sensing module is provided. The image sensing module includes an image sensor chip, a support member, a transparent layer, and a shielding layer. The support member is arranged on upper surface of the image sensor chip and surrounds an image sensing region of the image sensor chip. The transparent layer is arranged on upper surface of the support member. Lower surface of the transparent layer faces the image sensor chip, and includes a transparent region and a shielding region surrounding the transparent region. The transparent region corresponds to the image sensing region. Projection of the shielding region in normal direction of the lower surface of the transparent layer does not overlap with the image sensing region. The shielding layer is formed on the shielding region, and includes a frame portion and a plurality of reinforcing portions. The reinforcing portions are individually located at corners of the frame portion.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A light emitting diode package structure and a method for manufacturing the same are provided. The LED package structure includes a substrate having a first and a second surface opposite to each other, a conductive structure including a first and a second conductive structure electrically connected with each other, a first gold layer disposed on the first conductive structure, a second gold layer disposed on the second conductive structure, an LED chip disposed on the first gold layer, and a package layer disposed on the first surface and encapsulating the first conductive structure, the first gold layer, and the LED chip. The first conductive structure is disposed on the first surface. The second conductive structure is disposed on the second surface. A thickness of the first gold layer is greater than 1 μm. The second conductive structure is completely covered by the second gold layer.

IPC Classes  ?

• H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
• H01L 33/54 - Encapsulations having a particular shape

Abstract

A circuit board structure is provided. The circuit board structure includes a substrate, a solder mask coupler, a supporter, and a chip. The substrate has a conductive structure. The solder mask coupler is disposed on the substrate. The supporter contacts the solder mask coupler, and the supporter is fixed on the substrate via the solder mask coupler. The chip is disposed on the substrate, and the chip is electrically connected with the conductive structure.

IPC Classes  ?

• H05K 3/12 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using printing techniques to apply the conductive material
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A chip package structure and a manufacturing method are provided. The chip package structure includes a substrate, a first chip, an insulating layer and a plurality of routing layers. The substrate has a first metal pad and a second metal pad. The first chip is disposed on the first metal pad. The insulating layer is disposed on the substrate and partially covers the first metal pad, the second metal pad and the first chip. The plurality of routing layers are disposed on the substrate and electrically connected to the first metal pad, the second metal pad and the first chip.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass

Abstract

A ceramic substrate and a method for manufacturing the same are provided. The ceramic substrate includes a spheroidal aluminum nitride powder, a plate-shaped aluminum nitride powder, a boron nitride powder, and an yttrium oxide powder. A percentage by weight of the spheroidal aluminum nitride powder ranges between 63% and 90%. A percentage by weight of the plate-shaped aluminum nitride powder ranges between 0.05% and 30%. A percentage by weight of the boron nitride powder ranges between 0.05% and 2%. A percentage by weight of the yttrium oxide powder ranges between 0.05% and 5%. The method includes a tape casting operation and a primary and pressureless sintering process.

IPC Classes  ?

• C04B 35/581 - Shaped ceramic products characterised by their compositionCeramic compositionsProcessing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on non-oxides based on borides, nitrides or silicides based on aluminium nitride
• C04B 35/622 - Forming processesProcessing powders of inorganic compounds preparatory to the manufacturing of ceramic products
• C04B 35/626 - Preparing or treating the powders individually or as batches
• C04B 35/638 - Removal thereof
• C04B 35/64 - Burning or sintering processes

Abstract

A chip package structure includes a circuit substrate, a lead frame, a first chip, a second chip, a connecting member, and a package body. The lead frame is stacked on the circuit substrate, and the lead frame is bent to form an accommodating space. The first chip is disposed on the lead frame and located in the accommodating space. The second chip is disposed on the circuit substrate and located in the accommodating space. The connecting member is used to connect the lead frame and the circuit substrate. The package body is disposed on the circuit substrate and covers the first chip, the second chip, and the lead frame.

IPC Classes  ?

• H01L 23/495 - Lead-frames
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A semiconductor package structure and a method for producing the same are provided. The package structure includes a support substrate, a chip body disposed on the support substrate, a metal lead connected between the support substrate and the chip body, a spacer element disposed on the chip body, and a light-transmitting plate disposed on the chip body through the spacer element. The chip body, the spacer element, and the light-transmitting plate jointly define a closed space. The package structure further includes an encapsulation colloid formed on outsides of the closed space. The encapsulation colloid is formed by curing a liquid resin encapsulant and includes a plurality of first fillers and a plurality of second fillers dispersed therein. Before the liquid resin encapsulant is cured, a sinking rate of each of the second fillers in the liquid resin encapsulant is less than that of each of the first fillers.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a ring-shaped supporting layer disposed on the sensor chip, and a light-permeable layer disposed on the ring-shaped supporting layer. The ring-shaped supporting layer has an inner surrounding surface and an outer surrounding surface that is opposite to the inner surrounding surface. At least one of the inner surrounding surface and the outer surrounding surface has a plurality of round-ended microstructures that are sequentially connected to each other and that surround a sensing region of the sensor chip. An end of each of the round-ended microstructures is a round-ended portion having a radius of less than 1 μm. The light-permeable layer, the inner surrounding surface of the ring-shaped supporting layer, and the sensor chip jointly define an enclosed space.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

Abstract

A circuit board structure including metal materials with different thermal expansion coefficients and a method for producing the same are provided. The circuit board structure includes a core substrate layer, a first wiring layer formed on the core substrate layer, and an insulating dielectric layer formed on the first wiring layer. The insulating dielectric layer has a signal via hole formed at an inner side thereof. The circuit board structure further includes a first metal material and a second metal material formed in the signal via hole. The first metal material is formed on the first wiring layer, and the second metal material is formed on the first metal material. The first metal material has a first thermal expansion coefficient, the second metal material has a second thermal expansion coefficient, and the second thermal expansion coefficient is greater than the first thermal expansion coefficient.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H05K 1/09 - Use of materials for the metallic pattern
• H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits

Abstract

A wireless transistor outline (TO) package structure includes a carrying module, a chip and a lead frame both mounted on the carrying module, a sheet-like bonding module mounted on the chip and the lead frame in a flip chip manner, and an encapsulant that covers the above components therein. A connection pad of the chip and a connection segment of the lead frame are coplanar with each other. The sheet-like bonding module includes a ceramic substrate and a plurality of circuit layers that are stacked and formed on the ceramic substrate in a direct plated copper (DPC) manner. Areas of the circuit layers gradually decrease in a direction away from the ceramic substrate, and thicknesses of the circuit layers gradually increase in the same direction. The circuit layer arranged away from the ceramic substrate connects the connection pad and the connection segment for establishing an electrical connection therebetween.

IPC Classes  ?

• H01L 23/15 - Ceramic or glass substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
• H01L 23/498 - Leads on insulating substrates

Abstract

An active metal brazing substrate material and a method for producing the same are provided. The active metal brazing substrate material includes a ceramic substrate layer, a first brazing layer, a second brazing layer, and a conductive metal layer that are sequentially stacked. The first brazing layer includes a first metal composite material, which includes silver (Ag), copper (Cu), and a first active metal element. Based on a total weight of the first metal composite material being 100 parts by weight, a silver content is not less than 50 parts by weight. The second brazing layer includes a second metal composite material. The second metal composite material includes a low melting point metal element (e.g., Sn), copper (Cu), and a second active metal element, but does not include silver. A melting point of the low melting metal element is between 130° C. and 350° C.

IPC Classes  ?

• B23K 1/00 - Soldering, e.g. brazing, or unsoldering
• B23K 35/02 - Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
• B23K 35/30 - Selection of soldering or welding materials proper with the principal constituent melting at less than 1550°C
• B32B 15/04 - Layered products essentially comprising metal comprising metal as the main or only constituent of a layer, next to another layer of a specific substance

Abstract

An active metal brazing substrate material and a method for producing the same are provided. The active metal brazing substrate material includes a ceramic substrate layer, a first brazing layer, a second brazing layer, and a conductive metal layer that are sequentially stacked. The first brazing layer includes a first metal composite material, which includes silver (Ag), copper (Cu), and a first active metal element. Based on a total weight of the first metal composite material being 100 parts by weight, a silver content is not less than 50 parts by weight. The second brazing layer includes a second metal composite material, which includes aluminum (Al), copper (Cu), and a second active metal element, but does not contain silver. Based on a total weight of the second metal composite material being 100 parts by weight, an aluminum content is not less than 40 parts by weight.

IPC Classes  ?

• B23K 35/02 - Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
• B23K 35/28 - Selection of soldering or welding materials proper with the principal constituent melting at less than 950°C
• B23K 35/30 - Selection of soldering or welding materials proper with the principal constituent melting at less than 1550°C

Abstract

A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a first solder mask layer, a convex structure, a sensing chip, and an engaging layer. The first solder mask layer is disposed on the substrate. The convex structure is disposed on the first solder mask layer. The convex structure has a first stepped surface, and the first stepped surface is higher than an upper surface of the first solder mask layer. The sensing chip is disposed above the substrate. The engaging layer is adhered between the substrate and the sensing chip and covers the convex structure, such that the convex structure and the sensing chip are not in contact with each other.

IPC Classes  ?

• H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor

Abstract

A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a sensing chip, a light-permeable element, a photoresist layer, and a die-bonding film layer. The sensing chip is disposed on the substrate, and an upper surface of the sensing chip has a sensing region. The light-permeable element is disposed above the sensing chip. The photoresist layer is disposed on a first surface of the light-permeable element. The die-bonding film layer is adhered between the sensing chip and the light-permeable element and surrounds the sensing region.

IPC Classes  ?

• H01L 31/0203 - Containers; Encapsulations
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 27/146 - Imager structures

Abstract

A chip package structure and a method for producing the same are provided. The method at least includes: providing a substrate; placing a chip upside-down on the substrate; forming bonding wires coupled with the chip and the substrate; providing at least one reflecting member on an upper surface of the substrate, forming a support body on the substrate to cover the at least one reflecting member; providing a package cover adhered to the support body by a glass adhesive; performing a solidifying process in which a solidifying light beam is emitted to the reflecting member and the reflecting member reflects the solidifying light beam to the glass adhesive to solidify the glass adhesive; performing a packaging process in which a package body is formed to cover an edge surface of the package cover and a top part of the support body.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 27/146 - Imager structures

Abstract

A method for manufacturing a conductive circuit board includes the steps of: preparing a substrate having opposite upper and lower surfaces, and at least one via hole extending through the upper and lower surfaces and defined by an inner surface; forming a compound metal layer on at least one of the upper surface and the lower surface of the substrate and on the inner surface; etching the compound metal layer by a laser beam, so that a patterned metal circuit layer having a predetermined pattern formed on the substrate; and forming a surface finish layer on a top surface of the patterned metal circuit layer, so as to form a conductive circuit layer. A conductive circuit board manufactured therefrom is also enclosed.

IPC Classes  ?

• H05K 3/02 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
• H05K 1/02 - Printed circuits Details
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

Abstract

An intelligent power module (IPM) package structure and a hybrid ceramic board are provided. The hybrid ceramic board includes an insulating ceramic layer, a conductive layer connected to the insulating ceramic layer, and a direct-plated copper (DPC) ceramic substrate that is fixed onto the insulating ceramic layer. The conductive layer has a circuit layout slot recessed from an outer surface thereof to the insulating ceramic layer. The conductive layer has a plurality of first circuits, and any two of the first circuits adjacent to each other have a first conductor space therebetween that has a first minimal critical interval. The DPC ceramic substrate is disposed in the circuit layout slot and has a plurality of second circuits. Any two of the second circuits adjacent to each other have a second conductor space therebetween that has a second minimal critical interval less than the first minimal critical interval.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A composite ceramic substrate having multi-layer configuration includes a nitride ceramic core layer, two composite layers respectively formed on two opposite sides of the nitride ceramic core layer, and two ceramic covering layers that are respectively formed on the two composite layers. Each of the two ceramic covering layers is coated on the corresponding composite layer so as to be jointly sintered to the nitride ceramic core layer. Each of the two ceramic covering layers and the nitride ceramic core layer are of different materials, and a composite material of each of the two composite layers includes the material of the ceramic covering layer connected thereto and the material of the nitride ceramic core layer. A sum of the thicknesses of the two ceramic covering layers and the thicknesses of the two composite layers is less than or equal to a thickness of the nitride ceramic core layer.

IPC Classes  ?

• C04B 37/02 - Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles
• C04B 41/00 - After-treatment of mortars, concrete, artificial stone or ceramicsTreatment of natural stone
• C04B 41/50 - Coating or impregnating with inorganic materials
• C04B 41/52 - Multiple coating or impregnating
• C04B 41/87 - Ceramics
• C04B 41/89 - Coating or impregnating for obtaining at least two superposed coatings having different compositions

Abstract

A ceramic metal composite substrate includes a metal core layer, two soldering layers, and two ceramic covering layers. The metal core layer is a metal-diamond composite layer, and the metal core layer has two metallic surfaces spaced apart from each other along a thickness direction by a predetermined thickness. The two soldering layers are respectively formed on the two metallic surfaces. The two ceramic covering layers are respectively fixed to the two metallic surfaces through the two soldering layers. Each of the two ceramic covering layers has a heat-transfer coefficient greater than or equal to 20 W/m·k, and a sum of thicknesses of the two ceramic covering layers and thicknesses of the two soldering layers is less than or equal to the predetermined thickness. Each of the two ceramic covering layers overlaps at least 80% of an area of the corresponding metallic surface along the thickness direction.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• B32B 9/00 - Layered products essentially comprising a particular substance not covered by groups
• F28F 21/08 - Constructions of heat-exchange apparatus characterised by the selection of particular materials of metal

Abstract

A ceramic metal composite substrate (CMCS) includes a metal core layer, two soldering layers, and two ceramic covering layers. The metal core layer includes copper, and the metal core layer has two metallic surfaces spaced apart from each other along a thickness direction by a predetermined thickness. The two soldering layers are respectively formed on the two metallic surfaces. The two ceramic covering layers are respectively fixed to the two metallic surfaces through the two soldering layers. Each of the two ceramic covering layers has a heat-transfer coefficient greater than or equal to 20 W/m·k, and a sum of thicknesses of the two ceramic covering layers and thicknesses of the two soldering layers is less than or equal to the predetermined thickness. Each of the two ceramic covering layers overlaps at least 80% of an area of the corresponding metallic surface along the thickness direction.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H05K 1/02 - Printed circuits Details

Abstract

An optical device includes an electronic component, a light-permeable layer, and a ring-shaped adhesive layer that is sandwiched between the electronic component and the light-permeable layer. The ring-shaped adhesive layer surrounds an optical region of the electronic component and includes a plurality of light-weakening slots that are formed on an inner side surface thereof. The light-weakening slots are in a ring-shaped arrangement and surround the optical region. Each of the light-weakening slots has a slot opening having a slot width and a slot bottom spaced apart from the slot opening by a slot depth. A width of each of the light-weakening slots gradually decreases along a direction from the slot opening to the slot bottom, and a ratio of the slot width to the slot depth is within a range from 1:0.86 to 1:11.4, such that each of the light-weakening slots is configured to weaken light irradiated thereon.

IPC Classes  ?

• G02B 5/02 - Diffusing elementsAfocal elements

Abstract

A chip package structure includes a substrate, a chip, a light-permeable element, and an adhesive element. The chip is disposed on the substrate. The light-permeable element is disposed above the chip. The adhesive element is connected between the chip and the light-permeable element. The adhesive element surrounds the chip for formation of an accommodating space, and the chip is located in the accommodating space. The adhesive element includes two material layers having complementary visible light absorption spectra, such that the adhesive element is capable of being used to absorb full visible spectrum light.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A ceramic submount for a semiconductor device and a method for manufacturing the same are provided. The ceramic submount includes a ceramic core board, an electrode layer, and a solder unit. The electrode layer is disposed on one side of the ceramic core board. The solder unit includes a buffer containing layer and a soldering layer. A cross-section of the solder unit has an inversed-trapezoid shape. The buffer containing layer is disposed on a surface of the electrode layer. A receiving space is concavely formed on a top surface of the buffer containing layer, and the soldering layer is filled in the receiving space. The buffer containing layer surrounds the soldering layer.

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/15 - Ceramic or glass substrates
• H01L 23/498 - Leads on insulating substrates

Abstract

A bonding structure for connecting a chip and a metal material, and a manufacturing method thereof are provided. The bonding structure includes a substrate, a chip, a metal member, at least one metal wire and an alloy connection layer. An upper surface of the substrate has a first metal pad and a second metal pad. The chip is disposed on the first metal pad. The metal member is disposed above the chip. The at least one metal wire has a first end and a second end, the first end is connected to an upper surface of the metal piece, and the second end is connected to the second metal pad. The alloy connection layer is connected between the metal member and the chip, and covers at least a part of a lower surface of the metal member.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.

IPC Classes  ?

• H10F 19/20 - Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group , e.g. photovoltaic modules comprising photovoltaic cells in arrays in or on a single semiconductor substrate, the photovoltaic cells having planar junctions
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H10F 19/80 - Encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells
• H10F 77/30 - Coatings

Abstract

A printed circuit board (PCB) is disclosed. The PCB includes a substrate having a plurality of through holes, a plurality of thermally-conductive blocks disposed in the through holes respectively, bonding structures respectively disposed in each through holes, and a metal circuit formed on the substrate. Particularly, the thermally-conductive block is tightly attached to the inner wall of the through hole through the bonding structure. In brief, the bonding structure includes a metal block and metal layers coated on both surfaces of the metal block to replace the conventional adhesive layer made of epoxy resin to tightly fix the thermally-conductive block in the through hole.

IPC Classes  ?

• H05K 1/09 - Use of materials for the metallic pattern
• H05K 3/24 - Reinforcing of the conductive pattern

Abstract

A power chip packaging structure includes: a ceramic substrate; a first and a second top metal layers are formed on the ceramic substrate; a bottom metal layer formed on the ceramic substrate; a power chip having an active surface and a chip back surface. The active surface has a contact pad, and the chip back surface is connected to the first top metal layer. One or more first copper layers are formed on the contact pad, a top surface of the first copper layer has a peripheral region and an arrangement region surrounded by the peripheral region. Multiple second copper layers are formed in the arrangement region and separated from each other. Each of multiple wires is respectively connected to the second copper layer with one end and connected to the second top metal layer with the other end.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

This disclosure is related to a circuit board structure with an embedded ceramic substrate. A circuit substrate includes an insulating base, a first copper foil and a through-hole portion. A ceramic substrate is disposed in the through-hole portion and includes a ceramic substrate and a second copper foil. A plurality of positioning parts are arranged between the insulating base and the ceramic base. An adhesive layer is disposed between the insulating base and the ceramic base to seal the through-hole portion. A metal layer is disposed on the first copper foil and the second copper foil to cover the adhesive layer exposed from the through-hole portion. The metal layer is patterned to form a circuit layer. This disclosure also provides a manufacturing process of a circuit board structure with an embedded ceramic substrate.

IPC Classes  ?

• H05K 1/03 - Use of materials for the substrate
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 3/02 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
• H05K 3/24 - Reinforcing of the conductive pattern
• H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal

Abstract

A manufacturing method of a circuit board. The manufacturing method includes: providing a first substrate; forming an opening on the first substrate; disposing a second substrate, which has a plurality of through holes in the opening; forming an adhesive layer between the first substrate and the second substrate; forming a bonding layer on the first substrate and the second substrate; forming a metal layer on the bonding layer; and patterning the metal layer to form a circuit layer. A circuit board is also disclosed in the disclosure.

IPC Classes  ?

• H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
• H05K 1/03 - Use of materials for the substrate
• H05K 1/09 - Use of materials for the metallic pattern
• H05K 3/14 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material
• H05K 3/38 - Improvement of the adhesion between the insulating substrate and the metal
• H05K 3/44 - Manufacturing insulated metal core circuits

Abstract

A chip package structure includes a substrate, a chip, a light-permeable element, a first anti-reflective layer, and an adhesive element. The chip is disposed on the substrate. The light-permeable element is disposed above the chip. The light-permeable element has a first surface and a second surface opposite to each other, and the first surface faces the chip. The first anti-reflective layer covers at least part of the first surface. The adhesive element is connected between the chip and the light-permeable element, and the adhesive element separates the chip and the light-permeable element. The adhesive element and the first anti-reflective layer are not in contact with each other.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A chip package structure and a method for producing the same are provided. The method at least includes: providing a substrate; placing a chip upside-down on the substrate; forming bonding wires coupled with the chip and the substrate; forming a support body on the substrate; providing at least one reflecting member at a periphery of the support body; providing a package cover adhered to a top surface of the support body; performing a solidifying process in which a solidifying light beam is emitted to the reflecting member and the reflecting member reflects the solidifying light beam to the support body to solidify the support body; performing a packaging process in which a package layer is formed to cover the chip, an outer periphery of the support body, and the package cover; and performing a cutting process to form the chip package structure.

IPC Classes  ?

• H01L 21/52 - Mounting semiconductor bodies in containers
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/04 - ContainersSeals characterised by the shape
• H01L 27/146 - Imager structures

Abstract

A chip package structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a chip, a molding layer and a package cover. The conductive substrate has first and second board surfaces opposite to each other, and a die-bonding region is defined on the first board surface. The chip is disposed on the first board and located in the die-bonding region, and is electrically connected to the conductive substrate. The molding layer is disposed on the first board surface and surrounds the die-bonding region and the chip. The package cover is disposed on the molding layer, and the package cover, the molding layer and the conductive substrate jointly define an enclosed space surrounding the chip. Two of the conductive substrate, the molding layer and the package cover are connected to each other through a mortise-tenon joint structure.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or

Abstract

A chip package structure and a method for producing the same are provided. The method at least includes: providing a substrate; forming a mirror ink on the substrate; placing a chip upside-down on the substrate; forming soldering wires coupled with the chip and the substrate; forming a support body on the substrate; providing a package cover adhered to a top surface of the support body; performing a solidifying process in which a solidifying light beam is emitted to the mirror ink and the mirror ink reflects the solidifying light beam to the support body to solidify the support body; performing a packaging process in which a package layer is formed to cover the chip, an outer periphery of the support body, and the package cover; and performing a cutting process in which the package layer and the substrate are cut to form the chip package structure.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An optical package structure includes a light transmittable member, a bonding structural member, and an optical element. The bonding structural member includes a first bonding layer and a second bonding layer to form a light-scattering structure. The first bonding layer is connected to a bonding surface of the light transmittable member. An inner side of the first bonding layer includes a plurality of first protruded portions. An inner side of the second bonding layer includes a plurality of second protruded portions. The second protruded portions and the first protruded portions are arranged in a staggered manner. The bonding structural member includes the first bonding layer or the light-absorption member. The light-absorption member is filled in concaved portions of the first bonding layer. The optical element is connected to the bonding structural member, and is spaced apart from the light transmittable member.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Abstract

An optical package structure and a method for manufacturing the same are provided. The optical package structure includes an optical element, a bonding structural member, and a light transmittable member. The bonding structural member is bonded to a surface of the optical element. The bonding structural member includes a first bonding layer, a light-absorption layer, and a second bonding layer. The first bonding layer and the second bonding layer are made of an opaque material. The light-absorption layer is disposed between the first bonding layer and the second bonding layer. The light transmittable member is bonded to the bonding structural member and spaced apart from the optical element. The light-absorption layer is configured to absorb light emitted to the bonding structural member.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 31/0232 - Optical elements or arrangements associated with the device

Abstract

A chip packaging structure is provided. The chip packaging structure includes a first substrate, an image sensing chip, a supporting member, a second substrate, a grating film, and an encapsulant. The image sensing chip is disposed on an upper surface of the first substrate and has an image sensing region. The supporting member is disposed on an upper surface of the image sensing chip and surrounds the image sensing region. The second substrate is disposed on an upper surface of the supporting member. The grating film is disposed on a peripheral region of the second substrate and includes a plurality of grating units. The encapsulant is attached to the upper surface of the first substrate, a side surface of the supporting member, and a side surface of the second substrate.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A circuit substrate having an improved bonding structure includes a substrate core layer, an upper protective layer, and at least one bond finger portion. The substrate core layer has a top surface and a bottom surface. The upper protective layer is formed on the top surface of the substrate core layer. The upper protective layer has at least one channel. The at least one bond finger portion is formed on the top surface of the substrate core layer, and is disposed in the at least one channel. A plurality of protrusions are formed on an upper surface of the at least one bond finger portion, so as to increase a bonding area with a bonding wire.

IPC Classes  ?

• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on the substrate along a predetermined direction for being electrically coupled to each other, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer is formed with at least one type of a buffering cavity, wave-shaped slots, and rectangular slots, which penetrate therethrough along the predetermined direction. The buffering cavity can be located in the adhesive layer, and any one type of the wave-shaped slots and the rectangular slots can be respectively recessed in an inner side and an outer side of the adhesive layer. A minimum width of the adhesive layer is greater than or equal to 50% of a predetermined width between the inner side and the outer side.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer has two adhering surfaces having a same area and a middle cross section located at a middle position between the two adhering surfaces. An area of the middle cross section is 115% to 200% of an area of any one of the two adhering surfaces. The adhesive layer can provide for light to travel therethrough, and enables the light therein to change direction and to attenuate. The sensor chip, the adhesive layer, and the light-permeable layer are embedded in the encapsulant, and an outer surface of the light-permeable layer is at least partially exposed from the encapsulant.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a first chip, a second chip, a conductive substrate, a dielectric layer, a vertical conductive structure, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The vias penetrate through the substrate, and a part of the vias is disposed in a first die-bonding region and a second die-bonding region. The electrodes extend from the first board surface to the second board surface through the vias. The dielectric layer is formed on the substrate to cover a lower electrode portion of each of the electrodes. The vertical conductive structure is formed to be partially embedded into the dielectric layer and provide an electrical path between the first and second die-bonding regions. The dam is formed to surround the first and the second die-bonding regions.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/13 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group

Abstract

A chip packaging structure and a chip packaging method are provided. The chip packaging structure includes a first substrate, an image sensing chip, a supporting member, a second substrate, and an encapsulant. The image sensing chip is disposed on an upper surface of the first substrate, and the image sensing chip has an image sensing region. The supporting member is disposed on an upper surface of the image sensing chip and surrounds the image sensing region. The supporting member is formed by stacking microstructures with each other, so that the supporting member has pores. The second substrate is disposed on an upper surface of the supporting member, and the second substrate, the supporting member, and the image sensing chip define an air cavity. The encapsulant is attached to the upper surface of the first substrate and a side surface of the second substrate and filled into the pores.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.

IPC Classes  ?

• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or
• H01L 27/146 - Imager structures
• H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
• H01L 33/60 - Reflective elements
• H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls

Abstract

A sensor package structure is provided and includes a substrate, a sensor chip mounted on the substrate, a supporting layer being ring-shaped and disposed on the sensor chip, a light-permeable layer, and a grooved shielding layer that is ring-shaped and that is disposed on a lower surface of the light-permeable layer. The grooved shielding layer includes an inner barrier and an outer barrier respectively located at two opposite sides of the supporting layer. An inner edge of the inner barrier has an opening directly located above a sensing region of the sensor chip. The inner barrier, the outer barrier, and a part of the lower surface of the light-permeable layer jointly define a ring-shaped groove. The part of the lower surface of the light-permeable layer is disposed on the supporting layer, so that a part of the supporting layer is arranged in the ring-shaped groove.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a light-curing layer disposed on the sensor chip, a light-permeable layer disposed on the light-curing layer, a shielding layer disposed on an inner surface of the light-permeable layer, a light filter layer arranged between the light-curing layer and the shielding layer, and a package body that is formed on the substrate. A projection region defined by orthogonally projecting the shielding layer onto a top surface of the sensor chip surrounds a sensing region of the sensor chip. The shielding layer has at least one light-permeable slot being covered by the light filter layer. The sensor chip, the light-curing layer, the light-permeable layer, the light filter layer, and the shielding layer are embedded in the package body that exposes at least part of the light-permeable layer.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

A method for manufacturing a conductive circuit board includes the steps of: (a) preparing a substrate having opposite upper and lower surfaces, and at least one through hole extending through the upper and lower surfaces and defined by an inner surface; (b) forming a metal base layer on at least one of the upper and lower surfaces and on the inner surface; (c) etching the metal base layer by a laser beam so that the at least one of the upper and lower surfaces and the inner surface are formed with a patterned metal base layer; and (d) forming a metal circuit layer on the at least one of the upper and lower surfaces and on the inner surface to increase a thickness of the patterned metal base layer. A conductive circuit board manufactured therefrom is also enclosed.

IPC Classes  ?

• H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
• H05K 3/42 - Plated through-holes
• H05K 1/03 - Use of materials for the substrate

Abstract

A package substrate and a method for fabricating a chip assembly are provided. The method includes: providing a substrate, which has an upper substrate surface and a lower substrate surface, the upper substrate surface is divided into a plurality of scribe line regions that define a plurality of die-bonding regions, and any adjacent two of the die-bonding regions are separated by the scribe line regions. The die-bonding region is provided with a substrate conductor and a core material body, the substrate conductor penetrates the substrate and has upper and lower conductive ends exposed on the upper and lower substrate surfaces, respectively, and the core material body is disposed adjacent to the substrate conductor in the substrate. The method further includes: fixing chips in the die-bonding regions, respectively; and performing a dicing process along a plurality of scribe lines defined by the scribe line regions to form chip assemblies.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 23/498 - Leads on insulating substrates

Abstract

A sensor package structure is provided and includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a light-permeable layer, a supporting layer having a ring-shape and being sandwiched between the sensor chip and the light-permeable layer, and an encapsulant that is formed on the substrate. The supporting layer has an inner roughened surface being ring-shaped and having an irregular pattern. The light-permeable layer, the inner roughened surface of the supporting layer, and the sensor chip jointly define an enclosed space. The sensor chip, the supporting layer, and the light-permeable layer are embedded in the encapsulant, and at least part of outer surface of the light-permeable layer is exposed from the encapsulant. The inner roughened surface is configured to scatter light passing through the light-permeable layer to arrive thereon.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A sensor package structure and a chip-scale sensor package structure are provided. The chip-scale sensor package structure includes a sensor chip, a supporting layer having a ring-shape, and a light-permeable layer. A top surface of the sensor chip includes a sensing region and a carrying region that surrounds the sensing region. The supporting layer is disposed on the carrying region, and the light-permeable layer is disposed on the supporting layer through a ring-shaped segment thereof, so that the light-permeable layer, the supporting layer, and the sensor chip jointly define an enclosed space. The ring-shaped segment has a ring-shaped roughened region. A projection space defined by orthogonally projecting the ring-shaped roughened region toward the top surface of the sensor chip is located outside of the sensing region and overlaps an entirety of the supporting layer and a part of the enclosed space.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A sensor package structure is provided and includes a substrate, a sensor chip disposed on the substrate, a plurality of metal wires electrically coupling the substrate and the sensor chip, a frame fixed on the substrate, and a light-permeable layer that is disposed on the frame. The light-permeable layer has a transparent segment and a ring-shaped segment that surrounds the transparent segment. The ring-shaped segment is disposed on a top end surface of the frame, so that the light-permeable layer, the frame, and the substrate jointly define an enclosed space that accommodates the sensor chip and the metal wires therein. The ring-shaped segment has an inner ring-shaped roughened region that is arranged on an inner surface thereof and that is fixed onto the top end surface of the frame. Moreover, an inner edge of the inner ring-shaped roughened region is arranged in the enclosed space.

IPC Classes  ?

• H05K 5/02 - Casings, cabinets or drawers for electric apparatus Details
• H01L 27/146 - Imager structures
• H05K 5/00 - Casings, cabinets or drawers for electric apparatus
• H05K 7/14 - Mounting supporting structure in casing or on frame or rack

Abstract

A sensor lens assembly includes a circuit board, an optical module assembled onto the circuit board, and a sensing module that is surrounded by the optical module. The sensing module includes a sensor chip disposed on and electrically coupled to the circuit board, a supporting layer having a ring shape and disposed on the sensor chip, and a light-permeable layer. The light-permeable layer is disposed on the supporting layer through a ring-shaped segment thereof, so that the light-permeable layer, the supporting layer, and the sensor chip jointly define an enclosed space. The ring-shaped segment has a ring-shaped roughened region. A projection space defined by orthogonally projecting the ring-shaped roughened region toward the sensor chip is located outside of a sensing region of the sensor chip and overlaps an entirety of the supporting layer and a part of the enclosed space.

IPC Classes  ?

• G02B 5/02 - Diffusing elementsAfocal elements
• H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
• H04N 23/55 - Optical parts specially adapted for electronic image sensorsMounting thereof

Abstract

A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a sensor chip and a package cover. The substrate has first and second substrate surfaces that are opposite to each other. The sensing chip is disposed on the first substrate surface and has a sensing area. The package cover includes a molding layer, a supporting layer and a light-transmitting layer. The molding layer surrounds the sensing area and is disposed on the first board surface. The supporting layer surrounds the sensing area and is disposed on the molding layer. The light-transmitting layer is disposed on the supporting layer and covers the substrate, the sensor chip, the molding layer and the supporting layer. The light-transmitting layer, the supporting layer, and the molding layer are formed to surround an enclosed space, and the sensing area is located in the enclosed space.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/04 - ContainersSeals characterised by the shape
• H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container

Abstract

A sensor package structure is provided and includes a substrate, a sensor chip, a ring-shaped supporting layer, and a light-permeable sheet. The sensor chip is disposed on and electrically coupled to the substrate. The ring-shaped supporting layer is disposed on the sensor chip and surrounds a sensing region of the sensor chip. The light-permeable sheet has a ring-shaped notch recessed in a peripheral edge of an inner surface of the light-permeable sheet, and a depth of the ring-shaped notch with respect to the inner surface is at least 10 μm. The light-permeable sheet is disposed on the ring-shaped supporting layer through the ring-shaped notch, and the inner surface is not in contact with the ring-shaped supporting layer, so that the inner surface of the light-permeable sheet, an inner side of the ring-shaped supporting layer, and the top surface of the sensor chip jointly define an enclosed space.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip disposed on the substrate, a light-curing layer disposed on the substrate and surrounding the sensor chip, a light-permeable layer disposed on the light-curing layer, and a shielding layer that is ring-shaped and that is disposed on the light-permeable layer. And inner surface of the light-permeable layer, the light-curing layer, and the substrate jointly define an enclosed space that accommodates the sensor chip. A first projection area defined by orthogonally projecting the shielding layer onto the inner surface does not overlap the assembling region. A second projection area defined by orthogonally projecting the sensing region onto the inner surface along the predetermined direction does not overlap the first projection area and is located inside of the first projection area.

IPC Classes  ?

• H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
• H01L 23/492 - Bases or plates
• H01L 23/552 - Protection against radiation, e.g. light

Abstract

A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip, a ring-shaped wall, and a light-permeable layer. The substrate has a first surface and a second surface that is opposite to the first surface. The first surface of the substrate has a chip-bonding region and a connection region that surrounds the chip-bonding region, and the substrate has a plurality of protrusions arranged in the connection region. The sensor chip is disposed on the chip-bonding region of the substrate and is electrically coupled to the substrate. The ring-shaped wall is formed on the connection region of the substrate, and the protrusions of the substrate are embedded in and gaplessly connected to the ring-shaped wall. The light-permeable layer is disposed on the ring-shaped wall, and the light-permeable layer, the ring-shaped wall, and the substrate jointly define an enclosed space therein.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 μm. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

IPC Classes  ?

• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
• H01L 31/0203 - Containers; Encapsulations

Abstract

A sensor package structure is provided and includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a ring-shaped support disposed on the sensor chip, and a light-permeable layer disposed on the ring-shaped support. A top portion of the sensor chip defines a sensing region and a carrying region that surrounds the sensing region and that carries the ring-shaped support. The top portion of the sensor chip includes a passivation layer arranged in the sensing region and the carrying region, a color filter arranged in the sensing region and the carrying region, a pixel layer arranged in the sensing region and formed on the central segment, and a micro-lens layer that is formed on the pixel layer. A part of the color filter layer in the carrying region has a roughened surface and at least partially embedded in the ring-shaped support.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 μm. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

IPC Classes  ?

• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
• H01L 31/0203 - Containers; Encapsulations

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, an infrared light curing layer being in a ringed shape and disposed on the sensor chip, a light-permeable layer arranged above the sensor chip through the infrared light curing layer, and a visible light shielding layer that is in a ringed shape and that is disposed on the light-permeable layer. A sensing region of the sensor chip faces the light-permeable layer. The visible light shielding layer can block a visible light from passing therethrough, and has an opening located directly above the sensing region. The infrared light curing layer is located in a projection space defined by orthogonally projecting the visible light shielding layer toward the substrate, and the visible light shielding layer only allows an infrared light to travel onto the infrared light curing layer by passing therethrough.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a light-curing layer disposed on the sensor chip, a light-permeable layer disposed on the light-curing layer, a shielding layer being ring-shaped and disposed on an inner surface of the light-permeable layer, and a package body that is formed on the substrate. A projection region defined by orthogonally projecting the shielding layer onto a top surface of the sensor chip surrounds a sensing region of the sensor chip. A portion of the shielding layer in contact with the light-curing layer defines a ring-shaped arrangement region that has at last one light-permeable slot. The sensor chip, the light-curing layer, the light-permeable layer, and the shielding layer are embedded in the package body that exposes at least part of the light-permeable layer.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 μm. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

IPC Classes  ?

• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
• H01L 31/0203 - Containers; Encapsulations

Abstract

A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a sensor chip, and a cover. The sensor chip is disposed on and electrically coupled to the substrate. The cover is disposed on the substrate along an assembling direction, so that the sensor chip is arranged in a space surroundingly defined by the cover. The cover includes a light-permeable sheet, a light-shielding film, and an opaque frame. The light-shielding film is ring-shaped and is disposed on an inner surface of the light-permeable sheet, so as to divide the inner surface into a light-permeable region arranged inside of the light-shielding film and a formation region arranged outside of the light-shielding film The opaque frame is gaplessly formed on the formation region and is disposed on the substrate, and the opaque frame does not cover the light-shielding film.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A sensor lens assembly having a non-soldering configuration is provided. The sensor lens assembly includes a circuit board, an optical module fixed to the circuit board, a sensor chip and an extending wall both assembled to the circuit board, a plurality of wires electrically coupling the sensor chip and the circuit board, a supporting adhesive layer, and a light-permeable sheet. The extending wall surrounds the sensor chip and has an extending top surface that is substantially flush with a top surface of the sensor chip. The supporting adhesive layer is in a ringed shape and is disposed on the extending top surface of the extending wall and the top surface of the sensor chip. The light-permeable sheet is disposed on the supporting adhesive layer, so that the light-permeable sheet, the supporting adhesive layer, and the top surface of the sensor chip jointly define an enclosed space.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• H01L 23/00 - Details of semiconductor or other solid state devices
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A sensor lens assembly having a non-soldering configuration is provided. The sensor lens assembly includes a circuit board, an optical module fixed on the circuit board, a sensor chip assembled to the circuit board, a plurality of wires electrically coupled to the sensor chip and the circuit board, and a cover that overcovers the sensor chip and the wires. The cover includes a light-permeable sheet and an opaque frame. The light-permeable sheet has a ring-shaped notch recessed in an edge of an inner surface thereof. The opaque frame is formed on the ring-shaped notch and is disposed on the circuit board, the light-permeable sheet and the sensor chip are spaced apart from each other, and the sensor chip and the wires are arranged in a space that is defined by the light-permeable sheet and the opaque frame.

IPC Classes  ?

• G02B 7/02 - Mountings, adjusting means, or light-tight connections, for optical elements for lenses
• H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
• H04N 23/55 - Optical parts specially adapted for electronic image sensorsMounting thereof
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of wires electrically coupling the sensor chip to the substrate, a supporting colloid layer disposed on the substrate, and a light-permeable sheet that is disposed on the supporting colloid layer. The substrate has a first board surface and a second board surface that is opposite to the first board surface. The substrate has a chip-accommodating slot recessed in the first board surface. The sensor chip is disposed in the chip-accommodating slot, and a gap distance between a top surface of the sensor chip and the first board surface is less than or equal to 10 μm. The supporting colloid layer is ring-shaped and is disposed on the first board surface, and each of the wires is at least partially embedded in the supporting colloid layer.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A sensor lens assembly having a non-reflow configuration is provided. The sensor lens assembly includes a circuit board, an optical module fixed to a surface of the circuit board, a sensor chip assembled to the surface of the circuit board, a plurality of wires electrically coupling the sensor chip and the circuit board, a supporting adhesive layer, a light-permeable sheet, and a top shielding layer. The circuit board has no slot recessed in the surface thereof. The supporting adhesive layer is in a ringed shape and is disposed on a top surface of the sensor chip. The light-permeable sheet is disposed on the supporting adhesive layer and faces the sensor chip. The top shielding layer is formed on an outer surface of the light-permeable sheet and has an opening that is located above a sensing region of the sensor chip.

IPC Classes  ?

• H05K 1/02 - Printed circuits Details
• G02B 7/02 - Mountings, adjusting means, or light-tight connections, for optical elements for lenses
• G02B 7/00 - Mountings, adjusting means, or light-tight connections, for optical elements
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• H05K 1/18 - Printed circuits structurally associated with non-printed electric components

Abstract

A sensor lens assembly having a non-reflow configuration is provided. The sensor lens assembly includes a circuit board, an electronic chip assembled to the circuit board, a sensor chip, a die attach film (DAF) pre-bonded onto the sensor chip, a plurality of wires electrically coupling the electronic chip and the sensor chip to the circuit board, a supporting adhesive layer, a light-permeable sheet, and an optical module that is fixed to the circuit board for surrounding the above components. The sensor chip is adhered to the electronic chip through the DAF such that a sensing region of the sensor chip is perpendicular to a central axis of the optical module. The supporting adhesive layer is in a ringed shape and is disposed on a top surface of the sensor chip. The light-permeable sheet is disposed on the supporting adhesive layer and faces the sensor chip.

IPC Classes  ?

• G02B 7/00 - Mountings, adjusting means, or light-tight connections, for optical elements
• H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
• G02B 7/02 - Mountings, adjusting means, or light-tight connections, for optical elements for lenses
• H05K 1/02 - Printed circuits Details

Abstract

A sensor lens assembly having a non-reflow configuration is provided. The sensor lens assembly includes a circuit board, an optical module fixed to a surface of the circuit board, a sensor chip assembled to the circuit board, a plurality of wires electrically coupling the sensor chip and the circuit board, a supporting adhesive layer, and a light-permeable sheet. The circuit board has a chip-receiving slot recessed in the surface thereof. The sensor chip is arranged in the chip-receiving slot, and a top surface of the sensor chip and the surface of the circuit board have a step difference therebetween that is less than or equal to 10 μm. The supporting adhesive layer is in a ringed shape and is disposed on the top surface of the sensor chip. The light-permeable sheet is disposed on the supporting adhesive layer and faces the sensor chip.

IPC Classes  ?

• H04N 5/335 - Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
• H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
• H04N 23/51 - Housings
• H04N 23/55 - Optical parts specially adapted for electronic image sensorsMounting thereof

Abstract

A sensor package structure is provided and includes a substrate, a sensor chip disposed on the substrate, a plurality of wires electrically coupled to the substrate and the sensor chip, a light-permeable layer, and a colloid formed on the substrate to fix the light-permeable layer. The colloid covers the wires, a peripheral portion of the sensor chip, and lateral surfaces of the light-permeable layer. A top curved surface of the colloid is partially arranged beside the lateral surfaces. In a cross section of the sensor package structure, the top curved surface has a reference point spaced apart from one of the lateral surfaces adjacent thereto by 100 μm, a top edge of the top curved surface and the reference point define a connection line, and the connection line and the one of the lateral surfaces have an acute angle within a range from 25 degrees to 36 degrees.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

An image sensing chip package structure includes a chip, an adhesive loop and a light-transmissible substrate member. The chip includes an image sensing region. The adhesive loop is connected to the chip, and has an inner peripheral surface that defines a plurality of protrusions which surround the image sensing region of the chip. The light-transmissible substrate member is connected to the adhesive loop oppositely of the chip to cover the image sensing region of the chip. Methods of manufacturing the image sensing chip package structures are also provided.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of electrical connection members electrically connecting the sensor chip to the substrate, a supporting adhesive layer formed on the sensor chip, and a light-permeable sheet disposed on the supporting adhesive layer. Each of the electrical connection members includes a head solder disposed on a connecting pad of the sensor chip, a wire having a first end and a second end, and a tail solder. The first end of the wire extends from the head solder so as to connect the second end onto a soldering pad of the substrate, and the wire has a first bending portion arranged adjacent to the head solder. The head solder and the first bending portion of each of the electrical connection members are embedded in the supporting adhesive layer.

IPC Classes  ?

• H02H 1/00 - Details of emergency protective circuit arrangements
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A sensor package structure is provided and includes a substrate, a sensor chip disposed on the substrate, a padding layer disposed on the substrate, a plurality of wires, a support, and a light-permeable layer disposed on the support. A top side of the padding layer is coplanar with a top surface of the sensor chip, the support is disposed on the top side of the padding layer and the top surface of the sensor chip, and the wires are embedded in the support. Terminals at one end of the wires are connected to the top surface of the sensor chip, and terminals at the other end of the wires are connected to the top side of the padding layer, so that the sensor chip can be electrically coupled to the substrate through the wires and the padding layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 27/146 - Imager structures
• H01L 23/498 - Leads on insulating substrates

Abstract

A chip-scale sensor package structure includes a sensor chip, a first package body surrounding and connected to an outer lateral side of the sensor chip, a ring-shaped support disposed on a top side of the first package body, a light permeable member disposed on the ring-shaped support, and a redistribution layer (RDL) disposed on a bottom surface of the sensor chip and a bottom side of the first package body. The sensor chip includes a sensing region arranged on the top surface thereof, a plurality of internal contacts, and a plurality of conductive paths respectively connected to the internal contacts and electrically coupled to the sensing region. The sensing region is spaced apart from the ring-shaped support by a distance less than 300 μm. A bottom surface of the RDL has a plurality of external contacts electrically coupled to the internal contacts.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 21/22 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant
• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
• H01L 31/0203 - Containers; Encapsulations

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, an opaque support (e.g., a ring-shaped solder mask) disposed on the sensor chip, and a light permeable layer disposed on the opaque support. The sensor chip includes a sensing region. The opaque support surrounds the sensing region, and inner lateral sides of the opaque support form a light-scattering loop wall. The light permeable layer, the light-scattering loop wall of the opaque support, and the sensor chip jointly define an enclosed space therein. When light passes through the light permeable layer and impinges onto the light-scattering loop wall at an incident angle, the light-scattering loop wall scatters the light into multiple rays at angles different from the incident angle.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 31/0224 - Electrodes
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
• H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers

Abstract

A defect inspection method for a sensor package structure includes: using an image capture device to separately focus on and take pictures of at least three to-be-inspected regions of the sensor package structure along a height direction, so as to respectively obtain a defect image from one of the to-be-inspected regions, wherein the defect images are aligned with each other along the height direction and have different grayscale values; determining the defect image having a maximum grayscale value as a reference defect image, and defining any of the remaining defect images as a to-be-confirmed defect image; multiplying the maximum grayscale value by a predetermined grayscale ratio to obtain a predicted grayscale value, and confirming whether a difference between the to-be-confirmed and predicted grayscale values falls within an error range.

IPC Classes  ?

• G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
• G06T 7/00 - Image analysis
• G06T 7/30 - Determination of transform parameters for the alignment of images, i.e. image registration

Abstract

An electronic device includes a chip package module which includes a chip carrier substrate, a chip, a thermal conductive unit, and an encapsulant laver. The chip is electrically connected to the chip carrier substrate. The thermal conductive unit has a first thermal conductive surface connected to the chip, and a second thermal conductive surface opposite to the first thermal conductive surface. The thermal conductive unit has a thermal conductivity greater than that of the chip. The encapsulant layer covers the chip and partially covers the thermal conductive unit in such a manner that the second thermal conductive surface is exposed from the encapsulant layer.

IPC Classes  ?

• H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 27/146 - Imager structures

Abstract

A method for reducing warpage occurred to a substrate strip after a molding process is provided. First, several dies are mounted on a top surface of a substrate strip. Then, a base having a top surface with a surface curvature is provided, and the top surface of the base is contacted against a bottom surface of the substrate strip to bend the substrate strip. Next, under the status that the top surface of the base is contacted against the bottom surface of the substrate strip, a molding compound is wrapped around each die. Finally, the molding compound is cooled to a room temperature. Accordingly, the molding process is performed on the substrate strip reversely bent in a direction opposite to a warpage direction. Therefore, the warpage originally caused by the molding process is offset by the reverse bending.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An image sensing chip package structure includes a chip, an adhesive loop and a light-transmissible substrate member. The chip includes an image sensing region. The adhesive loop is connected to the chip, and has an inner peripheral surface that defines a plurality of protrusions which surround the image sensing region of the chip. The light-transmissible substrate member is connected to the adhesive loop oppositely of the chip to cover the image sensing region of the chip. Methods of manufacturing the image sensing chip package structures are also provided.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A sensor package structure and a sensing module thereof are provided. The sensor package structure includes a substrate, a sensor chip disposed on the substrate, a light-curing layer disposed on the sensor chip, a light-permeable layer arranged above the sensor chip through the light-curing layer, and a shielding layer disposed on a surface of the light-permeable layer. The light-curing layer has an inner lateral side and an outer lateral side opposite to the inner lateral side, and the inner lateral side is separated from the outer lateral side by a first distance. In a transverse direction parallel to a top surface of the sensor chip, the outer lateral side is separated from an outer lateral edge by a second distance which is within a range of ½ to ⅓ of the first distance.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A package component includes a base layer, a sensing layer, a photo-curable adhesive, a cover layer and a first filter structure. The photo-curable adhesive and the sensing layer are disposed on the base layer. The sensing layer includes a sensing unit surrounded by the photo-curable adhesive. The cover layer is disposed on the sensing layer. The first filter structure faces the photo-curable adhesive and is disposed on the cover layer. The first filter structure is configured for transmitting a curing light which is used to cure the photo-curable adhesive, and for reflecting a detectable light which is to be sensed by the sensing unit, where the wavelength of the curing light is different from the wavelength of the detectable light.

IPC Classes  ?

• H01L 31/0203 - Containers; Encapsulations
• B29C 35/08 - Heating or curing, e.g. crosslinking or vulcanising by wave energy or particle radiation
• C09D 5/00 - Coating compositions, e.g. paints, varnishes or lacquers, characterised by their physical nature or the effects producedFilling pastes

Abstract

An image sensor package includes a substrate, a sensor chip, a light-permeable cover, and a particle blocking dam. The substrate has a chip accommodating space, and the sensor chip is disposed in the chip accommodating space and electrically connected to the substrate. The light-permeable cover is disposed on the substrate and disposed above the sensor chip. The particle blocking dam is disposed above the sensor chip and extends from the light-permeable cover toward the sensor chip so as to be in contact with or close to the sensor chip.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A chip-scale sensor package structure includes a sensor chip, a ring-shaped support disposed on a top surface of the sensor chip, a light permeable member disposed on the ring-shaped support, a package body, and a redistribution layer (RDL). The package body surrounds outer lateral sides of the sensor chip, the ring-shaped support and the light permeable member. A bottom surface of the sensor chip and a surface of the light permeable member are exposed from the package body. The RDL is directly formed on the bottom surface of the sensor chip and a bottom side of the package body. The RDL includes a plurality of external contacts arranged on a bottom surface thereof and electrically coupled to the sensor chip. A portion of the external contacts are arranged outside of a projection region defined by orthogonally projecting the sensor chip onto the bottom surface of the RDL.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
• H01L 31/0203 - Containers; Encapsulations

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of metal wires electrically connecting the substrate and the sensor chip, a glass cover disposed on the sensor chip, and an adhesive layer connecting the glass cover to the substrate. The substrate is made of a material having a coefficient of thermal expansion (CTE) that is less than 10 ppm/° C. The glass cover includes a board body and an annular supporting body connected to the board body. The annular supporting body of the glass cover is fixed onto the substrate through the adhesive layer, so that the glass cover and the substrate jointly surround an enclosed accommodating space. The sensor chip and the metal wires are arranged in the accommodating space, and the sensing region of the sensor chip faces the light-permeable portion of the board body.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/04 - ContainersSeals characterised by the shape

Abstract

A sensor package structure includes a substrate, a sensor chip on the substrate, a ring-shaped support, a light permeable board on the ring-shaped support, and an opaque package body formed on the substrate. A top surface of the sensor chip includes a spacing region and a carrying region surrounding the spacing region. The support is disposed on the carrying region. The light permeable board has a ring-shaped notch recessed from an upper surface thereof, and the notch includes a platform surface at least partially located above the support and a wall surface connected to the platform surface and located above the spacing region. A portion of the opaque package body fills the notch and is defined as a light shielding portion. An inner lateral side of the support is arranged in a projection area formed by orthogonally projecting the platform surface onto the top surface.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/04 - ContainersSeals characterised by the shape
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

Disclosed is an optical sensor including a substrate, a redistribution chip structure disposed on the substrate, a sensor chip disposed on the redistribution chip structure, a light-permeable sheet arranged above the sensor chip, metal wires electrically connecting the substrate and the sensor chip, and a package body disposed on the substrate. The redistribution chip structure includes an insulating body, a first electronic chip embedded in the insulating body, and a redistribution layer (RDL) connected to bottoms of the insulating body and the first electronic chip. The RDL is fixed onto the substrate in a flip-chip manner. A projected region defined by orthogonally projecting a sensing area of the sensor chip onto the redistribution chip structure is located inside outer edges of the redistribution chip structure. The redistribution chip structure, the sensor chip, a part of the light-permeable sheet, and the metal wires are embedded in the package body.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A method for making a fingerprint sensor package module includes the steps of: providing a substrate, disposing a fingerprint sensor chip over a mounting region of the substrate, forming a masking layer on a sensing region of the fingerprint sensor chip, electrically connecting the substrate to the fingerprint sensor chip, molding an encapsulation structure, and removing the masking layer to expose the sensing region of the fingerprint sensor chip.

IPC Classes  ?

• G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
• G06K 9/20 - Image acquisition
• H01L 27/146 - Imager structures

Abstract

A sensor package structure includes a substrate, an electronic chip fixed on the substrate by flip-chip bonding, a sealant disposed on the substrate and embedding the electronic chip therein, a sensor chip with a size larger than that of the electronic chip, a light-permeable sheet, a plurality of metal wires electrically connected to the substrate and the sensor chip, and a package body. A bottom surface of the sensor chip is disposed on the sealant to be spaced apart from the electronic chip. A lateral surface of the sensor chip is horizontally spaced apart from that of the sealant by a distance less than or equal to 3 mm. The package body is disposed on the substrate and covers the metal wires as well as the lateral sides of the sealant and the sensor chip. The light-permeable sheet is fixed above the sensor chip through the package body.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 27/146 - Imager structures

Abstract

An inspection apparatus includes a focus assistant loader and a camera assembly. The focus assistant loader includes a fetching member and a focus member connected to the fetching member. The focus member includes a plurality of focus portions respectively located at different levels. The camera assembly includes a plurality of cameras. The cameras may face the focus assistant loader and respectively focus on the focus portions. Thus, by using the cameras to focus on the focus portions, the inspection apparatus may find out tiny defects on a tested device held by the focus assistant loader. In addition, the present disclosure also discloses a focus assistant loader of an inspection apparatus and a method for inspecting a sensor package structure.

IPC Classes  ?

• G06K 9/20 - Image acquisition
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
• B07C 5/342 - Sorting according to other particular properties according to optical properties, e.g. colour
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 27/146 - Imager structures

Abstract

A sensor package structure includes a substrate, a sensor chip, a plurality of wires, a supporting frame, a transparent cover, and a molding compound. The substrate includes a chip bonding region and a plurality of first pads outside the chip bonding region. The sensor chip is disposed on the chip bonding region, and includes a sensing region and a plurality of second pads. Each wire has two opposite ends respectively connected to one of the first pads and one of the second pads. The supporting frame is arranged above the substrate and/or the sensor chip and includes a positioning portion. The transparent cover is fixed in position above the sensor chip by the positioning portion so as to maintain a vertical distance there-between. The molding compound fills the space in-between the substrate and the supporting frame and covers a part of an upper surface of the supporting frame.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/053 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
• H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of wires electrically connected to the substrate and the sensor chip, a transparent layer facing the sensor chip, a support disposed on the substrate, and a packaging compound disposed on the substrate and covering side edges of the support and the transparent layer. A part of each wire is embedded in the support. A height from the upper surface of the substrate to the top of the support is larger than a height from the upper surface of the substrate to the top of any of the wires. The bottom surface of the transparent layer has a central region facing the sensor chip and a ring-shaped supporting region surrounded by the central region. The support is arranged outside the sensor chip and abuts against the supporting region.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A stack type sensor package structure includes a substrate, a semiconductor chip disposed on the substrate, a frame disposed on the substrate and aside the semiconductor chip, a sensor chip disposed on the frame, a plurality of wires electrically connecting the sensor chip and the substrate, a transparent layer being of its position corresponding to the sensor chip, a support maintaining the relative position between the sensor chip and the transparent layer, and a package compound disposed on the substrate and partially covering the frame, the support, and the transparent layer. Thus, through disposing a frame within the stack type sensor package structure, the structural strength of the overall sensor package structure is reinforced, and the stability of the wiring of the sensor chip is effectively increased.

IPC Classes  ?

• B81B 7/00 - Microstructural systems
• B81C 3/00 - Assembling of devices or systems from individually processed components
• H04N 5/225 - Television cameras
• B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 27/146 - Imager structures

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of metal wires electrically connecting the sensor chip to the substrate, a light-permeable layer, a combining layer connecting a portion of the light-permeable layer onto the sensor chip, and a packaging compound covering lateral sides of the sensor chip, the light-permeable layer, and the combining layer. Each of the metal wires is embedded in the combining layer and the packaging compound, and has a diameter within a range of 0.8-1.1 mil. Each of the metal wires includes a first segment connected to the substrate and a second segment connected to the sensor chip. In each of the metal wires, the second segment integrally and curvedly extends from the first segment, and the second segment and a top surface of the sensor chip have a sloping angle within a range of 5-45 degrees.

IPC Classes  ?

• H01L 31/0203 - Containers; Encapsulations
• H01L 27/146 - Imager structures
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates