A method for making a semiconductor device comprises: providing one or more packages, wherein each of the one or more packages includes: a first substrate comprising a first surface and a second surface, a protection tape attached onto the first surface of the first substrate, one or more electronic components mounted on the second surface of the first substrate, and one or more conductive structures mounted on the second surface of the second substrate; mounting the one or more packages onto a first surface of a second substrate, wherein the one or more conductive structures connect the first substrate and the second substrate; applying a molding material to cover the one or more electronic components and the one or more conductive structures; and removing the protection tape from each of the one or more packages.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
A semiconductor package including a first redistribution structure, a second redistribution structure disposed on the first redistribution structure, a semiconductor chip disposed on an upper surface of the second redistribution structure, a bridge chip disposed on a lower surface of the second redistribution structure, a molding layer disposed between the first redistribution structure and the second redistribution structure, where the molding layer surrounds the bridge chip, and a stiffener disposed on the upper surface of the second redistribution structure. The stiffener includes an opening. The semiconductor chip is disposed in the opening of the stiffener.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A semiconductor package that includes an upper package including a first package substrate, a first semiconductor chip mounted on the first package substrate, and a first molding layer surrounding the first semiconductor chip; a printed circuit board (PCB) on which the upper package is mounted in a central region; and a stiffener positioned on a top surface of the PCB and including an opening. A top surface of the PCB contacts a bottom surface of the stiffener in at least part of edge regions of the PCB. In the central region of the PCB and in edge regions other than the at least part of edge regions of the PCB, a top surface of the PCB is apart from the bottom surface of the stiffener in a vertical direction, and the opening of the stiffener overlaps the upper package in the vertical direction.
H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
4.
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package and a method of manufacturing the semiconductor package are provided. The semiconductor package includes an interposer, a semiconductor chip on the interposer, an under bump metal (UBM) pad between the interposer and the semiconductor chip and including an upper UBM pad and a lower UBM pad, and a connection member between the UBM pad and the semiconductor chip, wherein the connection member is in contact with one or more side surfaces of the UBM pad and is in contact with the interposer.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
5.
Semiconductor Device and Methods of Making and Using Pre-Molded Bridge Die
A semiconductor device has a first interconnect structure. A pre-molded bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the pre-molded bridge die. A second interconnect structure is disposed over the encapsulant and pre-molded bridge die. A first semiconductor die is disposed over the second interconnect structure within a footprint of the pre-molded bridge die. A second semiconductor die is disposed over the second interconnect structure within the footprint of the pre-molded bridge die.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
6.
Semiconductor Device and Method of Forming Fan-Out Package Structure with Embedded Overhanging Backside Antenna
A semiconductor device has an electrical component and a first interconnect structure disposed adjacent to the electrical component. The electrical component can be a direct metal bonded semiconductor die or a flipchip semiconductor die. The first interconnect structure can be an interposer unit or a conductive pillar. A split antenna is disposed over the electrical component and first interconnect structure. The split antenna has a first antenna section and a second antenna section with an adhesive material disposed between the first antenna section and second antenna section. A second interconnect structure is formed over the electrical component and first interconnect structure. The second interconnect structure has one or more conductive layers and insulating layers. The first interconnect structure and second interconnect structure provide a conduction path between the electrical component and split antenna. An encapsulant is deposited around the electrical component and first interconnect structure.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles
7.
Semiconductor Device and Method of Making a Dual-Sided Bridge Die Package Structure
A semiconductor device has a first interconnect structure. A first bridge die is disposed over the first interconnect structure. An encapsulant is deposited over the first bridge die. A second interconnect structure is formed over the first bridge die and encapsulant. A second bridge die is disposed over the second interconnect structure.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
An integrated package and a method for making the same are provided. The integrated package includes: an antenna module including: an antenna module substrate; and a top antenna structure disposed on the antenna module substrate; a first encapsulant encapsulating the antenna module; a first redistribution structure disposed on a bottom surface of the first encapsulant, wherein the first redistribution structure includes a bottom antenna structure configured for coupling electromagnetic energy with the top antenna structure; and a semiconductor chip mounted on a bottom surface of the first redistribution structure and electrically coupled with the bottom antenna structure.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A method for attaching a heat spreader to a semiconductor package is provided. The method comprises: providing a semiconductor package, wherein the semiconductor package comprises a package substrate, a semiconductor component mounted on the package substrate and a mold cap formed on the package substrate and encapsulating the semiconductor component, and wherein the mold cap comprises a laser-activatable mold compound; removing a portion of a thickness of the mold cap above the semiconductor component by laser ablation to form a cavity in the mold cap and transform the laser-activatable mold compound at an inner surface of the cavity to a conductive layer; dispensing a thermal interface material (TIM) in the cavity to form on the conductive layer a TIM layer that protrudes from the mold cap; and attaching the heater spreader to the semiconductor package at least through the TIM layer.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
10.
Semiconductor Device and Method of Inhibiting Creep of Underfill Material on Back Surface of Semiconductor Die
A semiconductor device has a first substrate with a surface. A thickness of the first substrate is less than 120 micrometers. The surface undergoes a grinding operation. The surface of the first substrate is then polished to produce a polished surface. The first substrate is singulated into a plurality of semiconductor die. The semiconductor die is over an interposer. The interposer has a second substrate and a conductive via formed through the second substrate. The interposer further has a first insulating layer formed over a first surface of the second substrate, first conductive layer formed over the first surface, second insulating layer formed over a second surface of the second substrate, second conductive layer formed over the second surface, and bump formed over the second conductive layer. An underfill material is deposited around the semiconductor die. The polished surface inhibits progression of the underfill material onto the polished surface.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
11.
ELECTRONIC PACKAGE ASSEMBLY AND A METHOD FOR FORMING THE SAME
An electronic package assembly and a method for forming the same is provided. The electronic package assembly comprises: a first electronic package comprising a first package substrate, and a first mold cap formed on the first package substrate, wherein the first mold cap has at its periphery a male gap; and a second electronic package comprising a second package substrate, and a second mold cap formed on the second package substrate, wherein the second mold cap has at its periphery a female gap which mates the male gap in shape; wherein the first mold cap is connected with the second mold cap through an adhesive material with the male gap of the first mold cap being adjacent to the female gap of the second mold cap.
A semiconductor manufacturing equipment has a wafer tape including a plurality of alignment holes formed through the wafer tape. A semiconductor wafer is disposed over the wafer tape. The semiconductor wafer includes a circular or rectangular form-factor. A light source is disposed under the wafer tape. The semiconductor wafer is misaligned on the wafer tape with light passing through one or more alignment holes. The semiconductor wafer is centered on the wafer tape with no light passing through one or more alignment holes. The wafer tape has a plurality of wafer alignment markings for different size semiconductor wafers. A light detector is disposed over the semiconductor wafer to detect light passing through the wafer tape. A control arm can be attached to the semiconductor wafer to provide the ability to move the semiconductor wafer in response to a control signal from the light detector.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
13.
Semiconductor Device and Methods of Making and Using Dummy Vias to Reduce Short-Circuits Between Solder Bumps
A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die to form a reconstituted wafer. A first insulating layer is formed over the reconstituted wafer. A first dummy opening is formed in the first insulating layer. A first conductive layer is formed on the first insulating layer including a first contact pad over the first dummy opening.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
14.
Semiconductor Device and Method of Forming FOWLP with Pre-Molded Embedded Discrete Electrical Component
A semiconductor device has a pre-molded discrete electrical component and a first encapsulant deposited over the pre-molded discrete electrical component. A first conductive layer is formed over the first encapsulant and pre-molded discrete electrical component. An electrical component is disposed over the first conductive layer. A second encapsulant is deposited over the electrical component and first conductive layer. A second conductive layer is formed over the second encapsulant. A conductive pillar is formed between the first conductive layer and second conductive layer through the second encapsulant. The pre-molded discrete electrical component has a discrete component and a third encapsulant deposited around the discrete component. The discrete component has an electrical terminal, a finish formed over the electrical terminal, and a third conductive layer formed over the finish. An interconnect structure formed on the electrical component is oriented toward the first conductive layer or the second conductive layer.
A semiconductor device has a carrier. A first redistribution layer is formed over the carrier. A capping layer is formed on the first redistribution layer. The capping layer includes an anti-reflective coating. An insulating layer is formed on the capping layer. An opening is formed through the insulating layer using photolithography. A conductive layer is formed in the opening.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A semiconductor device has a semiconductor wafer or substrate including a plurality of semiconductor die. A plurality of first bumps is formed over an active surface of the semiconductor wafer. A plurality of second bumps is formed within a saw street of the semiconductor wafer separating the plurality of semiconductor die. A top surface of the first bumps is coplanar with a top surface of the second bumps. The second bumps are formed within a first saw street of the semiconductor wafer and further within a second saw street of the semiconductor wafer different from the first saw street. The first bumps are electrically connected to the semiconductor die to provide a function for the semiconductor die. The second bumps are dummy bumps that have no electrical function for the semiconductor die. The semiconductor wafer is singulated through the saw street and second bumps.
A semiconductor device has a carrier. An electrical component is disposed over the carrier. An encapsulant is deposited over the electrical component. A conductive layer is formed over the encapsulant. The conductive layer is deposited as a plurality of graphene-coated metal balls in a matrix. The conductive layer is sintered by intensive pulsed light (IPL) irradiation.
A semiconductor device has an electrical component with bump structures. A conductive layer is formed over the electrical component with a first segment of the conductive layer coupled between the first and second bumps. The electrical component is disposed on a paddle of a lead frame interposer. A first bond wire is coupled between a first lead and the first bump. A second bond wire is coupled between a second lead and the second bump. A third bond wire is coupled between a third lead and a third bump, and a fourth bond wire is coupled between a fourth lead and a fourth bump. A fifth bond wire coupled between the second lead and third lead and a second segment of the conductive layer is coupled between the third bump and fourth bump to constitute a daisy chain loop to test continuity of the bump structures.
A semiconductor package is provided, comprising: a package substrate; a first plurality of semiconductor dice disposed on a front side of the package substrate; an embedded sub-package disposed on a back side of the package substrate, comprising: a sub-package substrate, wherein a front side of the sub-package substrate is attached to the back side of the package substrate; an interconnection layer attached to a back side of the sub-package substrate, comprising a second plurality of vertical interconnection portions and at least one horizontal interconnection portion; and a second plurality of semiconductor dice disposed on the back side of the sub-package substrate through the interconnection layer; and a first plurality of vertical interconnection portions disposed on the back side of the package substrate; and solder bumps attached to the first plurality of vertical interconnection portions.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
20.
SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME
A semiconductor device comprises: an interconnection substrate having a front side and a back side, wherein the interconnection substrate comprises interconnection structures extending between its front side and back side, and a bridge module embedded within the interconnection substrate and exposed from the back side of the interconnection substrate; a front side semiconductor component mounted at the front side of the interconnection substrate; two backside semiconductor components mounted at the back side of the interconnection substrate, wherein the two backside semiconductor components are electrically coupled to each other and electrically coupled to the front side semiconductor component; a backside encapsulant layer formed at the back side of the interconnection substrate and encapsulating the two backside semiconductor components, wherein the backside encapsulant layer comprises multiple sets of conductive pillars; and conductive bumps mounted at a back side of the backside encapsulant layer and electrically coupled to the interconnection substrate through conductive pillars.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/057 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads being parallel to the base
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
21.
Semiconductor Device and Method of Integrating eWLB with E-bar Structures and RF Antenna Interposer
A semiconductor device has an electrical component and a plurality of e-bar structures disposed adjacent to the electrical component. An antenna interposer is disposed over a first surface of the e-bar structures. A redistribution layer is formed over a second surface of the e-bar structures opposite the first surface of the e-bar structures. The redistribution layer has a conductive layer and an insulating layer formed over the conductive layer. An encapsulant is deposited over the electrical component. The antenna interposer has a first conductive layer, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the insulating layer. The second conductive layer can be arranged as a plurality of islands or in a serpentine pattern.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles
22.
Semiconductor Device and Method of Making Redistribution Layers with Intensive Pulsed Light Irradiation
A semiconductor device has a substrate. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component. A conductive layer is formed over the substrate opposite the electrical component after depositing the encapsulant. The conductive layer is deposited as a plurality of graphene-coated metal balls in a matrix. The conductive layer is sintered by intensive pulsed light (IPL) irradiation.
A method for forming conductive structures between two substrates is disclosed. The method comprises: forming a first patterned base layer and a second patterned base layer on a first substrate and a second substrate, wherein the first and second patterned base layers comprise through-holes; forming first and second metallic contact structures in the through holes of the first and second patterned base layer, wherein both the first and second metallic contact structures have front surfaces that are higher than respective front surfaces of the first and second patterned base layers; forming a first and a second patterned polymer layer on the respective front surfaces of the first and second patterned base layer, wherein the first and second metallic contact structures are exposed from and higher than respective front surfaces of the first and second patterned polymer layer; passivating the front surfaces of the first and second metallic contact structures; bonding the front surfaces of the first and second metallic contact structures with each other; and bonding the front surfaces of the first and second patterned polymer layers with each other after the front surfaces of the first and second metallic contact structures are bonded with each other.
A semiconductor device has a PCB with an antenna and a semiconductor package mounted onto the PCB. An epoxy molding compound bump is formed or disposed over the PCB opposite the semiconductor package. A first shielding layer is formed over the PCB. A second shielding layer is formed over the semiconductor package. A board-to-board (B2B) connector is disposed on the PCB or as part of the semiconductor package. A conductive bump is disposed between the semiconductor package and PCB.
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01R 12/71 - Coupling devices for rigid printing circuits or like structures
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
25.
SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME
A semiconductor package and a method for making the same are provided. The semiconductor package includes: a substrate having a lower substrate surface and an upper substrate surface; a first interposer attached on the upper substrate surface; at least one first electronic component mounted on and electronically connected with the first interposer; a second interposer disposed above the at least one first electronic component, wherein the second interposer has a concave portion and a protruding portion, the at least one first electronic component is accommodated in the concave portion, and the protruding portion is mounted on the upper substrate surface; and at least one second electronic component mounted on and electronically connected with the second interposer.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
26.
TWO-WAY OPTICAL SENSOR PACKAGE AND A METHOD FOR FORMING THE SAME
An optical sensor package comprises: a base substrate having a window; a first optical sensor mounted on a front surface of the base substrate, with its light receiving surface facing towards and aligned with the window; a first light-pervious encapsulant mold covering the light receiving surface of the first optical sensor; a first encapsulant layer formed on the front surface of the base substrate, wherein the first encapsulant layer comprises interlayer connects passing therethrough; an interposer mounted on the first encapsulant layer and electrically coupled to the base substrate through the interlayer connects of the first encapsulant layer; a second optical sensor mounted on a front surface of the interposer, with its light receiving surface facing away from the interposer; a second light-pervious encapsulant mold covering the light receiving surface of the second optical sensor; and a second encapsulant layer formed on the front surface of the interposer.
A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component. A shielding layer is formed over the encapsulant. The shielding layer includes a plurality of graphene-coated metal balls in a matrix. The shielding layer is sintered using intensive pulsed light (IPL) radiation.
A semiconductor device has a first substrate. A first semiconductor die and second semiconductor die are disposed over the substrate. An interconnect bridge is disposed over the first semiconductor die and second semiconductor die. The interconnect bridge has a second substrate. A conductive trace is formed over the second substrate. The conductive trace is electrically coupled from the first semiconductor die to the second semiconductor die. An IPD is also formed over the second substrate. The IPD is electrically coupled between the first semiconductor die and second semiconductor die. An encapsulant is deposited over the first substrate, first semiconductor die, second semiconductor die, and interconnect bridge.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A method for forming a sensor package is disclosed. The method comprises: providing a sensor; forming an optical filter and a transparent mold on the sensor to form a sensor assembly; providing a substrate, wherein one or more connectors are attached on a front surface of the substrate; forming a first encapsulant layer on the front surface of the substrate, wherein the one or more connectors are exposed from the first encapsulant layer; disposing the sensor assembly on the first encapsulant layer; connecting the sensor with the one or more connectors; and forming a second encapsulant layer on the first encapsulant layer to cover the sensor assembly.
A semiconductor device has a plurality of electrical components and an encapsulant deposited over the electrical components. A first saw street of the encapsulant separates a first electrical component from a second electrical component. A first channel is formed in a first surface of the encapsulant within the first saw street to reduce stress. A second channel is formed in a second surface of the encapsulant opposite the first surface and within the first saw street. A third channel is formed in the first surface of the encapsulant and within a second saw street of the encapsulant normal to the first saw street. An RDL is formed over the electrical components. The RDL has an insulating layer formed over the electrical component, and a conductive layer formed over the insulating layer. The insulating layer terminates prior to the first saw street.
An optical sensor package is disclosed. The package comprises: a package substrate having a front surface and a back surface; an optical sensor mounted on the package substrate, wherein the optical sensor is encapsulated by a first light-pervious encapsulant mold; a light source mounted on the front surface of the package substrate, wherein the light source is encapsulated by a second light-pervious encapsulant mold; a central interposer mounted on the front surface of the package substrate via a support wall and between the optical sensor and the light source, wherein the central interposer and the support wall are light-impervious to prevent the light source from illuminating directly onto the optical sensor; and at least one electronic component mounted on the central interposer, wherein the at least one electronic component is electrically coupled to the optical sensor via a first interconnect that passes through the first light-pervious encapsulant mold.
A semiconductor device and a method for making the same are provided. The method includes: providing a package including: a substrate having a front substrate surface and a back substrate surface, wherein the substrate includes a plurality of singulation areas separating the substrate into a plurality substrate units; a plurality of first electronic components mounted on the front substrate surface and within the plurality substrate units, respectively; and an encapsulant formed on the front substrate surface and encapsulating the plurality of first electronic components; forming a plurality of trenches at the plurality of singulation areas, respectively, wherein each of the plurality of trenches has a first portion extending through the encapsulant and a second portion extending through the encapsulant and the substrate; and forming an EMI shield to cover the encapsulant and lateral surfaces of the plurality of substrate units exposed by the second portions of the plurality of trenches.
An electronic package is provided. The electronic package includes: a substrate comprising a substrate surface, and a first set of conductive patterns and a second set of conductive patterns on the substrate surface; at least one electronic component attached on the substrate surface and electrically connected to the second set of conductive patterns; an encapsulant layer encapsulating the at least one electronic component and exposing the first set of conductive patterns; and a shielding layer formed over the encapsulant layer and not over the first set of conductive patterns, wherein the shielding layer is formed of a conductive ink cured by ultraviolet light.
A semiconductor package stack comprises: a base substrate having one or more sets of base conductive patterns on its front surface; an anisotropic conductive film formed on the front surface of the base substrate; one or more semiconductor packages disposed on the base substrate via the anisotropic conductive film, wherein each of the one or more semiconductor packages comprises package interconnect structures which have package conductive patterns exposed from a lateral surface of the semiconductor package; and wherein the package conductive patterns are aligned with base conductive patterns; and a vertical substrate disposed on the base substrate via the anisotropic conductive film, wherein the vertical substrate comprises vertical interconnect structures which have vertical conductive patterns exposed from a lateral surface of the vertical substrate; and wherein the vertical conductive patterns are aligned with base conductive patterns.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
36.
Semiconductor Device and Method of Forming Shielding Material Containing Conductive Spheres
A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A shielding material, containing a plurality of spheres embedded in a matrix, is formed on the encapsulant. The shielding material 144 can be formed by spray coating, printing, liquid flow, or droplets. The spheres can have a curved or angled shape, e.g., circular, oval, or many flat or curved surfaces joining as a globe. The spheres each have a shell formed over a core. The shell can be a conductive material, while the core is an insulating material. Alternatively, the shell can be an insulating material, while the core is a conductive material. The shielding material scatters electromagnetic interference noise waves by reflection off the shell of the spheres. The shielding material can absorb electromagnetic interference noise waves into the core of the spheres.
A semiconductor device has a substrate and a first electrical interconnect structure formed over a first surface of the substrate. A second electrical interconnect structure is formed over a second surface of the substrate. An electrical component is disposed over the first surface of the substrate or over the second surface of the substrate. A first antenna is formed over the first electrical interconnect structure. A second antenna is formed over the second electrical interconnect structure. The first electrical interconnect structure has an insulating material formed over the first surface of the substrate, and a conductive via formed through the insulating material. Alternatively, the first electrical interconnect structure has an insulating layer formed over the first surface of the substrate, a conductive layer formed over the insulating layer, and a conductive via formed through the insulating layer and conductive layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles
38.
Semiconductor Device and Method of Making a Fan-Out Semiconductor Package with Pre-Assembled Passive Modules
A semiconductor device includes a plurality of electrical components. A first encapsulant is deposited over the plurality of electrical components to form a module. The module is disposed adjacent to a semiconductor die. A second encapsulant is deposited over the semiconductor die and module. A build-up interconnect structure is formed over the second encapsulant, module, and semiconductor die.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
39.
Semiconductor Device and Method of Making a Dual-Side Molded System-in-Package with Fine-Pitched Interconnects
A semiconductor device has a substrate. An electrical component is disposed over a first surface of the substrate. A solder paste is disposed over the first surface of the substrate. A conductive pillar is disposed on the solder paste. An encapsulant is deposited over the first surface of the substrate, the electrical component, and the conductive pillar. A solder bump is formed over the conductive pillar.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/552 - Protection against radiation, e.g. light
40.
SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME
A semiconductor package and a method for making the same are provided. The semiconductor package may include: a substrate having a first surface and a second surface opposite to the first surface; a first insulating layer disposed on the first surface of the substrate and having a first concave portion; a first semiconductor interposer disposed in the first concave portion of the first insulating layer, the first semiconductor interposer including a first semiconductor layer and a plurality of first wiring patterns formed on the first semiconductor layer; a first electronic component overlapping with a first portion of the first semiconductor interposer and electrically connected with the first wiring patterns of the first semiconductor interposer; and a second electronic component overlapping with a second portion of the first semiconductor interposer and electrically connected with the first wiring patterns of the first semiconductor interposer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
41.
SEMICONDUCTOR PACKAGE AND METHOD FOR FORMING THE SAME
A semiconductor package is provided. The semiconductor package includes: a substrate having a substrate surface, wherein the substrate includes conductive patterns on the substrate surface; a first semiconductor die attached onto the substrate surface; a heat spreader mounted over and thermally coupled to the first semiconductor die, wherein the heat spreader includes an overhanging portion that extends laterally beyond the first semiconductor die; at least one second semiconductor die attached onto the spreader bottom surface of the overhanging portion and beneath the overhanging portion of the heat spreader, wherein the at least one second semiconductor die is thermally coupled to the overhanging portion of the heat spreader, and is electrically coupled to at least one of the conductive patterns of the substrate; and an encapsulant layer for encapsulating the first semiconductor die, the at least one second semiconductor die, the heat spreader and the conductive patterns on the substrate surface.
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
An electronic package and a packaging method are provided. The packaging method comprises: forming on a carrier film a first photoresist pattern having multiple sets of first openings; filling in the multiple sets of first openings of the first photoresist pattern with a solder material to form multiple sets of solder bumps; forming on the first photoresist pattern a second photoresist pattern having multiple second openings each exposing a set of the sets of solder bumps; attaching one or more electronic components to the set of solder bumps in each of the second openings; filling in the second openings of the second photoresist pattern with an encapsulant material to form an encapsulant layer that at least partially encapsulates the one or more electronic components in each of the second openings; and removing the second photoresist pattern from the carrier film to form multiple electronic packages.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
43.
Semiconductor Device and Method of Controlling Distribution of Liquid Metal TIM Using Lid Structure
A semiconductor device has an electrical component and a heat sink disposed over the electrical component. The heat sink has a cover with a wall extending from the cover forming a pocket around a perimeter of the electrical component. The heat sink also has a horizontal step, and a riser extending from the horizontal step to the cover. The wall extends from the cover to form the pocket. A TIM is disposed between the cover and a surface of the electrical component. The TIM can be liquid metal. The heat sink is pressed onto the TIM under force and heat to distribute the TIM between the cover and surface of the electrical component. The TIM remains contained within the pocket by the wall. The wall or cover can have a vent hole. The TIM may extend over a side surface of the electrical component.
A method for forming a sensor package, comprising: providing a substrate, wherein one or more connectors are attached onto a front side of the substrate; forming an encapsulant layer on the front side of the substrate, wherein the one or more connectors are exposed from the encapsulant layer; forming a sacrificial layer on the encapsulant layer, wherein a periphery of the sacrificial layer is smaller than a periphery of the encapsulant layer, and wherein the sacrificial layer is molded as including a base portion, a step portion with a periphery smaller than a periphery of the base portion, and at least one extrusion portion on the base portion; applying an encapsulant material surrounding the base portion of the sacrificial layer, to enlarge the encapsulant layer; removing the sacrificial layer from the encapsulant layer, to form a cavity corresponding to the step portion and the base portion of the sacrificial layer, and to form at least one hole corresponding to the at least one extrusion portion on the enlarged encapsulant layer; positioning a sensor within the cavity and connecting the sensor to the one or more connectors; and attaching a cap onto the enlarged encapsulant layer to cover the cavity.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
45.
SEMICONDUCTOR DEVICE AND A METHOD FOR FORMING A SEMICONDUCTOR DEVICE
A semiconductor device comprises: a substrate having a set of conductive patterns; a semiconductor die mounted on the substrate, wherein the semiconductor die has on its top surface a set of bonding pads; and a conductive bar assembly for electrically connecting the set of conductive patterns of the substrate with the set of bonding pads of the semiconductor die, wherein the conductive bar assembly comprises: an insulating body; and a set of conductive bars extending within the insulating body, wherein the set of conductive bars have a set of first ends exposed from a first surface of the insulating body to be electrically connected to the set of conductive patterns of the substrate and a set of second ends exposed from a second surface of the insulating body to be electrically connected to the set of bonding pads of the semiconductor die.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
46.
Semiconductor Device and Methods of Making and Using an Enhanced Carrier to Reduce Electrostatic Discharge
A semiconductor device is made with a boat carrier including stainless steel. A Polytetrafluoroethylene (PTFE) layer is formed over the boat carrier. A semiconductor package substrate is disposed over the boat carrier. A manufacturing step is performed on the semiconductor package substrate. An electrostatic discharge (ESD) is imparted on the boat carrier during the manufacturing step. The semiconductor package substrate is protected from the ESD by the PTFE layer.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
B32B 15/18 - Layered products essentially comprising metal comprising iron or steel
B32B 38/00 - Ancillary operations in connection with laminating processes
C09D 127/18 - Homopolymers or copolymers of tetrafluoroethene
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
47.
Semiconductor Device and Method of Forming Stress Relief Vias in Multi-Layer RDL
A semiconductor device has a substrate and a first RDL formed over the substrate. A second RDL is formed over the first RDL with a first conductive via electrically connecting the first RDL and second RDL and a first opening formed in the second RDL around the first conductive via for stress relief. The first opening formed in the second RDL can have a semi-circle shape or a plurality of semi-circles or segments. A third RDL is formed over the second RDL with a second conductive via electrically connecting the second RDL and third RDL and a second opening formed in the third RDL around the second conductive via for stress relief. The first opening is offset from the second opening. A plurality of first openings can be formed around the first conductive via for stress relief, each offset from one another.
A selective stencil mask and a stencil printing method are provided. The stencil mask is for printing a fluid material onto a substrate, and comprises: a stencil member comprising: at least one printing region each having an array of apertures that allow the fluid material to flow therethrough and deposit onto the substrate; and a blocking region configured to prevent the fluid material from flowing therethrough; and a supporting member attached to the stencil member and configured to, when the stencil mask is placed on the substrate, contact the substrate and create a gap between the stencil member and the substrate.
B41M 1/26 - Printing on other surfaces than ordinary paper
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
H01L 23/00 - Details of semiconductor or other solid state devices
49.
METHOD FOR FORMING A SHIELDING LAYER OVER A SEMICONDUCTOR PACKAGE WITH REDUCED METAL BURRS
A method for forming a shielding layer over a semiconductor package is provided. The method comprises: providing a jig having a metal frame and a carrier tape attached onto the metal frame via an adhesive layer; forming an opening through the adhesive layer and the carrier tape; disposing a semiconductor package on the jig over the opening such that the semiconductor package is supported on and attached to the carrier tape via the adhesive layer; forming a groove in the adhesive layer and around the opening by isotropic etching; forming a shielding layer over the semiconductor package and the jig; and removing the semiconductor package with the shielding layer from the jig.
A device for holding a package substrate is provided. The device comprises: a lower jig comprising a base material, and magnets embedded within the base material; and an upper jig comprising a frame and a grid pattern inside the frame, wherein the frame has a skirt portion that defines a gap between the lower jig and the grid pattern to accommodate the package substrate, and wherein the grid pattern is attractable by the magnets such that when the upper jig is placed on the lower jig to accommodate the package substrate the grid pattern is in contact with the package substrate to apply a pressure to the package substrate due to a magnetic interaction between the magnets and the grid pattern.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
51.
PARTIALLY SHIELDED SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME
A partially shielded semiconductor device and a method for making the same are provided. The method may include: providing a package including: a substrate; an electronic component mounted on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component; and a coating layer formed on the substrate and adjacent to the encapsulant; performing a laser hatching process on the encapsulant and a portion of the coating layer adjacent to the encapsulant to remove the portion of the coating layer to form a trench between the encapsulant and the coating layer; and electroless-plating a conductive material to cover the encapsulant and fill the trench between the encapsulant and the coating layer.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
52.
Semiconductor Device and Method of Forming High Crystal Quality Magnetic Layer for Shielding of Low Frequency Magnetic Fields
A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A magnetic film material is formed over the encapsulant. The magnetic film material may extend down a side surface of the semiconductor device. The magnetic film material is subject to laser spike annealing in a magnetic field. A shielding layer is formed over the magnetic film material. The laser spike annealing of the magnetic film material in the magnetic field can be done after forming the shielding layer. The shielding layer may extend down a side surface of the semiconductor device. A first magnet is disposed on a first side of the semiconductor device. A second magnet is disposed on a second side of the semiconductor device opposite the first side of the semiconductor device.
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A semiconductor device has a substrate and a first electrical component disposed over the substrate. A first encapsulant is deposited over the first electrical component and substrate. An interconnect structure including a graphene core shell is formed over or through the first encapsulant. The graphene core shell has a copper core or silver core. The interconnect structure has a plurality of cores covered by graphene and the graphene is interconnected within the interconnect structure to form an electrical path. The interconnect structure has thermoset material or polymer or composite epoxy type matrix and the graphene core shell is embedded within the thermoset material or polymer or composite epoxy type matrix. A second electrical component is disposed over the first encapsulant. A second encapsulant is deposited over the second electrical component. A shielding layer is formed over the second encapsulant. The shielding layer can have a graphene core shell.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
54.
METHOD FOR FORMING A SHIELDING LAYER ON A SEMICONDUCTOR DEVICE
A method for forming a shielding layer to a semiconductor device, wherein the semiconductor device comprises a substrate, one or more electronic components on a front surface of the substrate, an encapsulant layer on the front surface of the substrate that covers the one or more electronic components and one or more connectors on a back surface of the substrate, the method comprising: applying a coating layer onto the back surface of the substrate to cover the one or more connectors; attaching the coating layer onto a tape to load the semiconductor device to the tape, wherein the attachment between the coating layer and the tape is stronger than the attachment between the coating layer and the back surface of the substrate as well as the one or more connectors; forming the shielding layer onto the encapsulant layer to cover the one or more electronic components; and unloading the semiconductor device from the tape, wherein the coating layer is left on the tape.
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
An integrated package and a method for making the same are provided. The integrated package may include: a substate; a first electronic component mounted on the substrate; a first dielectric layer formed on the substrate and covering the first electric component, wherein the dielectric layer is made of photo imageable dielectric material; a first redistribution layer formed in the first dielectric layer, wherein the first redistribution layer includes a first vertical portion running through the first dielectric layer and a first lateral portion formed on a top surface of the first dielectric layer; a second electronic component mounted above the first dielectric layer and coupled with the lateral portion of the first redistribution layer; and a second dielectric layer formed above the first dielectric layer and covering the second electronic component.
H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers using masks
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
56.
System and Method of Providing FOUP or Cassette Supporting Structure for Handling Various Size or Shape Wafers and Panels
A front opening unified pod has a housing and a plurality of horizontal support members disposed within the housing and adapted to accommodate a plurality of semiconductor wafers or panels. The plurality of semiconductor wafers or panels have a different size or shape, such as circular and rectangular. A first one of the plurality of horizontal support members has a wing to support the plurality of different size or shape semiconductor wafers or panels. The plurality of horizontal support members has a first side horizontal support member, a second side horizontal support member, and a center horizontal support member disposed between the first side horizontal support member and the second side horizontal support member. The plurality of horizontal support members is insertable into the housing. One or more of the plurality of horizontal support members has an opening for laser identification.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
57.
Semiconductor Device and Method of Partial Shielding with Embedded Graphene Core Shells
A semiconductor device has a substrate and an electrical component disposed over the substrate. A first encapsulant is deposited over the electrical component and substrate. A first shielding layer with a graphene core shell is formed on a surface of the first encapsulant. A second encapsulant is deposited over the first encapsulant and first shielding layer. A second shielding layer is formed over the second encapsulant. The first shielding layer is formed at least partially in an opening of the first encapsulant. The graphene core shell has a copper core. The first shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the first shielding layer to form an electrical path. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.
A semiconductor device has a substrate and an electrical component disposed over a first surface of the substrate. A first encapsulant is deposited over the first surface of the substrate. A second encapsulant is deposited over a second surface of the substrate with a via formed in the second encapsulant. A conductive material containing a graphene core shell is deposited in the via in the second encapsulant to form a conductive post. The graphene core shell can have a copper core with a graphene coating formed over the copper core. The conductive material has a matrix to embed the graphene core shell. The conductive material can have a plurality of cores covered by graphene and the graphene is interconnected within the conductive material to form an electrical path. The conductive material can have thermoset material or polymer or composite epoxy type matrix to embed the graphene core shell.
A semiconductor package comprises: a package substrate comprising: a first portion comprising a first conductive pattern extending therewithin having a first thickness; and a second portion comprising a second conductive pattern extending therewithin having a second thickness smaller than the first thickness; at least one electronic component mounted on the second portion and electrically coupled to the second conductive pattern; an encapsulant layer formed on the second portion of the package substrate and covering the at least one electronic component, wherein the encapsulant layer comprises a cavity region; a connector assembly formed within the cavity region of the encapsulant layer and electrically coupled to the second conductive pattern, wherein the connector assembly is exposed from the encapsulant layer to allow for electrical connection with an external device; and a partial shielding layer formed on at least regions other than the cavity region of the encapsulant layer.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
60.
Semiconductor Device and Method of Coating a Semiconductor Wafer with High Viscosity Liquid Photoresist Using N2 Purge
A semiconductor manufacturing device has an outer cup and inner cup with a wafer suction mount disposed within the outer cup. A photoresist material is applied to a first surface of a semiconductor wafer disposed on the wafer suction mount while rotating at a first speed. A gas port is disposed on the inner cup for dispensing a gas oriented toward a bottom side of the semiconductor wafer. The gas port purges a second surface of the semiconductor wafer with a gas to remove contamination. The second surface of the semiconductor wafer is rinsed while purging with the gas. The gas can be a stable or inert gas, such as nitrogen. The contamination is removed from the second surface of the semiconductor wafer through an outlet between the inner cup and outer cup. The semiconductor wafer rotates at a second greater speed after discontinuing purge with the gas.
B05C 11/06 - Apparatus for spreading or distributing liquids or other fluent materials already applied to a surfaceControl of the thickness of a coating with a blast of gas or vapour
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
61.
Semiconductor device with compartment shield formed from metal bars and manufacturing method thereof
A semiconductor device has a substrate and first and second electrical component disposed over the substrate. A first metal bar is disposed over the substrate between the first electrical component and second electrical component. The first metal bar is formed by disposing a mask over a carrier. An opening is formed in the mask and a metal layer is sputtered over the mask. The mask is removed to leave the metal layer within the opening as the first metal bar. The first metal bar can be stored in a tape-and-reel.
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/50 - Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups or
H01L 21/52 - Mounting semiconductor bodies in containers
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
62.
SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME
A method for making a semiconductor device is provided. The method includes: providing a semiconductor assembly comprising a first semiconductor die and a second semiconductor die, wherein a first interconnection structure is electrically coupled to the first semiconductor die and a second interconnection structure is electrically coupled to the second semiconductor die; depositing an encapsulant layer over the semiconductor assembly to encapsulate the first interconnection structure and the second interconnection structure, wherein the encapsulant layer comprises an additive activatable by laser; forming an interconnection channel in the encapsulant layer and activating the additive of the encapsulant layer in the interconnection channel as a seed layer by laser patterning, wherein the interconnection channel exposes and interconnects the first and the second interconnection structures; forming a conductive layer in the interconnection channel of the encapsulant layer; and forming an outer layer on the encapsulant layer to cover the conductive layer.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
63.
METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING A DOUBLE SIDE MOLDING TECHNOLOGY
A method for making a semiconductor device using a double side molding technology is provided. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface, wherein the second surface of the substrate is uneven; forming a coating on the second surface of the substrate such that a first surface of the coating, which is facing away from the second surface of the substrate, is even; mounting a first electronic component on the first surface of the substrate; and forming a first encapsulant on the first surface of the substrate to cover the first electronic component.
A semiconductor device has a one-layer interconnect substrate and electrical component disposed over a first surface of the interconnect substrate. The electrical components can be discrete electrical devices, IPDs, semiconductor die, semiconductor packages, surface mount devices, and RF components. An RDL with a graphene core shell is formed over a second surface of the interconnect substrate. The graphene core shell has a copper core and a graphene coating formed over the copper core. The RDL further has a matrix to embed the graphene core shell. The graphene core shells through RDL form an electrical path. The RDL can be thermoset material or polymer or composite epoxy type matrix. The graphene core shell is embedded within the thermoset material or polymer or composite epoxy type matrix. The RDL with graphene core shell is useful for electrical conductivity and electrical interconnect within an SIP.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
65.
Semiconductor Device and Method of Making a Semiconductor Package with Graphene-Coated Interconnects
A semiconductor device includes a first substrate and a second substrate. A graphene-coated interconnect is disposed between the first substrate and second substrate. A semiconductor die is disposed between the first substrate and second substrate. The first substrate is electrically coupled to the second substrate through the graphene-coated interconnect. An encapsulant is deposited between the first substrate and second substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
66.
SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME
A semiconductor device and a method for making the same are provided. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface, wherein a plurality of conductive pillars are formed on the second surface of the substrate; forming a polyimide layer on the second surface of the substrate to cover the plurality of conductive pillars; mounting a first electronic component on the first surface of the substrate; and forming a first encapsulant on the first surface of the substrate to cover the first electronic component.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
67.
Semiconductor Device and Method of Forming Vertical Interconnect Structure for POP Module
A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
68.
Semiconductor Device and Method of Making a Semiconductor Package with Graphene for Die Attach
A semiconductor device has a substrate with a die pad. A conductive material is disposed on the die pad. The conductive material includes a plurality of graphene-coated metal balls in a matrix. A semiconductor die is disposed on the conductive material. The conductive material is sintered using an infrared laser. A bond wire is formed between the semiconductor die and substrate. An encapsulant is deposited over the semiconductor die and bond wire.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 33/62 - Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
A semiconductor device has a substrate and an adhesive layer with a graphene core shell deposited over a surface of the substrate. An electrical component is affixed to the substrate with the adhesive layer. A bond wire is connected between the electrical component and substrate. The graphene core shell has a copper core and graphene coating over the copper core. The graphene coated core shell is embedded within a matrix. The graphene core shells within the adhesive layer to form a thermal path. The matrix can be a thermoset material or polymer or composite epoxy type matrix. The graphene core shell is embedded within the thermoset material or polymer or composite epoxy type matrix. The adhesive layer with graphene core shell is useful for die attachment. The graphene core adhesive layer provides exceptional heat dissipation, shock absorption, and vibration dampening.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
70.
Cooling Device and Process for Cooling Double-Sided SiP Devices During Sputtering
A semiconductor manufacturing device has a cooling pad with a plurality of movable pins. The cooling pad includes a fluid pathway and a plurality of springs disposed in the fluid pathway. Each of the plurality of springs is disposed under a respective movable pin. A substrate includes an electrical component disposed over a surface of the substrate. The substrate is disposed over the cooling pad with the electrical component oriented toward the cooling pad. A force is applied to the substrate to compress the springs. At least one of the movable pins contacts the substrate. A cooling fluid is disposed through the fluid pathway.
A semiconductor device has a substrate. A first component and second component are disposed over the substrate. The first component includes an antenna. A lid is disposed over the substrate between the first component and second component. An encapsulant is deposited over the substrate and lid. A conductive layer is formed over the encapsulant and in contact with the lid. A first portion of the conductive layer over the first component is removed using laser ablation.
A method of making a semiconductor device involves the steps of disposing a first semiconductor die over a substrate and disposing a beam homogenizer over the first semiconductor die. A beam from the beam homogenizer impacts the first semiconductor die. The method further includes the steps of determining a positional offset of the beam relative to the first semiconductor die in a number of pixels, using a first calibration equation to convert the number of pixels into a distance in millimeters, and moving the beam homogenizer the distance in millimeters to align the beam and first semiconductor die.
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
73.
Semiconductor Device and Method of Forming Electrical Circuit Pattern Within Encapsulant of SIP Module
A semiconductor device has an electronic component assembly with a substrate and a plurality of electrical components disposed over the substrate. A conductive post is formed over the substrate. A molding compound sheet is disposed over the electrical component assembly. A carrier including a first electrical circuit pattern is disposed over the molding compound sheet. The carrier is pressed against the molding compound sheet to dispose a first encapsulant over and around the electrical component assembly and embed the first electrical circuit pattern in the first encapsulant. A shielding layer can be formed over the electrical components assembly. The carrier is removed to expose the first electrical circuit pattern. A second encapsulant is deposited over the first encapsulant and the first electrical circuit pattern. A second electrical circuit pattern is formed over the second encapsulant. A semiconductor package is disposed over the first electrical circuit pattern.
A semiconductor device has a substrate and a first component disposed over a first surface of the substrate. A connector is disposed over the first surface of the substrate. A first encapsulant is deposited over the first component while the connector remains outside of the first encapsulant. A shielding layer is formed over the first encapsulant while the connector remains outside of the shielding layer. A second component is disposed over a second surface of the substrate. A solder bump is disposed over the second surface of the substrate. A second encapsulant is deposited over the second surface of the substrate. An opening is formed through the second encapsulant to expose the solder bump. A solder ball is disposed in the opening. The solder ball and solder bump are reflowed to form a combined solder bump.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
75.
Semiconductor Device and Method of Forming Graphene Core Shell Embedded Within Shielding Layer
A semiconductor device has a substrate and an electrical component disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A shielding layer has a graphene core shell formed on a surface of the encapsulant. The shielding layer can be printed on the encapsulant. The graphene core shell includes a copper core. The shielding layer has a plurality of cores covered by graphene and the graphene is interconnected within the shielding layer to form an electrical path. The shielding layer also has thermoset material or polymer or composite epoxy type matrix and the graphene core shell is embedded within the matrix. A shielding material can be disposed around the electrical component. The electrical path dissipates any charge incident on shielding layer, such as an ESD event, to reduce or inhibit the effects of EMI, RFI, and other inter-device interference.
A semiconductor device has a substrate and an electrical component disposed over a surface of the substrate. An antenna interposer is disposed over the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made from an antenna substrate having a plurality of antenna interposers. Bumps are formed over the antenna substrate and the antenna substrate is singulated to make the plurality of antenna interposers. A second encapsulant is deposited over the electrical component. The second encapsulant has a low dielectric constant less than the high dielectric constant of the first encapsulant. A shielding layer is disposed over the second encapsulant.
A semiconductor device and a method for making the same are provided. The method includes: providing a package including: a substrate including a top substrate surface and a bottom substrate surface; an electronic component mounted on the top substrate surface; and a first encapsulant disposed on the top substrate surface and encapsulating the electronic component; forming a fiducial mark in the first encapsulant; and forming a first shielding layer on the first encapsulant using an aerosol jetting apparatus, wherein the first shielding layer is at a predetermined distance from the fiducial mark and above the electronic component.
A semiconductor device comprises a substrate; a primary semiconductor die attached onto the substrate comprising a front surface and a back surface, wherein the primary semiconductor die has a first region and a second region besides the first region; an auxiliary semiconductor die attached onto the front surface at the first region; a heat transfer block comprising a main body attached onto the front surface at the second region; a metal layer wrapping around the main body; a graphene layer formed outside of the metal layer; a heat spreader attached onto the substrate and defining with the substrate a chamber for accommodating the primary semiconductor die, the auxiliary semiconductor die and the heat transfer block, wherein the graphene layer extends between the heat spreader and the front surface such that heat generated by the first region can be transferred to the heat spreader through the graphene layer.
H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
79.
Laser-Based Redistribution and Multi-Stacked Packages
A semiconductor device has a first package layer. A first shielding layer is formed over the first package layer. The first shielding layer is patterned to form a redistribution layer. An electrical component is disposed over the redistribution layer. An encapsulant is deposited over the electrical component. A second shielding layer is formed over the encapsulant. The second shielding layer is patterned. The patterning of the first shielding layer and second shielding layer can be done with a laser. The second shielding layer can be patterned to form an antenna.
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A semiconductor device has a first RDL substrate with first conductive pillars formed over a first surface of the first RDL substrate. A first electrical component is disposed over the first surface of the first RDL substrate. A hybrid substrate is bonded to the first RDL substrate. An encapsulant is deposited around the hybrid substrate and first RDL substrate with the first conductive pillars and first electrical component embedded within the encapsulant. A second RDL substrate with second conductive pillars formed over the second RDL substrate and second electrical component disposed over the second RDL substrate can be bonded to the hybrid substrate. A second RDL can be formed over a second surface of the first RDL substrate. A third electrical component is disposed over a second surface of the first RDL substrate. A shielding frame is disposed over the third electrical component.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
81.
Semiconductor Device and Methods of Making and Using Thermally Advanced Semiconductor Packages
A semiconductor device includes a substrate. A semiconductor die is disposed over the substrate. An encapsulant is deposited over the substrate and semiconductor die. A first trench is formed in the encapsulant over the semiconductor die. A conductive layer is formed over the encapsulant and into the first trench.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
82.
SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME
A semiconductor device and a method for forming the same are provided. The method includes: providing a package including: a substrate including a first substrate surface and a second substrate surface opposite to the first substrate surface; a first conductive bump formed on the first substrate surface; and a first encapsulant disposed on the first substrate surface and encapsulating the first conductive bump; forming a groove in the first encapsulant to expose at least a portion of the first conductive bump; and forming a second conductive bump on the exposed portion of the first conductive bump using a laser soldering apparatus.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
An integrated package and a method for making the same are provided. The integrated package includes: a first substrate including: a first interconnection area having a plurality of first interconnection structures; and a first alignment structure disposed outside the first interconnection area; a second substrate stacked above the first substrate and including: a second interconnection area having a plurality of second interconnection structures; and a second alignment structure disposed outside the second interconnection area, wherein the second alignment structure is substantially aligned with the first alignment structure in a stacking direction of the first substrate and the second substrate; and a connecting element disposed between the first substrate and the second substrate and configured for electrically connecting at least one of the plurality of first interconnection structures with at least one of the plurality of second interconnection structures.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
84.
SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME
A method for singulating a semiconductor substrate into individual semiconductor devices, comprising: providing a semiconductor substrate having a front surface and a back surface, wherein the semiconductor substrate comprises device regions that are separated from each other by respective predetermined saw streets; forming an interconnect layer on the front surface; etching the front surface at the predetermined saw streets to form respective frontside openings each having a first depth, wherein the first depth is smaller than a thickness of the semiconductor substrate; attaching a semiconductor element onto the front surface in each device region; and etching the back surface at the respective predetermined saw streets to form respective backside openings each having a second depth, wherein each frontside opening is at least partially aligned with the backside opening at the same saw street to singulate the device regions of the semiconductor substrate into individual semiconductor devices.
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/528 - Layout of the interconnection structure
85.
Semiconductor Device and Method of Forming Graphene-Coated Core Embedded Within TIM
A semiconductor device has a substrate and electrical component disposed over the substrate. The electrical component can be a semiconductor die, semiconductor package, surface mount device, RF component, discrete electrical device, or IPD. A TIM is deposited over the electrical component. The TIM has a core, such as Cu, covered by graphene. A heat sink is disposed over the TIM, electrical component, and substrate. The TIM is printed on the electrical component. The graphene is interconnected within the TIM to form a thermal path from a first surface of the TIM to a second surface of the TIM opposite the first surface of the TIM. The TIM has thermoset material or soldering type matrix and the core covered by graphene is embedded within the thermoset material or soldering type matrix. A metal layer can be formed between the TIM and electrical component.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
86.
Semiconductor Device and Method of Stacking Hybrid Substrates
A semiconductor device has an RDL substrate and hybrid substrate with a plurality of bumps. The hybrid substrate is bonded to the RDL substrate. An encapsulant is deposited around the hybrid substrate and RDL substrate with the bumps embedded within the encapsulant. The hybrid substrate has a core substrate, first RDL formed over a first surface of the core substrate, conductive pillars formed over the first RDL, and second RDL over a second surface of the core substrate. A portion of the encapsulant is removed to expose the conductive pillars. The RDL substrate has a carrier and RDL formed over a surface of the carrier. The carrier is removed after bonding the hybrid substrate to the RDL substrate. Alternatively, the RDL substrate has a core substrate, first RDL formed over a first surface of the core substrate, and second RDL formed over a second surface of the core substrate.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
Provided is a sensor assembly, comprising: a sensor, wherein the sensor comprises a sensor front surface comprising a sensor area and an interconnect area; at least one filter layer formed on top of the sensor front surface, wherein the at least one filter layer covers and is in direct contact with the sensor area of the sensor; a first encapsulant layer formed on top of the at least one filter layer, wherein the first encapsulant layer is transmissive to light; and wherein the interconnect area is at least partially exposed from the at least one filter layer and the first encapsulant layer.
A semiconductor device has a first substrate and a first electrical component disposed over the first substrate. A first support frame is disposed over the first substrate. The first support frame has a horizontal support channel extending across the first substrate and a vertical support brace extending from the horizontal support channel to the first substrate. The first support frame can have a vertical shielding partition extending from the horizontal support channel to the first substrate. An encapsulant is deposited over the first electrical component and first substrate and around the first support frame. A second electrical component is disposed over the first electrical component. A second substrate is disposed over the first support frame. A second electrical component is disposed over the second substrate. A third substrate is disposed over the second substrate. A second support frame is disposed over the second substrate.
H01L 23/552 - Protection against radiation, e.g. light
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
An integrated package and a method for making the same are provided. The integrated package includes: a molded substrate having a top substrate surface and a bottom substrate surface; a semiconductor chip embedded in the molded substrate; a bottom antenna structure disposed on the bottom substrate surface and electrically connected to the semiconductor chip; and an antenna package embedded in the molded substrate, and including: an antenna package substrate; and a top antenna structure disposed on the antenna package substrate and configured for coupling electromagnetic energy with the bottom antenna structure.
A semiconductor device has a first hybrid substrate with a first thickness, and a second hybrid substrate with a second thickness different from the first thickness of the first hybrid substrate. An encapsulant is deposited around the first hybrid substrate and second hybrid substrate. A portion of the first hybrid substrate and a portion of the second hybrid substrate and a portion of the encapsulant can be removed after encapsulation to achieve uniform thickness for the first hybrid substate and second hybrid substrate. The first hybrid substrate has an embedded substrate, a first interconnect structure formed over a first surface of the embedded substrate, and a second interconnect structure formed over a second surface of the embedded substrate opposite the first surface of the embedded substrate. A plurality of conductive pillars is formed over the first interconnect structure. A plurality of conductive vias is formed through the embedded substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
91.
Semiconductor Device and Method of Forming Package with Double-Sided Integrated Passive Device
A semiconductor device has a semiconductor die, substrate, and plurality of first conductive pillars formed over the semiconductor die or substrate. Alternatively, the first conductive pillars formed over the semiconductor die and substrate. An electrical component is disposed over the semiconductor die. The electrical component can be a double-sided IPD. The semiconductor die and electrical component are disposed over the substrate. A shielding frame is disposed over the semiconductor die. A plurality of second conductive pillars is formed over a first surface of the electrical component. A plurality of third conductive pillars is formed over a second surface of the electrical component opposite the first surface of the electrical component. A bump cap can be formed over a distal end of the conductive pillars. The substrate has a cavity and the electrical component is disposed within the cavity. An underfill material is deposited between the semiconductor die and substrate.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/552 - Protection against radiation, e.g. light
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A semiconductor device has a first semiconductor package, second semiconductor package, and RDL. The first semiconductor package is disposed over a first surface of the RDL and the second semiconductor package is disposed over a second surface of the RDL opposite the first surface of the RDL. A carrier is initially disposed over the second surface of the RDL and removed after disposing the first semiconductor package over the first surface of the RDL. The first semiconductor package has a substrate, plurality of conductive pillars formed over the substrate, electrical component disposed over the substrate, and encapsulant deposited around the conductive pillars and electrical component. A shielding frame can be disposed around the electrical component. An antenna can be disposed over the first semiconductor package. A portion of the encapsulant is removed to planarize a surface of the encapsulant and expose the conductive pillars.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/552 - Protection against radiation, e.g. light
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
93.
Semiconductor Device and Method for Partial EMI Shielding
A semiconductor device includes a substrate. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component. A vertical interconnect structure is disposed in the encapsulant. A shielding layer is formed over the encapsulant and vertical interconnect structure. A groove is formed in the shielding layer around the vertical interconnect structure. A portion of the shielding layer remains over the vertical interconnect structure as a contact pad.
H01L 23/552 - Protection against radiation, e.g. light
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
94.
SEMICONDUCTOR DEVICES WITH PYRAMIDAL SHIELDING AND METHOD FOR MAKING THE SAME
A semiconductor device and a method for making the same are provided. The semiconductor device includes: a substrate; an electronic component mounted on the substrate; a first encapsulant disposed on the substrate and encapsulating the electronic component; and a first electromagnetic interference (EMI) shielding layer disposed on the first encapsulant, wherein the first EMI shielding layer includes a first plurality of shield protrusions each having one or more inclined sidewalls.
A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.
A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. The semiconductor wafer has a low resistivity. An insulating layer is formed over the semiconductor wafer. A first IPD is formed over the insulating layer. The first IPD can be a capacitor, resistor, or inductor. A second IPD is formed over a second surface of the semiconductor wafer opposite the first surface of the semiconductor wafer. An interconnect structure is formed over the first IPD. An interconnect substrate is provided with the semiconductor die disposed over the interconnect substrate. A bond wire is formed between the interconnect structure and the interconnect substrate. Alternatively, an active device is formed in a second surface of the semiconductor die opposite the first surface of the semiconductor die. The semiconductor die incorporates the hybrid substrate to allow IPD and active devices to be formed from a single substrate.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
97.
Power Envelope Analysis for the Thermal Optimization of Multi-Chip Modules
A semiconductor device is made by calculating a thermal resistance matrix for the semiconductor device. A plurality of maximum junction temperatures for the plurality of die of the semiconductor device is selected. A plurality of power envelope surfaces are calculated for the semiconductor device based on the thermal resistance matrix and the maximum junction temperatures. A plurality of powers is selected for the plurality of die. The plurality of powers are compared against the plurality of power envelope surfaces to determine a plurality of risk values.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Provided is a heat spreader assembly comprising: a pair of locking bars mounted on a substrate of a semiconductor device and at two opposite sides of at least one semiconductor die, wherein each of the pair of locking bars comprises a plurality of locking hooks disposed along the locking bar and defines a slot; and a heat spreader comprising: a heat spreader body comprising a top portion and a pair of lateral portions, the heat spreader body defining a space for receiving the at least one semiconductor die; and a pair of protrusion ribs extending in opposite directions from the pair of lateral portions, respectively, wherein the pair of protrusion ribs is configured to slide past the locking hooks of the pair of locking bars and be engaged within the slots to prevent the heat spreader from moving away from the substrate of the semiconductor device.
An electronic package comprises: a substrate; five-sided insulated electronic components, wherein each of the five-sided insulated electronic components comprises: a raw electronic component having a cuboid shape, wherein the raw electronic component has a bottom side at which the raw electronic component is mounted onto and connected with the substrate and five non-bottom sides; a conductive structure disposed on the bottom side of the raw electronic component; and an insulating layer disposed on the five non-bottom sides of the raw electronic component.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H05K 9/00 - Screening of apparatus or components against electric or magnetic fields
H01F 41/00 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatingsNon-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
H01C 17/00 - Apparatus or processes specially adapted for manufacturing resistors
100.
Semiconductor Device and Method of Forming Thin Heat Sink Using E-Bar Substrate
A semiconductor device has a substrate and a semiconductor package disposed over the substrate. An embedded bar (e-bar) substrate is disposed on the substrate around the semiconductor package. A heat sink is formed over the semiconductor package and supported by the e-bar substrate to elevate the heat sink from the substrate and reduce a thickness of the heat sink. A thermal interface material is deposited between the semiconductor package and heat sink. Alternatively, a shield layer can be formed over the semiconductor package and supported by the e-bar substrate. The e-bar substrate has a base layer and a first metal layer formed over a first surface of the base layer. A bump is formed over the first metal layer. A second metal layer can be over a second surface of the base layer opposite the first surface of the base layer. Two or more e-bar substrates can be stacked.
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
patents