Sony Semiconductor Solutions Corporation

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2026 April (MTD) 57
2026 March 67
2026 February 79
2026 January 104
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IPC Class
H01L 27/146 - Imager structures 3,380
H04N 5/369 - SSIS architecture; Circuitry associated therewith 1,105
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components 632
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters 569
H04N 5/374 - Addressed sensors, e.g. MOS or CMOS sensors 563
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09 - Scientific and electric apparatus and instruments 2
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1.

PHOTOELECTRIC CONVERSION ELEMENT AND PHOTODETECTOR

      
Application Number 19114682
Status Pending
Filing Date 2023-08-16
First Publication Date 2026-04-16
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Takaguchi, Ryotaro
  • Joei, Masahiro
  • Hirata, Shintarou
  • Yagi, Iwao
  • Suzuki, Ryosuke

Abstract

A first photoelectric conversion element according to an embodiment of the present disclosure includes: an electrode layer including a first electrode and a second electrode disposed side by side with each other; a third electrode disposed to be opposed to the first electrode and the second electrode; a photoelectric conversion layer provided between the electrode layer and the third electrode; an oxide semiconductor layer provided between the electrode layer and the photoelectric conversion layer; and a first insulating layer provided between the electrode layer and the oxide semiconductor layer. The first insulating layer has an opening in which an entire top surface of the first electrode is in contact with the oxide semiconductor layer without the first insulating layer being interposed therebetween.

IPC Classes  ?

  • H10K 30/81 - Electrodes
  • H10K 30/60 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation in which radiation controls flow of current through the devices, e.g. photoresistors

2.

PHOTODETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2025001518
Publication Number 2026/078901
Status In Force
Filing Date 2025-01-20
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hasumi, Ryoji
  • Hasegawa, Ryota
  • Matsuo, Junichi

Abstract

A first photodetection device of one embodiment disclosed herein comprises: a first semiconductor substrate that has a first surface and a second surface that face each other; a photoelectric conversion unit that is embedded in the first semiconductor substrate; a charge holding unit that is formed on the first surface of the first semiconductor substrate and temporarily holds charges transferred from the photoelectric conversion unit; a transistor that includes a gate extending from the first surface of the first semiconductor substrate toward the second surface, and transfers the charges generated in the photoelectric conversion unit to the charge holding unit; and an element isolation unit that is provided to the first surface of the first semiconductor substrate between the charge holding unit and the gate, at least a portion of a side surface of the element isolation unit being in contact with the charge holding unit and the gate.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/70 - SSIS architecturesCircuits associated therewith

3.

DISPLAY DEVICE AND DISPLAY SYSTEM

      
Application Number JP2025034848
Publication Number 2026/079245
Status In Force
Filing Date 2025-09-30
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yoshida Mayuko
  • Yokoyama Kazuki
  • Toyoda Takashi

Abstract

[Problem] To provide a display device and a display system with which it is possible to inhibit burn-in by accurately detecting the light emission luminance of a display unit. [Solution] A display device according to the present invention comprises: a display unit that has a plurality of pixels which are arrayed two-dimensionally; and a light-receiving unit that receives emitted light from the display unit and does not overlap in planar view with an optical system disposed between the display unit and an observer.

IPC Classes  ?

  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • G02B 27/02 - Viewing or reading apparatus
  • G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
  • G09F 9/33 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
  • G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
  • G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
  • G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
  • G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • H04N 17/04 - Diagnosis, testing or measuring for television systems or their details for receivers

4.

PHOTODETECTOR AND ELECTRONIC DEVICE

      
Application Number JP2025033720
Publication Number 2026/079140
Status In Force
Filing Date 2025-09-25
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sakuma Daiki
  • Hino Yasufumi
  • Ikeda Yusuke

Abstract

The present disclosure relates to a photodetector and an electronic device which make it possible to efficiently arrange different types of ADCs in a semiconductor chip. The photodetector includes: a pixel array unit in which a plurality of pixels are arranged in a matrix; a first ADC provided for each vertical signal line for transmitting pixel signals of pixels in the same column of the pixel array unit; a second ADC, the number of the second ADCs being smaller than the number of the first ADCs; and a selection unit for switching the connection between the second ADCs and the plurality of vertical signal lines. The technology of the present disclosure can be applied to, for example, a photodetector that generates a captured image by selectively using two ADCs in accordance with an operation mode or the like.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

5.

INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD

      
Application Number JP2025033732
Publication Number 2026/079141
Status In Force
Filing Date 2025-09-25
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kamada, Shohei
  • Imamura, Jun

Abstract

An information processing device according to the present technology comprises a calculation unit that calculates a deviation index value, which is an index value indicating the degree of deviation between an assumed spectrum and a target spectrum, on the basis of an eigenvalue and an eigenvector of a feature amount obtained by dimensionality reduction performed on the assumed spectrum, the assumed spectrum being an optical spectrum of an assumed object and the target spectrum being an optical spectrum acquired using a spectroscopic sensor.

IPC Classes  ?

6.

SEMICONDUCTOR DEVICE

      
Application Number JP2025034595
Publication Number 2026/079212
Status In Force
Filing Date 2025-09-30
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kitahara Gyo
  • Mori Shigetaka

Abstract

[Problem] To provide a semiconductor device with which it is possible to accurately evaluate plasma charge damage. [Solution] The semiconductor device comprises: a plasma charge damage detection target element; and a switching circuit that is disposed on a wiring path that is connected to the detection target element, and switches whether to supply a plasma charge damage detection signal to the detection target element. The detection target element and the switching circuit are disposed on mutually different substrates, or at least a portion of a wiring member linking the detection target element and the switching circuit is disposed on mutually different substrates.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

7.

DISPLAY DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING DISPLAY DEVICE

      
Application Number JP2025033699
Publication Number 2026/079136
Status In Force
Filing Date 2025-09-25
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamamura, Ikuhiro

Abstract

Provided is a display device in which: a first light-emitting unit (13A1) positioned in a pixel (A (i, j)) and a second light-emitting unit (13A2) positioned in a pixel (A (i, j +1)) are positioned in different first divided regions (ERA1, ERA2) corresponding to first layout portions (LA1, LA2) determined by a first exposure; a pixel circuit (14) connected to the first light-emitting unit (13A1) and a pixel circuit (14) connected to the second light-emitting unit (13A2) are disposed in the same second divided region (ERB1) corresponding to a third layout portion (LB1) determined by a second exposure; and a signal line drive circuit (15) for transmitting a signal to a pixel circuit (14) connected to the first light-emitting unit (13A1) and a signal line drive circuit (15) for transmitting a signal to a pixel circuit (14) connected to the second light-emitting unit (13A2) are disposed in the same third divided region (ERC1) corresponding to a third layout portion (LC1) determined by a third exposure.

IPC Classes  ?

  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
  • H10K 50/11 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
  • H10K 50/81 - Anodes
  • H10K 50/82 - Cathodes
  • H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
  • H10K 71/00 - Manufacture or treatment specially adapted for the organic devices covered by this subclass

8.

IMAGING DEVICE

      
Application Number JP2025028642
Publication Number 2026/078992
Status In Force
Filing Date 2025-08-13
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Umeda, Kengo
  • Sakano, Yorito
  • Iida, Satoko
  • Yoshida, Taishin

Abstract

The purpose of the invention is to make it possible to read pixel signals in which the pixel conversion efficiency has been switched while suppressing any decrease in the frame rate. This imaging device comprises a photoelectric conversion unit provided in a pixel, a transfer transistor that transfers charges accumulated in the photoelectric conversion unit to a first floating diffusion, an amplification transistor that outputs a pixel signal corresponding to the charges accumulated in the first floating diffusion, a selection transistor that selects an output from the amplification transistor, a first switching transistor that adds capacitance to the first floating diffusion on the basis of a first switching signal to switch conversion efficiency at the time of pixel signal output, and a second switching transistor that is connected in parallel to the first switching transistor and that adds capacitance to the first floating diffusion on the basis of a second switching signal to switch conversion efficiency at the time of pixel signal output.

IPC Classes  ?

  • H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance

9.

IOT DEVICE AND METHOD

      
Application Number EP2025079129
Publication Number 2026/078135
Status In Force
Filing Date 2025-10-09
Publication Date 2026-04-16
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY EUROPE LIMITED (United Kingdom)
Inventor
  • Semel, Lavi
  • Feldman, Dima

Abstract

The disclosure pertains to an IoT device of a first UE category, wherein the IoT device includes circuitry that is configured to: receive a first SIB1 according to a second UE category that is higher than the first UE category; determine a portion of content of the received first SIB1; receive a second SIB1 according to the first UE category; establish a radio communication connection with a base station based on the second SIB1; and report the determined portion of the content of the first SIB1 via the established radio communication connection for location estimation.

IPC Classes  ?

  • H04W 48/12 - Access restriction or access information delivery, e.g. discovery data delivery using downlink control channel
  • H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
  • H04W 4/70 - Services for machine-to-machine communication [M2M] or machine type communication [MTC]
  • G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinationsPosition-fixing by co-ordinating two or more distance determinations using radio waves

10.

IMAGING DEVICE

      
Application Number 19104348
Status Pending
Filing Date 2023-06-30
First Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Sato, Mamoru

Abstract

It is possible to prevent a black level output based on incidence of high brightness light. It is possible to prevent a black level output based on incidence of high brightness light. An imaging device includes: a signal line whose potential changes based on a charge stored according to a current flowing at a time of readout of a signal from a pixel; a signal line reset transistor that resets the potential of the signal line; a signal line reset level generation unit that generates a reset level of the potential of the signal line; a signal line clip transistor that clips the potential of the signal line; and a signal line clip voltage setting unit that sets a signal line clip voltage used to generate a clip level of the potential of the signal line. The signal line reset level generation unit may be a diode connection transistor.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H04N 25/67 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion

11.

LIGHT DETECTION DEVICE AND ELECTRONIC EQUIPMENT

      
Application Number JP2025032637
Publication Number 2026/079076
Status In Force
Filing Date 2025-09-17
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ogawa, Yasuhiro
  • Murase, Takuro

Abstract

A light detection device according to an embodiment of the present disclosure comprises: a first photoelectric conversion element that photoelectrically converts light; a first region provided in a first semiconductor layer; and a first readout circuit that has a first transistor provided to the first region branching off into a plurality of sections, the first readout circuit being capable of outputting a signal based on charges converted by the first photoelectric conversion element.

IPC Classes  ?

  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

12.

ELECTRODE ARRAY SENSOR AND ELECTRODE ARRAY SENSOR SYSTEM

      
Application Number JP2025029236
Publication Number 2026/078999
Status In Force
Filing Date 2025-08-20
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Sugimori Yusaku

Abstract

[Problem] To provide an electrode array sensor and an electrode array sensor system which are capable of extracting necessary data in a short time while reducing the capacity of data recording electrical activity of an inspection target. [Solution] An electrode array sensor according to the present embodiment comprises: an electrode array including a plurality of sub-arrays composed of a plurality of electrodes arranged two-dimensionally; an AD conversion unit that compares each of a plurality of first electrode signals indicating voltages applied to the plurality of electrodes with a reference signal that changes over time, thereby performing AD conversion of the first electrode signals into a plurality of second electrode signals; and an arithmetic processing unit that determines whether to apply a first flag signal to the plurality of second electrode signals of each sub-array on the basis of a comparison result signal obtained by comparing the plurality of first electrode signals with the reference signal.

IPC Classes  ?

  • G01N 27/26 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variablesInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by using electrolysis or electrophoresis
  • G01N 27/02 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance

13.

LIGHT DETECTION DEVICE

      
Application Number JP2025034589
Publication Number 2026/079210
Status In Force
Filing Date 2025-09-30
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Okazaki Tetsushi

Abstract

[Problem] To improve the image quality of a captured image by suppressing the occurrence of white spots in a floating diffusion region. [Solution] A light detection device includes: a first semiconductor region of a first conductivity type disposed along one main surface of a semiconductor layer; a second semiconductor region of a second conductivity type disposed close to the first semiconductor region of the semiconductor layer in a plane direction; a first conductive member extending upward from the first semiconductor region; a second conductive member extending from the first conductive member along the plane direction and disposed so as to face the first semiconductor region and to face at least a part of the second semiconductor region; a first insulating layer disposed between the first semiconductor region and the second semiconductor region, and the second conductive member; and a lowermost wiring layer connected to the first conductive member above the second conductive member.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

14.

LIGHT DETECTION DEVICE

      
Application Number JP2025035838
Publication Number 2026/079455
Status In Force
Filing Date 2025-10-09
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hasegawa, Ryo
  • Yanagida, Masaaki
  • Yoneda, Kazuhiro

Abstract

Provided is a light detection device comprising: a pixel array unit configured by arranging a plurality of light detection pixels, including an imaging pixel and a phase difference detection pixel, in a matrix on a semiconductor substrate; and a plurality of contacts for electrically connecting a predetermined region in the semiconductor substrate to a reference potential. Each of the contacts is provided in the region of the phase difference detection pixel.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

15.

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

      
Application Number JP2025028638
Publication Number 2026/078991
Status In Force
Filing Date 2025-08-13
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Furuya, Hiroshi

Abstract

The present invention enables flip-chip mounting via a liquid metal while preventing liquid leakage of the liquid metal. This semiconductor apparatus comprises: a semiconductor chip on which a semiconductor device is formed; a protruding electrode electrically connected to the semiconductor device; a mounting substrate provided with an opening in which a liquid metal electrically connected to the protruding electrode is placed; and a metal oxide film on the surface of the liquid metal. The protruding electrode may be inserted into the liquid metal through the metal oxide film. The metal oxide film may have flexibility. The metal oxide film may be an oxide of a liquid metal.

IPC Classes  ?

  • H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

16.

SEMICONDUCTOR INTEGRATED CIRCUIT

      
Application Number JP2025030336
Publication Number 2026/079017
Status In Force
Filing Date 2025-08-28
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ota, Kensuke
  • Okuno, Jun
  • Yonai, Tsubasa

Abstract

This semiconductor integrated circuit includes: a first insulated gate field effect transistor having a first floating gate electrode in an electrically floating state, and having a first channel conductivity type; a second insulated gate field effect transistor having a second floating gate electrode formed integrally with the first floating gate electrode and being in an electrically floating state, and having a second channel conductivity type opposite to the first channel conductivity type; and a first capacitive element electrically coupled in series to the first floating gate electrode and the second floating gate electrode, and including a ferroelectric insulator.

IPC Classes  ?

  • H10B 51/00 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
  • H10B 41/00 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B 53/00 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
  • H10D 1/68 - Capacitors having no potential barriers
  • H10D 30/68 - Floating-gate IGFETs
  • H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
  • H10D 84/85 - Complementary IGFETs, e.g. CMOS

17.

DISPLAY DEVICE AND ELECTRONIC DEVICE

      
Application Number JP2025032532
Publication Number 2026/079070
Status In Force
Filing Date 2025-09-16
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takagi, Akitsuna
  • Asano, Mitsuru
  • Yagi, Keiichi

Abstract

Provided is a display device capable of suppressing the reflection of light around a display pixel region while suppressing the deterioration in reliability due to the infiltration of moisture. This display device comprises: an electrode that is provided around a display pixel region; an inner light-shielding layer that has a first outer end on the side opposite to the display pixel region, the inner light-shielding layer covering the electrode; a waterproof layer that covers the first outer end; and an outer light-shielding layer that has a second outer end on the side opposite to the display pixel region, the second outer end being positioned further outside than the first outer end when viewed from the display pixel region.

IPC Classes  ?

  • H10K 50/86 - Arrangements for improving contrast, e.g. preventing reflection of ambient light
  • H10K 50/84 - PassivationContainersEncapsulations
  • H10K 50/88 - Terminals, e.g. bond pads
  • H10K 50/854 - Arrangements for extracting light from the devices comprising scattering means
  • H10K 50/858 - Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 59/131 - Interconnections, e.g. wiring lines or terminals

18.

ELECTRONIC CIRCUIT, SOLID-STATE IMAGING DEVICE, AND READOUT CIRCUIT

      
Application Number JP2025036038
Publication Number 2026/079493
Status In Force
Filing Date 2025-10-10
Publication Date 2026-04-16
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Makigawa Kiyoshi
  • Akutagawa Kazuki

Abstract

The present technology relates to an electronic circuit, a solid-state imaging device, and a readout circuit that make it possible to reduce power consumption. An electronic circuit comprises a push-pull buffer circuit, the push-pull buffer circuit including a switch for performing intermittent signal output and a bypass current circuit for forming a bypass current path when the signal output is temporarily halted. The present technology can be applied to solid-state imaging devices.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H03F 3/26 - Push-pull amplifiersPhase-splitters therefor

19.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

      
Application Number 19397065
Status Pending
Filing Date 2025-11-21
First Publication Date 2026-04-09
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Takino, Chiaki
  • Yamanaka, Kazuhiro

Abstract

Parking region analysis for display of available and potentially available parking regions is disclosed. In one example, a parking region analyzer accesses a camera-captured image and analyzes whether or not a vehicle is able to be parked. A display controller generates parking possibility identification graphic data on the basis of the analysis and superimposes and displays the data on the camera-captured image.

IPC Classes  ?

  • G08G 1/14 - Traffic control systems for road vehicles indicating individual free spaces in parking areas
  • B60K 35/28 - Output arrangements, i.e. from vehicle to user, associated with vehicle functions or specially adapted therefor characterised by the type of the output information, e.g. video entertainment or vehicle dynamics informationOutput arrangements, i.e. from vehicle to user, associated with vehicle functions or specially adapted therefor characterised by the purpose of the output information, e.g. for attracting the attention of the driver
  • B60W 30/06 - Automatic manoeuvring for parking
  • B60W 50/14 - Means for informing the driver, warning the driver or prompting a driver intervention
  • G06V 10/26 - Segmentation of patterns in the image fieldCutting or merging of image elements to establish the pattern region, e.g. clustering-based techniquesDetection of occlusion
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestriansRecognition of traffic objects, e.g. traffic signs, traffic lights or roads

20.

LENS OPTICAL SYSTEM AND IMAGING APPARATUS

      
Application Number 19114087
Status Pending
Filing Date 2023-09-11
First Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ogino, Shinpei
  • Murakami, Daichi
  • Hanzawa, Fumihiko
  • Takeuchi, Haruki
  • Nakamura, Masashi
  • Kimura, Katsuji

Abstract

The present technology relates to a lens optical system and an imaging apparatus capable of improving optical performance in a wide-angle lens optical system having a metasurface. The lens optical system includes, in order from an incident side of light, a metalens having positive refractive power and an optical lens having positive refractive power. A metasurface including a plurality of nanostructures is arranged in the metalens. An aperture stop is arranged on the incident side of the metasurface. At least one optical surface of the second lens has an aspherical shape. The present technology can be applied to, for example, a wide-angle lens optical system that condenses light from a subject on a solid-state imaging element.

IPC Classes  ?

  • G02B 9/08 - Optical objectives characterised both by the number of the components and their arrangements according to their sign, i.e. + or – having two components only two + components arranged about a stop
  • G02B 1/00 - Optical elements characterised by the material of which they are madeOptical coatings for optical elements
  • G02B 3/04 - Simple or compound lenses with non-spherical faces with continuous faces that are rotationally symmetrical but deviate from a true sphere
  • G02B 9/34 - Optical objectives characterised both by the number of the components and their arrangements according to their sign, i.e. + or – having four components only
  • G02B 13/04 - Reversed telephoto objectives
  • H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
  • H04N 23/55 - Optical parts specially adapted for electronic image sensorsMounting thereof

21.

INFORMATION PROCESSING APPARATUS, PROGRAM, AND INFORMATION PROCESSING METHOD

      
Application Number 19114794
Status Pending
Filing Date 2023-09-29
First Publication Date 2026-04-09
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Kurokawa, Tsubasa

Abstract

An information processing apparatus includes, a matching circuit that receives a first image indicating a field of view in a prescribed space based on three-dimensional point cloud data that represents the prescribed space by a point cloud and a second image captured in the prescribed space, and matches the second image and the first image, and a position information providing circuit that generates second position information based on first position information about an origin of the field of view indicated by the first image matched with the second image and provides the second position information to update the three-dimensional point cloud data.

IPC Classes  ?

  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06T 7/80 - Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration
  • G06T 11/00 - 2D [Two Dimensional] image generation
  • G06V 10/40 - Extraction of image or video features

22.

RANGING DEVICE

      
Application Number JP2025027944
Publication Number 2026/074806
Status In Force
Filing Date 2025-08-06
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Suzuki, Shunpei
  • Kado, Takahiro
  • Shimizu, Shuji

Abstract

The present invention improves ranging performance in a mechanical ranging device. This ranging device (100) is provided with an emission-side mirror (222), a light-emitting unit (120), a light-receiving-side mirror (221), a light-receiving unit (130), and a ranging calculation unit (150). The emission-side mirror (222) can rotate about a predetermined rotation shaft (224). The light-emitting unit (120) emits laser light to the emission-side mirror (222). The light-receiving-side mirror (221) can rotate about the rotation shaft (224) together with the emission-side mirror (222), and the distance between the light-receiving-side mirror (221) and the rotation shaft is different from that between the emission-side mirror (222) and the rotation shaft. The light-receiving unit (130) receives the laser light reflected by the light-receiving-side mirror (221). The ranging calculation unit (150) calculates a distance on the basis of the signal from the light-receiving unit (130).

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
  • G02B 26/10 - Scanning systems

23.

VOLTAGE-CURRENT CONVERSION CIRCUIT AND IMAGING DEVICE

      
Application Number JP2025028634
Publication Number 2026/074812
Status In Force
Filing Date 2025-08-13
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Morimune, Masayuki
  • Doi, Hitoshi

Abstract

Provided is a voltage-current conversion circuit having an increased time constant of a low-pass filter while having a suppressed increase in capacitance. This voltage-current conversion circuit comprises: a super source follower circuit provided with an input transistor to which an input voltage is input; a resistive element connected in series to the source of the input transistor; and a capacitive element connected to the drain of the input transistor. The super source follower circuit may include: a current source transistor connected in series to the input transistor; and a feedback transistor having a gate connected to the drain of the input transistor and a drain connected to the source of the input transistor.

IPC Classes  ?

  • H03F 3/34 - DC amplifiers in which all stages are DC-coupled
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

24.

CONTROL CIRCUIT, DISPLAY DEVICE, AND DISPLAY SYSTEM

      
Application Number JP2025028803
Publication Number 2026/074816
Status In Force
Filing Date 2025-08-15
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ishikawa Hirotaka
  • Kimoto Taiyou
  • Mase Kota
  • Sugiyama Takaaki

Abstract

[Problem] To make it possible to perform image processing on a region based on a viewing point while suppressing a data transmission amount. [Solution] This control circuit comprises: an acquisition unit that acquires first image data; an image processing unit that is capable of performing either first processing for generating a second pixel value using the pixel values of a plurality of first pixels in the first image data and/or second processing for increasing resolution by dividing each first pixel into a plurality of pixels while maintaining the pixel value of the first pixel, performs at least the first processing, and generates second image data having the second pixel value; and a display control unit that causes a display unit to display an image based on the second image data.

IPC Classes  ?

  • G09G 5/37 - Details of the operation on graphic patterns
  • G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
  • G06T 5/70 - DenoisingSmoothing
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
  • G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G 5/391 - Resolution modifying circuits, e.g. variable screen formats

25.

OPTICAL SWITCH, RANGING DEVICE, AND ELECTRONIC APPARATUS

      
Application Number JP2025030079
Publication Number 2026/074840
Status In Force
Filing Date 2025-08-27
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakano Hiroshi
  • Yasu Yohtaro

Abstract

The purpose of the present invention is to provide a technology for shortening the temperature switching speed of a waveguide and improving the switching performance of an optical switch by appropriately controlling a voltage waveform to be applied to a heater. The present technology provides an optical switch and the like. The optical switch changes the phase of light on the basis of a thermooptic effect, and comprises: a heater that changes the temperature of a region in which the refractive index changes by the thermooptic effect; and a waveform generation unit that generates a voltage waveform for controlling a temporal change in voltage to be applied to the heater. The waveform generation unit changes the voltage from an initial voltage toward a limit voltage (maximum voltage or minimum voltage) in the shortest possible time, and thereafter changes the voltage from the limit voltage toward a target voltage.

IPC Classes  ?

  • G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
  • G01C 3/06 - Use of electric means to obtain final indication
  • G02F 1/31 - Digital deflection devices

26.

INFORMATION PROCESSING DEVICE AND VEHICLE

      
Application Number JP2025032622
Publication Number 2026/074910
Status In Force
Filing Date 2025-09-17
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Norimatsu Naoto
  • Okubo Jun
  • Ikeda Tatsuhiko
  • Fujiya Kazufumi
  • Hashimoto Kenji
  • Nishioka Shinichiro

Abstract

The present technology relates to an information processing device and a vehicle that make it possible to perform automatic parking in accordance with a user's preferences. The information processing device comprises a parking lot map generating unit that generates a parking lot map of a parking lot on the basis of a sensing result of a sensor mounted in the vehicle, and a contextual information generating unit that generates contextual information of the parking lot on the basis of the sensing result and the parking lot map, wherein the parking lot map generating unit generates a contextual parking lot map in which the contextual information is added to the parking lot map. The present technology is applicable to vehicle control systems for vehicles that perform autonomous driving, for example.

IPC Classes  ?

  • G08G 1/16 - Anti-collision systems
  • G08G 1/09 - Arrangements for giving variable traffic instructions
  • G09B 29/00 - MapsPlansChartsDiagrams, e.g. route diagrams
  • G09B 29/10 - Map spot or co-ordinate position indicatorsMap-reading aids

27.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2025034535
Publication Number 2026/075084
Status In Force
Filing Date 2025-09-29
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Azuhata Satoshi

Abstract

[Problem] To reduce variations in output level. [Solution] This solid-state imaging device comprises a light-receiving element, a transfer transistor, a first transistor, and a voltage retention circuit. A first terminal of the transfer transistor is connected to an output terminal of the light-receiving element. When an ON signal is applied to a drive terminal, the transfer transistor transfers a signal output by the light-receiving element to the second terminal. A first terminal of the first transistor is connected to a power supply line, and a second terminal thereof is connected to the first terminal of the transfer transistor or the second terminal of the transfer transistor. The voltage retention circuit is connected between the drive terminal of the first transistor and the second terminal of the first transistor.

IPC Classes  ?

  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
  • H04N 25/60 - Noise processing, e.g. detecting, correcting, reducing or removing noise

28.

SENSOR DEVICE AND METHOD FOR OPERATING A SENSOR DEVICE

      
Application Number EP2025078208
Publication Number 2026/074015
Status In Force
Filing Date 2025-10-01
Publication Date 2026-04-09
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY EUROPE LIMITED (United Kingdom)
Inventor
  • Kaneko, Tatsuya
  • Olsson Picalausa, Jenny Anna Maria
  • Kawazu, Naoki
  • Balcioglu, Yalcin
  • Dien Phan, Van Long
  • Saifuddin, Mohammed
  • Simovic, Milorad
  • Sundbeck, Henrik Valø

Abstract

A sensor device (100) is provided that comprises an imaging unit (110) that is configured to capture raw images of a scene, a first image signal processing, ISP, unit (120) that is configured to generate first image data by performing a first type of image signal processing on the raw images, a second ISP unit (130) that is different from the first ISP unit (120) and configured to generate second image data by performing a second type of image signal processing on the raw images, and a first serializer/deserializer (140) that is configured to transmit the first image data to a first image processing chip (210), wherein the sensor device (100) is configured to transmit the second image data to a second image processing chip (220).

IPC Classes  ?

  • H04N 23/60 - Control of cameras or camera modules
  • H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
  • H04N 23/80 - Camera processing pipelinesComponents thereof
  • B60R 1/00 - Optical viewing arrangementsReal-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles

29.

PHOTOELECTRIC CONVERTER, SOLID-STATE IMAGE SENSOR, AND RANGING SYSTEM

      
Application Number 19109588
Status Pending
Filing Date 2022-09-15
First Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Maekawa, Nobue

Abstract

A photoelectric converter according to an aspect of the present disclosure includes a semiconductor layer that is a SiGe layer or a Ge layer and a photodiode formed in the semiconductor layer. This solid-state image sensor further includes a transistor and a Si layer. The transistor has a source region and a drain region in the semiconductor layer and has a gate electrode in contact with the semiconductor layer via a gate insulating film. The Si layer is formed at an interface between the semiconductor layer and the gate insulating film.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

30.

SOLID-STATE IMAGING DEVICE, ELECTRONIC APPARATUS, AND PROGRAM

      
Application Number 19112974
Status Pending
Filing Date 2023-09-12
First Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kazama, Ryohei
  • Wakayama, Kazuyuki
  • Kusakari, Takashi

Abstract

Authentication accuracy is improved. A solid-state imaging device includes a light source, a first light receiving region, and a second light receiving region. The light source is provided on an opposite side of a display surface of a display, and emits light in an infrared light band via the display. The first light receiving region is provided on an opposite side of the display surface of the display, and includes a pixel that receives light in a visible light band and a pixel that receives at least light in an infrared light band emitted from the light source. The second light receiving region is provided on an opposite side of the display surface of the display, and includes a pixel that receives at least light in an infrared light band emitted from the light source.

IPC Classes  ?

  • H04N 23/611 - Control of cameras or camera modules based on recognised objects where the recognised objects include parts of the human body
  • G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
  • G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
  • H04N 23/56 - Cameras or camera modules comprising electronic image sensorsControl thereof provided with illuminating means
  • H04N 23/63 - Control of cameras or camera modules by using electronic viewfinders

31.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND RECORDING MEDIUM

      
Application Number 19116386
Status Pending
Filing Date 2023-09-20
First Publication Date 2026-04-09
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Hosoi, Izumu

Abstract

An image processing device includes circuitry that recognizes and extracts an object included in a captured image, and that converts, using an artificial intelligence (AI) model, a region image including the object to generate a feature image. The circuitry generates a mask image by combining the captured image with the feature image.

IPC Classes  ?

  • G06V 20/52 - Surveillance or monitoring of activities, e.g. for recognising suspicious objects
  • G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
  • G06T 11/00 - 2D [Two Dimensional] image generation
  • G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]
  • G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
  • G06V 10/778 - Active pattern-learning, e.g. online learning of image or video features

32.

IMAGING DEVICE AND IMAGING SYSTEM

      
Application Number JP2025020497
Publication Number 2026/074758
Status In Force
Filing Date 2025-06-06
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kawazu, Naoki
  • Murozuka, Masaki
  • Kosaka, Takuro
  • Matsuura, Kouji

Abstract

There is provided an imaging device. The imaging device according to an embodiment of the present disclosure includes an imaging section, a diagnosis section, and an output section. The imaging section is configured to perform an imaging operation. The diagnosis section is configured to perform diagnosis processing of a defect of the imaging section. The output section is configured to output a first flag signal corresponding to a result of the diagnosis processing. The output section is configured to set the first flag signal to a ground level in a case where the result of the diagnosis processing indicates a predictor of a defect.

IPC Classes  ?

  • H04N 25/68 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects
  • H04N 17/00 - Diagnosis, testing or measuring for television systems or their details
  • H04N 25/69 - SSIS comprising testing or correcting structures for circuits other than pixel cells
  • H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors

33.

IMAGE SENSOR

      
Application Number JP2025027919
Publication Number 2026/074805
Status In Force
Filing Date 2025-08-06
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Mogami, Yosuke

Abstract

The present invention improves image quality in an image sensor in which high-sensitivity sub-pixels and low-sensitivity sub-pixels are disposed. The image sensor comprises a pixel array unit and a column processing unit. Disposed in the pixel array unit of the image sensor are a plurality of pixels, each including a high-sensitivity sub-pixel that has a sensitivity higher than a prescribed value and a low-sensitivity sub-pixel that has a sensitivity lower than a prescribed value. At least two low-sensitivity sub-pixels are disposed adjacently. The column processing unit performs AD conversion of the respective pixel signals of the low-sensitivity sub-pixels and the high-sensitivity sub-pixels.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/585 - Control of the dynamic range involving two or more exposures acquired simultaneously with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
  • H10F 39/12 - Image sensors

34.

STORAGE CIRCUIT

      
Application Number JP2025028827
Publication Number 2026/074817
Status In Force
Filing Date 2025-08-15
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hiraga, Keizo
  • Nishi, Yuuji
  • Tabata, Toshikazu

Abstract

A store driver circuit of this storage circuit includes a first transistor and a second transistor that are cascode-connected. The gates of the first transistor and the second transistor of the store driver circuit are connected to a node of a latch circuit. The cascode connection points of the first transistor and the second transistor of the store driver circuit are connected to a magnetoresistive element. A current terminal of the first transistor or the second transistor of the store driver circuit is directly connected to a power supply voltage or a reference voltage.

IPC Classes  ?

  • G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
  • H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components

35.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

      
Application Number JP2025030118
Publication Number 2026/074843
Status In Force
Filing Date 2025-08-27
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hosoi, Izumu

Abstract

This information processing device comprises a receiving unit that receives metadata generated on the basis of the results of sensing, and an answer acquiring unit that generates a prompt to be input to a large language model and inputs the prompt to the large language model to obtain an answer, wherein the answer acquiring unit executes: first prompt generation processing for generating a prompt for instructing analysis of the metadata and identification of a problem; second prompt generation processing for generating a prompt for instructing a search for solutions that solve the identified problem; third prompt generation processing for generating a prompt for instructing a requirements definition of an application for realizing a solution selected by a user from among the solutions obtained by the search; and fourth prompt generation processing for generating a prompt for instructing generation of an application based on the requirements definition.

IPC Classes  ?

36.

INFORMATION PROCESSING SYSTEM

      
Application Number JP2025030695
Publication Number 2026/074851
Status In Force
Filing Date 2025-09-01
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Matsuda, Shogo
  • Nishimura, Atsushi

Abstract

In order to achieve the above purpose, an information processing system according to one embodiment of the present technology is used for generating AR content, the information processing system comprising: a display device including a display unit that is capable of displaying AR content to a user, an imaging unit that is capable of imaging the environment surrounding the user, and a transmission unit that transmits a prompt for generating content to be displayed in the AR content; and a content generation device including a content generation unit that generates content on the basis of the prompt, and a content arrangement unit that, on the basis of a real image, arranges the content within the real image. The display device furthermore includes an AR content generation unit that generates the AR content on the basis of a composite image in which the content is arranged within the real image by the content arrangement unit.

IPC Classes  ?

  • G06T 19/00 - Manipulating 3D models or images for computer graphics

37.

PHOTODETECTOR AND ELECTRONIC EQUIPMENT

      
Application Number JP2025032619
Publication Number 2026/074907
Status In Force
Filing Date 2025-09-17
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Furusato Kento

Abstract

The present disclosure relates to a photodetector and electronic equipment that can achieve miniaturization and improve performance of phase difference detection. This photodetector has a pixel array section in which hexagonal pixels are arranged in an array, each pixel having a microlens and a photoelectric conversion section that is divided into multiple sections in a planar view. The photodetector is configured so that a phase difference is detected by using signals obtained from the multiple photoelectric conversion sections below the microlenses. The present disclosure can be applied to, for example, a photodetector that photoelectrically converts incident light and detects a phase difference.

IPC Classes  ?

  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H04N 25/704 - Pixels specially adapted for focusing, e.g. phase difference pixel sets

38.

LIGHT DETECTING DEVICE

      
Application Number JP2025032620
Publication Number 2026/074908
Status In Force
Filing Date 2025-09-17
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takatsuka Takafumi

Abstract

The present disclosure relates to a light detecting device that makes it possible to suppress a sudden drop in potential. The light detecting device comprises: a pixel array unit in which pixels are arranged, each pixel having an optical pulse response unit including at least a photoelectric conversion unit that multiplies charges generated from photons and a recharge unit that recharges the photoelectric conversion unit; and a capacitance provided between a first potential and a second potential for causing a current to flow through the optical pulse response unit in response to the incidence of photons, in units of one or a plurality of pixels. The present disclosure is applicable to image sensors that employ SPADs, for example.

IPC Classes  ?

  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

39.

LIGHT DETECTION DEVICE AND ELECTRONIC EQUIPMENT

      
Application Number JP2025032658
Publication Number 2026/074912
Status In Force
Filing Date 2025-09-17
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Itoh, Shinya

Abstract

A light detection device according to one embodiment of the present disclosure comprises: a semiconductor substrate having a first surface and a second surface that face each other; a first photoelectric conversion unit that is disposed on the first surface side and converts light into an electric charge; first through wiring that passes between the first surface and second surface of the semiconductor substrate and transfers the electric charge; a first well region that is provided so as to span the entire surface of the semiconductor substrate and is of a first conductivity type; a second well region that is provided so as to surround the first through wiring and is of the first conductivity type; and a third well region that is provided between the first well region and the second well region, electrically separates the first well region and the second well region, and is of a second conductivity type different from the first conductivity type.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10F 30/20 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
  • H10K 30/30 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising bulk heterojunctions, e.g. interpenetrating networks of donor and acceptor material domains
  • H10K 30/60 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation in which radiation controls flow of current through the devices, e.g. photoresistors

40.

DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE

      
Application Number JP2025033338
Publication Number 2026/074958
Status In Force
Filing Date 2025-09-22
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shibata, Kenji
  • Aoyagi, Akiyoshi
  • Ando, Yusuke

Abstract

A display device according to an embodiment comprises: a display unit; and an imaging element that is for detecting the line-of-sight, is provided outside the display unit, and is integrated with the display unit.

IPC Classes  ?

  • G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • H01L 23/02 - ContainersSeals
  • H10F 39/12 - Image sensors
  • H10K 50/88 - Terminals, e.g. bond pads
  • H10K 59/10 - OLED displays
  • H10K 59/65 - OLEDs integrated with inorganic image sensors
  • H10K 59/80 - Constructional details
  • H10K 59/82 - Interconnections, e.g. terminals
  • H10K 59/95 - Assemblies of multiple devices comprising at least one organic light-emitting element wherein all light-emitting elements are organic, e.g. assembled OLED displays
  • H10K 71/00 - Manufacture or treatment specially adapted for the organic devices covered by this subclass
  • H10K 77/10 - Substrates, e.g. flexible substrates

41.

INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD

      
Application Number JP2025034964
Publication Number 2026/075171
Status In Force
Filing Date 2025-10-01
Publication Date 2026-04-09
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kobayashi Toshiyuki
  • Sakakibara Masaki
  • Taki Hidetoshi
  • Ota Kensuke

Abstract

[Problem] To make it possible to suppress processing time while maintaining processing accuracy in analog-to-digital conversion processing. [Solution] The present disclosure provides an information processing device comprising: a cell array that has cells which output a calculated voltage to a signal line on the basis of an input signal and a coefficient to be retained; an analog-to-digital converter that outputs a digital value on the basis of a ramp voltage and the voltage of the signal line; and a voltage control unit that controls the voltage range of the ramp voltage.

IPC Classes  ?

  • H03M 1/56 - Input signal compared with linear ramp
  • G06N 3/04 - Architecture, e.g. interconnection topology
  • G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
  • G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using elements simulating biological cells, e.g. neuron

42.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 19110397
Status Pending
Filing Date 2023-09-22
First Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shigetoshi, Takushi
  • Okamoto, Masaki
  • Hiratsuka, Tatsumasa
  • Hirano, Takaaki
  • Kugimiya, Katsuhisa
  • Matsumoto, Shun
  • Furuhashi, Takahisa

Abstract

Reliability is improved in a semiconductor device in which an annular trench is formed around a through hole. A semiconductor device includes a semiconductor substrate, a through wiring, a back surface insulating film, and an annular trench. A wiring layer is formed on a front surface of the semiconductor substrate. The through hole penetrates the semiconductor substrate. The through wiring is formed along a side surface of the through hole. The back surface insulating film covers a back surface of the semiconductor substrate with respect to the front surface. The annular trench surrounds the periphery of the through hole when viewed from a direction perpendicular to the back surface, and a cavity closed by the back surface insulating film when viewed from the direction parallel to the back surface is formed inside.

IPC Classes  ?

  • H10W 20/20 -
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10W 20/00 -

43.

PHOTODETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number 19110424
Status Pending
Filing Date 2023-08-31
First Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hasegawa, Kenta
  • Moriya, Yusuke

Abstract

The present technology relates to a photodetection device and an electronic apparatus capable of improving reliability of a light condensing design. A photodetection device according to one aspect of the present technology includes: a semiconductor substrate including a photoelectric conversion unit; a spacer layer that is provided on the semiconductor substrate; a meta-surface layer that is provided on the spacer layer; and a sidewall protective film that is provided at least on a sidewall of the spacer layer. The present technology can be applied to an image sensor including a meta-surface layer.

IPC Classes  ?

44.

IMAGING DEVICE AND ELECTRONIC DEVICE

      
Application Number 19110823
Status Pending
Filing Date 2023-08-18
First Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takenaka, Kyoichi
  • Kayashima, Seiji

Abstract

To reduce manufacturing cost by simplifying a configuration for switching an electronic shutter method. Provided is an imaging device including: a photoelectric conversion unit that converts light into charge; an overflow transistor connected to the photoelectric conversion unit; a transfer transistor connected to the photoelectric conversion unit; a reset transistor connected to the transfer transistor; a capacitor connected between the transfer transistor and the reset transistor; and an amplifier transistor connected between the transfer transistor and the reset transistor.

IPC Classes  ?

  • H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
  • H04N 23/11 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from different wavelengths for generating image signals from visible and infrared light wavelengths
  • H04N 25/531 - Control of the integration time by controlling rolling shutters in CMOS SSIS
  • H04N 25/532 - Control of the integration time by controlling global shutters in CMOS SSIS
  • H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

45.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2025027657
Publication Number 2026/070037
Status In Force
Filing Date 2025-08-05
Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakata, Masashi
  • Yokochi, Kaito
  • Miyata, Koji
  • Yamaguchi, Tetsuji
  • Yamashita, Kazuyoshi
  • Kamiya, Takuro
  • Yamajo, Hiroaki
  • Iikawa, Kei
  • Hayashida, Naoto

Abstract

A light detection device of the present disclosure comprises: a light-receiving layer which has a plurality of pixels that each include a plurality of divided pixels and that each detect light of different colors and in which light-receiving elements are disposed with respect to the respective plurality of divided pixels; and a light-condensing layer which condenses incident light toward the light-receiving layer. The plurality of pixels have a first pixel which detects first color light and a second pixel which detects second color light. The light-condensing layer condenses the incident light from a light-condensing region with a first area for each divided pixel with respect to at least the first pixel among the plurality of pixels, and condenses the incident light from a light-condensing region with a second area greater than the first area onto the entire second pixel with respect to at least the second pixel among the plurality of pixels.

IPC Classes  ?

  • H04N 25/10 - Circuitry of solid-state image sensors [SSIS]Control thereof for transforming different wavelengths into image signals
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H04N 25/704 - Pixels specially adapted for focusing, e.g. phase difference pixel sets

46.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND IMAGING SYSTEM

      
Application Number JP2025030423
Publication Number 2026/070197
Status In Force
Filing Date 2025-08-29
Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takahashi, Hidekazu
  • Nagumo, Takefumi
  • Jo, Kensei
  • Honda, Motonari
  • Rad, Saeed
  • Aumiller, Andreas

Abstract

An information processing device according to the present disclosure comprises a control unit. The control unit encodes a first frame image to generate a first code word. The control unit generates a motion vector from a second frame image having a higher frame rate than the first frame image. The control unit generates a second code word of an interpolation frame image for interpolating the first frame image according to the motion vector. The control unit synthesizes the first code word and the second code word to generate a synthesized code word.

IPC Classes  ?

  • H04N 19/587 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence
  • H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
  • H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
  • H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
  • H04N 19/503 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction

47.

LIGHT DETECTION DEVICE, IMAGING DEVICE, AND ELECTRONIC APPARATUS

      
Application Number JP2025034349
Publication Number 2026/071148
Status In Force
Filing Date 2025-09-29
Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Komuro Yutaro
  • Noguchi Sayato
  • Watanabe Maho
  • Furuya Noboru
  • Matsubayashi Eri

Abstract

The present disclosure pertains to a light detection device, an imaging device, and an electronic apparatus with which it is possible to improve sensitivity and acquire appropriate phase difference information while suppressing color mixing. A reflection wall having a refractive index lower than a predetermined refractive index is provided between respective color filters of pixels including a regular pixel and a phase difference pixel having a light shielding film for detecting phase difference. An end part of the light shielding film is formed so as to extend below the reflection wall, where the incidence direction of incident light on a pixel is from above to below. The present disclosure can be applied to a light detection device.

IPC Classes  ?

  • H10F 39/12 - Image sensors
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

48.

SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS

      
Application Number 19110395
Status Pending
Filing Date 2023-08-10
First Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shigetoshi, Takushi
  • Okamoto, Masaki
  • Hiratsuka, Tatsumasa
  • Hirano, Takaaki
  • Kugimiya, Katsuhisa
  • Matsumoto, Shun

Abstract

Provided is a semiconductor apparatus including a semiconductor substrate having a front surface on which a wiring layer is formed, a through hole that penetrates the semiconductor substrate, a through wire formed along a side surface of the through hole, and an annular trench that surrounds a circumference of the through hole when seen in a direction perpendicular to a rear surface of the semiconductor substrate which is on a side opposite to the front surface and that has formed therein a cavity when seen in a direction parallel to a rear surface.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/528 - Layout of the interconnection structure
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

49.

SERVER DEVICE, TERMINAL DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM

      
Application Number 19110449
Status Pending
Filing Date 2023-10-06
First Publication Date 2026-04-02
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Shimomura, Munehiro
  • Ishikawa, Hirotaka

Abstract

An information processing system configured to transmit a first command to a first electronic device requesting processing capability information of the first electronic device; receive first parameters from the first electronic device in response to the first command; divide a deep neural network (DNN) into at least a first DNN and a second DNN based on the first parameters received from the first electronic device; and transmit the first divided DNN to the first electronic device.

IPC Classes  ?

  • G06N 3/045 - Combinations of networks
  • G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections

50.

PHOTODETECTION DEVICE

      
Application Number 19112978
Status Pending
Filing Date 2023-08-18
First Publication Date 2026-04-02
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Ishii, Hiroyasu
  • Moriyama, Yusuke
  • Baba, Tomohiro
  • Kaji, Nobuaki
  • Wakayama, Kazuyuki
  • Izuhara, Kunihiko

Abstract

A device capable of improving characteristics of a light sensor by applying an appropriate bias voltage to the light sensor. A device according to one embodiment includes a first light source configured to emit a first light, a second light source configured to emit a second light having a first characteristic different from a second characteristic of the first light, a first light sensor configured to detect first reflected light that is the first light emitted from the first light source and reflected by an object, and a second light sensor configured to detect second reflected light that is the second light emitted from the second light source and reflected by a first member that is distinct from the object.

IPC Classes  ?

  • G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves

51.

PHOTODETECTION DEVICE AND RANGING SYSTEM

      
Application Number 19113136
Status Pending
Filing Date 2023-09-27
First Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sekiya, Akito
  • Hamamatsu, Masamune
  • Endo, Noriaki
  • Saito, Yoshiyuki

Abstract

To improve ranging accuracy with a small number of times of light emission and light reception regardless of a distance of an object. A photodetection device includes: a light receiving section that receives, within a first time range, a first reflected light pulse signal in which a first light pulse signal emitted at a first time interval is reflected by an object, and receives, within a second time range different from the first time range, a second reflected light pulse signal in which a second light pulse signal emitted at a second time interval different from the first time interval is reflected by the object; and a histogram generator that generates a first histogram in which a light reception frequency of the first reflected light pulse signal received within the first time range is classified for each predetermined fixed unit period, and generates a second histogram in which a light reception frequency of the second reflected light pulse signal received within the second time range is classified for each unit period.

IPC Classes  ?

  • G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
  • G01S 7/484 - Transmitters
  • G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
  • G01S 17/931 - Lidar systems, specially adapted for specific applications for anti-collision purposes of land vehicles

52.

APPARATUSES AND METHODS FOR POLARIZATION BASED SURFACE NORMAL IMAGING

      
Application Number 19113144
Status Pending
Filing Date 2023-09-18
First Publication Date 2026-04-02
Owner
  • Sony Semiconductor Solutions Corporation (Japan)
  • University of Zurich (Switzerland)
Inventor
  • Muglikar, Manasi
  • Moeys, Diederik Paul
  • Scaramuzza, Davide

Abstract

The present disclosure relates to an apparatus for polarization-based surface normal imaging, the apparatus comprising a linear polarizer configured to rotate and to subsequently pass light from a scene, an event-based vision sensor. EVS, configured to detect a set of events of the scene based on the rotation angle of the linear polarizer, and a shape estimation processor configured to compute surface normal information of the scene based on the set of events and the corresponding rotation angle of the polarizer.

IPC Classes  ?

  • G01B 11/24 - Measuring arrangements characterised by the use of optical techniques for measuring contours or curvatures
  • G02B 26/00 - Optical devices or arrangements for the control of light using movable or deformable optical elements
  • G02B 27/28 - Optical systems or apparatus not provided for by any of the groups , for polarising
  • H04N 23/55 - Optical parts specially adapted for electronic image sensorsMounting thereof
  • H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data

53.

INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING SYSTEM

      
Application Number JP2025027980
Publication Number 2026/070053
Status In Force
Filing Date 2025-08-06
Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sakurada, Taishi
  • Masuo, Akira
  • Hagio, Namiki
  • Matsukawa, Genta
  • Nakamura, Tatsuya

Abstract

[Problem] To automatically identify work to be performed on a vehicle. [Solution] An information processing device comprising a processing unit that identifies the start of work on the basis of the overlapping of a first detection target of a vehicle and a second detection target that performs work on the vehicle in an image captured by a camera.

IPC Classes  ?

  • G06Q 10/08 - Logistics, e.g. warehousing, loading or distributionInventory or stock management
  • G06T 7/20 - Analysis of motion
  • H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast

54.

LIGHT DETECTION DEVICE AND ELECTRONIC EQUIPMENT

      
Application Number JP2025029655
Publication Number 2026/070146
Status In Force
Filing Date 2025-08-25
Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Naruse, Junji

Abstract

A light detection device according to an embodiment of the present disclosure comprises: a semiconductor layer; first photoelectric conversion regions and second photoelectric conversion regions provided adjacent to each other in the semiconductor layer; and light collection elements provided above the semiconductor layer. The semiconductor layer has first protrusion parts provided between the light collection elements and the first photoelectric conversion regions.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

55.

LIGHT EMISSION DRIVING DEVICE

      
Application Number JP2025030119
Publication Number 2026/070177
Status In Force
Filing Date 2025-08-27
Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamashita, Yutaro

Abstract

A light emission driving device according to the present technology comprises: a first accumulation selection unit that selects, in accordance with a charge signal, whether or not to perform charge accumulation in a first charge accumulation unit using a power supply; a second accumulation selection unit that selects, in accordance with a charge signal, whether or not to perform charge accumulation in a second charge accumulation unit using the power supply; and an output selection unit that selects, in accordance with a boost signal, whether or not to connect the first charge accumulation unit and the second charge accumulation unit in series on a path of light emission current to a light emission unit.

IPC Classes  ?

  • G01S 7/484 - Transmitters
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

56.

IMAGING DEVICE, IMAGING CONTROL DEVICE, AND IMAGING SYSTEM

      
Application Number JP2025030832
Publication Number 2026/070232
Status In Force
Filing Date 2025-09-02
Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kawai, Koji

Abstract

The present invention reduces the cost of a signal cable. An imaging device comprises: a balanced channel transmission unit that transmits image data using a first communication line and a second communication line which constitute a balanced channel during a transfer period in a transfer cycle composed of the transfer period, in which a frame of image data for one screen is repeatedly transferred synchronously with generation of the frame, and a pause period that follows the transfer period; an unbalanced channel reception unit that receives a command transmitted using the second communication line as an unbalanced channel during the pause period; and a control unit that performs image data transmission control for causing the balanced channel transmission unit to transmit the image data during the transfer period and command reception control for causing the unbalanced channel reception unit to receive the command during the pause period.

IPC Classes  ?

  • H04N 23/66 - Remote control of cameras or camera parts, e.g. by remote control devices
  • H04L 25/02 - Baseband systems Details
  • H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
  • H04N 21/436 - Interfacing a local distribution network, e.g. communicating with another STB or inside the home
  • H04N 23/40 - Circuit details for pick-up tubes
  • H04N 23/60 - Control of cameras or camera modules

57.

LIGHT DETECTION DEVICE

      
Application Number JP2025031748
Publication Number 2026/070341
Status In Force
Filing Date 2025-09-09
Publication Date 2026-04-02
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yorikado Yuhi
  • Ushiku Yuki

Abstract

The present disclosure relates to a light detection device that makes it possible to achieve a supply path for supplying a prescribed voltage with low resistance. This light detection device is provided with: a semiconductor substrate having a photoelectric conversion region for photoelectrically converting incident light; a light shielding film formed on a light incident surface side of the semiconductor substrate; and an electrode pad formed on a side opposite to the light incident surface side of the semiconductor substrate. The light detection device has: a pixel array part having pixels; and a pad region having the electrode pad, wherein the pad region includes a guard ring in which a metal material is embedded in a trench penetrating the semiconductor substrate. The light detection device is configured so that the guard ring extracts, to the light incident surface side of the semiconductor substrate, a prescribed voltage which is supplied to the electrode pad, and so that the prescribed voltage extracted to the light incident surface side of the semiconductor substrate by the guard ring is supplied to the pixels of the pixel array part through the light shielding film. The technology of the present disclosure can be applied to, for example, an electronic apparatus or the like that detects the distance to a subject.

IPC Classes  ?

  • H10F 39/12 - Image sensors
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

58.

IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number 19108834
Status Pending
Filing Date 2023-08-16
First Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Shiihara, Yu

Abstract

An imaging device with a semiconductor substrate, a photoelectric converter, an electric charge holder, and a first light-blocking section. The semiconductor substrate includes a pixel array section of unit pixels. The first light-blocking section includes a first horizontal light-blocking part and a first vertical light-blocking part that is orthogonal to the first horizontal light-blocking part. The first vertical light-blocking part includes a first row light-blocking part and a first column light-blocking part. The first vertical light-blocking part is provided for each of the unit pixels positioned every other column and in a 45-degree oblique direction. The first horizontal light-blocking part has, in plan view, an end at or in the vicinity of a position connecting one and another of intersections of the first row light-blocking parts and the first column light-blocking parts that are provided for the respective unit pixels positioned every other column and in the 45-degree oblique direction.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

59.

IMAGING ELEMENT AND ELECTRONIC DEVICE

      
Application Number 19108843
Status Pending
Filing Date 2023-07-25
First Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Komatsu, Yoshihide
  • Date, Koshiro
  • Tagami, Hiroyasu

Abstract

To achieve lower power consumption of an imaging element mounted on an electronic device such as a smartphone. An imaging element of the present technology includes: an analog circuit unit including a pixel that performs photoelectric conversion; a logic circuit unit configured to process a signal read out from the pixel; a body potential generation unit configured to apply a body potential in a direction of lowering a threshold voltage to a well doped to enclose a transistor structure in a transistor forming the logic circuit unit; and a control unit configured to control the body potential for each operation mode designated from an outside.

IPC Classes  ?

  • H04N 25/709 - Circuitry for control of the power supply
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

60.

IMAGING DEVICE AND ELECTRONIC DEVICE

      
Application Number 19109746
Status Pending
Filing Date 2023-07-24
First Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takahashi, Seiki
  • Noudo, Shinichiro
  • Watanabe, Maho
  • Ikehara, Shigehiro

Abstract

An isolation ratio between a plurality of sub-pixels included in a pixel is further improved. An imaging device including a semiconductor substrate including a photoelectric conversion unit provided for each of pixels arranged two-dimensionally and a pixel isolation unit that isolates the photoelectric conversion units from each other, a color filter and an on-chip lens provided for each of the pixels on one surface of the semiconductor substrate, an inter-filter isolation unit provided to include a low refractive index material having a refractive index lower than a refractive index of the color filter between the color filters and isolate the color filter for each of the pixels, and a sub-pixel isolation unit that isolates the photoelectric conversion units of the pixels including a plurality of sub-pixels for each of the sub-pixels.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

61.

ELECTRONIC DEVICE AND MANUFACTURING METHOD FOR ELECTRONIC DEVICE

      
Application Number 19110383
Status Pending
Filing Date 2023-07-12
First Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Shigetoshi, Takushi

Abstract

An electronic device includes a substrate, a first through-hole penetrating the substrate, a capacitive element above the substrate, and a first conductor film. A first portion of the first conductor film traverses the substrate along a side wall of the first through-hole and a second portion of the first conductor film is in contact with the capacitive element.

IPC Classes  ?

  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits

62.

SOLID-STATE IMAGING DEVICE AND COMPARISON DEVICE

      
Application Number 19111607
Status Pending
Filing Date 2023-09-14
First Publication Date 2026-03-26
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Azuhata, Satoshi

Abstract

High-speed and high-performance signals are compared. In one example, a solid-state imaging element includes a comparison circuit, a first switch, a second switch, a third switch, a first capacitor, and a second capacitor. The comparison circuit includes a non-inverting input terminal and an inverting input terminal. The first switch is connected to the inverting input terminal. The second switch is connected to the inverting input terminal and controlled at a timing different from that of the first switch. The third switch is connected between an output terminal of the comparison circuit and the inverting input terminal. One end of the first capacitor is connected to the inverting input terminal via the first switch, and a reference signal is applied to the other end. One end of the second capacitor is connected to the inverting input terminal via the second switch, and a reference signal is applied to the other end.

IPC Classes  ?

  • H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

63.

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM

      
Application Number 19112246
Status Pending
Filing Date 2023-09-07
First Publication Date 2026-03-26
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Agresti, Gianluca
  • Rossi, Mattia
  • Rad, Saeed
  • Fujii, Yusuke

Abstract

An image processing method, and a program capable of easily generating a three-dimensional model including spectral information includes a three-dimensional model generated on the basis of an RGB image group, mapped spectral information of a spectral image group, and a spectral three-dimensional model in which the spectral information has been mapped onto the three-dimensional model is generated which can be applied in techniques for generating a spectral three-dimensional image in which spectral information is superimposed on a three-dimensional model.

IPC Classes  ?

  • G06T 17/00 - 3D modelling for computer graphics
  • G06T 7/70 - Determining position or orientation of objects or cameras

64.

SIGNAL PROCESSING DEVICE AND IMAGING DEVICE

      
Application Number JP2025027155
Publication Number 2026/063067
Status In Force
Filing Date 2025-07-31
Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nagumo, Masahiko
  • Kasuga, Takashi
  • Sawada, Kentaro

Abstract

A signal processing device according to the present disclosure comprises: an exposure control unit that divides a plurality of pixels for respective one or more colors in an image sensor having the plurality of pixels into a plurality of pixel groups for each of the colors, and exposes the plurality of pixel groups for different exposure durations; an extraction unit that acquires a difference signal between a pixel signal from one pixel group among the plurality of pixel groups and a signal obtained by multiplying a pixel signal from a pixel group different from the one pixel group among the plurality of pixel groups by the reciprocal of an exposure ratio to thereby extract an optical noise component; and a subtraction unit that performs a process for subtracting the optical noise component from pixel signals from the plurality of pixel groups on the basis of the difference signal and the exposure ratio.

IPC Classes  ?

  • H04N 25/60 - Noise processing, e.g. detecting, correcting, reducing or removing noise
  • H04N 23/12 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from different wavelengths with one sensor only

65.

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

      
Application Number JP2025030690
Publication Number 2026/063181
Status In Force
Filing Date 2025-09-01
Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Maekawa, Takahiro

Abstract

This image processing device comprises an image conversion unit that performs aspect ratio conversion by image expansion on an image to be recognized by an image recognition AI model, which is an AI model for performing image recognition processing, before the image is resized to an input tensor size of the image recognition AI model.

IPC Classes  ?

66.

TRANSMISSION DEVICE, TRANSMISSION METHOD, RECEPTION DEVICE, AND RECEPTION METHOD

      
Application Number JP2025031236
Publication Number 2026/063218
Status In Force
Filing Date 2025-09-04
Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kojima Tomoya
  • Takahashi Kazuyuki
  • Okada Satoshi

Abstract

The present disclosure relates to a transmission device, a transmission method, a reception device, and a reception method that enable appropriate selection of a broadcast service. Provided is a transmission device that comprises: a generation unit that generates configuration information necessary for selecting an Lch level; and a transmission unit that transmits a broadcast signal including the generated configuration information. According to the present disclosure, the present invention can be, for example, applied to broadcasting, such as a TLV multiplexing method or TMCC, that uses OFDM frames.

IPC Classes  ?

  • H04N 21/2362 - Generation or processing of SI [Service Information]
  • H04N 21/61 - Network physical structureSignal processing
  • H04N 21/434 - Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams or extraction of additional data from a video streamRemultiplexing of multiplex streamsExtraction or processing of SIDisassembling of packetised elementary stream

67.

DISPLAY DEVICE, OPTICAL SYSTEM, AND ELECTRONIC APPARATUS

      
Application Number JP2025031656
Publication Number 2026/063264
Status In Force
Filing Date 2025-09-08
Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kato, Takayoshi

Abstract

Provided is a display device in which the chief ray angle (CRA) is controlled. This display device comprises: a plurality of light-emitting elements that are two-dimensionally arranged; and a protective layer that contains an inorganic material and that seals a display surface side. The protective layer has a lens array on a surface opposite to the side of the plurality of light-emitting elements.

IPC Classes  ?

  • H10K 50/858 - Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • H05B 33/02 - Electroluminescent light sources Details
  • H05B 33/04 - Sealing arrangements
  • H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
  • H10K 50/844 - Encapsulations
  • H10K 50/852 - Arrangements for extracting light from the devices comprising a resonant cavity structure, e.g. Bragg reflector pair
  • H10K 50/856 - Arrangements for extracting light from the devices comprising reflective means
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 59/95 - Assemblies of multiple devices comprising at least one organic light-emitting element wherein all light-emitting elements are organic, e.g. assembled OLED displays

68.

DISPLAY DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18844700
Status Pending
Filing Date 2023-03-23
First Publication Date 2026-03-26
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Sudo, Shoji
  • Imabayashi, Daichi

Abstract

Provided is a display device capable of suppressing a decrease in light emission luminance. Provided is a display device capable of suppressing a decrease in light emission luminance. The display device includes a plurality of inorganic light emitting diodes arranged two-dimensionally and a plurality of organic light emitting diodes arranged two-dimensionally. At least one of the organic light emitting diodes is provided on an upper portion of or above at least one of the inorganic light emitting diodes or on a lower portion of or below at least one of the inorganic light emitting diodes.

IPC Classes  ?

  • H10K 59/70 - OLEDs integrated with inorganic light-emitting elements, e.g. with inorganic electroluminescent elements
  • H10K 59/35 - Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

69.

TERMINAL, COMMUNICATION SYSTEM, AND TERMINAL SYNCHRONIZATION METHOD

      
Application Number 19109639
Status Pending
Filing Date 2023-07-21
First Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kitayama, Hideya
  • Nakahara, Kentaro

Abstract

To equalize power consumption of each terminal by grasping a power supply state of each terminal, and to achieve power saving of the entire system in a communication system including a plurality of terminals. To equalize power consumption of each terminal by grasping a power supply state of each terminal, and to achieve power saving of the entire system in a communication system including a plurality of terminals. A power supply state determination information acquisition unit acquires power supply state determination information for determining the power supply state of a local terminal. A power supply state determination information communication unit performs communication for exchanging the power supply state determination information with another terminal. A representative terminal determination unit determines a representative terminal on the basis of the power supply state determination information of the local terminal and the another terminal. In a case where the local terminal corresponds to the representative terminal, a reference signal reception unit receives a reference signal necessary for synchronization and generates time information. A time information communication unit transmits the time information to the another terminal in a case where the local terminal corresponds to the representative terminal, and receives the time information from the representative terminal in a case where the local terminal does not correspond to the representative terminal.

IPC Classes  ?

70.

SOLID-STATE IMAGING DEVICE

      
Application Number 19109847
Status Pending
Filing Date 2023-08-22
First Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takeuchi, Koichi

Abstract

The present technology provides a solid-state imaging device capable of suppressing reflection of light at an upper portion of a separation wall. The present technology provides a solid-state imaging device capable of suppressing reflection of light at an upper portion of a separation wall. The solid-state imaging device according to the present technology includes a pixel that includes: first and second light receiving units that are adjacent to each other and receive light in a same wavelength band; and a separation wall provided between the first and second light receiving units. The first light receiving unit includes: a first photoelectric conversion element; and a first phase imparting structure that is provided on an incident side of the light of the first photoelectric conversion element and imparts a first phase to incident light. The second light receiving unit includes: a second photoelectric conversion element; and a second phase imparting structure that is provided on an incident side of the light of the second photoelectric conversion element and imparts a second phase different from the first phase to incident light.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

71.

INFORMATION PROCESSING APPARATUS AND METHOD, AND PROGRAM

      
Application Number 19110824
Status Pending
Filing Date 2023-09-06
First Publication Date 2026-03-26
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Ebihara, Munetake

Abstract

The present technique relates to an information processing apparatus, an information processing method, and a program that enable a contextual relationship of data to be proved even when troubleshooting of equipment has been carried out. The present technique relates to an information processing apparatus, an information processing method, and a program that enable a contextual relationship of data to be proved even when troubleshooting of equipment has been carried out. The information processing apparatus is an information processing apparatus that generates output data including object data to be a verification object of a temporal contextual relationship, the information processing apparatus including: a control unit configured to generate the output data including a hash value calculated on the basis of a part of or all of output data that temporally immediately-precedes the output data, the object data, and a plurality of mutually-different types of ID information related to the object data. The present technique can be applied to cameras.

IPC Classes  ?

  • G06F 21/60 - Protecting data
  • G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures

72.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number JP2025030691
Publication Number 2026/063182
Status In Force
Filing Date 2025-09-01
Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takaiwa, Tsukasa

Abstract

This semiconductor device comprises: a semiconductor chip; a wiring board on which a semiconductor chip is mounted and on the rear surface side of which an external connection terminal for performing electrical connection with the outside is formed, the rear surface being opposite to the front surface on which the semiconductor chip is mounted; and a lid part which is bonded to the semiconductor chip by an adhesive member formed on an outer edge part of the semiconductor chip and covers the semiconductor chip. A part of the adhesive member protrudes outward beyond the outer edge end of the semiconductor chip.

IPC Classes  ?

  • H01L 23/02 - ContainersSeals
  • H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container

73.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD

      
Application Number JP2025031743
Publication Number 2026/063272
Status In Force
Filing Date 2025-09-09
Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nishiya, Hiroaki

Abstract

An information processing device according to the present disclosure includes a first processing unit for executing processing by a first network from among the first network, which includes an input layer, and a second network, which includes an output layer, the first and second networks being obtained by splitting a network that processes input image data using an n-pixel × n-line filter (where n is an integer of 2 or more) at an intermediate layer between an N-th layer and an (N+1)-th layer (where N is an integer of 2 or more). The first processing unit causes the first network to perform the processing on the input image in units of n lines, and outputs the result of the processing line by line to the second network.

IPC Classes  ?

  • H04N 23/60 - Control of cameras or camera modules
  • G06N 3/045 - Combinations of networks
  • G06T 1/40 - Neural networks
  • G06T 7/00 - Image analysis
  • G06V 10/10 - Image acquisition
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks

74.

DISPLAY DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2025032432
Publication Number 2026/063373
Status In Force
Filing Date 2025-09-16
Publication Date 2026-03-26
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Shiraiwa, Toshiaki
  • Kasahara, Naoya
  • Ohshima, Keiji
  • Mochiyama, Suguru
  • Ono, Keisuke
  • Sugino, Yuta
  • Sawabe, Tomoaki
  • Ichikawa, Tomoyoshi

Abstract

Provided is a display device comprising a plurality of light-emitting elements arrayed on a substrate and separated from each other. Each of the light-emitting elements includes lamination layers constituted by a first electrode, a light-emitting unit provided on the first electrode, and a second electrode provided on the light-emitting unit. Second electrodes that are adjacent to each other are electrically connected to each other by a wire extending on the second electrodes. A first auxiliary wire is provided between light-emitting elements that are adjacent to each other such that the first auxiliary wire comes into contact with the aforementioned wire. The first auxiliary wire includes a first conductive layer constituted by a material common to the second electrodes. At least a portion of the first conductive layer is located at the same heights as the lamination layers in a cross section obtained by cutting a light-emitting element in the lamination direction.

IPC Classes  ?

  • H10K 50/824 - Cathodes combined with auxiliary electrodes
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
  • H10K 50/818 - Reflective anodes, e.g. ITO combined with thick metallic layers
  • H10K 50/844 - Encapsulations
  • H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/131 - Interconnections, e.g. wiring lines or terminals

75.

ACTUATOR MECHANISM AND ROBOT DEVICE

      
Application Number JP2025031235
Publication Number 2026/063217
Status In Force
Filing Date 2025-09-04
Publication Date 2026-03-26
Owner
  • SONY GROUP CORPORATION (Japan)
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ogawa Takahiro
  • Fuchiwaki Ohmi
  • Kitamura Yuta
  • Fujita Shuji
  • Inoue Yukito
  • Yamaji Hideo
  • Takei Tomoya

Abstract

The present disclosure relates to an actuator mechanism and a robot device which make it possible to achieve driving with high responsiveness. The actuator mechanism according to the present disclosure includes: a plurality of shape memory alloy wires, each of which has one end as a fixed end; and a plurality of fitting mechanisms, which are connected to the other ends of the respective shape memory alloy wires and are detachably fitted to an object to be driven. The fitting mechanism is adhered to the object when the shape memory alloy wire is energized, and is detached from the object when the shape memory alloy wire is not energized. The present disclosure can be applied to, for example, an actuator of a robot.

IPC Classes  ?

  • F03G 7/06 - Mechanical-power-producing mechanisms, not otherwise provided for or using energy sources not otherwise provided for using expansion or contraction of bodies due to heating, cooling, moistening, drying, or the like
  • B25J 19/00 - Accessories fitted to manipulators, e.g. for monitoring, for viewingSafety devices combined with or specially adapted for use in connection with manipulators
  • B64C 33/02 - WingsActuating mechanisms therefor
  • B64U 10/40 - Ornithopters

76.

ELECTRONIC DEVICE

      
Application Number 19394050
Status Pending
Filing Date 2025-11-19
First Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nakata, Masashi

Abstract

Provided is an electronic device that implements image-capturing with a wide angle of view with a compact housing. An electronic device according to the present disclosure includes: a display unit (2) configured to be deformable; and at least one first imaging unit (3) arranged on an opposite side of a display surface of the display unit (2) and configured to image incident light transmitted through the display unit. The display unit (2) may be foldable. Furthermore, at least a part of the display unit (2) may be bendable. Moreover, in the first imaging unit (3), an optical system used for image-capturing may be switchable in accordance with a shape of the display unit (2).

IPC Classes  ?

  • H04N 23/698 - Control of cameras or camera modules for achieving an enlarged field of view, e.g. panoramic image capture
  • G06F 1/16 - Constructional details or arrangements
  • H04N 5/262 - Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects
  • H04N 5/77 - Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
  • H04N 23/51 - Housings
  • H04N 23/63 - Control of cameras or camera modules by using electronic viewfinders
  • H04N 23/90 - Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums

77.

LIGHT DETECTION ELEMENT AND ELECTRONIC APPARATUS

      
Application Number 19396865
Status Pending
Filing Date 2025-11-21
First Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takase, Hiroaki
  • Yokochi, Kaito
  • Miyata, Koji
  • Takahashi, Seiki
  • Ogasahara, Takayuki

Abstract

A light detection element according to the present disclosure includes a plurality of photoelectric converters, a color splitter layer, and a plurality of condensers. The plurality of photoelectric converters are disposed side by side in a matrix in a semiconductor layer. The color splitter layer is disposed on a light incident side with respect to the plurality of photoelectric converters, and includes a low refractive index layer and a plurality of columnar high refractive index portions. The plurality of condensers are disposed on the light incident side with respect to the color splitter layer, and condenses incident light to the corresponding high refractive index portions.

IPC Classes  ?

  • G02B 19/00 - Condensers
  • G02B 27/10 - Beam splitting or combining systems
  • H04N 25/13 - Arrangement of colour filter arrays [CFA]Filter mosaics characterised by the spectral characteristics of the filter elements
  • H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors

78.

SOLID-STATE IMAGING ELEMENT AND MANUFACTURING METHOD, AND ELECTRONIC DEVICE

      
Application Number 19106244
Status Pending
Filing Date 2023-08-21
First Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ishizaki, Takeshi

Abstract

The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic device that can achieve higher image quality. The solid-state imaging element includes a plurality of pixels, a capacitor provided for each of the pixels and formed in a three-dimensional shape between an upper wiring and a lower wiring of a wiring layer of the pixels, and an isolation unit that electrically isolates capacitors of adjacent pixels from each other. Then, the isolation unit is provided for each of the pixels so as to surround the capacitor, and an interlayer insulating film is provided between the isolation units of the respective pixels. The present technology can be applied to a CMOS image sensor, for example.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
  • H10D 1/00 - Resistors, capacitors or inductors
  • H10D 1/68 - Capacitors having no potential barriers

79.

IMAGING ELEMENT AND ELECTRONIC APPARATUS

      
Application Number 19108824
Status Pending
Filing Date 2023-08-16
First Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kawamura, Tomohiko
  • Uchida, Tetsuya

Abstract

An imaging element of an embodiment of the present disclosure includes: a semiconductor substrate including a photoelectric converter for each pixel; one or more pixel transistors provided in one surface of the semiconductor substrate; and a first element isolation section and a second element isolation section having different depths from each other that are embedded in the one surface of the semiconductor substrate and define an active region of the one or more pixel transistors, in which a portion of a gate electrode of the one or more pixel transistors is embedded in at least one of the first and second element isolation sections at different depths.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

80.

PHOTODETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number 19108837
Status Pending
Filing Date 2023-09-05
First Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yoshiba, Ippei

Abstract

Provided is a photodetection device capable of suppressing deterioration of a captured image. A photodetection device includes: a semiconductor layer including a plurality of cell regions arranged in a row direction and a column direction in a pixel region, one surface of the semiconductor layer being an element formation surface, and another surface of the semiconductor layer being a light incident surface; and a deflection layer provided at a position facing the light incident surface of the cell region or provided in a portion of the cell region on the light incident surface side. A photoelectric conversion element, a light shielding film extending along a direction perpendicular to a thickness direction of the semiconductor layer, and a charge holding unit located closer to the element formation surface than the light shielding film in a thickness direction of the semiconductor layer are provided in the cell region. The deflection layer includes, for each of the cell regions, a first region having a first refractive index and a second region having a second refractive index higher than the first refractive index at different positions in plan view. The second region is located at a position overlapping the light shielding film in plan view.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

81.

MAGNETORESISTIVE ELEMENT, STORAGE DEVICE, AND ELECTRONIC APPARATUS

      
Application Number 19110432
Status Pending
Filing Date 2023-09-12
First Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Endo, Masaki

Abstract

A magnetoresistive element according to an embodiment of the present disclosure includes: a laminated body; a storage layer laminated on the laminated body and having a variable magnetization direction; a non-magnetic layer laminated on the storage layer; and a reference layer laminated on the non-magnetic layer and having a fixed magnetization direction, in which the laminated body includes a magnetic layer having a variable magnetization direction, and a non-magnetic metal layer laminated on the magnetic layer.

IPC Classes  ?

  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/10 - Magnetoresistive devices

82.

LIGHT CONTROL PART, SEMICONDUCTOR MOUNTING APPARATUS, AND PRODUCTION METHOD FOR SEMICONDUCTOR MOUNTING APPARATUS

      
Application Number JP2025027911
Publication Number 2026/058609
Status In Force
Filing Date 2025-08-06
Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ebiko, Yoshiki
  • Ohtorii, Hiizu

Abstract

A light control part comprising: a first base body that has a first surface and a second surface opposite to one another; a meta lens layer that is disposed on a portion of the first surface and controls a light property; and a first positioning pad that is disposed on another portion of the first surface and determines the position of the meta lens layer.

IPC Classes  ?

  • G02B 7/00 - Mountings, adjusting means, or light-tight connections, for optical elements
  • G01J 1/02 - Photometry, e.g. photographic exposure meter Details
  • G01J 1/04 - Optical or mechanical part
  • G02B 3/00 - Simple or compound lenses
  • H01S 5/02253 - Out-coupling of light using lenses
  • H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
  • H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
  • H10F 39/12 - Image sensors
  • H10F 77/00 - Constructional details of devices covered by this subclass

83.

MULTILAYER SUBSTRATE, ANTENNA ELEMENT, AND ANTENNA MODULE

      
Application Number JP2025029058
Publication Number 2026/058657
Status In Force
Filing Date 2025-08-19
Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ueda, Shin

Abstract

A multilayer substrate according to one embodiment of the present technology is provided with a plurality of conductor layers, an interlayer connection part, and one or more ridge parts. The plurality of conductor layers include a pair of waveguide conductor layers which form a pair of main waveguide surfaces facing each other. The interlayer connection part has a pair of post walls which are disposed in a manner facing each other, define a waveguide between the pair of main waveguide surfaces, and is configured from a plurality of conductor posts which individually connect the pair of waveguide conductor layers to each other and which are disposed in rows. The one or more ridge parts have a width narrower than the interval between the pair of post walls, are disposed in a manner protruding from the main waveguide surfaces toward the waveguide, and form ridge waveguide surfaces uniformly extending along the waveguide.

IPC Classes  ?

  • H01P 3/123 - Hollow waveguides with a complex or stepped cross-section, e.g. ridged or grooved waveguides
  • H01P 3/12 - Hollow waveguides
  • H01Q 13/06 - Waveguide mouths

84.

DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE

      
Application Number JP2025031018
Publication Number 2026/058768
Status In Force
Filing Date 2025-09-03
Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Aoyagi, Akiyoshi
  • Matsubara, Hiroaki

Abstract

According to one embodiment of the present invention, a display device comprises: a display unit; a flexible substrate electrically connected to the display unit by a wire; and a reinforcing plate supporting the display unit and the flexible substrate.

IPC Classes  ?

  • G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H10K 50/842 - Containers
  • H10K 50/844 - Encapsulations
  • H10K 59/10 - OLED displays
  • H10K 59/82 - Interconnections, e.g. terminals
  • H10K 77/10 - Substrates, e.g. flexible substrates

85.

GRATING COUPLER, PHOTONIC CHIP, LIDAR SYSTEM AND METHOD

      
Application Number EP2025076157
Publication Number 2026/057835
Status In Force
Filing Date 2025-09-15
Publication Date 2026-03-19
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY EUROPE LIMITED (United Kingdom)
Inventor
  • Schäfer, Henrik
  • Ott, Arndt

Abstract

The disclosure pertains to a grating coupler for coherent lidar, wherein the grating coupler includes: a waveguide that extends along a guidance direction; and pairs of radiating elements that are arranged along the guidance direction at an emission side of the waveguide, wherein each pair includes a left radiating element and a right radiating element that are separated from each other by a gap.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 17/08 - Systems determining position data of a target for measuring distance only
  • G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
  • G02B 6/34 - Optical coupling means utilising prism or grating
  • G02B 27/09 - Beam shaping, e.g. changing the cross-sectioned area, not otherwise provided for

86.

LIGHT DETECTION ELEMENT AND ELECTRONIC APPARATUS

      
Application Number 19105931
Status Pending
Filing Date 2023-08-30
First Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Mori, Hiroyuki

Abstract

A light detection element including: a photoelectric conversion section that is in a semiconductor substrate and generates a charge corresponding to incident light; a first accumulation section that accumulates the generate charge; an amplification transistor that generates an input signal corresponding to an amount of the accumulated charge; a second accumulation section to which a saturated charge is transferred from the photoelectric conversion section via the first accumulation section; a conversion efficiency switching transistor that transfers the saturated charge to the second accumulation section to switch a conversion efficiency; a reset transistor that resets the charge accumulated in the first accumulation section and the saturated charge accumulated in the second accumulation section; and a differential input circuit that compares the input signal generated by the amplification transistor with a reference signal and outputs a comparison result, in which the second accumulation section includes a MIM capacitor having a three-dimensional structure.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

87.

WIRELESS COMMUNICATION TERMINAL, BASE STATION, AND WIRELESS COMMUNICATION SYSTEM

      
Application Number 19106240
Status Pending
Filing Date 2023-07-13
First Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Motoyama, Hideshi
  • Nakamura, Kazuya

Abstract

To reduce power consumption of a wireless communication terminal at the time of positioning processing. A wireless communication terminal includes: a wireless communication unit that performs wireless communication; a positioning processing unit that performs positioning processing on the basis of reception data received via the wireless communication unit; and a control unit that controls power consumption related to the positioning processing on the basis of control information regarding the positioning processing acquired via the wireless communication unit. The wireless communication terminal further includes an amplifier that amplifies a signal received via an antenna, in which the wireless communication unit transmits position information obtained by the positioning processing unit, and the control unit controls an operation of the amplifier on the basis of control information regarding the positioning processing obtained via the wireless communication unit.

IPC Classes  ?

  • H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
  • H04W 52/02 - Power saving arrangements

88.

SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE

      
Application Number 19110004
Status Pending
Filing Date 2023-07-20
First Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Koyama, Toshiki
  • Miyaki, Harumi
  • Kumon, Satoshi

Abstract

To suppress flowing out of an adhesive to the outside of a prescribed region in a semiconductor package in which a substrate is bonded to a support by the adhesive. A semiconductor package includes a substrate, a semiconductor chip, a support, and a first adhesive. In this semiconductor package, the semiconductor chip is placed on a substrate flat surface of the substrate and electrically connected to the substrate. Further, in the semiconductor package, a part of the first adhesive flows into a gap between the substrate flat surface and the semiconductor chip, and adheres the substrate to the support.

IPC Classes  ?

89.

ANTENNA ARRAY AND RADAR DEVICE

      
Application Number JP2025024198
Publication Number 2026/058552
Status In Force
Filing Date 2025-07-04
Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ichihara Takuya
  • Hashiguchi Takaaki

Abstract

k12NN) of each of the antenna elements is the solution of formula (1) defined as a maximization problem for maximizing the aperture length A.

IPC Classes  ?

  • G01S 7/03 - Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver
  • G01S 7/42 - Diversity systems specially adapted for radar
  • H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart

90.

LIGHT DETECTION DEVICE

      
Application Number JP2025024460
Publication Number 2026/058559
Status In Force
Filing Date 2025-07-08
Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Horio Masaya
  • Hagiwara Daichi

Abstract

The present disclosure relates to a light detection device that makes it possible to achieve even greater improvements in performance. SPAD pixels include: a cathode contact which is provided at a center part of a surface of a semiconductor substrate and is directly connected to an electrode for supplying a cathode potential to a multiplication region for multiplying charges generated in a photoelectric conversion part; and an anode contact which is provided at an outer peripheral part of the surface of the semiconductor substrate within a certain range from the surface to a predetermined depth, and is connected to a light shielding metal for supplying an anode potential to the multiplication region via a conductor. The anode contact and the conductor are connected via a connection surface along at least the depth direction of the semiconductor substrate. The present technology can be applied to, for example, a light detection device provided with SPAD pixels.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes
  • H10F 39/12 - Image sensors

91.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM

      
Application Number JP2025028855
Publication Number 2026/058652
Status In Force
Filing Date 2025-08-18
Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Masuyama, Kyota

Abstract

This information processing device comprises: an inference unit that uses an AI model to perform inference processing on a captured image; a score calculation unit that calculates an inference uncertainty score on the basis of inference result information obtained by the inference processing; a determination processing unit that determines, on the basis of the uncertainty score, whether drift has occurred; and a transmission processing unit that, if the determination processing unit determines that drift has occurred, performs processing for transmitting the captured image, which is subjected to inference, to an external device.

IPC Classes  ?

92.

MULTILAYER SUBSTRATE AND ANTENNA MODULE

      
Application Number JP2025029007
Publication Number 2026/058656
Status In Force
Filing Date 2025-08-19
Publication Date 2026-03-19
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Murakami, Tomomichi
  • Ueda, Shin

Abstract

A multilayer substrate according to an embodiment of the present technology is provided with a plurality of conductor layers and an interlayer connection section. The plurality of conductor layers has a line conductor layer having a coplanar line and a pair of adjacent conductor layers neighboring the line conductor layer. The interlayer connection section has a plurality of columnar conductors connecting the plurality of conductor layers to each other. The multilayer substrate is such that, in a frequency band used by the coplanar line, a path of a return current is configured such that transmission loss due to the return current flowing through the columnar conductors between the coplanar line and the pair of adjacent conductor layers is prevented.

IPC Classes  ?

  • H01P 3/00 - WaveguidesTransmission lines of the waveguide type
  • H05K 3/46 - Manufacturing multi-layer circuits

93.

IMAGING DEVICE

      
Application Number 19387221
Status Pending
Filing Date 2025-11-12
First Publication Date 2026-03-12
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yokochi, Kaito

Abstract

An imaging device according to one embodiment of the present disclosure includes a first filter having a first refractive index for entering light, a first photoelectric conversion section that performs photoelectric conversion on light transmitted through the first filter, a second filter that has a second refractive index lower than the first refractive index for entering light and is adjacent to the first filter, a second photoelectric conversion section that performs photoelectric conversion on light transmitted through the second filter, a first medium that is provided on an opposite side of the first photoelectric conversion section as viewed from the first filter and has a third refractive index for entering light, and a second medium that is provided on an opposite side of the second photoelectric conversion section as viewed from the second filter and has a fourth refractive index higher than the third refractive index for entering light.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

94.

SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND ELECTRONIC APPARATUS

      
Application Number 19101772
Status Pending
Filing Date 2023-06-28
First Publication Date 2026-03-12
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takeuchi, Katsuhiko

Abstract

A semiconductor device includes a multi-gate transistor, a first terminal, and a second terminal. The multi-gate transistor includes field effect transistors that each have a pair of main electrodes and a gate electrode disposed between the pair of main electrodes and that are electrically coupled in series while sharing the main electrodes. The first terminal is electrically coupled to one of the main electrodes of the field effect transistor at one end of the series-coupled field effect transistors of the multi-gate transistor, and receives or outputs a signal. The second terminal is electrically coupled to another of the main electrodes of the field effect transistor at another end of the series-coupled field effect transistors of the multi-gate transistor and receives supply of a fixed potential. The gate electrode of at least one of the field effect transistors of the multi-gate transistor is electrically coupled to the other main electrode of the same field effect transistor.

IPC Classes  ?

  • H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
  • H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
  • H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
  • H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]

95.

LIGHT EMITTING DEVICE AND EYEWEAR DEVICE

      
Application Number 19105321
Status Pending
Filing Date 2023-08-29
First Publication Date 2026-03-12
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hamachi, Chugen
  • Motoyama, Yosuke

Abstract

Provided is a light emitting device capable of suppressing reflection of near infrared rays. The light emitting device includes a near-infrared absorption layer. The near-infrared absorption layer is provided in the effective pixel region and a peripheral region located around the effective pixel region. The near-infrared absorption layer has a pattern portion in the effective pixel region.

IPC Classes  ?

  • H10K 59/80 - Constructional details
  • H10K 59/38 - Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]

96.

PHOTODETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number 19108693
Status Pending
Filing Date 2023-08-17
First Publication Date 2026-03-12
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Uchida, Tetsuya

Abstract

A photodetection device according to an embodiment of the present disclosure includes: a semiconductor layer including a plurality of photoelectric conversion sections that performs photoelectric conversion on light; a pad that is provided on a first surface side of the semiconductor layer; a via that penetrates the semiconductor layer and is electrically coupled to the pad; and a first trench that is provided in such a manner that the first trench penetrates the semiconductor layer around the via to surround the via. The first trench is provided in such a manner that the first trenches form a lattice shape around the via in plan view.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

97.

LIGHT DETECTION DEVICE

      
Application Number JP2025025926
Publication Number 2026/053610
Status In Force
Filing Date 2025-07-22
Publication Date 2026-03-12
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Watarai, Yuma
  • Yamaguchi, Kazuki
  • Ueno, Shuuichirou
  • Suzuki, Kohei
  • Sugawara, Takuya
  • Takahashi, Ryusei

Abstract

A light detection device according to an embodiment of the present disclosure comprises: a photoelectric conversion element; a first transistor that is capable of generating a first signal based on a charge converted by the photoelectric conversion element; and a second transistor that is capable of outputting the first signal. The first transistor has a first portion that is part of a semiconductor layer, and a first gate electrode that is provided so as to sandwich the first portion. The second transistor has a second portion that is another part of the semiconductor layer, and a second gate electrode that is provided so as to sandwich the second portion. The length of the second portion in the thickness direction of the semiconductor layer is different from the length of the first portion in the thickness direction of the semiconductor layer.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

98.

LIGHT-EMITTING DEVICE AND ELECTRONIC EQUIPMENT

      
Application Number JP2025028560
Publication Number 2026/053696
Status In Force
Filing Date 2025-08-13
Publication Date 2026-03-12
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kugimiya, Katsuhisa

Abstract

A light-emitting device according to an embodiment of the present disclosure has an insulation layer, an insulating side wall, a lower electrode, an organic layer, and an upper electrode. The side wall is erected so as to enclose the light-emitting region on the insulation layer surface when observed in plan view. The lower electrode is disposed such as to cover from the insulation layer surface enclosed by the side wall to a portion of the side wall inner surface. The organic layer is disposed such as to cover the lower electrode surface and the side wall inner surface not covered by the lower electrode. The upper electrode is disposed such as to cover the organic layer inner surface.

IPC Classes  ?

  • H10K 50/813 - Anodes characterised by their shape
  • H10K 50/814 - Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
  • H10K 50/822 - Cathodes characterised by their shape
  • H10K 50/856 - Arrangements for extracting light from the devices comprising reflective means
  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/35 - Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

99.

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE

      
Application Number JP2025028857
Publication Number 2026/053713
Status In Force
Filing Date 2025-08-18
Publication Date 2026-03-12
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Fujiwara, Susumu
  • Kugimiya, Eiji
  • Shigeta, Hiroyuki
  • Seki, Kousuke
  • Tokiwa, Hirokazu
  • Hosokawa, Kohyoh

Abstract

Provided is a semiconductor package in which a semiconductor chip is connected by wire bonding, wherein problems at the time of manufacturing and mounting are solved. The semiconductor package is provided with a semiconductor chip, a substrate, a rib material, a transparent member, and a frame material. The substrate is connected to a light-receiving surface of the semiconductor chip by means of a bonding wire. The rib material is formed along the outer circumference of the light-receiving surface of the semiconductor chip. The frame material covers a lateral surface of the transparent member and/or a section of a rear surface that is a surface which is one of the two surfaces of the transparent member and which does not correspond to the light-receiving surface. A sealing resin seals lateral surfaces of the semiconductor chip.

IPC Classes  ?

100.

SENSOR DEVICE

      
Application Number JP2025029642
Publication Number 2026/053770
Status In Force
Filing Date 2025-08-25
Publication Date 2026-03-12
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Bessho, Kazuhiro
  • Hiraga, Keizo
  • Higo, Yutaka
  • Suemitsu, Katsumi
  • Tanigawa, Hironobu

Abstract

Provided is a sensor device comprising: a plurality of sensor elements that each change from a first state to a second state according to temperature and the duration of exposure to the temperature; and a magnetic field application unit that applies a magnetic field in a prescribed direction to the plurality of sensor elements. The plurality of sensor elements each include a magnetic tunnel junction element having an energy barrier between the first state and the second state. The magnetic field application unit applies the magnetic field to the plurality of sensor elements, thereby increasing the asymmetry of each of the sensor elements between the potential in the first state and the potential in the second state with the energy barrier interposed therebetween.

IPC Classes  ?

  • G01K 7/36 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using magnetic elements, e.g. magnets, coils
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/10 - Magnetoresistive devices
  • H10N 50/80 - Constructional details
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