Sony Semiconductor Solutions Corporation

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2025 August (MTD) 42
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H01L 27/146 - Imager structures 3,452
H04N 5/369 - SSIS architecture; Circuitry associated therewith 1,107
H04N 5/3745 - Addressed sensors, e.g. MOS or CMOS sensors having additional components embedded within a pixel or connected to a group of pixels within a sensor matrix, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components 634
H04N 5/378 - Readout circuits, e.g. correlated double sampling [CDS] circuits, output amplifiers or A/D converters 571
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1.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number 18630616
Status Pending
Filing Date 2024-04-09
First Publication Date 2025-08-14
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Hoshino, Kozo

Abstract

The present technology relates to a solid-state imaging device and an electronic apparatus that enable simultaneous acquisition of a signal for generating a high dynamic range image and a signal for detecting a phase difference. The solid-state imaging device includes a plurality of pixel sets each including color filters of the same color, for a plurality of colors, each pixel set including a plurality of pixels. Each pixel includes a plurality of photodiodes PD. The present technology can be applied, for example, to a solid-state imaging device that generates a high dynamic range image and detects a phase difference, and the like.

IPC Classes  ?

  • H04N 25/13 - Arrangement of colour filter arrays [CFA]Filter mosaics characterised by the spectral characteristics of the filter elements
  • H04N 25/533 - Control of the integration time by using differing integration times for different sensor regions
  • H04N 25/589 - Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields with different integration times, e.g. short and long exposures
  • H04N 25/704 - Pixels specially adapted for focusing, e.g. phase difference pixel sets

2.

SYSTEM

      
Application Number 18849405
Status Pending
Filing Date 2023-03-15
First Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sakakibara, Masaki
  • Sakano, Yorito
  • Toyoshima, Takahiro
  • Yamanaka, Takaya

Abstract

A system includes: a light source that emits light to a subject; a photodetection element that receives the light from the light source; and a light source control part that controls a light emission timing of the light source. The photodetection element includes: a photoelectric conversion part that generates by photoelectric conversion a charge pursuant to an amount of the received light; a transfer part that transfers the charge generated by the photoelectric conversion part; and a charge accumulation part that accumulates the charge transferred by the transfer part. The charge accumulated in the charge accumulation part is read at least twice or more nondestructively without being initialized, over a plurality of frames.

IPC Classes  ?

  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
  • H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling

3.

SOLID-STATE IMAGING DEVICE

      
Application Number 18859147
Status Pending
Filing Date 2023-03-14
First Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Okuno, Jun

Abstract

Provided is a solid-state imaging device capable of reducing cost related to a capacitor. A solid-state imaging device of the present disclosure includes: a first substrate; a photoelectric conversion unit provided in the first substrate; a floating diffusion unit provided in the first substrate; a pixel transistor electrically connected to the floating diffusion unit; and a capacitor including a first electrode electrically connected or connectable to the pixel transistor, a second electrode different from the first electrode, and a first ferroelectric film or a first antiferroelectric film provided between the first electrode and the second electrode.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

4.

LIGHT DETECTION DEVICE

      
Application Number JP2024044833
Publication Number 2025/169614
Status In Force
Filing Date 2024-12-18
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ohtsuka, Yusuke
  • Hojo, Naoto
  • Takisawa, Kota
  • Kambe, Tomoki
  • Mizoguchi, Takuto

Abstract

A first light detection device according to an embodiment of the present disclosure comprises: a semiconductor substrate having opposing first and second surfaces, in which a plurality of pixels are arranged in a two-dimensional array and a plurality of photoelectric conversion units adjacent to each other in each of a first direction and a second direction orthogonal to the first direction are formed in an embedded manner in each of the pixels; an inter-pixel isolation part formed in an embedded manner in the semiconductor substrate so as to surround each of the plurality of pixels; and an inter-element isolation part formed an embedded manner in the semiconductor substrate and including, within a pixel, a first isolation part provided between the plurality of photoelectric conversion units adjacent to each other in the first direction and a second isolation part provided between the plurality of photoelectric conversion units adjacent to each other in the first direction, wherein the first isolation part and/or the second isolation part has a gap between itself and the inter-pixel isolation part.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10F 77/00 - Constructional details of devices covered by this subclass

5.

CAPACITIVE ELEMENT, AND DISPLAY DEVICE

      
Application Number JP2024045031
Publication Number 2025/169617
Status In Force
Filing Date 2024-12-19
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Jiang Yuyang
  • Yoshioka Masaki

Abstract

[Problem] To provide a display capacitive element and a display device with which it is possible to minimize any decrease in the accuracy of a control operation resulting from parasitic capacitance. [Solution] According to the present disclosure, there is provided a capacitive element connected to an electronic circuit having a first node that has a first impedance and a second node that has a second impedance that is lower than the first impedance, said capacitive element comprising a substrate, and a first capacitance layer formed in a plane along the upper surface of the substrate, said first capacitance layer having looped metal wiring, pectinate first metal wiring connected to the looped metal wiring and formed within the looped metal wiring, and pectinate second metal wiring formed within the looped metal wiring of the first metal wiring. The first metal wiring is connected to the first node, and the second metal wiring is connected to the second node.

IPC Classes  ?

  • H10D 1/68 - Capacitors having no potential barriers
  • G09F 9/00 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
  • G09G 3/325 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
  • G09G 3/3275 - Details of drivers for data electrodes
  • H10K 50/00 - Organic light-emitting devices
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays

6.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2025001401
Publication Number 2025/169690
Status In Force
Filing Date 2025-01-17
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kubo Komomo

Abstract

[PROBLEM] To provide an image sensor that is resilient to fluctuations in threshold voltage and that exhibits little variation in ranging. [SOLUTION] A solid-state imaging device includes a pixel comprising: a light-receiving element; one or a plurality of accumulation units; and a plurality of transfer gates. The one or plurality of accumulation units accumulate signals output by the light-receiving element. At a prescribed timing, the plurality of transfer gates transfer the signals output by the light-receiving element to the accumulation unit. In addition, the plurality of transfer gates are configured so that at least two of the transfer gates are used for transfer to the respective accumulation units, and if there are a plurality of accumulation units, at least one of the transfer gates is used for transfer to the plurality of accumulation units.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • G01S 7/4863 - Detector arrays, e.g. charge-transfer gates
  • H04N 25/70 - SSIS architecturesCircuits associated therewith

7.

IMAGING DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2025002919
Publication Number 2025/169823
Status In Force
Filing Date 2025-01-30
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Mizoguchi Kyoji

Abstract

[Problem] To provide: an imaging device capable of suppressing deterioration in the accuracy of image-capture driving; and an electronic apparatus. [Solution] The present disclosure provides an imaging device comprising: a pixel array unit having a plurality of first pixel circuits which each output a detection signal indicating whether an output signal corresponding to the amount of incident light has changed due to exceeding a predetermined threshold value, and having a plurality of second pixel circuits which each output a gradation signal corresponding to the amount of incident light; and a control unit for controlling an image capture drive of the plurality of second pixel circuits on the basis of the detection signal.

IPC Classes  ?

8.

DISTANCE MEASURING DEVICE

      
Application Number JP2024044581
Publication Number 2025/169609
Status In Force
Filing Date 2024-12-17
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tsukuda, Yasunori
  • Yamamoto, Kentaro
  • Shimizu, Kosuke
  • Ito, Takashi

Abstract

A distance measuring device according to the present disclosure includes: a light receiving element capable of light detection; a reading circuit that generates, in accordance with the light detection in the light receiving element, a light receiving signal having a pulse width corresponding to a set delay time; a dead time calculation unit that calculates a dead time that is the shortest interval of the light detection in the light receiving element; a control circuit that controls the delay time on the basis of a setting value; a setting value calculation unit that calculates, on the basis of the calculated dead time, a setting value with which to approach a target dead time; and a distance measurement unit that generates distance measurement data on the basis of the light receiving signal in a state in which the delay time is controlled on the basis of the setting value calculated by the setting value calculation unit.

IPC Classes  ?

  • G01S 7/497 - Means for monitoring or calibrating
  • G01S 7/4861 - Circuits for detection, sampling, integration or read-out
  • H03K 17/945 - Proximity switches
  • H04N 25/773 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
  • H10F 30/225 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier working in avalanche mode, e.g. avalanche photodiodes

9.

PHOTODETECTOR

      
Application Number JP2025003795
Publication Number 2025/169963
Status In Force
Filing Date 2025-02-05
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Takahashi, Shingo
  • Soeda, Takaaki

Abstract

A photodetector according to one embodiment of the present disclosure includes semiconductor substrate, a plurality of microlenses and a waveguide section provided between the semiconductor substrate and the plurality of microlenses. The waveguide section includes a multilayered structure arranged in a vertical direction and at least one layer of the multilayered structure is offset with respect to other layers of the multilayered structure in a horizontal direction. Each layer of the multilayered structure includes a color filter and at least one separation section provided between portions of the color filter. The at least one separation section includes an air gap provided therein.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

10.

SENSOR APPARATUS, CONTROL METHOD, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING SYSTEM

      
Application Number 18850071
Status Pending
Filing Date 2023-02-17
First Publication Date 2025-08-14
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Ebihara, Munetake
  • Hibino, Tomokazu
  • Eki, Ryoji
  • Okumura, Hiroyuki

Abstract

It is attempted to prevent undesirable fraudulent use of AI models by fraudulent acts or the like when the AI models are used in a subscription-service-like manner for image-capturing apparatuses having AI functions. It is attempted to prevent undesirable fraudulent use of AI models by fraudulent acts or the like when the AI models are used in a subscription-service-like manner for image-capturing apparatuses having AI functions. A sensor apparatus according to the present technology includes an image-capturing section that captures an image of a subject, an AI processing section that performs AI processing which is a process using an AI model on an image captured by the image-capturing section, and a control section that receives, from an external apparatus, license data representing a use upper limit condition related to the AI model and performs execution control of the AI processing performed by the AI processing section, such that the use upper limit condition is satisfied.

IPC Classes  ?

  • G06F 21/10 - Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
  • H04L 9/08 - Key distribution
  • H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system

11.

PHOTODETECTION DEVICE, DISTANCE MEASURING DEVICE, AND ELECTRONIC DEVICE

      
Application Number 18851149
Status Pending
Filing Date 2023-02-24
First Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takatsuka, Takafumi

Abstract

To provide a photodetection device capable of improving sensitivity characteristics under an environment of high illuminance. To provide a photodetection device capable of improving sensitivity characteristics under an environment of high illuminance. A photodetection device according to the present disclosure includes: a plurality of pixels that counts the number of photons included in incident light; a memory that stores a correction value used to correct a count value by each of the plurality of pixels; and a correction circuit that corrects the count value by using the correction value. In the photodetection device, the plurality of pixels includes: an optical response unit that reacts to the photons; a pulse detection unit that includes an input transistor to which a result of reaction of the optical response unit is input and detects a pulse indicating the result of reaction; a counter that measures the count value on the basis of the pulse; a dynamic separation switch unit that dynamically separates electrical connection between the optical response unit and the pulse detection unit; and an input fixing unit that temporarily fixes an input voltage of the pulse detection unit to a potential at which the input transistor is turned on.

IPC Classes  ?

  • G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves

12.

IMAGING ELEMENT AND ELECTRONIC DEVICE

      
Application Number 18703822
Status Pending
Filing Date 2022-10-24
First Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kasashima, Shunsuke

Abstract

The present technology relates to an imaging element and an electronic device capable of arranging pixels having different sizes efficiently. Provided are a first photoelectric converter that generate a charge corresponding to a light amount, and a second photoelectric converter having a smaller light receiving area than the first photoelectric converter, in which the first photoelectric converter has an L shape in plan view, the second photoelectric converter has a quadrangular shape, and a shape obtained by combining the first photoelectric converter and the second photoelectric converter is a quadrangular shape. The present technology can be applied to, for example, an imaging apparatus that acquires an image with a wide dynamic range by arranging pixels having different light receiving areas and processing signals from each of the pixels.

IPC Classes  ?

  • H04N 25/57 - Control of the dynamic range
  • H04N 25/11 - Arrangement of colour filter arrays [CFA]Filter mosaics

13.

INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING DEVICE, AND INFORMATION PROCESSING METHOD

      
Application Number 19116119
Status Pending
Filing Date 2023-10-24
First Publication Date 2025-08-14
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor Nakahara, Daisaku

Abstract

An information processing system according to an embodiment of the present disclosure includes: a transmission unit that transmits an adjustment pulse signal during a blanking period related to video data; a detection unit that detects that a duty ratio of the adjustment pulse signal transmitted by the transmission unit is not a predetermined value; an adjustment unit that acquires a correction value in such a manner that the duty ratio of the adjustment pulse signal becomes the predetermined value in a case where the detection unit detects that the duty ratio of the adjustment pulse signal is not the predetermined value; and a correction unit that corrects a duty ratio of a pulse signal related to the video data on the basis of the correction value acquired by the adjustment unit.

IPC Classes  ?

  • H04N 17/00 - Diagnosis, testing or measuring for television systems or their details
  • H04N 7/035 - Circuits for the digital non-picture data signal, e.g. for slicing of the data signal, for regeneration of the data-clock signal, for error detection or correction of the data signal

14.

IMAGING DEVICE AND ELECTRONIC DEVICE

      
Application Number 19193800
Status Pending
Filing Date 2025-04-29
First Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamaguchi, Tetsuya

Abstract

Provided are an imaging device and an electronic device configured such that deterioration in imaging performance due to high-angle incident light can be inhibited. The imaging device includes: a semiconductor substrate including a plurality of photoelectric conversion elements; a plurality of color filters that are provided on the semiconductor substrate and face each of the plurality of photoelectric conversion elements; and a partition wall that is provided on the semiconductor substrate and provides separation between one color filter and another color filter adjacent to each other among the plurality of color filters. The partition wall includes a first metal layer, a translucent first partition wall layer that covers a side surface of the first metal layer, and a translucent second partition wall layer located between the first metal layer and the first partition wall layer. A refractive index of the second partition wall layer is larger than a refractive index of the first partition wall layer.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

15.

LIQUID CRYSTAL PANEL AND DISPLAY DEVICE

      
Application Number JP2024044648
Publication Number 2025/169611
Status In Force
Filing Date 2024-12-17
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kozu, Takumi
  • Jinta, Seiichiro
  • Miyazaki, Masafumi

Abstract

A liquid crystal panel according to one embodiment of the present disclosure comprises an effective pixel region and a peripheral region. The peripheral region includes: a peripheral circuit capable of driving a plurality of pixels in the effective pixel region; and a wiring section including a plurality of wires. The peripheral circuit is composed of a plurality of circuit blocks. A plurality of first wires, which constitute a portion of the plurality of wires included in the wiring section, are disposed in a gap between the effective pixel region and at least one circuit block from among the plurality of circuit blocks and extend along the outer edge of the effective pixel region across the entire gap. A plurality of second wires, which are wires other than the plurality of first wires among the plurality of wires included in the wiring section, are disposed at positions opposite the effective pixel region with the plurality of circuit blocks therebetween.

IPC Classes  ?

  • G02F 1/1368 - Active matrix addressed cells in which the switching element is a three-electrode device
  • G02F 1/13 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
  • G02F 1/1345 - Conductors connecting electrodes to cell terminals
  • G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
  • G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
  • G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals

16.

LIGHT DETECTION DEVICE

      
Application Number JP2024003645
Publication Number 2025/169257
Status In Force
Filing Date 2024-02-05
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sekine Ryotaro
  • Nakanishi Masaharu
  • Ito Satoshi
  • Murase Takuro
  • Kato Hiroshi

Abstract

Provided is a light detection device in which a decrease in light absorption in a photoelectric conversion layer can be suppressed. A light detection device according to the present invention comprises a pixel substrate in which at least a first electrode, a photoelectric conversion layer, and a second electrode are laminated in this order from a light incident side, the pixel substrate having at least one pixel, wherein the first electrode has an opening corresponding to the at least one pixel. According to the light detection device according to the present invention, a decrease in light absorption in the photoelectric conversion layer can be suppressed.

IPC Classes  ?

17.

IMAGE PROCESSING DEVICE, DRIVING METHOD, AND RECORDING MEDIUM

      
Application Number JP2025001536
Publication Number 2025/169698
Status In Force
Filing Date 2025-01-20
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Fukuda Yusuke
  • Tatsuzawa Yukiyasu
  • Iwaya Nozomi
  • Kuribayashi Hajime

Abstract

The present technology relates to an image processing device, a driving method, and a recording medium with which it is possible to suppress any increase in power consumption while ensuring detection accuracy. The image processing device comprises: a plurality of image sensors; and a control unit that, on the basis of at least one of imaging conditions and information relating to a surrounding environment, determines a driving mode for the image sensor from among a plurality of driving modes, including a first mode for outputting an image and a second mode for performing only a process relating to detection for each image sensor. When driving in the second mode is performed, the image sensor stops the operation of an image pipeline composed of a processing block that performs a process for generating an image to be outputted. The present technology can be applied to mobile devices.

IPC Classes  ?

  • H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
  • G03B 19/06 - Roll-film cameras adapted to be loaded with more than one film, e.g. with exposure of one or the other at will
  • H04N 23/45 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from two or more image sensors being of different type or operating in different modes, e.g. with a CMOS sensor for moving images in combination with a charge-coupled device [CCD] for still images
  • H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
  • H04N 23/65 - Control of camera operation in relation to power supply
  • H04N 23/67 - Focus control based on electronic image sensor signals
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

18.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2025001499
Publication Number 2025/169695
Status In Force
Filing Date 2025-01-20
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Watanabe, Maho
  • Sato, Naoyuki
  • Sueoka, Ren

Abstract

A light detection device according to one embodiment of the present disclosure comprises: a semiconductor substrate which has a first surface and a second surface that face each other, on which a plurality of pixels are arranged in a two-dimensional array, and in which a plurality of photoelectric conversion parts each for generating a charge corresponding to the amount of received light by photoelectric conversion are formed to be embedded in each pixel; a plurality of microlenses which are each disposed in each pixel on the first surface side of the semiconductor substrate; a first separation part which is formed to be embedded in the semiconductor substrate so as to surround each of the plurality of pixels; a plurality of second separation parts which extend from the first separation part toward the center of the pixel in plan view so as to separate the plurality of photoelectric conversion parts adjacent to each other in the pixel up to the middle; and a plurality of scatterers which are provided on the first surface of the semiconductor substrate on a light collection optical path of the microlens in each pixel.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H10F 39/12 - Image sensors

19.

IMAGING ELEMENT, ELECTRONIC APPARATUS

      
Application Number JP2024044818
Publication Number 2025/169613
Status In Force
Filing Date 2024-12-18
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kasukawa Shuhei

Abstract

[Problem] To provide an imaging element that has an improved FD-boosting function. [Solution] An imaging element 101 includes a plurality of photoelectric conversion units PD, a plurality of floating diffusions FD, a plurality of transfer gates TG that transfer charge that has been generated at the photoelectric conversion units PD to the floating diffusions FD, an FD connection region 50 that is a wiring region that connects the plurality of floating diffusions FD, an FD-boosting region 60 that is a wiring region that is for boosting the FD connection region 50, a plurality of first wiring paths 61 that electrically connect gate signal lines of the plurality of transfer gates TG and the FD-boosting region 60, and a second wiring path 62 that electrically connects the FD-boosting region 60 and a ground GND via a resistance. The FD connection region 50 and the FD-boosting region 60 are formed from an N-type semiconductor region, and the first wiring paths 61 have a PN junction that is formed from a P-type semiconductor region and an N-type semiconductor region.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/50 - Control of the SSIS exposure

20.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2024004427
Publication Number 2025/169431
Status In Force
Filing Date 2024-02-08
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Maruyama Shunsuke

Abstract

[PROBLEM] A correction parameter of crosstalk is accurately acquired. [SOLUTION] A solid-state imaging device according to the present invention includes a light-receiving pixel region, a light-shielding pixel region, and a signal processing circuit. In the light-receiving pixel region, at least two light-receiving pixels among a plurality of light-receiving pixels share a photoelectric conversion region, and the plurality of light-receiving pixels are arranged in a two-dimensional array. Around the light-receiving pixel region, the light-shielding pixel region shares the photoelectric conversion region with the light-receiving pixels belonging to the light-receiving pixel region. Also, a plurality of light-shielding pixels shielded from light are arranged in the light-shielding pixel region. In addition, the light-shielding pixel region includes a defective pixel formed differently from the other light-shielding pixels. The signal processing circuit acquires a parameter for correcting crosstalk in the light-receiving pixel region on the basis of an output from at least one light-shielding pixel arranged around the defective pixel.

IPC Classes  ?

21.

LIGHT DETECTION DEVICE

      
Application Number JP2024045140
Publication Number 2025/169621
Status In Force
Filing Date 2024-12-20
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Matsuo, Junichi
  • Tanaka, Harumi
  • Wakano, Toshifumi
  • Ogawa, Takahisa
  • Kubo, Norihiro

Abstract

A light detection device according to an embodiment of the present invention comprises: a semiconductor layer; a plurality of pixels provided in the semiconductor layer and including a first pixel having a first photoelectric conversion element, a second photoelectric conversion element, a third photoelectric conversion element, and a fourth photoelectric conversion element; and a pixel isolation region. The first pixel includes a first isolation region, a second isolation region, a third isolation region, a fourth isolation region, a floating diffusion provided between the third isolation region and the fourth isolation region, and a first region of a first conductivity type provided between the third isolation region and the floating diffusion.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H10F 39/12 - Image sensors

22.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2024045137
Publication Number 2025/169620
Status In Force
Filing Date 2024-12-20
Publication Date 2025-08-14
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ohri, Hiroyuki

Abstract

A light detection device according to one embodiment of the present disclosure comprises: a first semiconductor layer; a plurality of pixels including a first pixel having a first photoelectric conversion element and a second photoelectric conversion element; and a pixel separation region having a first electrode. The first pixel has a first separation region, a second separation region, and an overflow path provided between the first separation region and the second separation region so as to be in contact with the first photoelectric conversion element and the second photoelectric conversion element. The first separation region has a second electrode provided between the first electrode and the overflow path and comprising a material having a work function different from the work function of the first electrode.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/70 - SSIS architecturesCircuits associated therewith

23.

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

      
Application Number 18291311
Status Pending
Filing Date 2022-02-24
First Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nishida, Yuji
  • Yokoyama, Kazutoshi

Abstract

To improve the mounting reliability of a semiconductor device. The semiconductor device includes: a package body including a semiconductor chip and having a plurality of electrode pads arranged on one surface; and a plurality of bump electrodes that are individually bonded to the plurality of electrode pads, respectively. The plurality of bump electrodes include core bump electrodes including cores and coreless bump electrodes without cores.

IPC Classes  ?

  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H05K 1/02 - Printed circuits Details
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

24.

IMAGING DEVICE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING IMAGING DEVICE

      
Application Number 18692495
Status Pending
Filing Date 2022-03-14
First Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakagawa, Kanae
  • Takaoka, Yuji

Abstract

In an imaging device, the device is reduced in size and height without deteriorating the imaging capability of an imaging element. An imaging device includes: an imaging element having a pixel region and a peripheral region on the front side, the pixel region including multiple pixels, the peripheral region surrounding the pixel region; a rewiring layer that is provided on the front side of the imaging element and has an opening formed through a region including the pixel region; a sealing resin portion that is made of a sealing resin material and is provided to cover a portion around the imaging element and the back side of the rewiring layer; and a connecting portion that is provided on the peripheral region of the imaging element and electrically connects the imaging element and the rewiring layer.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

25.

ENERGY COLLECTION DEVICE AND RECTIFIER CIRCUIT

      
Application Number 18721274
Status Pending
Filing Date 2022-12-26
First Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Yoshino, Yoshitaka
  • Toeda, Yuta

Abstract

An energy collection device that increases output power to be collected is provided. Provided is an energy collection device that includes: an antenna unit having a dipole structure, the antenna unit including a first antenna element that is in contact with an industrial product metal portion or a human body and functions as an antenna, and a second antenna element including a conductor, the antenna unit receiving electric field energy of a radio wave and a quasi-electrostatic field existing in space; a rectifier circuit provided with a switching element that rectifies alternating current (AC) energy output from the antenna unit; and a power storage capacitor configured to store charge output from the rectifier circuit, in which the power storage capacitor has a capacitance value of at least 1 μF or more in order to receive power in a low frequency band.

IPC Classes  ?

  • H02J 50/27 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves characterised by the type of receiving antennas, e.g. rectennas
  • H02J 50/00 - Circuit arrangements or systems for wireless supply or distribution of electric power
  • H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only

26.

SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND DATA PRODUCTION METHOD

      
Application Number 18856737
Status Pending
Filing Date 2023-04-11
First Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ashitani, Tatsuji
  • Kitamura, Takaya

Abstract

A signal processing device according to the present technology includes a frequency data generation section that generates frequency data that is data indicating a frequency of a point in at least a depth direction, on the basis of three-dimensional point cloud data acquired through three-dimensional measurement of a target space, and a data reduction section that executes data reduction processing for the three-dimensional point cloud data on the basis of the frequency data generated by the frequency data generation section.

IPC Classes  ?

27.

ORGANIC SEMICONDUCTOR FILM, PHOTOELECTRIC CONVERSION ELEMENT, AND IMAGING DEVICE

      
Application Number 18707083
Status Pending
Filing Date 2022-11-02
First Publication Date 2025-08-07
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY GROUP CORPORATION (Japan)
Inventor
  • Mogi, Hideaki
  • Kobayashi, Hajime
  • Murata, Masaki
  • Suda, Yosuke
  • Nakagome, Yushiro
  • Sugimura, Chika

Abstract

An organic semiconductor film according to an embodiment of the present disclosure includes an organic semiconductor material having a crystalline property, and the organic semiconductor film has carrier transportability and has three crystalline peaks in a range of a diffraction angle (2θ) of 15° or more and 30° or less in an XRD spectrum.

IPC Classes  ?

  • H10K 30/60 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation in which radiation controls flow of current through the devices, e.g. photoresistors
  • H10K 30/85 - Layers having high electron mobility, e.g. electron-transporting layers or hole-blocking layers
  • H10K 30/86 - Layers having high hole mobility, e.g. hole-transporting layers or electron-blocking layers
  • H10K 39/32 - Organic image sensors
  • H10K 39/38 - Interconnections, e.g. terminals
  • H10K 85/20 - Carbon compounds, e.g. carbon nanotubes or fullerenes
  • H10K 85/60 - Organic compounds having low molecular weight
  • H10K 101/30 - Highest occupied molecular orbital [HOMO], lowest unoccupied molecular orbital [LUMO] or Fermi energy values
  • H10K 101/40 - Interrelation of parameters between multiple constituent active layers or sublayers, e.g. HOMO values in adjacent layers

28.

MEASUREMENT DEVICE AND SEMICONDUCTOR CHIP

      
Application Number JP2025000856
Publication Number 2025/164284
Status In Force
Filing Date 2025-01-14
Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kondo Fumitaka
  • Maruyama Hirofumi
  • Nakajima Tomonori

Abstract

The present disclosure relates to a measurement device capable of improving the accuracy of measurement results, and a semiconductor chip. Provided is a measurement device comprising: a transmission circuit that transmits a high-frequency signal via a transmission antenna; a reception circuit that receives, via a reception antenna, the high-frequency signal transmitted from the transmission antenna and passed through or reflected by a specimen; a signal processing circuit that is connected to the transmission circuit and the reception circuit, and analyzes propagation characteristics of the high-frequency signal; and an impedance adjustment circuit that is connected to at least one of the transmission antenna and the reception antenna, and adjusts impedance. For example, the present disclosure can be applied to VNA or the like.

IPC Classes  ?

  • A61B 5/053 - Measuring electrical impedance or conductance of a portion of the body
  • A61B 5/11 - Measuring movement of the entire body or parts thereof, e.g. head or hand tremor or mobility of a limb
  • A61B 5/145 - Measuring characteristics of blood in vivo, e.g. gas concentration or pH-value
  • A61B 5/0507 - Detecting, measuring or recording for diagnosis by means of electric currents or magnetic fieldsMeasuring using microwaves or radio waves using microwaves or terahertz waves

29.

LIGHT SOURCE DRIVING DEVICE, LIGHT-EMITTING DEVICE, AND RANGING SYSTEM

      
Application Number JP2025001463
Publication Number 2025/164386
Status In Force
Filing Date 2025-01-17
Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Noda Raika
  • Masuda Takashi
  • Suzuki Daisuke

Abstract

[Problem] To prevent deterioration of light-emitting characteristics of a light-emitting element. [Solution] This light source driving device includes: a plurality of first transistors that are respectively provided for a plurality of light-emitting elements and that generate a current which flows in the corresponding light-emitting elements; and a plurality of second transistors arranged along a first direction with respect to the plurality of first transistors and that perform switching control with regard to whether or not to generate the current in the corresponding first transistors. The corresponding first transistors and the corresponding second transistors are arranged according to the pitch of two or more of the light-emitting elements arranged in a second direction intersecting the first direction.

IPC Classes  ?

  • H01S 5/042 - Electrical excitation
  • G01S 7/484 - Transmitters
  • H01S 5/0239 - Combinations of electrical or optical elements
  • H01S 5/42 - Arrays of surface emitting lasers
  • H10H 20/00 - Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]

30.

IN-CABIN MONITORING CIRCUITRY AND IN-CABIN MONITORING METHOD

      
Application Number EP2025051669
Publication Number 2025/162812
Status In Force
Filing Date 2025-01-23
Publication Date 2025-08-07
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY DEPTHSENSING SOLUTIONS SA/NV (Belgium)
Inventor
  • Cambareri, Valerio
  • Zlokolica, Vladimir
  • Durigneux, Antoine

Abstract

The present disclosure generally pertains to in-cabin monitoring circuitry for monitoring an in-cabin environment of a vehicle, the circuitry being configured to: obtain infrared sensor data; and generate monocular depth data with a machine-learned model, wherein the machine-learned model has depth data as ground truth and uses the obtained infrared sensor data as input.

IPC Classes  ?

  • G06V 10/143 - Sensing or illuminating at different wavelengths
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • G06V 20/59 - Context or environment of the image inside of a vehicle, e.g. relating to seat occupancy, driver state or inner lighting conditions

31.

SEMICONDUCTOR PACKAGE AND MODULE

      
Application Number 18710284
Status Pending
Filing Date 2022-09-30
First Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ochiai, Yasuhiro

Abstract

To improve the measurement accuracy of a sensor in a semiconductor package provided with the sensor. A semiconductor package includes a laminated chip and a measurement unit. In the semiconductor package including the laminated chip and the measurement unit, the laminated chip measures a temperature and estimates a degree of warpage of the laminated chip on the basis of the temperature. Moreover, in the semiconductor package, the measurement unit performs processing of measuring a predetermined physical quantity and generating measurement information and processing of correcting the measurement information on the basis of the degree of warpage.

IPC Classes  ?

  • G01B 21/30 - Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring roughness or irregularity of surfaces
  • G01P 1/00 - Details of instruments
  • G01P 15/02 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces

32.

ENERGY HARVESTER AND CHARGING APPARATUS

      
Application Number 18719458
Status Pending
Filing Date 2022-12-21
First Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yoshino, Yoshitaka

Abstract

An energy harvester according to an embodiment of the present technology includes a coil section, a maintaining portion, and a rectifier. The coil section includes a core that is made of a magnetic material, and a wire rod that is wound around the core. The maintaining portion maintains the coil section on a surface of a target that includes a metallic body or a human body, such that an axis of the coil section intersects the surface of the target. The rectifier rectifies output from the coil section.

IPC Classes  ?

  • H02J 50/00 - Circuit arrangements or systems for wireless supply or distribution of electric power
  • H01M 10/44 - Methods for charging or discharging
  • H01M 10/46 - Accumulators structurally combined with charging apparatus
  • H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
  • H02J 50/27 - Circuit arrangements or systems for wireless supply or distribution of electric power using microwaves or radio frequency waves characterised by the type of receiving antennas, e.g. rectennas
  • H02J 50/40 - Circuit arrangements or systems for wireless supply or distribution of electric power using two or more transmitting or receiving devices

33.

GLASS CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF AND IMAGING DEVICE

      
Application Number 18849285
Status Pending
Filing Date 2023-03-14
First Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Mitarai, Shun

Abstract

Provided is a glass circuit board and a manufacturing method thereof and an imaging device that achieve higher reliability. A glass circuit board including: a glass substrate serving as a core material including a first side, a second side located opposite from the first side, an outer end face located between the first side and the second side, and a through hole penetrating between the first side and the second side; an insulating first resin layer covering the first side; an insulating second resin layer covering the second side; a third resin layer that covers the inner surface of the through hole and is continuous with the first resin layer and the second resin layer; a fourth resin layer that covers the outer end face and is continuous with the first resin layer and the second resin layer; a first core wiring provided on the first side with the first resin layer interposed between the first core wiring and the first side; a second core wiring provided on the second side with the second resin layer interposed between the second core wiring and the second side; and a feed-through wiring provided on the inner surface of the through hole with the third resin layer interposed between the feed-through wiring and the inner surface.

IPC Classes  ?

  • H05K 1/02 - Printed circuits Details
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H05K 1/03 - Use of materials for the substrate
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
  • H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/95 - Assemblies of multiple devices comprising at least one integrated device covered by group , e.g. comprising integrated image sensors

34.

STORAGE DEVICE, ELECTRONIC APPARATUS, AND STORAGE DEVICE CONTROL METHOD

      
Application Number 18856115
Status Pending
Filing Date 2022-09-29
First Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Higo, Yutaka
  • Sakai, Lui
  • Hiraga, Keizo
  • Hosomi, Masanori

Abstract

A memory system (1), which is an example of a storage device according to an aspect of the present disclosure, includes: a magnetoresistive element (120) whose magnetization direction is variable between a first state and a second state by voltage application; a selection element (110) connected to the magnetoresistive element (120); and a write circuit (70) which is an example of a write unit that switchably applies, to the magnetoresistive element (120), a first write voltage for setting the magnetization direction of the magnetoresistive element (120) to the first state and a second write voltage for setting the magnetization direction of the magnetoresistive element (120) to the second state.

IPC Classes  ?

  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • H10N 50/10 - Magnetoresistive devices
  • H10N 50/85 - Materials of the active region

35.

LIGHT DETECTION DEVICE, OPTICAL ELEMENT, AND ELECTRONIC DEVICE

      
Application Number JP2024043928
Publication Number 2025/164103
Status In Force
Filing Date 2024-12-12
Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Wada, Kohei
  • Hasegawa, Kenta

Abstract

A light detection device according to one embodiment of the present disclosure comprises: a first layer that includes a first material layer to which a first structure having a columnar shape is provided; and a photoelectric conversion element that carries out photoelectric conversion of light which is incident via the first layer. The first structure includes a first member that is provided to the first material layer, and a second member that is provided inside the first member and that has a refractive index which is different from the refractive index of the first member.

IPC Classes  ?

  • H10F 39/12 - Image sensors
  • G02B 5/18 - Diffracting gratings
  • G02B 5/20 - Filters
  • H04N 25/13 - Arrangement of colour filter arrays [CFA]Filter mosaics characterised by the spectral characteristics of the filter elements
  • H04N 25/70 - SSIS architecturesCircuits associated therewith

36.

LIGHT-SOURCE-DRIVING DEVICE, LIGHT-EMITTING DEVICE, AND DISTANCE-MEASURING SYSTEM

      
Application Number JP2025001272
Publication Number 2025/164349
Status In Force
Filing Date 2025-01-17
Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Noda Raika
  • Masuda Takashi
  • Suzuki Daisuke
  • Shinoda Ryota

Abstract

[Problem] To make it possible to suppress any deviation of light emission timing. [Solution] A light-source-driving device according to the present invention comprises: a first transistor for generating an electric current to be channeled through a light-emitting element; a second transistor for switching and controlling whether to allow the first transistor to generate the electric current; a third transistor for stopping emission of light by the light-emitting element; and a fourth transistor for switching and controlling whether to allow the third transistor to stop the emission of light by the light-emitting element.

IPC Classes  ?

  • H01S 5/042 - Electrical excitation
  • G01S 7/484 - Transmitters
  • H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
  • H10H 20/00 - Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]

37.

RANGING DEVICE AND RANGING METHOD

      
Application Number JP2025002012
Publication Number 2025/164491
Status In Force
Filing Date 2025-01-23
Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hanzawa, Katsuhiko

Abstract

A ranging device according to the present invention comprises a light reception unit and a conversion unit. The light reception unit receives, as return light, reference light reflected by an object. The conversion unit switches, in accordance with the distance to the object or the light intensity of the return light, a detection method for light reception timing of the return light between an edge detection method and a level detection method.

IPC Classes  ?

  • G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak

38.

INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD

      
Application Number JP2025002672
Publication Number 2025/164633
Status In Force
Filing Date 2025-01-29
Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kitano, Katsuhiko

Abstract

Provided is an information processing device including circuitry configured to identify from image data based on a first captured image a subportion area that contains a recognition target object, the recognition target object containing features, and determine the features of the recognition target object based on image data of a plurality of captured images that respectively include the recognition target object, and each captured under a different condition, the plurality of captured images at least include images other than the first captured image.

IPC Classes  ?

  • H04N 23/60 - Control of cameras or camera modules
  • G06T 7/00 - Image analysis
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • H04N 23/54 - Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils

39.

PROGRAM, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING APPARATUS

      
Application Number JP2025002770
Publication Number 2025/164662
Status In Force
Filing Date 2025-01-29
Publication Date 2025-08-07
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Doi, Hiromasa

Abstract

To provide a program, an information processing method, and an information processing apparatus capable of acquiring a situation of a game. A program causes a computer to execute an information processing method including: detecting a position of a card in an image that is obtained by photographing a range in which game cards are to be disposed by a camera; generating a cropped image by cropping a region of the card from the image on the basis of the position of the card; and acquiring a situation of the game on the basis of the cropped image.

IPC Classes  ?

  • A63F 13/213 - Input arrangements for video game devices characterised by their sensors, purposes or types comprising photodetecting means, e.g. cameras, photodiodes or infrared cells
  • A63F 13/655 - Generating or modifying game content before or while executing the game program, e.g. authoring tools specially adapted for game development or game-integrated level editor automatically by game devices or servers from real world data, e.g. measurement in live racing competition by importing photos, e.g. of the player
  • G06V 20/00 - ScenesScene-specific elements
  • A63F 1/00 - Card games

40.

SYSTEM AND METHOD FOR 3D-IMAGING USING RECONFIGURABLE TOF SENSOR AND PERIPHERAL SENSOR

      
Application Number EP2025051971
Publication Number 2025/162875
Status In Force
Filing Date 2025-01-27
Publication Date 2025-08-07
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY EUROPE B.V. (United Kingdom)
Inventor
  • Perenzoni, Matteo
  • Jeong, Ji Yong
  • Giorgetti, Daniele
  • Semel, Lavi
  • Lusky, Itay
  • Nosko, Pavel
  • Nakamura, Masashi
  • Stoppa, David

Abstract

A system, wherein the system includes: a transmitter configured to illuminate a scene by emitting modulated light; a receiver configured to detect modulated light reflected in the scene to generate time-of- flight data; at least one peripheral sensor, each being configured to generate sensor data; a processor unit configured to: run an application that uses the time-of-flight data and the sensor data, and control, based on at least one of the time-of-flight data and the sensor data, a configuration of the transmitter and the receiver depending on the application.

IPC Classes  ?

  • G01S 7/48 - Details of systems according to groups , , of systems according to group
  • G01S 7/497 - Means for monitoring or calibrating
  • G01S 17/08 - Systems determining position data of a target for measuring distance only
  • G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer

41.

TIME-OF-FLIGHT CIRCUITRY, VEHICLE SAFETY SYSTEM, AND METHODS

      
Application Number EP2025052288
Publication Number 2025/163012
Status In Force
Filing Date 2025-01-29
Publication Date 2025-08-07
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY DEPTHSENSING SOLUTIONS SA/NV (Belgium)
Inventor
  • Zlokolica, Vladimir
  • Kopfer, Jan Martin
  • Cambareri, Valerio
  • Arora, Varun
  • Van Der Noot, Nicolas
  • Oba, Eiji
  • Elg, Johannes

Abstract

The present disclosure generally pertains to Time-of-flight circuitry for a vehicle safety system, the circuitry being configured to: obtain time-of-flight data indicative of an occupant of a vehicle; generate, based on the time-of-flight data, body feature information regarding the occupant; and provide the body feature information to a safety function of the vehicle safety system.

IPC Classes  ?

  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
  • G01S 7/48 - Details of systems according to groups , , of systems according to group
  • B60R 21/015 - Electrical circuits for triggering safety arrangements in case of vehicle accidents or impending vehicle accidents including means for detecting the presence or position of passengers, passenger seats or child seats, e.g. for disabling triggering
  • G01S 7/4865 - Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
  • G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
  • G01S 17/931 - Lidar systems, specially adapted for specific applications for anti-collision purposes of land vehicles

42.

IMAGING CIRCUITRY AND METHOD FOR OPERATING AN IMAGING CIRCUITRY

      
Application Number EP2025052317
Publication Number 2025/163024
Status In Force
Filing Date 2025-01-30
Publication Date 2025-08-07
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY DEPTHSENSING SOLUTIONS SA/NV (Belgium)
Inventor Bulteel, Olivier

Abstract

The present disclosure generally pertains to imaging circuitry including: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transfer gate coupled between the photodiode and the global shutter memory node; and a second transfer gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including analog to digital conversion circuitry.

IPC Classes  ?

  • H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
  • H04N 25/532 - Control of the integration time by controlling global shutters in CMOS SSIS
  • H04N 25/531 - Control of the integration time by controlling rolling shutters in CMOS SSIS
  • H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion

43.

DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND PROGRAM

      
Application Number 18853590
Status Pending
Filing Date 2023-05-01
First Publication Date 2025-07-31
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Nagao, Akihiko
  • Mahara, Kumiko

Abstract

The present technology relates to a data processing apparatus, a data processing method, and a program that enable communication with improved security. The present technology relates to a data processing apparatus, a data processing method, and a program that enable communication with improved security. There are provided a register including, as an address region, a setting region that stores setting information transmitted from a host, a security data region that stores security data for the setting information, and a communication information region that stores communication information with the host, and a communication unit that performs register communication between the host and the register, in which communication mode information indicating at least one communication mode of the register communication is written in the communication information region in a case where the communication mode information is received from the host, and a register definition for a same space of the register is set for each of the communication modes based on the communication mode information written in the communication information region. The present technology can be applied to an image sensor and a host that controls the image sensor.

IPC Classes  ?

  • H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
  • H04N 23/661 - Transmitting camera control signals through networks, e.g. control via the Internet

44.

BINNING IN HYBRID PIXEL STRUCTURE OF IMAGE PIXELS AND EVENT VISION SENSOR (EVS) PIXELS

      
Application Number 18854780
Status Pending
Filing Date 2023-03-22
First Publication Date 2025-07-31
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Mostafalu, Pooria
  • Brady, Frederick T.
  • Han, Sungin
  • Mi, Hongyi

Abstract

Binning in a hybrid pixel structure of image pixels and event vision sensor (EVS) pixels. In one embodiment, the imaging sensor includes a pixel array including a plurality of pixel circuits and a plurality of binning transistors. A first portion of the plurality of pixel circuits individually includes an intensity photodiode. A second portion of the plurality of pixel circuits individually includes an event vision sensor (EVS) photodiode. The plurality of binning transistors is configured to bin together at least one of the first portion or the second portion.

IPC Classes  ?

  • H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

45.

SOLID-STATE IMAGE SENSOR

      
Application Number 19181600
Status Pending
Filing Date 2025-04-17
First Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Sato, Yusuke

Abstract

A solid-state image sensor includes a plurality of imaging element blocks 10 each configured from a plurality of imaging elements. Each of the imaging elements includes a first electrode, a charge accumulating electrode arranged in a spaced relation from the first electrode, a photoelectric conversion portion contacting with the first electrode and formed above the charge accumulating electrode with an insulating layer interposed therebetween, and a second electrode formed on the photoelectric conversion portion. The first electrode and the charge accumulating electrode are provided on an interlayer insulating layer, and the first electrode is connected to a connection portion provided in the interlayer insulating layer.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H04N 23/10 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from different wavelengths
  • H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10K 19/20 - Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group comprising components having an active region that includes an inorganic semiconductor
  • H10K 30/30 - Organic devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation comprising bulk heterojunctions, e.g. interpenetrating networks of donor and acceptor material domains
  • H10K 30/82 - Transparent electrodes, e.g. indium tin oxide [ITO] electrodes
  • H10K 39/32 - Organic image sensors

46.

LIGHT-EMITTING ELEMENT AND DISPLAY DEVICE

      
Application Number 19182137
Status Pending
Filing Date 2025-04-17
First Publication Date 2025-07-31
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Nishikawa, Tomotaka
  • Hikichi, Kunihiko
  • Sakai, Yuuki
  • Shimayama, Tsutomu

Abstract

A light-emitting element and a display device capable of improving the light emission property are provided. Each of a plurality of anode electrodes (11) is provided for a corresponding pixel. The pixel-isolating insulation film (12) has an opening (120) exposing corresponding one of the plurality of anode electrodes (11) to outside, and has an eave (123B) in the middle of a thickness direction of an inner wall of the opening (120). An organic layer (13) includes a CGL (132) cut by the eave (123B) of the pixel-isolating insulation film (12), and covers the opening (120). A cathode electrode (14) is disposed on a surface of the organic layer (13), the surface being a surface on the opposite side of the anode electrode (11).

IPC Classes  ?

47.

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE

      
Application Number JP2024042302
Publication Number 2025/158775
Status In Force
Filing Date 2024-11-29
Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Seki, Ayaka
  • Kishigami, Yuuji

Abstract

The present invention alleviates stress in a semiconductor package in which a chip is connected to a substrate by wire bonding. A semiconductor package includes a substrate, a semiconductor chip, a sealing material, an adhesive layer, and a transparent member. In the semiconductor package, the semiconductor chip is electrically connected to the substrate by a wire. The sealing material seals the wire. Further, in the semiconductor package, the thickness of the adhesive layer is not less than 1/10 of the thickness of the substrate. Furthermore, the transparent member is bonded to the sealing material by the adhesive layer.

IPC Classes  ?

  • H10F 39/12 - Image sensors
  • H01L 23/02 - ContainersSeals
  • H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
  • H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings

48.

OPTICAL DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2024042423
Publication Number 2025/158778
Status In Force
Filing Date 2024-11-29
Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Takase Hiroaki

Abstract

Provided is an optical detection device capable of suppressing a reduction in sensitivity due to thinning of a semiconductor substrate. Specifically, the present invention is configured to comprise: a semiconductor substrate on which a plurality of pixels each having a photoelectric conversion unit are disposed; and a wiring layer that is laminated on the surface of the semiconductor substrate opposite to a light-receiving surface. The wiring layer is disposed so as to overlap at least some photoelectric conversion units among the plurality of photoelectric conversion units in a lamination direction in which the semiconductor substrate and the wiring layer are laminated, and has a reflective layer for reflecting the light passing through the semiconductor substrate to the semiconductor substrate side. The reflective layer is configured to form a reflective metasurface including a plurality of microstructures.

IPC Classes  ?

  • H10F 39/12 - Image sensors
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

49.

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2025000119
Publication Number 2025/158884
Status In Force
Filing Date 2025-01-07
Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ohri Hiroyuki

Abstract

The present invention relates to a semiconductor device and an electronic apparatus capable of miniaturizing pixels. This semiconductor device includes first and second transistors formed on an upper part of a semiconductor substrate and connected in series. Channels of the first and second transistors are formed above the semiconductor substrate. A source of the first transistor and a drain of the second transistor are formed in one semiconductor region above the semiconductor substrate. The technology disclosed herein can be applied to, for example, a light detection device or the like that photoelectrically converts incident light and outputs a signal corresponding to the amount of received light.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H10D 30/60 - Insulated-gate field-effect transistors [IGFET]
  • H10D 30/67 - Thin-film transistors [TFT]

50.

LIGHT-EMITTING DEVICE

      
Application Number JP2025000923
Publication Number 2025/158963
Status In Force
Filing Date 2025-01-15
Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Fujimaki, Hiroshi
  • Shimatsu, Tomohiko

Abstract

Provided is a light-emitting device comprising: a substrate; a pixel region which is formed by arranging a plurality of light-emitting elements in a matrix configuration at the centre of the substrate; a peripheral part which is provided to the substrate so as to surround the pixel region; a protective film which is laminated on the pixel region and on the peripheral part; a groove which is provided to a portion of the protective film located above the peripheral part, and which passes through at least part of the protective film along the film thickness direction of the protective film; and one or a plurality of light-blocking parts which are provided inside the groove and block the propagation of light from the light-emitting elements.

IPC Classes  ?

  • H10K 50/86 - Arrangements for improving contrast, e.g. preventing reflection of ambient light
  • G02B 5/20 - Filters
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • H05B 33/14 - Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material
  • H10K 50/84 - PassivationContainersEncapsulations
  • H10K 50/842 - Containers
  • H10K 59/32 - Stacked devices having two or more layers, each emitting at different wavelengths
  • H10K 59/38 - Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]
  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/131 - Interconnections, e.g. wiring lines or terminals

51.

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE

      
Application Number JP2025001721
Publication Number 2025/159072
Status In Force
Filing Date 2025-01-21
Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Moriyama, Kenji
  • Kagotani, Hiroshi
  • Takeya, Yukari
  • Mizuguchi, Tetsuya
  • Haneda, Masaki
  • Tanaka, Hiroshi
  • Tanaka, Keishi
  • Tozawa, Katsunori
  • Koyanagi, Shoya
  • Furuhashi, Takahisa

Abstract

This invention improves reliability of an electrode formed in an opening part. This electronic device is provided with: an opening part in which the inner surface is insulated; and an electrode formed on the inner surface of the opening part. The electrode is provided with a metal lamination part in which metals with differing compositions or structures are laminated on the bottom surface of the opening part. The metal lamination part in which the metals are laminated may include a sputtering layer, an electroless plating layer laminated on the sputtering layer, and an electrolytic plating layer laminated on the electroless plating layer. The metal lamination part in which the metals are laminated may be positioned on the bottom surface of the opening part and on the side surface of the opening part.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

52.

MUSIC PRODUCTION DEVICE AND METHOD FOR OPERATING A MUSIC PRODUCTION DEVICE

      
Application Number EP2025050873
Publication Number 2025/157639
Status In Force
Filing Date 2025-01-15
Publication Date 2025-07-31
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY EUROPE B. V. (United Kingdom)
Inventor
  • Parret, Vincent
  • Cavinato, Valentina
  • Incesu, Yalcin

Abstract

A music production device (100) comprises a user interface (110) that is configured to receive user inputs from a user and to convert the user inputs into digital signals, and a control unit (150) that is configured to receive the digital signals and to generate music data based on the received digital signals The user interface (110) comprises at least one vision based tactile sensor (120) that comprises a transparent gel (130) on or in which markers (135) are placed and an image sensor (140) that observes the markers (135) through the transparent gel (130). User inputs are received by receiving a pressing action of the user on the transparent gel (130) that deforms the gel such that positions of the markers (135) change. During the pressing action the image sensor (140) is configured to capture image data of the change of positions of the markers (135), which image data allow deduction of physical parameters of the pressing action. The digital signals are generated from the image data obtained during the pressing action such as to represent the physical parameters of the pressing action. The music data are generated according to the physical parameters of the pressing action represented by the digital signals.

IPC Classes  ?

  • G06F 3/048 - Interaction techniques based on graphical user interfaces [GUI]
  • G10H 1/055 - Means for controlling the tone frequencies, e.g. attack or decayMeans for producing special musical effects, e.g. vibratos or glissandos by additional modulation during execution only by switches with variable impedance elements
  • G01L 1/04 - Measuring force or stress, in general by measuring elastic deformation of gauges, e.g. of springs
  • G01L 5/00 - Apparatus for, or methods of, measuring force, work, mechanical power, or torque, specially adapted for specific purposes

53.

SENSOR DEVICE AND METHOD FOR OPERATING A SENSOR DEVICE FOR CAPTURING A HYPERSPECTRAL IMAGE

      
Application Number EP2025051456
Publication Number 2025/157805
Status In Force
Filing Date 2025-01-22
Publication Date 2025-07-31
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY ADVANCED VISUAL SENSING AG (Switzerland)
Inventor
  • Piro, Nicolas
  • Cosentino, Costantino

Abstract

A sensor device (100) for capturing a hyperspectral image of an object (200) comprises a localization unit (110) that is configured to determine a position and an orientation of the sensor device (100) with respect to the object (200), a light emitting unit (120) that is configured to emit light of a predetermined wavelength band to the object (200), an image capturing unit (130) comprising an optical system (131) and an image sensor (135) having a plurality of pixels (136), which optical system (131) is configured to project reflected light that has been reflected from the object (200) onto the image sensor (135) such that specific wavelength of the reflected light are projected to specific, corresponding locations on the image sensor (135), the specific wavelength bands being part of the predetermined wavelength band, and which image sensor (135) is configured to capture a spectral image of a scene that contains the object (200) by detecting for each pixel (136) the intensity of light received at said pixel (136), and a control unit (140) that is configured to generate a hyperspectral image of the object (200), which hyperspectral image indicates for each region of the object (200) the intensity of light in the specific wavelength bands, based on a plurality of spectral images of the object (200) captured from different points in space and the positions and orientations of the sensor device (100) with respect to the object (200) during capturing of said spectral images.

IPC Classes  ?

  • G01J 3/02 - SpectrometrySpectrophotometryMonochromatorsMeasuring colours Details
  • G01J 3/06 - Scanning arrangements
  • G01J 3/10 - Arrangements of light sources specially adapted for spectrometry or colorimetry
  • G01J 3/14 - Generating the spectrumMonochromators using refracting elements, e.g. prism
  • G01J 3/28 - Investigating the spectrum
  • G01J 3/51 - Measurement of colourColour measuring devices, e.g. colorimeters using electric radiation detectors using colour filters
  • G01J 3/18 - Generating the spectrumMonochromators using diffraction elements, e.g. grating

54.

IMAGING DEVICE

      
Application Number 18702264
Status Pending
Filing Date 2022-09-15
First Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nakamoto, Yuta

Abstract

There are provided: a pixel separation section including an insulating film and extending in first and second directions between pixels and extending from a first surface of a semiconductor substrate toward a second surface; pixel transistors provided on the second surface side, arranged in the first direction to overlap the pixel separation section extending in the first direction in plan view, constituting a readout circuit that outputs a pixel signal based on electric charge outputted from each of light-receiving pixels; and an element separation section including an insulating film formed to be embedded on the second surface side, extending in the first direction along the pixel transistors arranged in the first direction, being divided at at least a portion of an intersection of the pixel separation section extending in the first and second directions in plan view, and electrically separating the pixel transistors and light-receiving sections from each other.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

55.

DISPLAY DEVICE

      
Application Number 18992372
Status Pending
Filing Date 2023-07-11
First Publication Date 2025-07-31
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Tanaka, Koji
  • Yumoto, Shintaro
  • Kawamura, Masahiro

Abstract

A display device includes: a light emitting element layer provided on a base; and a lens layer provided on a side opposite to the base across the light emitting element layer, the lens layer including a plurality of main lenses arranged in an array in a plane direction of the lens layer and an auxiliary lens provided on a side opposite to the light emitting element layer across the array of the plurality of main lenses, the auxiliary lens being located between adjacent main lenses among the plurality of main lenses in a plan view of the lens layer.

IPC Classes  ?

56.

IMAGE PROCESSING SYSTEM, IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM

      
Application Number JP2024042313
Publication Number 2025/158776
Status In Force
Filing Date 2024-11-29
Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kawase, Satomi
  • Miyake, Toshihisa
  • Iwanami, Ren
  • Hiraoka, Kotoko

Abstract

The present invention improves image quality in an image processing system for processing a color image captured using a polarization filter. This image processing system includes a false color amount calculation unit and a noise reduction strength calculation unit. In the image processing system, the false color amount calculation unit calculates a false color amount after polarization signal processing, which is polarization component-related processing. On the basis of the false color amount, the noise reduction strength calculation unit calculates, as a noise reduction strength, the degree of noise reduction processing for a color image captured using a polarization filter.

IPC Classes  ?

  • H04N 23/60 - Control of cameras or camera modules
  • G06T 1/00 - General purpose image data processing
  • G06T 5/70 - DenoisingSmoothing
  • H04N 23/55 - Optical parts specially adapted for electronic image sensorsMounting thereof
  • H04N 25/60 - Noise processing, e.g. detecting, correcting, reducing or removing noise

57.

IMAGING DEVICE

      
Application Number JP2024042390
Publication Number 2025/158777
Status In Force
Filing Date 2024-11-29
Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nakamoto, Yuta

Abstract

The present invention makes it possible to transfer charge from a photoelectric conversion unit while eliminating a trade-off relationship with pinning of an insulating layer. This imaging device is provided with pixels separated by a pixel separation region. Each pixel comprises a photoelectric conversion unit, a transfer transistor that transfers charge accumulated in the photoelectric conversion unit to a floating diffusion, an amplification transistor that outputs a signal corresponding to the potential of the floating diffusion, a selection transistor that selects an output of the amplification transistor, a reset transistor that resets the floating diffusion, an overflow control transistor that can set a path for charge overflowing from the photoelectric conversion unit, an element separation region that separates the transfer transistor from the amplification transistor, the selection transistor, and the reset transistor, and a P-type impurity diffusion layer that separates the transfer transistor from the overflow control transistor.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/63 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion

58.

SEMICONDUCTOR ELEMENT, DISPLAY DEVICE, AND ELECTRONIC APPARATUS

      
Application Number JP2025001740
Publication Number 2025/159078
Status In Force
Filing Date 2025-01-21
Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nishikawa, Hiroshi

Abstract

Provided is a semiconductor element that can be miniaturized. This semiconductor element comprises: an oxide semiconductor layer having an outer-circumferential lateral surface; a first conductive part that is connected to the outer-circumferential lateral surface and that is disposed extending from the outer-circumferential lateral surface in a first thickness direction of the oxide semiconductor layer; and a first electrode that is connected to the first conductive part.

IPC Classes  ?

  • H10D 30/67 - Thin-film transistors [TFT]
  • G09F 9/30 - Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
  • H10D 30/01 - Manufacture or treatment
  • H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]

59.

SETTLING ACCELERATION CIRCUIT AND IMAGE SENSOR READING CIRCUIT INCLUDING THE SAME

      
Application Number JP2025002176
Publication Number 2025/159176
Status In Force
Filing Date 2025-01-24
Publication Date 2025-07-31
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Fujimoto Yoshihisa
  • Tokunaga Yusuke

Abstract

To improve performance such as RC time constant reduction and slew rate improvement regarding analog signal settling. A settling acceleration circuit includes a first transistor having an output terminal where a capacitive component exists, a gate electrode being connected to the output terminal; a first capacitor connected to a source terminal of the first transistor; a first constant current source connected to the source terminal of the first transistor; a current mirror circuit that amplifies a current from a drain terminal of the first transistor to output the amplified current to an output node; a second constant current source connected to the output node; and a first switch disposed between the output terminal and the output node. Then, after an end of the settling acceleration period in which the first switch is made conductive to accelerate the settling of the voltage of the output terminal, the first switch is cut off, and the reading circuit connected to the output terminal reads the voltage of the output terminal. The present technology can be applied to, for example, an imaging element such as a CMOS image sensor.

IPC Classes  ?

  • H03K 17/284 - Modifications for introducing a time delay before switching in field-effect transistor switches
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

60.

HYDROPHILIC FILM, ANTIREFLECTIVE FILM, CAMERA, AND FILM FORMATION METHOD

      
Application Number JP2025001488
Publication Number 2025/159034
Status In Force
Filing Date 2025-01-20
Publication Date 2025-07-31
Owner
  • SONY GROUP CORPORATION (Japan)
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Sudo, Go
  • Onoda, Yoshitomo
  • Shimoda, Kazuhito
  • Nakagawa, Yasuro
  • Takeda, Ayari
  • Tsutsui, Yoshikazu

Abstract

233 are compounded, wherein M is a metal element. In the hydrophilic film according to the present technology, polarization occurs between oxygen atoms and atoms of the metal element, and the atoms of the metal element are negatively charged.

IPC Classes  ?

61.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM

      
Application Number 18698112
Status Pending
Filing Date 2022-09-29
First Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Miyaoka, Hirosada

Abstract

The present disclosure relates to an information processing device, an information processing method, and a program that achieve highly accurate simulation in accordance with a real running environment using a millimeter-wave radar. A radio wave interference model for a radar device mounted on a vehicle in a simulation environment is stored, the stored radio wave interference model is selected on the basis of a simulation scenario, and output data representing a result of perception of an object with the radar device is generated on the basis of the selected radio wave interference model. The present disclosure is applicable to an automated driving simulator.

IPC Classes  ?

  • G01S 7/40 - Means for monitoring or calibrating
  • G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles

62.

SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

      
Application Number 18703667
Status Pending
Filing Date 2022-09-16
First Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yuga, Yui

Abstract

In order to regulate the characteristics of each of a plurality of individualized semiconductor elements, the present technique provides a semiconductor device including a first semiconductor element and a plurality of second semiconductor elements with a circuit configured to process a signal from the first semiconductor element, wherein the first semiconductor element and each of the plurality of second semiconductor elements are stacked and arranged; and a first film formed on at least one of the plurality of second semiconductor elements is different in configuration from a second film formed on another of the second semiconductor elements.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H10F 39/12 - Image sensors
  • H10F 77/30 - Coatings

63.

SOLID-STATE IMAGING DEVICE AND ELECTRONIC DEVICE

      
Application Number 18852635
Status Pending
Filing Date 2023-04-10
First Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakamura, Takashi
  • Higashi, Akimi

Abstract

The present disclosure relates to a solid-state imaging device and an electronic device, which are capable of achieving a high-speed communication interface. The solid-state imaging device includes a pixel substrate on which a pixel is formed, and a control substrate, the pixel substrate and the control substrate being stacked. The pixel substrate includes a pad serving as a contact point with an external device. The control substrate includes a signal pad wiring connected to the pad, a shield wiring disposed around the signal pad wiring, and a high-resistance element connected to the shield wiring. The present disclosure is applicable to the solid-state imaging device and other devices, for example.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

64.

IMAGING DEVICE

      
Application Number 19172034
Status Pending
Filing Date 2025-04-07
First Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamashita, Hirofumi

Abstract

An imaging device includes a first section including a first semiconductor substrate, at least one first photoelectric conversion region, a first floating diffusion, a first bonding portion, a first wiring electrically connected between the first floating diffusion and the first bonding portion, at least one second photoelectric conversion region, a second floating diffusion coupled to the at least one second photoelectric conversion region, a second bonding portion, a second wiring electrically connected between the second floating diffusion and the second bonding portion, a first region coupled to a node that receives a reference voltage, and a third wiring coupled to the first region at a location that is between the first wiring and the second wiring. The imaging device includes a second section bonded to the first section via the first and second bonding portions and including readout circuitry coupled to the first bonding portion and the second bonding portion.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

65.

IMAGING DEVICE AND DISTANCE MEASUREMENT SYSTEM

      
Application Number 19173054
Status Pending
Filing Date 2025-04-08
First Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kumata, Keishi

Abstract

Provided is an imaging device capable of suppressing a decrease in a frame rate while improving charge transfer efficiency. An imaging device according to an embodiment of the present disclosure includes: a photoelectric conversion element; a signal converter that is boosted when charge transferred from the photoelectric conversion element is converted into a pixel signal; a selection transistor that interrupts a signal line of the pixel signal during a boosting period of the signal converter; a comparator including a non-inverting input terminal to which the pixel signal is input via the selection transistor, an inverting input terminal to which a ramp signal is input, and an output terminal which outputs a comparison result between the pixel signal and the ramp signal; and a correction circuit that holds a potential of the non-inverting input terminal in the boosting period at a potential of the non-inverting input terminal before the boosting period.

IPC Classes  ?

  • H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
  • H04N 23/56 - Cameras or camera modules comprising electronic image sensorsControl thereof provided with illuminating means
  • H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
  • H04N 25/705 - Pixels for depth measurement, e.g. RGBZ
  • H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors
  • H04N 25/767 - Horizontal readout lines, multiplexers or registers
  • H04N 25/779 - Circuitry for scanning or addressing the pixel array
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

66.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2024001299
Publication Number 2025/154240
Status In Force
Filing Date 2024-01-18
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Otsuka Yusuke

Abstract

[Problem] To optimize a pixel configuration by connecting elements using a connector other than metal wiring. [Solution] This solid-state imaging device comprises a light receiving element, a transfer transistor, a capacitor, an amplification transistor, and a floating diffusion layer. The transfer transistor transfers a signal output by the light receiving element. The capacitor is connected at one end to the light receiving element via the transfer transistor, is connected at the other end to a negative-side power supply voltage, and converts charges output by the light receiving element into voltages and accumulates the same. A voltage from the capacitor is applied to a gate of the amplification transistor and the amplification transistor outputs a signal corresponding to the voltage. The floating diffusion layer includes one end of the capacitor and a gate of the amplification transistor, and is formed from an electrode integrated with the one end of the capacitor and the gate of the amplification transistor.

IPC Classes  ?

  • H04N 25/70 - SSIS architecturesCircuits associated therewith

67.

IMAGE SENSOR AND IMAGING DEVICE

      
Application Number JP2024041398
Publication Number 2025/154389
Status In Force
Filing Date 2024-11-22
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hayashida, Mitsuki

Abstract

The number of elements per pixel is reduced in an FD sharing type device. An image sensor according to the present invention comprises a plurality of main pixels, a plurality of sub pixels, a floating diffusion, a plurality of first on-chip lenses, and a plurality of second on-chip lenses. The plurality of main pixels are arranged in a two-dimensional grid. The plurality of sub pixels have sensitivity lower than that of the plurality of main pixels, and are disposed in regions which are surrounded by the plurality of main pixels. The floating diffusion is disposed in a region which is surrounded by the plurality of main pixels, and is shared by the plurality of main pixels and the plurality of sub pixels. The plurality of first on-chip lenses each cover one of the plurality of main pixels. The plurality of first on-chip lenses are disposed in regions which are surrounded by the plurality of first on-chip lenses.

IPC Classes  ?

  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

68.

OSCILLATION DEVICE

      
Application Number JP2024041481
Publication Number 2025/154390
Status In Force
Filing Date 2024-11-22
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Ono, Kazutoshi

Abstract

The present invention can reduce phase noise while characteristics of an oscillation device are addressed. This oscillation device comprises: a field effect transistor that outputs an oscillation signal through the drain thereof; and a control unit that controls the oscillation amplitude of the oscillation signal on the basis of the source potential of the field effect transistor. The field effect transistor may operate as a negative resistor of an LC oscillator. In the case in which the field effect transistor is an N-channel field effect transistor, the control unit may control the oscillation amplitude in a direction in which the lower limit value of the oscillation amplitude approaches the source potential of the N-channel field effect transistor.

IPC Classes  ?

  • H03B 5/08 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance

69.

SOLID-STATE IMAGING DEVICE

      
Application Number JP2024046113
Publication Number 2025/154529
Status In Force
Filing Date 2024-12-26
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Uchida Tetsuya

Abstract

The present disclosure relates to a solid-state imaging device configured so that the power consumption thereof is reduced. Provided is a solid-state imaging device comprising a pixel array unit in which a plurality of pixels are arranged. The pixels include: a photoelectric conversion unit that converts incident light into an electric charge; a charge-to-voltage conversion unit that accumulates the electric charge obtained by photoelectric conversion; a conversion efficiency switching unit that is provided to the charge-to-voltage conversion unit and switches conversion efficiency; and a conversion efficiency switching control unit that controls the switching of conversion efficiency by the conversion efficiency switching unit, on the basis of the potential of the charge-to-voltage conversion unit. The present disclosure can be applied to, for example, a CMOS-type image sensor.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion

70.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND IMAGING DEVICE

      
Application Number JP2024046116
Publication Number 2025/154532
Status In Force
Filing Date 2024-12-26
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Terasawa Takashi

Abstract

The present disclosure relates to an information processing device, an information processing method, and an imaging device, which make it possible to perform DNN processing with a lower data amount and lower power consumption. A RAW format conversion processing unit converts the format of a RAW format image outputted from a sensor unit such that the data amount is reduced on the basis of a pixel array of the sensor unit, thereby acquiring a sensing RAW format image. A sensing processing unit executes sensing processing by performing DNN processing on the sensing RAW format image. This technology can be applied to, for example, an imaging device that recognizes a subject by DNN processing.

IPC Classes  ?

  • H04N 23/65 - Control of camera operation in relation to power supply
  • H04N 23/60 - Control of cameras or camera modules
  • H04N 25/11 - Arrangement of colour filter arrays [CFA]Filter mosaics

71.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2024046412
Publication Number 2025/154549
Status In Force
Filing Date 2024-12-27
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakashima Yoshimitsu
  • Hiroki Mizuha

Abstract

Provided is a light detection device in which the influence of dark current is suppressed. The light detection device comprises: a semiconductor layer having a back surface on one side and an element formation surface on the other side, the semiconductor layer including a plurality of cell regions that are arranged in a matrix and include a photoelectric conversion region, namely, a semiconductor region of a first conductivity type; separator walls that are provided in a groove extending between the back surface and the element formation surface of the semiconductor layer and separate the cell regions from each other; and a first transistor and a second transistor provided on the element formation surface side of the cell regions. The first transistor is a transistor having a transfer path that is a semiconductor region of the first conductivity type directly connected to the photoelectric conversion regions, the second transistor is a transistor other than the first transistor, the first transistor is provided at a position closer to a first separator wall among the separator walls than the centers of the cell regions in a plan view, the transfer path is provided spaced apart from the first separator wall, and the semiconductor region of the second transistor is in contact with the separator walls.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10F 30/20 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors

72.

SEMICONDUCTOR DEVICE

      
Application Number JP2025000438
Publication Number 2025/154626
Status In Force
Filing Date 2025-01-09
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Fukushima Kenta
  • Kiji Mitsuru
  • Nakano Takuya
  • Nishikido Kenju

Abstract

A light detecting device comprises a main structure comprising a first section that includes a pixel region including a plurality of pixels to convert light incident to a first side of the first section into electric charge, and a peripheral region adjacent to the pixel region that includes a first conductive structure located at the first side of the first section. The main structure includes a second section that includes logic to process signals for the pixel region. In a cross sectional view, the first conductive structure electrically connects to the second section at a first level within the main structure. The main structure also includes a second conductive structure which, in the cross sectional view, is located at a second level within main structure that is between the first level and at least part of the second section.

IPC Classes  ?

  • H10F 39/12 - Image sensors
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

73.

VOLTAGE TIME CONVERTER, ANALOG DIGITAL CONVERTER, AND ELECTRONIC DEVICE

      
Application Number JP2025000615
Publication Number 2025/154666
Status In Force
Filing Date 2025-01-10
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Nogamida, Takeru

Abstract

in_pccout_pdref1dcref1ref1).

IPC Classes  ?

  • H03M 1/50 - Analogue/digital converters with intermediate conversion to time interval

74.

IMAGE SENSOR AND IMAGING DEVICE

      
Application Number JP2025001082
Publication Number 2025/154748
Status In Force
Filing Date 2025-01-16
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Hayashida, Mitsuki
  • Yahata, Ken

Abstract

The present invention pertains to a floating diffusion (FD) sharing-type device where the number of elements per pixel is reduced. An image sensor according to the present invention includes a plurality of main pixels, a plurality of sub-pixels, a floating diffusion, a plurality of first on-chip lenses, and a plurality of second on-chip lenses. The plurality of main pixels are arranged in a two-dimensional grid. The plurality of sub-pixels have lower sensitivity than the plurality of main pixels and are each disposed in a region surrounded by a plurality of the main pixels. The floating diffusion is disposed in a region surrounded by a plurality of the main pixels and is shared by said plurality of main pixels and a plurality of the sub-pixels.

IPC Classes  ?

  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

75.

DISTANCE MEASURING DEVICE

      
Application Number 18698487
Status Pending
Filing Date 2022-07-26
First Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ebiko, Yoshiki
  • Mizuta, Kyohei
  • Komuro, Yutaro
  • Yasu, Yohtaro
  • Narisawa, Sousuke
  • Yokogawa, Sozo
  • Toda, Atsushi
  • Goi, Kazuhiro

Abstract

A distance measuring device according to an embodiment of the present disclosure comprises a first substrate including a first optical waveguide configured to convey a chirp signal, a splitter configured to split the chirp signal into a transmission signal and a reference signal, and a coupler and detector block configured to output a beat signal based on the reference signal and a reflected signal. The distance measure device comprises a second substrate stacked on the first substrate and including a converter configured to output a digital beat signal based on the beat signal; and a controller configured to output an electronic control signal that controls generation of the chirp signal.

IPC Classes  ?

  • G01S 17/34 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01S 7/4911 - Transmitters
  • G01S 7/4912 - Receivers
  • G01S 7/4913 - Circuits for detection, sampling, integration or read-out
  • G01S 17/931 - Lidar systems, specially adapted for specific applications for anti-collision purposes of land vehicles
  • H01L 23/498 - Leads on insulating substrates
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

76.

SEMICONDUCTOR INTEGRATED CIRCUIT AND ELECTRONIC DEVICE

      
Application Number 18852709
Status Pending
Filing Date 2023-02-09
First Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Tanimoto, Tadaaki
  • Hiraga, Keizo
  • Eguchi, Takeshi
  • Bessho, Kazuhiro

Abstract

To reduce power consumption in a semiconductor integrated circuit that holds configuration data. The semiconductor integrated circuit includes a long-term holding memory and a short-term holding memory. Among these memories in the semiconductor integrated circuit, the short-term holding memory has a data holding time shorter than a predetermined time and holds predetermined configuration data. Furthermore, the long-term holding memory in the semiconductor integrated circuit has a data holding time being the predetermined time and holds a specific data indicating whether or not a power supply voltage is recovered after dropping to a value lower than a constant voltage.

IPC Classes  ?

  • G11C 14/00 - Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
  • G11C 5/14 - Power supply arrangements

77.

LIGHT DETECTION DEVICE

      
Application Number JP2024001053
Publication Number 2025/154188
Status In Force
Filing Date 2024-01-17
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Noudo Shinichiro
  • He Yilun
  • Terada Keisuke
  • Komuro Yutaro
  • Iwase Toshihito

Abstract

The present disclosure relates to a light detection device whereby both improved quantum efficiency and flare suppression can be achieved. The light detection device comprises a pixel array section in which a plurality of pixels are arranged two-dimensionally on a semiconductor substrate. The pixels comprise a photoelectric conversion part formed on the semiconductor substrate to perform photoelectric conversion in response to incident light, a light condensing part that condenses incident light onto the photoelectric conversion unit, and a light guide part formed inside the photoelectric conversion part. The technology of the present disclosure can be applied to, e.g., a light detection device that receives light in the infrared region and generates a signal.

IPC Classes  ?

78.

NOISE EVENT REMOVAL DEVICE, OPTICAL DETECTION DEVICE, AND NOISE EVENT REMOVAL METHOD

      
Application Number JP2024042856
Publication Number 2025/154417
Status In Force
Filing Date 2024-12-04
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kinugawa Hiroshi
  • Matsuura Koji
  • Nishina Yuki

Abstract

[Problem] To provide a noise event removal device making it possible to maintain the detection accuracy of true events while also removing flicker noise events. [Solution] An optical detection device according to one embodiment of the present disclosure is provided with: a noise event mask unit for performing mask processing to remove illumination flicker noise from an event signal indicating a result of detecting, as an event, a change in the amount of light reception at pixels when a subject lit by the illumination was imaged in a predetermined frame; and an event restoration unit for performing event restoration processing to restore a true event that was lost due to the mask processing.

IPC Classes  ?

  • H04N 25/60 - Noise processing, e.g. detecting, correcting, reducing or removing noise
  • H04N 23/60 - Control of cameras or camera modules
  • H04N 23/745 - Detection of flicker frequency or suppression of flicker wherein the flicker is caused by illumination, e.g. due to fluorescent tube illumination or pulsed LED illumination
  • H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data
  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

79.

INFORMATION PROCESSING DEVICE, PROGRAM, AND NEURAL NETWORK ARCHITECTURE MANUFACTURING METHOD

      
Application Number JP2024045902
Publication Number 2025/154513
Status In Force
Filing Date 2024-12-25
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Oniki, Kazumasa

Abstract

An information processing device includes processing circuitry configured to obtain predicted performance index values indicating results of prediction of performance of a learned AI model that would result from subjecting a neural network architecture to learning, wherein the predicted performance index values are obtained using multiple performance predictors configured to predict the performance without undergoing a learning phase, calculate an integrated index value of the neural network architecture by integrating the predicted performance index values obtained from the multiple performance predictors, and select a neural network architecture from among multiple neural network architectures based on integrated index values calculated for each of the multiple neural network architectures.

IPC Classes  ?

  • G06N 3/0464 - Convolutional networks [CNN, ConvNet]
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
  • G06N 3/086 - Learning methods using evolutionary algorithms, e.g. genetic algorithms or genetic programming

80.

LIGHT DETECTION DEVICE

      
Application Number JP2024046079
Publication Number 2025/154525
Status In Force
Filing Date 2024-12-26
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Iida Satoko
  • Noguchi Shunta

Abstract

[Problem] To provide a light detection device that makes it possible to reduce chip size without deteriorating imaging quality. [Solution] A pixel array part of this light detection device has an effective pixel region having a plurality of pixels and a light shielding region disposed around the effective pixel region. The light shielding region has a process dummy region in which a plurality of dummy pixels are disposed in order to suppress processing variations, an effective optical black region for generating a black level reference signal in the plurality of pixels, an ineffective optical black region disposed between the effective pixel region and the effective optical black region without generating the reference signal, and a specific function transistor region having a transistor for executing a specific function. The process dummy region and/or the ineffective optical black region is disposed so as to avoid a region where the specific function transistor region is not present.

IPC Classes  ?

  • H10F 39/12 - Image sensors
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

81.

IMAGING ELEMENT AND ELECTRONIC DEVICE

      
Application Number JP2024046114
Publication Number 2025/154530
Status In Force
Filing Date 2024-12-26
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nishida Mizuki
  • Goi Kazuhiro

Abstract

The present disclosure relates to an imaging element and an electronic device that make it possible to further improve an imaging property. A well contact electrode for supplying a predetermined potential to a well of a semiconductor substrate is provided on a back surface side serving as a light receiving surface of the semiconductor substrate on which a photoelectric conversion unit is provided for each pixel, and a negative bias electrode for applying a negative bias to a side wall of the pixel is provided in a trench that separates the pixels in the semiconductor substrate. A first connection terminal provided on a front surface of the semiconductor substrate and the well contact electrode are connected by a well contact connection structure, and a second connection terminal provided on a front surface of the semiconductor substrate and the negative bias electrode are connected by a negative bias connection structure. The present technology can be applied, for example, to a back-illuminated CMOS image sensor.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10F 39/12 - Image sensors

82.

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING SYSTEM

      
Application Number JP2024046332
Publication Number 2025/154545
Status In Force
Filing Date 2024-12-27
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ono, Hiroaki
  • Di, Mengzhi

Abstract

This information processing device comprises: a point group generation unit that generates, on the basis of sensing data of a target area, point group data indicating a three-dimensional structure of the target area, the structure being configured to include at least three-dimensional coordinate information for each point of an object present in the target area; an object recognition processing unit that performs object recognition processing on the point group data on the basis of the sensing data; a feature information generation unit that generates, on the basis of the three-dimensional coordinate information included in the point group data, three-dimensional feature information indicating three-dimensional features of the object present in the target area; and an association processing unit that associates, with the point group data, object classification index information based on the three-dimensional feature information and recognition type information that indicates an object type recognized in the object recognition processing.

IPC Classes  ?

83.

ANTENNA DEVICE AND RADAR DEVICE

      
Application Number JP2025000546
Publication Number 2025/154646
Status In Force
Filing Date 2025-01-09
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Li Xi

Abstract

[Problem] To provide an antenna device and a radar capable of improving power supply efficiency. [Solution] An antenna device of the present disclosure includes: a waveguide that transmits a signal; a plurality of openings which are arranged in rows in a waveguide direction of the waveguide and are alternately offset along the waveguide direction; and a plurality of radiation elements that are disposed corresponding to the plurality of openings and that receive the signal from the waveguide via the plurality of openings.

IPC Classes  ?

  • H01P 5/08 - Coupling devices of the waveguide type for linking lines or devices of different kinds
  • G01S 7/03 - Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver
  • G01S 13/86 - Combinations of radar systems with non-radar systems, e.g. sonar, direction finder
  • H01Q 13/08 - Radiating ends of two-conductor microwave transmission lines, e.g. of coaxial lines, of microstrip lines
  • H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart

84.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2025001178
Publication Number 2025/154763
Status In Force
Filing Date 2025-01-16
Publication Date 2025-07-24
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Matsuo Junichi
  • Yamamoto Masahiro

Abstract

The present invention improves image quality. This light detection device is provided with: a semiconductor layer having a first surface part and a second surface part positioned on mutually opposite sides in one direction; a separation region including a dug part extending from the first surface part side toward the second surface part side of the semiconductor layer; a photoelectric conversion region demarcated by the separation region and provided in the semiconductor layer; a photoelectric conversion part including a first conductivity type first semiconductor region separated from the separation region and the first surface part of the semiconductor layer and provided in the photoelectric conversion region; a first conductivity type second semiconductor region provided on the photoelectric conversion region side between the separation region and the first semiconductor region; and a second conductivity type third semiconductor region provided in the photoelectric conversion region between the first semiconductor region and the second semiconductor region. The second semiconductor region is connected to a conductor to which a potential is applied.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H10F 30/20 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors

85.

IMAGE GENERATION CIRCUITRY AND IMAGE GENERATION METHOD

      
Application Number EP2025050470
Publication Number 2025/153394
Status In Force
Filing Date 2025-01-09
Publication Date 2025-07-24
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY DEPTHSENSING SOLUTIONS SA/NV (Belgium)
Inventor
  • Szasz, Pal
  • Mattisson, Fredrik

Abstract

The disclosure pertains to image generation circuitry that is configured to: obtain a set of input image frames that represent a first and at least a subsequent capture; iteratively merge two neighboring frames of the set of input image frames based on a determined optical flow between them until a criterion is met; and generate an output frame based on the merged set of input image frames.

IPC Classes  ?

  • G06T 5/50 - Image enhancement or restoration using two or more images, e.g. averaging or subtraction
  • G06T 5/70 - DenoisingSmoothing

86.

SENSOR DEVICE AND METHOD FOR OPERATING A SENSOR DEVICE

      
Application Number EP2025050628
Publication Number 2025/153420
Status In Force
Filing Date 2025-01-13
Publication Date 2025-07-24
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY EUROPE B. V. (United Kingdom)
Inventor Moeys, Diederik Paul

Abstract

Sensor for event detection comprising, a control unit (110) that determines an event generation rate that indicates how many events have occurred during a predetermined time interval, and a timestamp unit (120) that receives from an event detection unit (100) requests for permission for outputting event data and adds to the event data a timestamp that indicates the time at which the request for permission for outputting of said event data had been allowed. The control unit instructs the event detection unit to asynchronously request permission for outputting event data from the timestamp unit, if the event generation rate is below or equal to a readout threshold, and the control unit instructs the event detection unit to output event data synchronously at predetermined time points and to add a timestamp that indicates the respective time point to the event data, if the event generation rate is above the readout threshold.

IPC Classes  ?

  • H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data

87.

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC APPARATUS

      
Application Number 18702247
Status Pending
Filing Date 2022-09-28
First Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Hatano, Keisuke

Abstract

A semiconductor device, a manufacturing method therefor, and an electronic apparatus that reduces a parasitic capacitance generated between an internal electrode and a board silicon to suppress waveform distortion and signal delay of high-frequency signals, thereby enabling a high-speed operation. A configuration to include: a board silicon; a silicon oxide film stacked on the board silicon; an inter-wiring-layer film having an internal electrode stacked on the silicon oxide film; a through-hole forming a stepped hole with a larger-diameter hole extending from the board silicon to the silicon oxide film and a smaller-diameter hole extending from the silicon oxide film to the internal electrode; an interlayer dielectric film stacked on a circumferential side surface of the larger-diameter hole and the board silicon; and a redistribution layer on an inner peripheral surface of the through-hole and the interlayer dielectric film and connected to the internal electrode.

IPC Classes  ?

  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/12 - Image sensors
  • H10F 77/122 - Active materials comprising only Group IV materials
  • H10F 77/20 - Electrodes
  • H10F 77/30 - Coatings

88.

LIGHT EMITTING DEVICE AND DISTANCE MEASURING DEVICE

      
Application Number 18702813
Status Pending
Filing Date 2022-10-17
First Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Izuhara, Kunihiko

Abstract

To reduce power consumption of a light emitting device. The light emitting device includes a plurality of light emitting elements, a plurality of driving thyristors, a selection unit, a light emission current supply unit, and a current adjustment unit. The driving thyristors are disposed for each of the plurality of light emitting elements and become conductive themselves to thereby feed a light emission current to the light emitting elements ad drive the light emitting elements. The selection unit includes a plurality of selection thyristors that are disposed for each of the plurality of driving thyristors and output a conduction signal for making the driving thyristors conductive when the selection thyristors become conductive themselves and alternately repeats a transfer period for sequentially selecting the plurality of driving thyristors by shifting, in order, a position of the selection thyristor coming into a conduction state among the plurality of selection thyristors and a driving period for causing the selected driving thyristor to drive the light emitting element. The light emission current supply unit supplies a light emission current to the light emitting element via the selected driving thyristor in the driving period. The current adjustment unit supplies a conduction current of the selection thyristor and adjusts the conduction current of the selection thyristor in the driving period.

IPC Classes  ?

  • H05B 45/345 - Current stabilisationMaintaining constant current
  • G01S 7/484 - Transmitters
  • G01S 17/10 - Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
  • H05B 47/155 - Coordinated control of two or more light sources
  • H05B 47/16 - Controlling the light source by timing means

89.

IMAGING ELEMENT, IMAGING APPARATUS, AND SEMICONDUCTOR ELEMENT

      
Application Number 18847600
Status Pending
Filing Date 2023-03-24
First Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Fukui, Ryo
  • Tomita, Ken
  • Okawa, Tatsuya

Abstract

A voltage to be applied to a charge holding section to which charges generated by a plurality of photoelectric conversion sections are transferred is adjusted. An imaging element includes a plurality of photoelectric conversion sections, a charge holding section, a plurality of charge transfer sections, an image signal generation section, and a plurality of capacitive coupling wirings. The photoelectric conversion section performs photoelectric conversion of incident light to generate a charge. The charge holding section holds the generated charge. The charge transfer section is arranged for each photoelectric conversion section and transfers the generated charge to the charge holding section. The image signal generation section generates an image signal corresponding to the held electric charge. The capacitive coupling wirings are capacitively coupled to the charge holding section, and are individually applied with an adjustment signal for adjusting the potential of the charge holding section.

IPC Classes  ?

  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

90.

MEMORY CONTROL DEVICE

      
Application Number 18849180
Status Pending
Filing Date 2023-03-09
First Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Ikezoe, Takeharu
  • Ikarashi, Takahiro

Abstract

A memory control device according to one embodiment of the present disclosure includes a detector and a converter. The detector detects switching between read bank group interleaving and a write request or switching between write bank group interleaving and a read request in a plurality of memory access requests received for memory access. The converter converts a BL length of a memory access request included in the read bank group interleaving or the write bank group interleaving, on the basis of a number of memory access requests in the read bank group interleaving or the write bank group interleaving and timing information of a command corresponding to a memory access request immediately before the read bank group interleaving or the write bank group interleaving.

IPC Classes  ?

  • G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
  • G11C 11/4076 - Timing circuits
  • G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers

91.

IMAGING DEVICE AND IMAGING METHOD

      
Application Number JP2024041707
Publication Number 2025/150275
Status In Force
Filing Date 2024-11-26
Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kodama Kazutoshi

Abstract

[Problem] To provide an imaging device and an imaging method capable of suppressing potential variation in accordance with the elapsed time from pixel initialization. [Solution] The present disclosure provides an imaging device comprising: a pixel array unit in which a plurality of first pixels each outputting a luminance signal corresponding to a light amount are configured in a matrix; a detection circuit unit that outputs a detection signal indicating the occurrence of an address event when the luminance signal of each of the plurality of first pixels exceeds a predetermined threshold; and a drive unit having a first drive for resetting the accumulated charge of the first pixels in a partial region within the plurality of first pixels.

IPC Classes  ?

  • H04N 25/707 - Pixels for event detection
  • H04N 25/47 - Image sensors with pixel address outputEvent-driven image sensorsSelection of pixels to be read out based on image data

92.

LIGHT DETECTION DEVICE

      
Application Number JP2024046080
Publication Number 2025/150439
Status In Force
Filing Date 2024-12-26
Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Toyofuku, Takuya
  • Aoki, Yohei

Abstract

Provided is a light detection device comprising: a photoelectric conversion unit that converts light into a charge; a charge accumulation unit that accumulates the charge from the photoelectric conversion unit; an amplifying transistor that converts the charge accumulated in the charge accumulation unit into a pixel signal; a first additional capacitive unit that adds capacitance to the charge accumulation unit; and an additional transistor that switches conversion efficiency by switching between enabling and disabling addition to the charge accumulation unit by the first additional capacitive unit, said light detection device being formed by lamination of a first layer, which has the photoelectric conversion unit, the charge accumulation unit, and the first additional capacitive unit, and a second layer, which has the amplifying transistor and which is laminated on the first layer.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

93.

SELF-MIXING INTERFEROMETRY SENSOR, READOUT AND CONTROL METHOD AND ELECTRONIC DEVICE

      
Application Number EP2025050425
Publication Number 2025/149566
Status In Force
Filing Date 2025-01-09
Publication Date 2025-07-17
Owner
  • SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
  • SONY EUROPE B.V. (United Kingdom)
Inventor
  • Perenzoni, Matteo
  • Perenzoni, Daniele
  • Mattioli Della Rocca, Francescopaolo
  • Stoppa, David

Abstract

A self-mixing interferometry sensor having a stacked structure, comprising in order from top to bottom: a plurality of self-mixing interferometry devices arranged in an array; and a readout and control circuit provided for each self-mixing interferometry device or for each group of self-mixing interferometry devices, wherein each readout and control circuit is configured to: generate a drive current signal, apply the drive current signal, read out a self-mixing interferometry signal, receive a reference signal having a constant reference frequency, compare the reference signal with the self-mixing interferometry signal to generate a frequency difference signal, control, based on the generated frequency difference signal, a time derivative of the drive current signal such that a frequency of the self-mixing interferometry signal is locked to the reference frequency.

IPC Classes  ?

  • G01B 9/02004 - Interferometers characterised by controlling or generating intrinsic radiation properties using two or more frequencies using frequency scans
  • G01B 9/02 - Interferometers
  • G01B 11/02 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness
  • G01S 7/4912 - Receivers

94.

IMAGING ELEMENT AND IMAGING DEVICE

      
Application Number 19055304
Status Pending
Filing Date 2025-02-17
First Publication Date 2025-07-17
Owner Sony Semiconductor Solutions Corporation (Japan)
Inventor
  • Hattori, Yuki
  • Iida, Satoko

Abstract

A potential of a charge retaining unit that retains a charge generated by photoelectric conversion is adjusted. An imaging element includes a photoelectric conversion unit, a charge retaining unit, a charge transfer unit, a reset unit, an image signal generating unit that generates an image signal, capacitive coupling wiring, and a potential adjustment unit. The photoelectric conversion unit is formed on a semiconductor substrate and performs photoelectric conversion of incident light. The charge retaining unit retains a charge generated by photoelectric conversion. The charge transfer unit transfers the charge generated by photoelectric conversion to the charge retaining unit. The reset unit discharges the charge retained in the charge retaining unit. The image signal generating unit generates an image signal on the basis of the charge retained in the charge retaining unit. The capacitive coupling wiring is different from wiring that transmits control signals of the charge transfer unit, the reset unit, and the image signal generating unit and wiring that transmits a generated image signal and is capacitively coupled to the charge retaining unit. The potential adjustment unit applies an adjustment signal for adjusting the potential of the charge retaining unit via the capacitive coupling wiring.

IPC Classes  ?

  • H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
  • H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

95.

IMAGING DEVICE, IMAGING CONTROL METHOD, AND COMPUTER-READABLE NON-TRANSITORY STORAGE MEDIUM

      
Application Number JP2024042260
Publication Number 2025/150289
Status In Force
Filing Date 2024-11-29
Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Kato, Akihiko

Abstract

An imaging device according to the present invention comprises a motion extraction unit, a region determination unit, and a mode control unit. The motion extraction unit extracts motion of a subject on the basis of image information obtained in a motion detection mode. The region determination unit acquires, as a motion region, an image region in which the motion of the subject was extracted. The mode control unit determines, on the basis of the size of the motion region, the resolution of image information acquired in a feature detection mode. The mode control unit switches to a specific processing mode in response to detection of a specific feature of interest from the image information obtained in the feature detection mode.

IPC Classes  ?

  • H04N 23/65 - Control of camera operation in relation to power supply
  • G03B 15/00 - Special procedures for taking photographsApparatus therefor
  • H04N 23/61 - Control of cameras or camera modules based on recognised objects

96.

POINT CLOUD PROCESSING DEVICE AND POINT CLOUD PROCESSING SYSTEM

      
Application Number JP2024044597
Publication Number 2025/150362
Status In Force
Filing Date 2024-12-17
Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Goto, Yuki
  • Sekiya, Tarou
  • Iwasa, Takeshi
  • Kato, Hiroshi
  • Hitomi, Yasunobu
  • Iwama, Haruyuki

Abstract

Provided is a point cloud processing device comprising: a first point cloud generation unit that generates a first three-dimensional point cloud of a target region using a plurality of images captured by a camera comprised by a moving body; and a second point cloud generation unit that generates a second three-dimensional point cloud of a partial region within the target region using an image, among the plurality of images, selected on the basis of information relating to a terminal device set up in the target region.

IPC Classes  ?

  • G01C 11/06 - Interpretation of pictures by comparison of two or more pictures of the same area
  • G01C 15/00 - Surveying instruments or accessories not provided for in groups
  • G06T 7/593 - Depth or shape recovery from multiple images from stereo images

97.

PHOTODETECTION DEVICE, METHOD FOR PRODUCING SAME, AND ELECTRONIC APPARATUS

      
Application Number JP2024045361
Publication Number 2025/150402
Status In Force
Filing Date 2024-12-23
Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Watanabe Ryota

Abstract

The present disclosure pertains to: a photodetection device in which a deterioration in dark-time characteristics can be inhibited; a method for manufacturing the photodetection device; and an electronic apparatus. This photodetection device comprises: a photoelectric conversion unit; a pixel transistor; and an element separation layer provided in the vicinity of the pixel transistor. An end surface of the gate electrode of the pixel transistor is in contact with an end surface of the element separation layer or is disposed away from the end surface of the element separation layer toward a center line connecting the gate electrode and two source/drain regions. The technology of the present disclosure is applicable to a photodetection device or the like that photoelectrically converts incoming light and outputs a pixel signal corresponding to the amount of received light.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H01L 21/76 - Making of isolation regions between components
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
  • H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10F 30/20 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors

98.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2024046157
Publication Number 2025/150445
Status In Force
Filing Date 2024-12-26
Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor Yamashita Hirofumi

Abstract

This disclosure relates to a light detection device and an electronic apparatus with which transfer efficiency can be optimised. This disclosure involves: a photoelectric conversion part for converting light formed in a semiconductor substrate into electric charges; a storage part for temporarily storing the electric charges; and a transfer part configured to transfer the electric charges to the storage part. The transfer part includes a transfer gate at least a part of which is provided in the semiconductor substrate. An extension line in a movement direction of the electric charges at a point where the potential becomes highest within the part of the semiconductor substrate where the potential is modulated by the transfer part intersects with the storage part in a plan view. This disclosure can be applied to, for example, a light detection device that detects a phase difference.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H04N 25/704 - Pixels specially adapted for focusing, e.g. phase difference pixel sets
  • H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
  • H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D 88/00 - Three-dimensional [3D] integrated devices

99.

LIGHT DETECTION DEVICE AND ELECTRONIC APPARATUS

      
Application Number JP2024046158
Publication Number 2025/150446
Status In Force
Filing Date 2024-12-26
Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Nakamura Yusuke
  • Ogita Tomoharu
  • Okawa Tatsuya
  • Takahashi Naohiro

Abstract

The present disclosure relates to a light detection device and an electronic apparatus with which it is possible to miniaturize pixels. This light detection device comprises a vertical transistor which includes: a gate electrode having a trench electrode formed by boring a semiconductor substrate to at least a section thereof in the depth direction; and a first source/drain region and a second source/drain region, one of which is a source and the other of which is a drain. The first source/drain region is formed in the vicinity of an interface of a first surface of the semiconductor substrate, and the second source/drain region is formed in the vicinity of a second surface of the semiconductor substrate, opposite to the first surface, below the gate electrode. The technology of the present disclosure can be applied, for example, to a light detection device that generates and outputs an imaging signal corresponding to the amount of incident light.

IPC Classes  ?

  • H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
  • H04N 25/70 - SSIS architecturesCircuits associated therewith
  • H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
  • H10D 84/85 - Complementary IGFETs, e.g. CMOS

100.

MAGNETIC STORAGE ELEMENT, STORAGE DEVICE, AND ELECTRONIC APPARATUS

      
Application Number JP2024046320
Publication Number 2025/150455
Status In Force
Filing Date 2024-12-27
Publication Date 2025-07-17
Owner SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Japan)
Inventor
  • Kageyama, Yuito
  • Nozaki, Takayuki
  • Ichinose, Tomohiro
  • Yamamoto, Tatsuya
  • Hosomi, Masanori
  • Higo, Yutaka
  • Sakai, Lui
  • Ohba, Kazuhiro
  • Hiraga, Keizo

Abstract

A magnetic storage element according to one embodiment of the present disclosure comprises: a tunnel barrier layer; a storage layer provided to the tunnel barrier layer; and a voltage modulation enhancement layer provided on a surface of the storage layer on the side opposite to the tunnel barrier layer side.

IPC Classes  ?

  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H01F 10/08 - Thin magnetic films, e.g. of one-domain structure characterised by magnetic layers
  • H10N 50/01 - Manufacture or treatment
  • H10N 50/10 - Magnetoresistive devices
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