This disclosure relates generally to a patterning structure including an underlayer and an imaging layer, as well as methods and apparatuses thereof. In particular embodiments, the underlayer provides an increase in radiation absorptivity and/or patterning performance of the imaging layer.
G03F 7/09 - Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
C23C 16/04 - Coating on selected surface areas, e.g. using masks
G03F 1/22 - Masks or mask blanks for imaging by radiation of 100 nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masksPreparation thereof
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
Examples are disclosed that relate to use of extreme ultraviolet (EUV)-absorbing photoelectron-emissive dopants that are bonded to atoms in a hydrogen-contributing photosensitive underlayer for a photoresist. One example provides a method of forming a hydrogen-contributing photosensitive underlayer on a substrate. The method comprises exposing the substrate to a dopant precursor and a hydrocarbon precursor, the dopant precursor comprising an extreme ultraviolet (EUV)-absorbing photoelectron-emissive dopant bonded within a carbon-containing polymerizable molecule. The method further comprises exposing the substrate to a radical species formed by a plasma. The method further comprises forming the hydrogen-contributing photosensitive underlayer on the substrate from the dopant precursor and the hydrocarbon precursor by reaction of the dopant precursor and the hydrocarbon precursor with the radical species.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
Ring storage carrier and ring storage buffers for semiconductor processing are provided. A ring storage carrier may have a housing at least partially defined by a front side with an opening that is configured to receive an edge ring and a ring carrier, a back side opposite the front side, a top, and a baseplate, four ring support structures inside the housing, and two alignment rails inside the housing. Each ring support structure has a plurality of support fingers arranged along a vertical axis perpendicular to the baseplate, each support finger extends along an axis perpendicular to the vertical axis. A first support structure has a first set of support fingers and each support finger of the first set has a support pin extending upwards, and each support finger of a second support structure does not have a support pin.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
5.
CUSTOMIZING ETCH SELECTIVITY AND HIGH ASPECT RATIO FEATURE LOADING THROUGH MULTI-LEVEL PULSING SCHEMES UTILIZING SINUSOIDAL AND CUSTOM RF WAVEFORMS
A method for performing a plasma etch process in a process chamber is provided, including: applying a source radiofrequency (RF) signal to a top electrode of the process chamber; applying a bias RF signal to a lower electrode of the process chamber; wherein the bias RF signal has two or more pulsed duty cycles, including a first duty cycle having a first sinusoidal waveform at a first frequency and pulsed at a first voltage level, and a second duty cycle having a custom waveform pulsed at a second voltage level, the custom waveform consisting of a second sinusoidal waveform at a second frequency that is combined with a non-sinusoidal waveform.
Disclosed is a method and apparatus configured to perform an in-situ plasma cleaning of an end effector. The method comprises moving the end effector into a process module from a vacuum transfer module attached to the process module, positioning the end effector below a gas distribution plate, flowing a plasma over the gas distribution plate, exposing the end effector to the plasma, and retracting the end effector into the vacuum transfer module.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
A method for isolating bitlines of a 3D-DRAM includes depositing a conductive layer on an etch stop layer and in trenches between facing stacks of transistors; depositing a filler material in the trenches; and depositing and patterning a mask layer including a plurality of vertical openings on the etch stop layer and the filler material. The plurality of vertical openings of the mask layer are arranged above corresponding locations of the conductive layer that need to be removed to isolate bitlines of the 3D-DRAM. The method includes etching the filler material in the trenches through the plurality of vertical openings to remove portions of the filler material to expose portions of the conductive layer located between vertical bitline locations.
Methods and apparatuses for depositing silicon-containing materials such as silicon oxide using an oxygen-free plasma are provided. Methods involve using a silicon-containing precursor having an oxygen atom and igniting an oxygen-free plasma to convert the silicon-containing precursor to silicon oxide.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/507 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using external electrodes, e.g. in tunnel type reactors
Epitaxial techniques for forming films using radical-assisted remote plasma deposition are provided. Some films may be doped. Deposition may be performed selectively. Deposition may be performed in conjunction with etching, which also may be performed selectively. Additional operations may also be performed, including pre-cleaning and pre-treating the substrate. Also described are apparatuses and systems for preparing and making the films and materials including doped layers.
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
Semiconductor manufacturing machines; semiconductor
substrates manufacturing machines; semiconductor wafer
processing equipment; semiconductor wafer processing
machines; replacement parts and fittings for all of the
aforementioned goods; machine parts, namely, etch chambers
sold as an integral part of semiconductor manufacturing
machines; machine parts, namely, processing chambers sold as
an integral part of semiconductor manufacturing machines;
semiconductor manufacturing machine parts, namely,
processing chambers; semiconductor manufacturing machine
parts, namely etch chambers.
11.
Ion Energy Distribution Control Over Substrate Edge with Non-Sinusoidal Voltage Source
A bias voltage supply system includes a primary bias electrode disposed below a substrate support surface. The primary bias electrode controls a voltage on a top surface of a substrate present on the substrate support surface. The bias voltage supply system includes an edge ring electrode disposed within an edge ring that circumscribes the substrate support surface. The edge ring electrode controls a voltage on a top surface of the edge ring. The bias voltage supply system includes a voltage supply system that generates a prescribed voltage waveform as a function of time on a bias voltage supply node. A first branch circuit electrically connects the bias voltage supply node and the primary bias electrode. A second branch circuit electrically connects the bias voltage supply node and the edge ring electrode. The second branch circuit includes a series capacitor and a shunt capacitor.
A substrate support includes at least three pockets defined along a perimeter of the substrate support, an edge gas groove located on a top surface of the substrate support, and a first clamping groove located radially inward from the edge gas groove on the top surface of the substrate support. Each pocket comprises a narrow portion and a wide portion located radially outward from the narrow portion. The edge gas groove is concentric with the substrate support. The edge gas groove intersects the narrow portion of each pocket. At least thirty through holes are within the edge gas groove and at least one through hole is within the narrow portion of each pocket.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
Examples are disclosed that relate to etching carbon-containing films using an etching agent and a carbon-containing film precursor. This helps to etch the carbon-containing film at a higher rate on a field region of the substrate than within a feature. One example provides, on a substrate comprising a feature and a field region adjacent to the feature, a method of etching a carbon film deposited on the field region and within the feature. The method comprises forming a plasma using a gas mixture comprising an etching agent and a carbon-containing film precursor to generate reactive etching species and reactive deposition species. The method further comprises etching the carbon film at a higher rate in the field region than within the feature by depositing carbon within the feature during etching.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Methods and apparatuses for using molecules having a carbon-nitrogen triple bond as inhibitors on metal-containing surfaces to selectively deposit dielectric material on a dielectric surface on a substrate surface having a metal-containing surface and a dielectric surface are provided. A method for processing substrates comprises providing a substrate having a first material and a second material thereon to a process chamber, exposing the substrate to an isonitrile inhibitor to adsorb onto the first material to inhibit deposition on the first material, and depositing a dielectric film on the second material.
Provided are methods of filling patterned features with molybdenum (Mo). The methods involve selective deposition of Mo films on bottom metal-containing surfaces of a feature including dielectric sidewalls. The selective growth of Mo on the bottom surface allows bottom-up growth and high quality, void-free fill. Also provided are related apparatus.
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
16.
METHOD FOR PREVENTING LINE BENDING DURING METAL FILL PROCESS
Provided herein are methods and apparatuses for reducing line bending when depositing a metal such as tungsten, molybdenum, ruthenium, or cobalt into features on substrates by periodically exposing the feature to nitrogen, oxygen, or ammonia during atomic layer deposition, chemical vapor deposition, or sequential chemical vapor deposition to reduce interactions between metal deposited onto sidewalls of a feature. Methods are suitable for deposition into V-shaped features.
A method of etching recessed features in a stack comprising silicon oxide is provided. An etch gas is provided comprising a halogen containing component and a nitrogen containing component. The etch gas is transformed into a plasma, wherein the nitrogen containing component provides nitrogen containing species wherein the nitrogen containing species causes silicon oxide to etch more similarly to silicon nitride and wherein the halogen containing component provides a halogen containing species, wherein the halogen containing species etches the silicon oxide.
A method for etching features in a stack is provided. A plurality of cycles is provided wherein each cycle comprises providing a first etch, comprising flowing a first etch gas comprising a first etchant and a metal containing passivant, forming the first etch gas into a first plasma, and exposing the stack to the first plasma to simultaneously etch features into the stack and deposit electrically conductive metal containing passivation on sidewalls of the features, and providing a second etch, comprising flowing a second etch gas comprising a second etchant, forming the second etch gas into a second plasma, and exposing the stack to the second plasma to simultaneously etch features into the stack and remove at least some of the electrically conductive metal containing passivation on sidewalls of the features.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01J 37/305 - Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating, or etching
19.
EDGE RING COMPENSATION MONITORING AND ADJUSTMENT DURING PLASMA PROCESSING
A system includes a substrate support with an electrostatic chuck and an edge ring, an edge ring RF power source configured to provide an RF voltage to the edge ring based on a tuning edge sheath compensation during processing of a substrate, a measurement power source configured to provide an RF voltage to the electrostatic chuck and the edge ring, and a controller configured to determine an impedance associated with the electrostatic chuck and an impedance associated with the edge ring based on the RF voltage provided to the electrostatic chuck and the edge ring from the measurement power source, adjust the tuning edge sheath compensation based on the impedance associated with the electrostatic chuck and the impedance associated with the edge ring, and control the edge ring RF power source to adjust the RF voltage based on the adjusted tuning edge sheath compensation.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
An edge ring is configured to be arranged around a substrate support in a substrate processing chamber. The edge ring includes an upper surface, a horizontal lower surface arranged to thermally couple with a thermal edge ring via a thermal interface material, and an inner diameter arranged to surround a radially outer surface of the substrate support, wherein a ledge is defined in the inner diameter of the edge ring, a slanted surface is defined to extend at an angle downward and radially outward from the inner diameter to the horizontal lower surface, and the slanted surface is arranged to define a gap between the slanted surface and a chamfered edge of the substrate support. The edge ring includes an outer diameter, wherein the outer diameter of the edge ring includes a projection that extends radially outward from the edge ring and defines an inward step in the outer diameter.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
21.
ELECTROSTATIC CHUCK WITH MULTI-COMPONENT CERAMIC COATING APPLIED TO BASEPLATE
An electrostatic chuck (ESC) baseplate is provided with a shoulder region configured to support an edge ring, and a multi-component ceramic coating is spray coat applied on at least the shoulder region, the coating having a first component and a second component, the first component having a first dielectric constant that is higher than a dielectric constant of aluminum oxide and also having a first thermal conductivity, and the second component having a second thermal conductivity that is higher than the first thermal conductivity, and wherein a dielectric constant for the multi-component ceramic coating is higher than the dielectric constant of aluminum oxide. The multi-component ceramic coating has a value X within a range of 10/millimeters (mm) to 350/mm, wherein X = k/d, and wherein k is a dielectric constant of the multi-component ceramic coating and d is a thickness of the multi-component ceramic coating.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H02N 13/00 - Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
B23Q 3/15 - Devices for holding work using magnetic or electric force acting directly on the work
Examples are disclosed that relate to virtual semiconductor fab environments. One example provides a method of monitoring a process performed on a substrate in a processing tool. The method comprises obtaining runtime data from sensors of the processing tool while running the process in the processing tool. The method further comprises performing a runtime simulation by simulating a digital twin using the runtime data and a recipe for the process. The method further comprises receiving a selection of a spatial viewpoint within the digital twin of the processing tool. The method further comprises rendering an image of a virtual state of the processing tool using the runtime simulation and the spatial viewpoint, and outputting the image of the virtual state.
Provided are reduced temperature plasma enhanced chemical vapor deposition processes for producing high modulus oxide thin films on a substrate. The substrate temperature for deposition of the oxide thin film is less than about 700° C.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
C23C 16/52 - Controlling or regulating the coating process
Disclosed herein are techniques for control of spatial density of plasma with process stations by return path reactance tuning. In some embodiments, a semiconductor fabrication chamber comprises a pedestal configured to support a wafer undergoing processing. The chamber may further comprise a showerhead. The chamber may further comprise two or more unpowered electrodes operatively coupled to the showerhead or to the pedestal. The chamber may further comprise one or more variable reactances coupled to at least one of the two or more unpowered electrodes, wherein reactances of the one or more variable reactances are modified to control a spatial density of plasma within the fabrication chamber.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
25.
VIRTUAL EXPERIMENTATION PLATFORM FOR PHOTOLITHOGRAPHY PROCESS FLOW
A digital twin of an EUV photolithography workflow determines a patterning performance of an EUV photolithography process. The digital twin includes an EUV exposure model, a bake model coupled to the EUV exposure model, and a development model coupled to the bake model. The digital twin receives inputs related to photons used in EUV exposure, a material of the EUV resist, and processes used in bake and development. Using a semi-empirical kinetic Monte Carlo framework, the digital twin can predict patterning outcomes of the EUV photolithography process.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
In one embodiment, the disclosed subject-matter is a method for determining a level of a liquid in a container, which includes capturing multiple images of the liquid within the container and analyzing the multiple images to generate a liquid-level determination result. The analyzing includes differentiating components of the liquid including at least one component selected from components of foam and bubbles within the liquid. The analyzing further including at least one operation selected from operations of increasing the contrast of the components of the liquid, within the multiple images and increasing the edge detection of the components of the liquid within the multiple of images. Other apparatuses and systems are disclosed.
An edge ring system comprising a substrate support configured to support a substrate during plasma processing and including a baseplate and an upper layer arranged on the baseplate. An edge ring support includes a first body and an electrostatic clamping electrode arranged in the first body. The edge ring support is arranged above the baseplate and radially outside of the substrate during processing. An edge ring includes a second body arranged on and electrostatically clamped to the edge ring support during plasma processing.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
28.
GAS DISTRIBUTION ASSEMBLY FOR SEMICONDUCTOR PROCESSING CHAMBER WITH ALUMINUM NITRIDE LAYER
A gas distribution assembly for use in a semiconductor processing chamber with an interior is provided. A back plate has a first side facing toward the interior of the semiconductor processing chamber and a second side away from the interior of the semiconductor processing chamber. At least one electrode is on the first side of the back plate. An aluminum nitride (AlN) containing thermal interface layer is between the back plate and the at least one electrode.
A cooling plate for a showerhead includes an outer annular portion comprising a first annular body including a first cavity extending in an axial direction, an inlet, a first fluid passage extending from the inlet to the first cavity, an outlet, and a second fluid passage extending from the first cavity to the outlet. An inner annular portion is arranged in the first cavity of the outer annular portion and comprises a second annular body including a second cavity extending in an axial direction and configured to receive a stem portion of a showerhead, a radially outer surface, and a fluid channel defined on the radially outer surface. The fluid channel is in fluid communication with the first fluid passage and the second fluid passage.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
30.
CRYOGENIC CHUCK FOR NARROW ION ANGULAR SPREAD IN SUBSTRATE PROCESSING SYSTEMS
An example substrate processing system includes a processing chamber including a window, a substrate support arranged in the processing chamber, configured to support a substrate on an upper surface thereof, at least one radio frequency (RF) source configured to supply an RF signal to one or more coils, at least one of a liquid nitrogen source or a liquid helium source arranged to supply at least one of liquid nitrogen or liquid helium to the substrate support, and a controller configured to strike plasma by supplying RF power from the at least one radio frequency (RF) source to the one or more coils, and to supply the at least one of liquid nitrogen or liquid helium to the substrate support to control a temperature of the substrate support at or below a target cooling temperature value to control an ion angular spread during etching of the substrate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
31.
DRY DEVELOPMENT SIMULATION METHODS FOR PHOTORESIST FILMS
Dry development models of a dry development process predict patterning outcomes for EUV resist patterning. A static threshold model identifies a threshold value of cross-linked states in an EUV resist that represents a completion point for a dry development process based on experimental data. The static threshold model determines a location in the EUV resist that meets the threshold value. A transient particle tracing model provides a semi-empirical kinetic Monte Carlo framework to predict patterning metrics for a dry development process. A developer particle is identified with a certain particle trajectory, and a photoresist unit is identified that the developer particle interacts with. The reaction probability for removing the photoresist unit is based on a dry development mechanism and rate determined from experimental data. The EUV resist profile is updated and the transient particle tracing model monitors EUV resist profile and roughness changes over time.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
Provided herein are examples of methods and related apparatus for depositing an ashable hardmask (AHM) on a substrate using a process gas including hydrocarbons and halide-containing species and pulsed low frequency (LF) power. Halide-containing species may decrease the hydrogen content of the AHM, and a plasma using pulsed LF power may improve mechanical properties of the AHM. Also provided herein are examples of annealed hardmasks and examples of processes for annealing hardmasks.
C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
C23C 16/52 - Controlling or regulating the coating process
An edge ring system for a substrate processing chamber includes a middle ring configured for arrangement around a substrate support. The edge ring system includes an outer ring portion, an inner ring portion, N arcuate openings arranged between the outer ring portion and the inner ring portion, where N is an integer greater than 1, N bridges connecting the outer ring portion and the inner ring portion between the N arcuate openings, and an annular cavity arranged on a radially inner surface of the outer ring portion. A cover ring is arranged in the annular cavity. A top edge ring is arranged above the middle ring between the cover ring and the inner ring portion and above the N arcuate openings and the N bridges of the middle ring.
A method for selectively etching at least one feature in a nitrogen or carbon containing dielectric etch layer or a polysilicon etch layer under a mask in a stack, while providing profile control and CD control, is provided. An etch gas is flowed comprising an etchant and a metal containing passivant. The etch gas is formed into a plasma. The dielectric etch layer or polysilicon etch layer is exposed to the plasma to simultaneously etch features into the dielectric etch layer and deposit metal containing passivation on sidewalls of the features.
An apparatus includes a stem body and interior flow paths. The stem body has proximal and distal ends. The proximal end includes inlets, each of which is distinct and configured to receive a corresponding gas(es). The distal end is opposite the proximal end along a longitudinal axis of the stem body and configured to interface with a gas distributor. The distal end includes outlets, at least one of which is distinct. The interior flow paths include first and second interior flow paths. Each of the interior flow paths extends between a corresponding inlet among the inlets and at least one corresponding outlet among the outlets such that the interior flow paths are distinct from one another. Each of the interior flow paths includes structure(s) configured to induce turbulent flow along the longitudinal axis in response to a flow of the corresponding gas(es) along that interior flow path.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
37.
HIGH-EFFICIENCY LED SUBSTRATE HEATER FOR DEPOSITION APPLICATIONS
An optical array arranged in a pedestal configured to deposit material on a substrate includes a plurality of optical elements, a window, and an array of pinholes. The optical elements are arranged on a printed circuit board (PCB). The optical elements are configured to emit light. The window comprises an optically transparent material covering the optical elements arranged on the PCB. The array of pinholes is disposed between the optical elements and the window. The pinholes are vertically aligned with the optical elements to direct the light emitted by the optical elements through the window to heat the substrate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
Embodiments herein relate to methods and apparatus for etching a substrate. In particular, the substrate is a semiconductor substrate and the material being etched is an oxide material such as silicon oxide. In various embodiments, the method may include receiving a substrate having an oxide material thereon; and exposing the substrate to a reactant gas to etch the oxide material on the substrate, where the reactant gas is in a vapor phase and comprises an ammonium-based hydroxide source.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Multi-modal electrostatic chuck (ESC) apparatus, and systems and methods for operating an ESC are provided. In some embodiments, the ESC may operate in monopolar clamping mode or bipolar clamping mode. In some embodiments, the ESC may utilize a pair of electrodes for the monopolar and bipolar clamping mode. In some embodiments, each of the pair of electrodes may be electrically coupled to a respective power source. In some embodiments, the ESC may be operated in a first clamping mode (e.g., bipolar clamping mode), and based at least on a change in a processing environment, operated in a second clamping mode (e.g., monopolar clamping mode).
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
Various embodiments herein relate to methods, apparatus, and systems for etching high aspect ratio features in dielectric material. The dielectric material is etched using a multi-layer or graded hardmask having at least two different compositions. Different etching regimes are used when the different portions of the hardmask are exposed. For example, a feature may be etched to a first depth at a first temperature while an upper portion of the hardmask is exposed, and then etched to a final depth at a second temperature while a lower portion of the hardmask is exposed, the second temperature being higher than the first temperature.
An apparatus includes a main body having a first surface including gas distribution ports (hereinafter, “ports”). The first surface is divided into zones. The ports include: first ports distributed across a first zone among the zones, each first port being fluidically connected to a first gas inlet(s) via a corresponding first gas distribution flow path; second ports distributed across a second zone among the zones, each second port being fluidica Hy connected to a second gas inlet(s) via a corresponding second gas distribution flow path; and third ports distributed across a third zone among the zones, each third port being fluidically connected to a third gas inlet(s) via a corresponding third gas distribution flow path. The first zone separates the second and third zones from one another. Within the main body, the first gas distribution flow paths are separated from each of the second and third gas distribution flow paths.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
42.
IN SITU TREATMENT OF MOLYBDENUM OXYHALIDE BYPRODUCTS IN SEMICONDUCTOR PROCESSING EQUIPMENT
Provided are methods for increasing the efficiency of atomic layer deposition of molybdenum metal by in situ cleaning and decontamination of molybdenum oxyhalide precursor delivery lines to a deposition chamber. The cleaning process may take place by pre-treating the delivery lines with at least one surface passivating agent and/or by periodically treating the delivery lines with at least one corrosion inhibitor. Also provided are methods of removing oxidation from a deposited molybdenum film.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/14 - Deposition of only one other metal element
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
A method for detecting a leak in an electrodeposition system comprising a separated anode chamber is presented. The method comprises isolating a separated anode chamber. A static pressure in the separated anode chamber is modified. Pressure change is monitored in the separated anode chamber. Whether the leak is present is determined based on the pressure change monitored being greater than a threshold pressure change.
Examples are disclosed that relate to depositing carbon films using a pulsed plasma. One example provides a processing tool, comprising a processing chamber, a substrate holder, a showerhead, flow control hardware configured to connect one or more processing gas sources with the showerhead, a radiofrequency (RF) power supply configured to provide RF power to form a plasma between the substrate holder and the showerhead, and a controller configured to control the flow control hardware to introduce a flow of a carbon-containing precursor and an etchant into the processing chamber through the showerhead during a deposition process, and to control the RF power supply to pulse the plasma during the deposition process.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
In some examples, a gas supply line arrangement is provided for inhibiting particle contamination in a substrate process chamber. An example gas supply line arrangement comprises a cleaning gas source for a clean cycle of the substrate process chamber, a purge gas source for a purge cycle of the substrate process chamber, and a gas supply line to carry cleaning gas and purge gas towards the substrate process chamber. A three-port valve in the gas supply line arrangement comprises a valve inlet connected to the gas supply line, a first valve outlet in fluid communication with the substrate process chamber, the first valve outlet operable to admit or prevent a passage of cleaning gas to the substrate process chamber, and a second valve outlet connected to a divert line and operable to admit or prevent a passage of particle-containing purge gas to the divert line.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
A large beam spot spectral reflectometer system for measuring a substrate is provided. Hardware components for collecting in situ large beam spot optical signals is disclosed. Machine learning models for denoising large beam spot optical signals are disclosed. Machine learning models for interpreting in situ optical data and facilitating process control are also disclosed.
Methods and apparatuses for forming films using a mixed mode atomic layer deposition chemical vapor deposition process are provided. Methods involve exposing a semiconductor substrate to partially temporally overlapping pulses of a plasma-free deposition precursor (a dose) and a plasma generated by igniting a deposition reactant (such as an oxidant) to form a film on the semiconductor substrate.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
48.
Manifold for supplying coolant to components of substrate processing systems
Systems and techniques for determining and using multiple types of offsets for providing wafers to a wafer support of a wafer station of a semiconductor processing tool are disclosed; such techniques and systems may use an autocalibration wafer that may include a plurality of sensors, including a plurality of edge-located imaging sensors that may be used to image fiducials associated with two different structures located in a selected wafer station.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
Disclosed is an apparatus comprising a showerhead mounting fixture operable to mount a showerhead and a thermochromic film coupled to a gantry mechanism. In at least one implementation, the gantry mechanism is operable to raise and lower the thermochromic film over a faceplate of the showerhead, wherein the faceplate comprises a plurality of orifices arranged in an array pattern, wherein the thermochromic film is operable to image the array pattern of the plurality of orifices.
G01K 11/12 - Measuring temperature based on physical or chemical changes not covered by group , , , or using changes in colour, translucency or reflectance
G01J 5/48 - ThermographyTechniques using wholly visual means
G01J 5/60 - Radiation pyrometry, e.g. infrared or optical thermometry using determination of colour temperature
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
51.
INTEGRATION OF DRY DEVELOPMENT AND ETCH PROCESSES FOR EUV PATTERNING IN A SINGLE PROCESS CHAMBER
Process condition management facilitates the combination of dry development and etching into a single process chamber; eliminating the necessity for a post-dry development bake step during semiconductor manufacturing. Methods and apparatuses for rapidly instituting a large drop in process chamber pressure allow thermal dry development and an O2 flash treatment or thermal dry development and plasma hardmask open operations to take place without wafer transfer.
A seal for a substrate processing system includes a body comprised of a base material, an outer surface, and a marker material disposed at least one of throughout the base material within the body of the seal, in an outer edge region of the seal, in a coating disposed on the outer surface of the seal, and in an interior region of the seal. The marker material is different from the base material.
G01M 3/04 - Investigating fluid tightness of structures by using fluid or vacuum by detecting the presence of fluid at the leakage point
G01N 21/3504 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing gases, e.g. multi-gas analysis
G01N 21/62 - Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
Systems and techniques for dry deposition of extreme ultraviolet-sensitive (EUV-sensitive) photoresist layers are discussed. In some such systems, a processing chamber may be provided that features a multi-plenum showerhead that is configured to receive a vaporized organometallic precursor in one plenum and a vaporized counter-reactant thereof in another plenum. The two vaporized reactants may be delivered to a reaction space within the processing chamber and over a wafer support that supports the substrate.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
54.
NEAR IR LASER BASED CONTACTLESS WAFER TEMPERATURE MEASUREMENT
Techniques for semiconductor processing includes a pedestal for supporting a semiconductor substrate positioned within a processing chamber. The semiconductor substrate has a bottom surface proximal to the pedestal and a top surface distal from the pedestal. A at least one laser light source is configured to operate at IR or near IR wavelengths and to illuminate, at two or more separated locations, one of the top surface or the bottom surface. Each of two or more detectors is configured to detect radiation, from the at least one laser light source transmitted through the substrate, proximate to a respective one of the two or more separated locations. At least one controller is configured to determine, from the detected radiation, a respective transmittance of the substrate at each of the two or more separated locations and a respective temperature corresponding to the respective transmittance.
G01J 5/061 - Arrangements for eliminating effects of disturbing radiationArrangements for compensating changes in sensitivity by controlling the temperature of the apparatus or parts thereof, e.g. using cooling means or thermostats
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
Methods and apparatus for backside sealing of a semiconductor substrate are provided. In some embodiments, such techniques may include: causing delivery of a first set of one or more process gases to a first process chamber of a deposition apparatus, the first process chamber having a semiconductor substrate disposed therein; applying a first process temperature in presence of plasma to form a first layer of material on the backside of the semiconductor substrate; causing delivery of a second set of one or more process gases to the first process chamber; and applying the first process temperature in the presence of plasma to form a second layer of material on the first layer of material on the backside of the semiconductor substrate to collectively form a stack of materials that seals the backside of the semiconductor substrate and mitigates diffusion of dopants from the semiconductor substrate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
56.
SINGLE WAFER REACTOR, LOW TEMPERATURE, THERMAL SILICON NITRIDE DEPOSITION
Methods and apparatuses for depositing silicon nitride using a thermal atomic layer deposition process are provided. The temperature of a substrate during deposition is higher than the surround process chamber walls to reduce deposition on the chamber walls, reducing the frequency of chamber cleans.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
A carrier ring with tabs for use with a semiconductor processing apparatus is provided. The carrier ring may include a ring having an outer portion and an inner portion and defining a plane. The carrier ring may include tabs about an inner perimeter of the inner portion. The ring and the tabs may have physical characteristics configured to enable more backside deposition of the semiconductor substrate at a plurality of locations of the semiconductor substrate corresponding to the tabs, as compared to a ring without the physical characteristics. Such characteristics of the ring and tabs may include an inner diameter of the ring, inner diameter of the tabs, quantity of the tabs, width of the tabs, an angle of the tab with respect to the plane. These characteristics may reduce a substrate contact area and increase deposition areas near substrate edges, which may increase the evenness of film thicknesses.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
58.
AMPOULE CONTAINING SOLID PRECURSOR FOR ATOMIC LAYER DEPOSITION PROCESSES
An ampoule of a substrate processing system includes an enclosure for containing a solid precursor and a control valve arrangement including a plurality of control valves, including at least an outlet valve disposed between the enclosure and a substrate processing chamber. The substrate processing system is configured to cause at least a portion of the solid precursor to sublimate, and to deliver resulting gaseous precursor chemicals, through at least the outlet valve, to the substrate processing chamber. Each of the plurality of control valves has a cyclic lifetime of at least thirty million cycles.
C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
In one embodiment, the disclosed apparatus is a composite-manifold assembly including a manifold-base portion having a plurality of valve-mounting areas formed thereon. At least one of the valve-mounting areas has one or more gas inlets. The manifold-base portion is configured to flow at least one first gas. An edge-inserted manifold-portion is in fluid communication with the manifold-base portion to receive the at least one first gas therefrom. The edge-inserted manifold-portion is formed from a second material. The edge-inserted manifold-portion is to receive and flow one or more second gases through one or more through-holes formed therein. The second material is more corrosion -resistant to the one or more second gases than the first material. Other apparatuses and systems are disclosed.
C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
Provided are processes of filling features with method. The processes include deposition, etch, and clean operations using a molybdenum chloride (MoClx) compound. The MoClx compound may be controlled to selectively deposit on metal nitride features compared to dielectric, form plugs and crystals on dielectric materials, and perform a net etch of materials within the feature. Also provided are in-situ clean processes in which the MoClx compound is used to remove oxidation from underlying surfaces prior to deposition. Subsequent deposition using the MoClx precursor may deposit an initial layer and/or fill a feature.
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Described is a method for thermally protecting an electronic circuit. In at least one implementation, electronic circuit comprises at least a first component and a second component. In at least one implementation, method comprises measuring a first input voltage and a first input current of the first component. In at least one implementation, method further comprises computing a second input voltage and a second input current of the second component. In at least one implementation, method further comprises computing a first temperature of the first component and a second temperature of the second component, wherein the first temperature is a function of the first input current and the second temperature is a function of the second input current.
Embodiments of methods of filling features with molybdenum (Mo) include depositing a first layer of Mo in a feature including an opening and an interior and non-conformally treating the first layer such that regions near the opening preferentially treated over regions in the interior. In some embodiments, a second Mo layer is deposited on the treated first layer. Embodiments of methods of filling features with Mo include controlling Mo precursor flux to transition between conformal and non-conformal fill.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
63.
TRANSFORMERLESS PULSED BIAS VOLTAGE GENERATOR WITH DAMPER
A system including a pulsed bias voltage generator is described. The pulsed bias voltage generator includes a pulsed current source that increases a voltage during a charging process to create a pulse of a non-sinusoidal radio frequency (RF) signal. The pulsed bias voltage generator includes a pulsed current sink coupled to the pulsed current source. The pulsed current sink decreases the voltage to create the pulse of the non-sinusoidal RF signal. The pulsed current source repeats the increase in the voltage and the pulsed current sink repeats the decrease in the voltage to generate additional pulses of the non-sinusoidal RF signal. The system includes a damper coupled to the pulsed current sink to modify a voltage step of the pulse.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
A zero dead-leg orifice bypass apparatus includes a first multi-port valve, a second multi-port valve, and. a flow restrictor. The first multi-port valve includes a first plurality of valve legs with an inlet port. The second multi-port valve includes a second plurality of valve legs with an outlet port. The first plurality of valve legs and the second plurality of valve legs form at least one unrestricted path between the inlet port and the outlet port. The flow restrictor is pneumatically coupled to the first multi-port valve and the second multi-port, valve. The first plurality of valve legs and the second plurality of valve legs form at least one restricted path between the inlet port and the outlet port, with the at least one restricted path passing through a restricted port of the flow restrictor.
F16K 51/02 - Other details not peculiar to particular types of valves or cut-off apparatus specially adapted for high-vacuum installations
F16K 31/06 - Operating meansReleasing devices electricOperating meansReleasing devices magnetic using a magnet
F16K 7/12 - Diaphragm cut-off apparatus, e.g. with a member deformed, but not moved bodily, to close the passage with flat, dished, or bowl-shaped diaphragm
F16K 27/00 - Construction of housingsUse of materials therefor
F16K 27/02 - Construction of housingsUse of materials therefor of lift valves
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Examples are disclosed that relate to treating a substrate in a degas module to remove water vapor prior to depositing a film by pulsed laser deposition. One example provides a processing tool. The processing tool comprises a transfer module. The processing tool further comprises a pulsed laser deposition module connected to the transfer module. The processing tool further comprises a degas module connected to the transfer module. The degas module comprises a substrate support. The degas module further comprises a cryopump configured to form a high vacuum (P ≤ 10-5 Torr) in the degas module and the transfer module. The degas module further comprises an infrared radiation source.
A method for providing forward power during a bin is described. The method includes receiving a first waveform indicating a plurality of power levels of power to be delivered from a radio frequency (RF) power supply. The plurality of power levels of the first waveform vary with a progression of bins of a voltage waveform. The method further includes identifying, from a mapping between a first plurality of waveforms and a second plurality of waveforms, one of the waveforms of the second plurality corresponding to the first waveform. The one of the waveforms of the second plurality includes a plurality of power levels that vary with the progression of the bins. The method includes controlling the RF power supply to supply power according to the plurality of power levels of the one of the waveforms of the second plurality with the progression of the bins.
Semiconductor manufacturing machines; semiconductor
substrates manufacturing machines; semiconductor wafer
processing equipment; semiconductor wafer processing
machines; replacement parts and fittings for all of the
aforementioned goods; machine parts, namely, ion shields
inside etch chambers sold as an integral part of
semiconductor manufacturing machines; semiconductor
manufacturing machine parts, namely, ion shields;
semiconductor manufacturing machine parts, namely etch
chambers embedded with ion shields; machine parts, namely,
ion shields sold as an integral part of semiconductor
manufacturing machines; replacement parts for semiconductor
manufacturing machines, namely, ion shields.
68.
ORGANOCHLORIDE ETCH WITH PASSIVATION AND PROFILE CONTROL
A method of etching recessed features in stack with a silicon containing layer below a mask and over a wafer on a substrate support is provided. An etch gas comprising a carbon source, a fluorine source, and an organochloride source selected from the group consisting of carbon tetrachloride (CCI4), CxHyClz (where x>0 and z>0), and combinations thereof, is provided. The etch gas is formed into a plasma. The stack is exposed to the plasma to etch recessed features into the stack.
A sensor probe includes an elongated body defining an inner cavity having an inner diameter. A printed circuit board is configured to be fitted within the inner cavity. A first temperature-sensing integrated circuit mounted at a first end of the printed circuit board. A cap is mounted to a first end of the elongated body adjacent to the first temperature-sensing integrated circuit. A housing is configured to receive a second end of the elongated body, wherein the housing is configured to be mounted to a baseplate of a substrate support.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
70.
RAPID TUNING OF CRITICAL DIMENSION NON-UNIFORMITY BY MODULATING TEMPERATURE TRANSIENTS OF MULTI-ZONE SUBSTRATE SUPPORTS
A substrate processing system includes a processing chamber, a substrate support including a plurality of heater zones arranged in the processing chamber, a gas delivery system configured to deliver process gases to the processing chamber, and a controller configured to communicate with the gas delivery system and the plurality of heater zones, initiate a first treatment step of a process during a transient temperature period after a substrate is arranged on the substrate support and prior to the substrate reaching a steady-state temperature of the substrate support, and adjust heating to each of the plurality of heater zones during the first treatment step based on average heat functions determined for corresponding ones of the plurality of heater zones during a period corresponding to the first treatment step.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
An anode chamber for an electroplating apparatus includes an inert anode, an anode support in contact with the inert anode, an ionically conductive membrane separated from the inert anode by a gap in the anode chamber, a membrane clamp configured to hold the ionically conductive membrane, at least one inlet configured to flow anolyte into the gap at a first position, and at least one outlet configured to receive the anolyte flowing out of the gap at a second position.
Examples are disclosed that relate to a thermal interface component for a plasma processing tool, and a plasma processing tool with a thermal interface component. In one example, a plasma processing tool comprises an outer electrode surrounding an inner electrode, and a gas distribution plate. The plasma processing tool further comprises a thermal interface component situated between the gas distribution plate and one or more of the inner electrode and the outer electrode. The thermal interface component comprises a non-silicone polymeric elastomer as a continuous phase and thermally conductive particles as a dispersed phase.
In some examples, a showerhead testing apparatus includes an enclosure forming an internal volume. The enclosure is configured to support a showerhead, positioned within the internal volume. The showerhead testing apparatus further includes a first supply line removably attached to the enclosure. The first supply line is configured to supply compressed gas to the internal volume of the enclosure. The showerhead testing apparatus further includes a second supply line that is removably attached to the showerhead. The second supply line is configured to supply the compressed gas to an internal volume of the showerhead. The showerhead testing apparatus further includes a measuring probe that is removably attached to the enclosure. The measuring probe obtains a particle count measurement associated with gas flow through one or both of the internal volume of the showerhead and the internal volume of the enclosure.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Techniques for performing fabrication process simulations are provided. In some embodiments, a method may involve receiving, via a user interface, user-specified target output values for a set of output parameters associated with a fabrication process. The method may further involve determining optimized process parameter values by providing the user-specified target output values as input to a trained model, wherein the trained model has been trained to represent a function that associates output parameter values to process parameter values such that a simulation of a fabrication process using the process parameter values yields a simulated fabricated substrate having the output parameter values. The method may further involve simulating the fabrication process using the optimized process parameter values by using a fabrication process simulation algorithm.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/66 - Testing or measuring during manufacture or treatment
75.
SYSTEMS AND TECHNIQUES FOR BULK PRECURSOR DELIVERY FOR SEMICONDUCTOR PROCESSING
Precursor delivery systems are provided. In one embodiment, a precursor delivery system has an ampoule having an inlet and an outlet, and configured to contain a precursor, heat the precursor to a vapor, receive an inert gas through the inlet, and flow a first mixture of the inert gas and the precursor vapor out of the outlet, and have a plurality of flow paths that are each fluidically connected to the outlet of the ampoule and configured to be fluidically connected to one corresponding processing module of a plurality of processing modules. Each flow path may be configured to flow the first mixture, configured to maintain the first mixture at a temperature between 100 °C and 150 °C, and have a high-temperature mass flow controller configured to control flow of the first mixture along the flow path.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
76.
FLOW MONITORING AND DISTRIBUTION CONTROL VIA SHOWERHEAD FLOW DISTRIBUTION DEVICES
A first flow distribution device, to be disposed in a body or a stem of a showerhead of a substrate processing system, includes: a pair of electrodes; and an intermediate layer disposed between the pair of electrodes and comprising an electroactive polymer that changes state based on a voltage applied to the pair of electrodes. The pair of electrodes and the intermediate layer are collectively implemented as a baffle plate affecting flow of a substance through the showerhead.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/52 - Controlling or regulating the coating process
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
77.
USE OF VARIABLE CAPACITOR DIODES FOR IMPEDANCE MATCHING
Disclosed herein are methods, systems, and apparatuses that involve variable capacitor diodes for impedance matching. In some embodiments, an RF match circuit for impedance matching in a semiconductor fabrication chamber may comprise a variable reactance comprising a variable capacitor diode. A voltage associated with the variable capacitor diode is modified to cause a change in a width of a depletion region of the variable capacitor diode based at least in part on an impedance of a plasma load associated with plasma within at least one station of the semiconductor fabrication chamber to perform impedance matching between an RF source and the plasma load.
Provided herein are methods and apparatus for growing molybdenum (Mo) in features. The methods may be used to grow single-grain Mo in features with super-conformal, conformal, and/or top-heavy growth profiles. In some embodiments, methods involve inducing a local crystallization in an amorphous molybdenum-containing material, etching at least a portion of the amorphous molybdenum containing material, and growing the molybdenum crystallites. The methods may be used for bottom-up deposition of Mo in a feature. In some embodiments, then methods may produce molybdenum gap-fill with a reduced number of crystallite grains inside a feature, nearly a single crystalline domain, or a single crystal inside a feature. The methods may be used for logic and memory applications.
Systems and techniques for enhancing wafer-to-wafer and in-wafer uniformity in the context of extreme ultraviolet (EUV) lithography are disclosed. By performing post-exposure bake operations and dry-development operations on an EUV-exposed wafer without breaking vacuum, wafer-to-wafer uniformity and in-wafer uniformity are improved. Performing a cooling and treatment operation in between the post-exposure bake and the dry-development process and in which the wafer is exposed to a controlled pseudo-atmospheric environment may recover dose-to-size that may be lost by performing the post-exposure bake operations and dry-development operations on the EUV-exposed wafer without breaking vacuum.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
G03F 7/38 - Treatment before imagewise removal, e.g. prebaking
80.
LOW-TEMPERATURE DEPOSITION OF PROTECTIVE MATERIAL IN A FEATURE
Methods and apparatuses for forming a protective material on a sidewall of a feature to protect the sidewall during subsequent etching and other operations are provided herein. The metal-containing protective layer is deposited thermally or using a plasma and may include forming an underlayer having a hydrogen-terminated surface prior to forming a metal-containing layer over the underlayer to form the protective material.
Dry development or dry removal of metal-containing extreme ultraviolet radiation (EUV) photoresist is performed in atmospheric conditions or performed in process tools without vacuum equipment. Dry removal of the metal-containing EUV photoresist may be performed under atmospheric pressure or over-atmospheric pressure. Dry removal of the metal-containing EUV photoresist may be performed with exposure to an air environment or with non-oxidizing gases. A process chamber or module may be modified or integrated to perform dry removal of the metal-containing EUV photoresist with baking, wafer cleaning, wafer treatment, or other photoresist processing function. In some embodiments, the process chamber for dry removal of the metal-containing EUV photoresist includes a heating assembly for localized heating of a semiconductor substrate and a movable discharge nozzle for localized gas delivery above the semiconductor substrate.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
G03F 7/36 - Imagewise removal not covered by groups , e.g. using gas streams, using plasma
A substrate support includes a plurality of clamping zones arranged in the substrate support. The plurality of clamping zones is configured to clamp a substrate to the substrate support. A controller is configured to cause operation of a first set of clamping zones of the plurality of clamping zones according to a first set of conditions, and to cause operation of a second set of clamping zones of the plurality of clamping zones according to a second set of conditions. The first and second sets of conditions are different.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A method for achieving process rate uniformity by identifying one or more bins is described. The method includes receiving a voltage signal provided from an output of an impedance matching circuit. The method further includes dividing the voltage signal into a predetermined number of bins during each of a plurality of cycles of a clock signal, accessing a recipe set identifying one or more of the bins for achieving the process rate uniformity, and controlling delivered power to be of a predetermined amount during the one or more of the bins to achieve the process rate uniformity.
A substrate support for supporting a substrate includes a baseplate and a coolant channel arranged in the baseplate. The coolant channel comprises a plurality of turns distributed between an outer diameter of the substrate support to a center of the substrate support, and an inlet for a coolant connected to an outermost turn of the plurality of turns. The inlet is tilted relative to an axis perpendicular to a plane in which the coolant channel lies in the substrate support. In one example, a feeding assembly is connected to an inner edge of an outermost turn of the plurality of turns to feed a coolant to the outermost turn of the coolant channel. In another example, a plenum is connected to an outermost turn of the plurality of turns to supply a coolant to the outermost turn of the coolant channel.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
86.
NEGATIVE COEFFICIENT THERMAL EXPANSION MATERIALS FOR DYNAMIC BOW COMPENSATION APPLICATION
Mitigating wafer bow of a semiconductor wafer includes depositing one or more backside layers that compensate for wafer bow caused by one or more frontside layers. Deposition of a backside layer stack may mitigate wafer bow caused by one or more frontside layers, including changes in wafer bow caused by the one or more frontside layers when the wafer is heated. Each of the backside layers may be deposited by a backside deposition apparatus.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 14/22 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
87.
LIQUID-COOLED OPTICAL WINDOW FOR SEMICONDUCTOR PROCESSING CHAMBER
Window/cooling plate assemblies for use with illumination-based radiative heating systems for semiconductor wafer processing tools are provided. Such assemblies may have a window and a cooling plate that are placed adjacent each other; one or more cooling passages may be located within one or both of the window and the cooling plate. The window and cooling plate may be optically transparent to at least some visible light and the window additionally optically transparent to at least some infrared light.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
88.
SYSTEMS AND METHODS FOR USING BINNING TO INCREASE POWER DURING A LOW FREQUENCY CYCLE
A method for achieving uniformity in an etch rate is described. The method includes receiving a voltage signal from an output of a match, and determining a positive crossing and a negative crossing of the voltage signal for each cycle of the voltage signal. The negative crossing of each cycle is consecutive to the positive crossing of the cycle. The method further includes dividing a time interval of each cycle of the voltage signal into a plurality of bins. For one or more of the plurality of bins associated with the positive crossing and one or more of the plurality of bins associated with the negative crossing, the method includes adjusting a frequency of a radio frequency generator to achieve the uniformity in the etch rate.
A direct drive system for providing RF power to a component of a substrate processing system includes a direct drive circuit including a switch and configured to supply RF power to the component. A switch protection module is configured to monitor a load current and a load voltage in a processing chamber, calculate load resistance based on the load current and the load voltage, compare the load resistance to a first predetermined load resistance, and adjust at least one of an RF power limit and an RF current limit of the direct drive circuit based on the comparison.
The present disclosure relates to the use of a metal chelator to treat an exposed photoresist film. In particular embodiments, the metal chelator is employed to remove an interfacial area that is disposed between exposed and unexposed areas or disposed within an exposed area, thereby enhancing patterning quality.
A method of electroplating metal into features of a partially fabricated electronic device on a substrate having high open area portions is provided. The method includes initiating a bulk electrofill phase with a pulse at a high level of current; reducing the current to a baseline current level; and optionally increasing the current in one or more steps until electroplating is complete.
Methods and system are provided for dynamic process control in substrate processing, for example in semiconductor manufacturing applications. Some example systems and methods are provided for advanced monitoring and machine learning in atomic layer deposition (ALD) processes. Some examples also relate to dynamic process control and monitoring for chamber parameter matching and gas line charge times.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
A substrate support for processing a substrate includes a baseplate, a first heater, and a second heater. The first heater is arranged in a first portion of the baseplate. The second heater is arranged in a second portion of the baseplate and partially arranged in the first portion of the baseplate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
Aspects of the present disclosure relate to forming planarized films on substrates. Embodiments include filling gaps with insulating material, including silicon-containing films. Vapor deposition of a flowable film on a substrate is followed by non-contact planarization of the flowable film. Non-contact planarization may include one or more techniques such as subjecting the substrate and deposited film to inertial forces (e.g., by spinning), vibration, or sonic energy.
One example provides a showerhead for a substrate processing tool. The showerhead comprises a faceplate comprising a plurality of outlet holes; a backplate coupled to the faceplate, the backplate comprising a plurality of post access holes; a plenum between the faceplate and backplate; and a plurality of posts connecting the faceplate and the backplate, each post of the plurality of posts extending from the faceplate into a corresponding post access hole in the backplate, each post comprising a post shoulder recessed within the backplate relative to a plenum-facing surface of the backplate, and each post having a post diameter between the faceplate and the post shoulder that is smaller than a hole diameter of a post accommodation portion of the corresponding post access hole into which the post extends.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
97.
VARIABLE FILM DOPANT CONCENTRATIONS FOR LATERAL ETCH RATE CONTROL IN REDUCED TEMPERATURE ETCHING
One disclosed example provides a method of performing cryoetching. The method comprises cooling a substrate in a processing chamber, while cooling the substrate, etching through a first film portion comprising a film material with a first dopant profile, and while cooling the substrate, etching at least partially through a second film portion comprising the film material with a second dopant profile different than the first dopant profile. The first dopant profile causes a different lateral etch rate of the film material than the second dopant profile.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
98.
ION BEAM APERTURE CONTROL FOR ION BEAM SUBSTRATE PROCESSING SYSTEMS
An ion beam processing system includes a plasma source configured to generate plasma. A grid assembly includes a first grid including a first plurality of through holes arranged within a first circular aperture, a second grid including a second plurality of through holes arranged within a second circular aperture, and a third grid including a third plurality of through holes arranged within a third circular aperture. An aperture shaping grid is arranged between the first grid and the plasma source and includes an aperture smaller than the first, second and third circular apertures. The aperture has a shape corresponding a profile of a substrate or a shape corresponding to a spatial plasma distribution, tilted at a predetermined angle relative to a plane transverse to an ion travel direction, projected onto the plane.
Examples are disclosed that relate to a purge plate comprising a shroud. The shroud helps to avoid crosstalk between stations in a multi-station processing chamber. One example provides a processing tool comprising a processing chamber comprising a plurality of stations. The processing tool also comprises a purge plate comprising a chamber-facing surface. The purge plate further comprises a plurality of cutouts configured to accommodate process gas outlets of the plurality of stations. The purge plate further comprises a shroud arranged around at least a portion of a perimeter of a first cutout of a plurality of cutout. The shroud extends away from the chamber-facing surface. The purge plate further comprises a plurality of purge gas holes formed in the chamber-facing surface and the shroud.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A method for coating a component of a plasma processing chamber is provided. An electrolytic oxidation coating is formed over a surface of the component, wherein the electrolytic oxidation coating has a plurality of pores, wherein the electrolytic oxidation coating has a thickness and at least some of the plurality of pores extends through the thickness of the electrolytic oxidation coating. An atomic layer deposition is deposited on the electrolytic oxidation coating. The atomic layer deposition comprises a plurality of cycles, where each cycle comprises flowing a first reactant, wherein the first reactant forms a first reactant layer in the pores of the electrolytic oxidation coating, wherein the first reactant layer extends through the thickness of the electrolytic oxidation coating, stopping the flow of the first reactant, flowing a second reactant, wherein the second reactant reacts with the first reactant layer, and stopping the flow of the second reactant.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
