Averatek Corporation

United States of America

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IPC Class
C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating 9
H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material 7
H05K 3/00 - Apparatus or processes for manufacturing printed circuits 6
H05K 3/42 - Plated through-holes 5
C23C 18/18 - Pretreatment of the material to be coated 4
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NICE Class
42 - Scientific, technological and industrial services, research and design 3
01 - Chemical and biological materials for industrial, scientific and agricultural use 1
06 - Common metals and ores; objects made of metal 1
Status
Pending 10
Registered / In Force 21

1.

ELCAT

      
Serial Number 98508092
Status Pending
Filing Date 2024-04-18
Owner Averatek Corporation ()
NICE Classes  ? 42 - Scientific, technological and industrial services, research and design

Goods & Services

Development of technologies in the nature of chemicals and compositions for the fabrication of electric and electronic circuits

2.

ASYMMETRICAL ELECTROLYTIC PLATING FOR A CONDUCTIVE PATTERN

      
Application Number 18214391
Status Pending
Filing Date 2023-06-26
First Publication Date 2023-10-26
Owner AVERATEK CORPORATION (USA)
Inventor
  • Vinson, Michael Riley
  • Iketani, Shinichi

Abstract

The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.

IPC Classes  ?

  • H05K 3/42 - Plated through-holes
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • C25D 7/00 - Electroplating characterised by the article coated

3.

SYSTEMS AND METHODS FOR MANUFACTURING

      
Application Number 17896893
Status Pending
Filing Date 2022-08-26
First Publication Date 2022-12-29
Owner AVERATEK CORPORATION (USA)
Inventor
  • Vinson, Michael Riley
  • Sharma, Sunity K.
  • Basit, Haris
  • Iketani, Shinichi

Abstract

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.

IPC Classes  ?

  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • C25D 5/02 - Electroplating of selected surface areas
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C25D 5/48 - After-treatment of electroplated surfaces
  • C25D 7/12 - Semiconductors
  • C25D 5/50 - After-treatment of electroplated surfaces by heat-treatment
  • C25D 5/10 - Electroplating with more than one layer of the same or of different metals

4.

Methods and Devices for High Resistance and Low Resistance Conductor Layers Mitigating Skin Depth Loss

      
Application Number 17709047
Status Pending
Filing Date 2022-03-30
First Publication Date 2022-10-06
Owner Averatek Corporation (USA)
Inventor Iketani, Shinichi

Abstract

Methods and devices are contemplated incorporating both high resistance conductive materials (HRCM) and conductors. A HRCM is deposited on a conductor, such that the surface between the HRCM and the conductor is relatively smooth. A dielectric material is then deposited onto an exposed surface of the HRCM. The surface of the HRCM meeting the dielectric material is roughed or otherwise impressed such that it has a Ra of at least 5 μm. The ratio of resistivity between the HRCM and the conductor is at least 50:1 or 100:1, and the ratio of conductivity between the conductive material and the resistive material is at least 9:1, 19:1, or 99:1.

IPC Classes  ?

  • H01B 13/00 - Apparatus or processes specially adapted for manufacturing conductors or cables
  • H01B 5/16 - Non-insulated conductors or conductive bodies characterised by their form comprising conductive material in insulating or poorly conductive material, e.g. conductive rubber

5.

METHODS AND DEVICES FOR HIGH RESISTANCE AND LOW RESISTANCE CONDUCTOR LAYERS MITIGATING SKIN DEPTH LOSS

      
Application Number US2022022627
Publication Number 2022/212565
Status In Force
Filing Date 2022-03-30
Publication Date 2022-10-06
Owner AVERATEK CORPORATION (USA)
Inventor Shinichi, Iketani

Abstract

Methods and devices are contemplated incorporating both high resistance conductive materials (HRCM) and conductors. A HRCM is deposited on a conductor, such that the surface between the HRCM and the conductor is relatively smooth. A dielectric material is then deposited onto an exposed surface of the HRCM. The surface of the HRCM meeting the dielectric material is roughed or otherwise impressed such that it has a Ra of at least 5µm. The ratio of resistivity between the HRCM and the conductor is at least 50:1 or 100:1, and the ratio of conductivity between the conductive material and the resistive material is at least 9:1, 19:1, or 99:1.

IPC Classes  ?

  • H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/14 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material

6.

Coating of nano-scaled cavities

      
Application Number 17492283
Grant Number 11549184
Status In Force
Filing Date 2021-10-01
First Publication Date 2022-01-27
Grant Date 2023-01-10
Owner Averatek Corporation (USA)
Inventor
  • Sharma, Sunity K.
  • Iketani, Shinichi

Abstract

Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.

IPC Classes  ?

  • C23C 18/31 - Coating with metals
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C23C 14/04 - Coating on selected surface areas, e.g. using masks
  • H05K 3/42 - Plated through-holes
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks

7.

THREE DIMENSIONAL CIRCUIT FORMATION

      
Application Number 17373543
Status Pending
Filing Date 2021-07-12
First Publication Date 2021-11-04
Owner AVERATEK CORPORATION (USA)
Inventor
  • Iketani, Shinichi
  • Vinson, Michael Riley
  • Basit, Haris

Abstract

Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.

IPC Classes  ?

  • H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 1/02 - Printed circuits Details

8.

Methods of Plating onto Sacrificial Material and Components Made Therefrom

      
Application Number 17180456
Status Pending
Filing Date 2021-02-19
First Publication Date 2021-08-26
Owner AVERATEK CORPORATION (USA)
Inventor
  • Basit, Haris
  • Vinson, Michael Riley

Abstract

Systems, methods, and devices related to hollow metallic objects are disclosed. A solid sacrificial material is formed in a desired three-dimensional shape, and a precursor is deposited about an exterior surface of the solid sacrificial material. The precursor is used to deposit a first conductor about the exterior surface of the solid sacrificial material, and the solid sacrificial material is then removed. The first conductor assumes the three-dimensional shape, and is substantially hollow after removing the solid sacrificial material. Contemplated hollow metallic objects include waveguides, heat pipes, and vapor chambers.

IPC Classes  ?

  • H01P 11/00 - Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
  • H01P 3/12 - Hollow waveguides
  • C25D 7/04 - TubesRingsHollow bodies
  • C25D 1/02 - TubesRingsHollow bodies

9.

METHODS OF PLATING ONTO SACRIFICIAL MATERIAL AND COMPONENTS MADE THEREFROM

      
Application Number US2021018870
Publication Number 2021/168319
Status In Force
Filing Date 2021-02-19
Publication Date 2021-08-26
Owner AVERATEK CORPORATION (USA)
Inventor
  • Basit, Haris
  • Vinson, Michael Riley

Abstract

Systems, methods, and devices related to hollow metallic objects are disclosed. A solid sacrificial material is formed in a desired three-dimensional shape, and a precursor is deposited about an exterior surface of the solid sacrificial material. The precursor is used to deposit a first conductor about the exterior surface of the solid sacrificial material, and the solid sacrificial material is then removed. The first conductor assumes the three-dimensional shape, and is substantially hollow after removing the solid sacrificial material. Contemplated hollow metallic objects include waveguides, heat pipes, and vapor chambers.

IPC Classes  ?

  • H01P 11/00 - Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
  • H01P 3/12 - Hollow waveguides

10.

CATALYZED METAL FOIL AND USES THEREOF

      
Application Number US2021017802
Publication Number 2021/163440
Status In Force
Filing Date 2021-02-12
Publication Date 2021-08-19
Owner AVERATEK CORPORATION (USA)
Inventor
  • Iketani, Shinichi
  • Sharma, Sunity, K.
  • Borges, Gary, Lawrence
  • Vinson, Michael, Riley

Abstract

Systems, methods, and devices related to catalyzed metal foils are disclosed. Contemplated metal foils have a bottom surface, preferably roughened to Ra of at least 0.1m, bearing a catalyst material. The metal foils are etchable, typically of aluminum or derivative thereof, and is less than 500m thick. Methods and systems for forming circuits from catalyzed metal foils are also disclosed. The catalyst material bearing surface of the metal foil is applied to a substrate and laminated, in some embodiments with a thermoset resin or thermoplastic resin there between or an organic material first coating the catalytic material. The metal foil is removed to expose the catalyst material, and a conductor is plated to the catalyst material.

IPC Classes  ?

  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

11.

A-SAP

      
Serial Number 90803858
Status Pending
Filing Date 2021-06-30
Owner Averatek Corporation ()
NICE Classes  ? 42 - Scientific, technological and industrial services, research and design

Goods & Services

Development of technologies in the nature of chemicals for the fabrication of electric and electronic circuits

12.

ACL

      
Serial Number 90803874
Status Registered
Filing Date 2021-06-30
Registration Date 2023-10-03
Owner Averatek Corporation ()
NICE Classes  ? 06 - Common metals and ores; objects made of metal

Goods & Services

Materials in the nature of laminated aluminum for the manufacture of electric and electronic circuits

13.

LMI

      
Serial Number 90803728
Status Registered
Filing Date 2021-06-30
Registration Date 2025-04-15
Owner Averatek Corporation ()
NICE Classes  ?
  • 01 - Chemical and biological materials for industrial, scientific and agricultural use
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Chemical compositions for use in the manufacture of electronics Development of technologies in the nature of chemicals for the fabrication of electric and electronic circuits

14.

SYSTEMS AND METHODS FOR MANUFACTURING

      
Application Number 16845856
Status Pending
Filing Date 2020-04-10
First Publication Date 2021-02-11
Owner AVERATEK CORPORATION (USA)
Inventor
  • Basit, Haris
  • Vinson, Michael Riley
  • Sharma, Sunity K.
  • Iketani, Shinichi
  • Kadiwala, Divyakant

Abstract

Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject mater further discloses methods of electrolytic plating by controlling surface area of an anode.

IPC Classes  ?

  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • C25D 5/48 - After-treatment of electroplated surfaces
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C25D 5/02 - Electroplating of selected surface areas

15.

Coating of nano-scaled cavities

      
Application Number 16780715
Grant Number 11142825
Status In Force
Filing Date 2020-02-03
First Publication Date 2020-08-06
Grant Date 2021-10-12
Owner AVERATEK CORPORATION (USA)
Inventor
  • Sharma, Sunity K.
  • Iketani, Shinichi

Abstract

Methods, systems, and apparatus for coating the internal surface of nano-scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is converted to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10 nm thick.

IPC Classes  ?

  • H05K 3/42 - Plated through-holes
  • C23C 18/31 - Coating with metals
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C23C 14/04 - Coating on selected surface areas, e.g. using masks
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks

16.

COATING OF NANO-SCALED CAVITIES

      
Application Number US2020016414
Publication Number 2020/160545
Status In Force
Filing Date 2020-02-03
Publication Date 2020-08-06
Owner AVERATEK CORPORATION (USA)
Inventor
  • Sharma, Sunity K.
  • Iketani, Shinichi

Abstract

Methods, systems, and apparatus for coating the internal surface of nano- scale cavities on a substrate are contemplated. A first fluid of high wettability is applied to the nano-scale cavity, filling the cavity. A second fluid carrying a conductor or a catalyst is applied over the opening of the nano-scale cavity. The second fluid has a lower vapor pressure than the first fluid. The first fluid is vaporized to a gas, for example by heating the substrate. The gas exits the nano-scale cavity, creating a negative pressure or vacuum in the nano-scale cavity. The negative pressure draws the second fluid into the nano-scale cavity. The conductor is deposited on the interior surface of the nano-scale cavity, preferably less than 10nm thick.

IPC Classes  ?

  • C23C 18/06 - Coating on selected surface areas, e.g. using masks
  • C23C 18/04 - Pretreatment of the material to be coated
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/18 - Pretreatment of the material to be coated
  • C25D 5/00 - Electroplating characterised by the processPretreatment or after-treatment of workpieces
  • C25D 5/02 - Electroplating of selected surface areas
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

17.

PATTERN FORMATION USING CATALYST BLOCKER

      
Application Number US2020014414
Publication Number 2020/154294
Status In Force
Filing Date 2020-01-21
Publication Date 2020-07-30
Owner AVERATEK CORPORATION (USA)
Inventor
  • Vinson, Michael Riley
  • Sharma, Sunity K.
  • Iketani, Shinichi
  • Chen, Calvin
  • Rahangdale, Shalaka

Abstract

Methods of patterning electroless metals on a substrate are presented. The substrate is covered by a blocking reagent. After formation of a catalyst blocking layer on the substrate, portions of the catalyst blocking layer are removed to form a circuit pattern. A catalyst is placed the surfaces of both the catalyst blocking layer and the exposed substrate. The catalyst blocking layer prevents or reduces catalytic activity of the catalyst. Electroless metal plating is performed to plate a metal at the active portions of the catalyst.

IPC Classes  ?

  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

18.

PATTERN FORMATION USING CATALYST BLOCKER

      
Application Number 16748335
Status Pending
Filing Date 2020-01-21
First Publication Date 2020-07-23
Owner AVERATEK CORPORATION (USA)
Inventor
  • Vinson, Michael Riley
  • Sharma, Sunity K.
  • Iketani, Shinichi
  • Chen, Calvin
  • Rahangdale, Shalaka

Abstract

Methods of patterning electroless metals on a substrate are presented. The substrate is covered by a blocking reagent. After formation of a catalyst blocking layer on the substrate, portions of the catalyst blocking layer are removed to form a circuit pattern. A catalyst is placed the surfaces of both the catalyst blocking layer and the exposed substrate. The catalyst blocking layer prevents or reduces catalytic activity of the catalyst. Electroless metal plating is performed to plate a metal at the active portions of the catalyst.

IPC Classes  ?

  • C23C 18/18 - Pretreatment of the material to be coated
  • H05K 3/04 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
  • H05K 3/02 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating

19.

THREE DIMENSIONAL CIRCUIT FORMATION

      
Application Number US2019066891
Publication Number 2020/131897
Status In Force
Filing Date 2019-12-17
Publication Date 2020-06-25
Owner AVERATEK CORPORATION (USA)
Inventor
  • Iketani, Shinichi
  • Vinson, Michael Riley
  • Basit, Haris

Abstract

Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition

20.

NANO METAL FILM DEPOSITION

      
Application Number 16714036
Status Pending
Filing Date 2019-12-13
First Publication Date 2020-06-18
Owner AVERATEK CORPORATION (USA)
Inventor
  • Sharma, Sunity K
  • Chen, Calvin
  • Iketani, Shinichi
  • Vinson, Michael Riley

Abstract

Devices, systems, and methods are contemplated for depositing metals to the surface of a substrate. A first precursor ink including a metal is applied to a surface of the substrate, and the precursor ink is reduced to deposit the metal to the substrate, preferably by thermal reduction, forming a first metal layer. A second precursor ink having a second metal is then applied to the substrate, at least partially over the first metal layer. The second precursor ink is then reduced, typically by chemical reduction, depositing the second metal over the first metal layer in a globular fashion. Precursor inks are also disclosed having an alkyl metal carboxylate, a cyclic amine, and at least one of an ester, a hydrocarbon, or an ether.

IPC Classes  ?

  • C23C 18/44 - Coating with noble metals using reducing agents
  • C09D 11/037 - Printing inks characterised by features other than the chemical nature of the binder characterised by the pigment
  • C09D 11/033 - Printing inks characterised by features other than the chemical nature of the binder characterised by the solvent
  • C23C 18/40 - Coating with copper using reducing agents

21.

Three dimensional circuit formation

      
Application Number 16717719
Grant Number 11076492
Status In Force
Filing Date 2019-12-17
First Publication Date 2020-06-18
Grant Date 2021-07-27
Owner Averatek Corporation (USA)
Inventor
  • Iketani, Shinichi
  • Vinson, Michael Riley
  • Basit, Haris

Abstract

Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.

IPC Classes  ?

  • H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 1/02 - Printed circuits Details
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits

22.

NANO METAL FILM DEPOSITION

      
Application Number US2019066274
Publication Number 2020/123970
Status In Force
Filing Date 2019-12-13
Publication Date 2020-06-18
Owner AVERATEK CORPORATION (USA)
Inventor
  • Sharma, Sunity K
  • Chen, Calvin
  • Iketani, Shinichi
  • Vinson, Michael Riley

Abstract

Devices, systems, and methods are contemplated for depositing metals to the surface of a substrate. A first precursor ink including a metal is applied to a surface of the substrate, and the precursor ink is reduced to deposit the metal to the substrate, preferably by thermal reduction, forming a first metal layer. A second precursor ink having a second metal is then applied to the substrate, at least partially over the first metal layer. The second precursor ink is then reduced, typically by chemical reduction, depositing the second metal over the first metal layer in a globular fashion. Precursor inks are also disclosed having an alkyl metal carboxylate, a cyclic amine, and at least one of an ester, a hydrocarbon, or an ether.

IPC Classes  ?

  • C23C 18/08 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by thermal decomposition characterised by the deposition of metallic material
  • C23C 18/31 - Coating with metals
  • H05K 3/10 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern

23.

METHOD OF MANUFACTURE FOR EMBEDDED IC CHIP DIRECTLY CONNECTED TO PCB

      
Application Number US2019056548
Publication Number 2020/081691
Status In Force
Filing Date 2019-10-16
Publication Date 2020-04-23
Owner AVERATEK CORPORATION (USA)
Inventor
  • Basit, Haris
  • Vinson, Michael Riley
  • Iketani, Shinichi

Abstract

Methods and systems are contemplated for making portions of electrical circuits with embedded electrical components, and the electrical circuits produced thereby. A layer of dielectric material is deposited over a substrate, and a cavity is formed in the dielectric material. An electrical component (e.g., integrated chip, etc.) is deposited in the cavity and covered by a further dielectric material, embedding the electrical component. Another cavity is formed in the further dielectric material, and a catalyst (e.g., electrolytic deposition catalyst, electroless deposition catalyst, etc.) is deposited over the further dielectric material and at least a portion of the electrical component. A conductor is then plated at the catalyst, preferably contacting the I/O ports of the electrical component.

IPC Classes  ?

  • H05K 3/14 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material
  • H05K 3/40 - Forming printed elements for providing electric connections to or between printed circuits
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components

24.

Method of manufacture for embedded IC chip directly connected to PCB

      
Application Number 16654637
Grant Number 12213258
Status In Force
Filing Date 2019-10-16
First Publication Date 2020-04-16
Grant Date 2025-01-28
Owner Averatek Corporation (USA)
Inventor
  • Basit, Haris
  • Vinson, Michael Riley
  • Iketani, Shinichi

Abstract

Devices and methods for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.

IPC Classes  ?

  • H05K 3/42 - Plated through-holes
  • H05K 1/02 - Printed circuits Details
  • H05K 3/04 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
  • H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
  • H05K 3/46 - Manufacturing multi-layer circuits
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

25.

PATTERNING OF ELECTROLESS METALS

      
Application Number US2019038519
Publication Number 2019/246547
Status In Force
Filing Date 2019-06-21
Publication Date 2019-12-26
Owner AVERATEK CORPORATION (USA)
Inventor
  • Iketani, Shinichi
  • Vinson, Michael Riley

Abstract

The present invention relates to methods and systems that utilize a catalyst or thin metal film by atomic level deposition (ALD) of one or more metals that allows fine traces deposition to the trench formed in a dielectric material, thereby minimizing potential physical damage due to embedded conductor format and making the fine space between traces to prevent electromigration in the traces.

IPC Classes  ?

  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/18 - Pretreatment of the material to be coated
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material

26.

Asymmetrical electrolytic plating for a conductive pattern

      
Application Number 16449202
Grant Number 11716819
Status In Force
Filing Date 2019-06-21
First Publication Date 2019-12-26
Grant Date 2023-08-01
Owner Averatek Corporation (USA)
Inventor
  • Vinson, Michael Riley
  • Iketani, Shinichi

Abstract

The present invention relates to methods and systems for deposition of metal conductors using asymmetrical electrolytic plating, in which one surface (e.g., top) of a substrate is coated with an electrical conductor, and an opposite (e.g., bottom, or other) surface of which is not coated. A channel is formed between the two sides of the substrate, passing through the substrate and, in some embodiments, passing through the conductor. Electrolytic plating is performed such that metal is deposited from the edge of the conduct proximal to the channel, along the side walls of the channel, and up to, and in some embodiments on to, the other side of the substrate. Use of etching or plate resist layers are also contemplated.

IPC Classes  ?

  • H05K 3/42 - Plated through-holes
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits
  • C25D 7/00 - Electroplating characterised by the article coated

27.

MAXIMIZING SURFACES AND MINIMIZING PROXIMITY EFFECTS FOR ELECTRIC WIRES AND CABLES

      
Application Number US2019016305
Publication Number 2019/152813
Status In Force
Filing Date 2019-02-01
Publication Date 2019-08-08
Owner AVERATEK CORPORATION (USA)
Inventor Basit, Haris

Abstract

A cable for propagating high frequency signals comprises a first insulated hollow conductor and a second insulated hollow conductor in a braided arrangement to form the cable. The braided arrangement distributes the first and second hollow conductors such that the cable is equalized.

IPC Classes  ?

  • H01B 7/30 - Insulated conductors or cables characterised by their form with arrangements for reducing conductor losses when carrying AC, e.g. due to skin effect
  • H01B 7/00 - Insulated conductors or cables characterised by their form
  • H01B 7/02 - Disposition of insulation
  • H01B 3/30 - Insulators or insulating bodies characterised by the insulating materialsSelection of materials for their insulating or dielectric properties mainly consisting of organic substances plasticsInsulators or insulating bodies characterised by the insulating materialsSelection of materials for their insulating or dielectric properties mainly consisting of organic substances resinsInsulators or insulating bodies characterised by the insulating materialsSelection of materials for their insulating or dielectric properties mainly consisting of organic substances waxes

28.

PRINTABLE SURFACE TREATMENT FOR ALUMINUM BONDING

      
Application Number US2018026300
Publication Number 2018/187599
Status In Force
Filing Date 2018-04-05
Publication Date 2018-10-11
Owner AVERATEK CORPORATION (USA)
Inventor
  • Vinson, Michael Riley
  • Chen, Calvin
  • Kadiwala, Divyakant P.
  • Sharma, Sunity K.

Abstract

Compositions and methods for coupling metals to aluminum surfaces are provided. The compositions are prepared as aqueous solutions or suspensions, and can be applied to the aluminum surface using conventional printing techniques. Rheology of the printable composition can be adjusted to provide a gel or a cream. Curing steps, if necessary, are performed at low temperatures that are compatible with plastic/polymer components of mass produced devices, such as aluminum RFID antennae.

IPC Classes  ?

  • C09D 11/033 - Printing inks characterised by features other than the chemical nature of the binder characterised by the solvent
  • C09D 11/03 - Printing inks characterised by features other than the chemical nature of the binder
  • B05D 7/24 - Processes, other than flocking, specially adapted for applying liquids or other fluent materials to particular surfaces or for applying particular liquids or other fluent materials for applying particular liquids or other fluent materials
  • B05D 7/14 - Processes, other than flocking, specially adapted for applying liquids or other fluent materials to particular surfaces or for applying particular liquids or other fluent materials to metal, e.g. car bodies

29.

Patterning of electroless metals by selective deactivation of catalysts

      
Application Number 15632216
Grant Number 10034386
Status In Force
Filing Date 2017-06-23
First Publication Date 2017-12-07
Grant Date 2018-07-24
Owner AVERATEK CORPORATION (USA)
Inventor
  • Reddy, Mihir
  • Vinson, Michael Riley
  • Sharma, Sunity K.

Abstract

Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.

IPC Classes  ?

  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • C23C 18/18 - Pretreatment of the material to be coated
  • C23C 18/00 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating
  • C23C 18/20 - Pretreatment of the material to be coated of organic surfaces, e.g. resins
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/38 - Coating with copper
  • C23C 18/32 - Coating with one of iron, cobalt or nickelCoating with mixtures of phosphorus or boron with one of these metals
  • C23C 18/30 - Activating

30.

Patterning of electroless metals by selective deactivation of catalysts

      
Application Number 14918227
Grant Number 09699914
Status In Force
Filing Date 2015-10-20
First Publication Date 2016-04-21
Grant Date 2017-07-04
Owner AVERATEK CORPORATION (USA)
Inventor
  • Reddy, Mihir
  • Vinson, Michael Riley
  • Sharma, Sunity K.

Abstract

Methods and devices for patterning electroless metals on a substrate are presented. An active catalyst layer on the substrate can be covered with a patterned mask and treated with a deactivating chemical reagent, which deactivates the catalyst layer not covered by the mask. Once the patterned mask is removed, the electroless metal layer can be placed to have a patterned electroless metals. Alternatively, a substrate can be coated with a blocking reagent in a pattern first to inhibit formation of the catalyst layer before a catalyst layer can be placed over the blocking agent layer and then electroless metal layer is placed on the catalyst layer. The pattern of the blocking reagent acts as a negative pattern of the final conductive line pattern.

IPC Classes  ?

  • H05K 1/09 - Use of materials for the metallic pattern
  • H05K 3/18 - Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
  • C23C 18/00 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coatingContact plating

31.

Indium-less transparent metalized layers

      
Application Number 12721557
Grant Number 08895874
Status In Force
Filing Date 2010-03-10
First Publication Date 2014-11-25
Grant Date 2014-11-25
Owner Averatek Corp. (USA)
Inventor
  • Sharma, Sunity Kumar
  • Beavers, Jr., Alex Newsom
  • Furst, Thomas

Abstract

Thin indium-less “optically porous” layers adapted to replace traditional ITO layers are provided herein. A thin metalized film adapted to carry an electrical charge can include a dense pattern of small openings to allow the transmission of light to or from an underlying semiconductor material. The pattern of openings can create a regular or irregular grid pattern of low aspect ratio fine-line metal conductors. Creation of this optically porous metalized film can include the printing of a catalytic precursor material, such as palladium in solution in a pattern on a substrate, drying or curing the catalytic precursor, and the deposition of a thin layer of metal, such as copper on the dried precursor to form the final conductive and optically porous film.

IPC Classes  ?