A sensor includes an array of optically active pixels disposed on a semiconductor die. The array of optically active pixels includes at least one pixel (P1) configured to detect short wavelength infrared radiation (SWIR), and at least one pixel (P2) configured to detect visible light incident on the sensor.
B82Y 20/00 - Nanooptics, e.g. quantum optics or photonic crystals
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
An imager is configured for capturing short-wavelength infrared (SWIR) images. The imager includes an optical sensor die including a semiconductor substrate, at least one device fabricated in the semiconductor substrate, a layer of colloidal quantum dots (CQD) photodetectors disposed above of the semiconductor substrate, and an intermetal dielectric (IMD) layer disposed on a bottom surface of the semiconductor substrate. The IMD layer includes at least a metal level of a redistribution layer of the optical sensor die.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
3.
THERMAL MISMATCH REDUCTION IN SEMICONDUCTOR DEVICE MODULES
In some aspects, the techniques described herein relate to a semiconductor device assembly including: a direct-bonded-metal (DBM) substrate including: a ceramic layer; a first metal layer disposed on a first surface of the DBM substrate, the first metal layer having a uniform thickness; and a second metal layer disposed on a second surface of the DBM substrate opposite the first surface, the second metal layer including: a first portion having a first thickness; and a second portion having a second thickness, the second thickness being greater than the first thickness, the second portion of the second metal layer including a metal alloy having a coefficient of thermal expansion (CTE) in a range of 7 to 11 parts-per-million per degrees Celsius (ppm/° C.); and a semiconductor die having a first surface coupled with the second portion of the second metal layer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
4.
Imaging System with Rolling Shutter Readout and an Electronic Shutter
A system may include an image sensor, an electronic shutter, a light source, and a lens module. The imaging system may include control circuitry configured to selectively control one or more of the image sensor, the electronic shutter, and the light source. In particular, the electronic shutter may be controlled in synchronization with the image sensor. The electronic shutter may have a maximum transparency during a common time interval for all rows, while all of the rows of imaging pixels in the image sensor are integrating. The electronic shutter may have a minimum transparency while more than one but less than all of the plurality of rows of imaging pixels are integrating. Synchronizing the electronic shutter with the image sensor in this manner may achieve global shutter like performance with a rolling shutter image sensor.
In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
An illustrative fault detection system may include an input node, a transport circuit, and a comparison circuit. The input node may electrically connect to a row driver that produces, on the input node, a row driver voltage having one of a plurality of analog voltage levels. The transport circuit may be configured to transport, when the row driver is selected from a plurality of row drivers, the row driver voltage to a monitoring node shared by a plurality of fault detection systems including the fault detection system. The comparison circuit may be shared by the plurality of fault detection systems and may be configured to generate a digital output by conditioning a voltage from the monitoring node, performing a comparison between the conditioned voltage and a reference voltage, and latching the digital output based on the comparison. Corresponding systems, integrated circuits, and methods are also disclosed.
Devices and methods are disclosed for facilitating faster switching of silicon-based and silicon carbide-based power transistors suitable for use in electric vehicles. The disclosed techniques can minimize the impact on turn-on and turn-off losses, while reducing gate voltage and drain voltage spikes during device switching. A fast/slow cell design incorporating shielded gate MOSFETs controls gate-to-drain capacitance and gate resistances to optimize suppression of voltage overshoot.
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
8.
HIGH DNAMIC RANGE OPTICAL SENSOR USING TRENCH CAPACITORS WITH SIDEWALL STRUCTURES
An optical sensor and included pixel circuits of an array of pixel circuits are described. Each pixel circuit may include a microlens, a color filter disposed adjacent the microlens, and an epitaxial substrate layer disposed adjacent the color filter opposite the microlens. An isolation trench may be formed in the epitaxial substrate layer to provide a trench capacitor for the pixel circuit, and having sidewalls with sidewall recesses formed therein that increase a surface area, and therefore a capacitance, of the trench capacitor.
A method of operating an image sensor having a pixel array is provided. The method can include outputting a row control signal to a row of pixels in the pixel array at a first time, sampling a first output signal from a first pixel in the row of pixels at a second time, and sampling a second output signal from a second pixel in the row of pixels at a third time after the second time. The row control signal can arrive at the first pixel in the row of pixels a first row propagation delay after the first time. The row control signal can arrive at the second pixel in the row of pixels a second row propagation delay after the first time. The difference between the second and third times may be equal to the difference between the first and second row propagation delays.
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H04N 25/441 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by partially reading an SSIS array by reading contiguous pixels from selected rows or columns of the array, e.g. interlaced scanning
H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors
A converter circuit may require sensing an average current as feedback for regulating the average current supplied to a load. Sensing the average current may be inaccurate due to the non-ideal behavior of devices in the converter circuit. The disclosed circuits and methods help to improve the accuracy of the sensed average current by ignoring portions of a PWM cycle. Some of the ignored portions are based on a peak threshold for a rising current of a PWM cycle and a valley threshold for a falling current of a PWM cycle. The peak threshold and the valley threshold may be adjusted to control the average current and the switching frequency of the converter circuit.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
Implementations of a packaging system may include a wafer; and a curvature adjustment structure coupled thereto where the curvature adjustment structure may be configured to alter a curvature of a largest planar surface of the wafer.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
B21D 11/10 - Bending specially adapted to produce specific articles, e.g. leaf springs
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A high dynamic range (HDR) imaging system is disclosed in which the speed of digitizing and storing image data is increased by efficient signal management, without a need for additional resources. By managing the data transfer process in a successive approximation register (SAR) analog-to-digital converter (ADC) circuit, using techniques such as synchronization of control signals, multi-stage memory, and time-multiplexing, higher frame rates can be achieved without relying on increasing bandwidth with additional channels, or increasing power consumption or complexity of the imaging system.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H04N 25/709 - Circuitry for control of the power supply
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
Systems for power conversion, multistage power converters, and methods for operating multistage power converters. The system includes a multistage power converter and a controller. The multistage power converter includes a first stage circuit and a second stage circuit. The first stage circuit includes a first pair of field-effect transistors (FETs), a first output inductor, and a first capacitor coupled between the first pair of FETs. The second stage circuit includes a second pair of FETs, a second output inductor, and a second capacitor coupled between the second pair of FETs. During a first on-time, the controller is configured to turn on the first stage circuit and to couple the first capacitor's cathode terminal to the second capacitor's anode terminal. During a second on-time, the controller is configured to turn on the second stage circuit and to couple the second capacitor's cathode terminal to the first capacitor's anode terminal.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
14.
CURRENT-BASED BUILT-IN SELF-TEST FOR CIRCUIT COMPONENTS ARRANGED IN VARIED CONFIGURATIONS
A self-testing circuit may transmit a first test vector to a test block of a plurality of test blocks in the self-testing circuit. The first test vector may correspond to a first configuration for a set of components in the test block. The self-testing circuit may measure a first current drawn by the test block when the set of components is in the first configuration. The self-testing circuit may also transmit a second test vector to the test block, the second test vector corresponding to a second configuration for the set of components. The self-testing circuit may measure a second current drawn by the test block when the set of components is in the second configuration. Based on a comparison between the first and second currents, the self-testing circuit may detect a defect in the test block.
Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.
H10D 30/62 - Fin field-effect transistors [FinFET]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
16.
SEMICONDUCTOR PACKAGE WITH WETTABLE FLANK AND RELATED METHODS
Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
An optical sensor module includes a transparent lid spaced apart from an optical sensor die by a protective dam. The protective dam can be formed from an insulating material that blocks moisture and contaminants from reaching the optical sensor die. The protective dam can be formed as a notched or grooved recess that extends into the substrate at a designated singulation point and forms a support for the transparent lid. The transparent lid protects the optical sensor die while permitting light to pass through and reach the optical sensors. In some implementations, the optical sensor die is surrounded by an air cavity. A solder mask with a redistribution layer protects a lower surface of the substrate. The solder mask may wrap around the substrate, or a planar solder mask can be used.
A sensor subsystem is disclosed. The sensor subsystem includes a sensor coupled to an interface circuit. The sensor may generate a fine sensor signal and a coarse sensor signal based on a rotation of the sensor. The interface circuit may generate first and second absolute angle values based on the fine and coarse sensor signals, respectively. The interface circuit may additionally generate an output angle value using a difference between the first and second absolute angle values.
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
A semiconductor device module for use in high-power applications incorporates a lead frame and a wire bonding scheme designed to improve reliability and reduce cost. A combination of aluminum wire bonds and gold wire bonds can be used to connect dies of different sizes, formed on different substrates, or that use different bonding materials to a shared underlying structure. Instead of making direct connections between the dies, the different types of wire bonds can be coupled to an intermediate floating pad.
A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
21.
JET IMPINGEMENT COOLING WITH BYPASS FLUID PORTION FOR HIGH POWER SEMICONDUCTOR DEVICES
A jet impingement cooling assembly for semiconductor devices includes an inlet chamber configured to receive an inlet fluid flow, and a jet plate having a plurality of jet nozzles formed therein and coupled to the inlet chamber, and positioned to direct a jet fluid portion of the inlet fluid flow from the inlet chamber through the jet nozzles. The jet impingement cooling assembly may further include an outlet chamber positioned to receive the jet fluid portion once the jet fluid portion has passed through the jet nozzles, and at least one bypass nozzle in fluid connection with the inlet chamber and configured to direct a bypass fluid portion of the inlet fluid flow into the outlet chamber with the jet fluid portion to thereby define an outlet fluid flow.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
22.
CHARGE-TO-VOLTAGE CONVERSION CIRCUIT WITH INLINE AMPLIFICATION
An illustrative charge-to-voltage conversion circuit includes a charge detection transistor, a biasing current source, and an inline amplifier stage. The charge detection transistor is powered by a supply voltage and is configured, when activated by a bias current, to produce an output voltage based on a charge received at a gate of the charge detection transistor. The biasing current source is electrically connected to the charge detection transistor and configured to generate the bias current to activate the charge detection transistor. The inline amplifier stage includes an amplifier transistor and is positioned between the charge detection transistor and the biasing current source. The inline amplifier stage is configured to use the bias current generated by the biasing current source to activate the amplifier transistor to amplify the output voltage on an output voltage node of the charge-to-voltage conversion circuit. Corresponding circuits and methods are also disclosed.
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
H04N 25/74 - Circuitry for scanning or addressing the pixel array
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
H04N 25/779 - Circuitry for scanning or addressing the pixel array
Implementations of a semiconductor device may include a first surface having a first perimeter; and a second surface opposite the first surface, the second surface having a second perimeter, the first perimeter being greater than the second perimeter. The semiconductor device may include a sidewall extending between the first surface and the second surface, the sidewall defining an overhang where a width of the overhang extends between the first perimeter and the second perimeter, and a thickness of the overhang is less than a thickness of the semiconductor device. The overhang may be configured to keep epoxy away from the first side.
Implementations of a method of singulating a plurality of die from a substrate may include removing a die stack coupled to a substrate in a die street by etching the die stack to expose a top surface of a substrate material of the substrate in the die street. The first width of the top surface of the substrate material may be exposed. The method also may include forming a plurality of die by singulating, using a kerf width of a second width, the exposed substrate material of the substrate in the die street. The second width may be smaller than the first width.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
A method includes disposing a first direct bonded metal (DBM) substrate substantially parallel to a second DBM substrate a distance apart to enclose a space. The method further includes disposing at least a semiconductor die in the space, and bonding the semiconductor die to the first DBM substrate using a first adhesive layer without an intervening spacer block between the semiconductor die and the first DBM substrate, and bonding the semiconductor die to the second DBM substrate using a second adhesive without an intervening spacer block between the semiconductor die and the second DBM substrate.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
26.
JET IMPINGEMENT COOLING WITH BYPASS FLUID PORTION FOR HIGH POWER SEMICONDUCTOR DEVICES
A jet impingement cooling assembly for semiconductor devices includes an inlet chamber configured to receive an inlet fluid flow, and a jet plate having a plurality of jet nozzles formed therein and coupled to the inlet chamber, and positioned to direct a jet fluid portion of the inlet fluid flow from the inlet chamber through the jet nozzles. The jet impingement cooling assembly may further include an outlet chamber positioned to receive the jet fluid portion once the jet fluid portion has passed through the jet nozzles, and at least one bypass nozzle in fluid connection with the inlet chamber and configured to direct a bypass fluid portion of the inlet fluid flow into the outlet chamber with the jet fluid portion to thereby define an outlet fluid flow.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
27.
METHOD AND SYSTEM TO IMPROVE UNIFORMITY IN POWER FET ARRAYS
A vertical, fin-based field effect transistor (FinFET) device includes an array of individual FinFET cells. The array includes a plurality of rows and columns of separated fins. Each of the separated fins is in electrical communication with a source contact. The vertical FinFET device also includes one or more rows of first inactive fins disposed on a first set of sides of the array of individual FinFET cells, one or more columns of second inactive fins disposed on a second set of sides of the array of individual FinFET cells, and a gate region surrounding the individual FinFET cells of the array of individual FinFET cells, the first inactive fins, and the second inactive fins.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
29.
METHODS FOR MANUFACTURING POWER SEMICONDUCTOR DEVICES AND POWER SEMICONDUCTOR STRUCTURES
A method of manufacturing a semiconductor device (10,30,30A,30B,30C,110,211) includes providing a body of semiconductor material (11,111) including a substrate (12,112) and a semiconductor region (14,114). A spacer (21B,210A,121B,221B) is provided over the semiconductor region. A first feature (28A,31A 33A,123A,123B,123C,180A,223A,223B,223C) is provided as part of the body of semiconductor material self-aligned to a first side wall of the spacer and a second feature (28B,31B,33A,123A,123B,123C,180B,223A,223B,223C) is provided as part of the body of semiconductor material self-aligned to a second side wall of the spacer. Part of the semiconductor region is interposed between the first feature and the second feature, the first feature and the second feature can be doped regions or recesses, and the portion of the semiconductor region interposed between the first feature and the second feature comprises a channel region (45) of a JFET device or a JFET region (450) of an insulated gate field effect transistor device.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
H01L 21/337 - Field-effect transistors with a PN junction gate
30.
PROPAGATION DELAY COMPENSATION AND INTERPOLATION FILTER
Measurement systems, methods for operating an angular sensor interface, and angular sensor interfaces. The measurement system includes a position sensor, a signal processor, and a propagation delay compensation filter. The position sensor is configured to generate analog signals. The signal processor is configured to generate position signals from the analog signals. The propagation delay compensation filter is configured to generate low-pass filtered position signals from the position signals, and calculate speed signals from the low-pass filtered position signals. The propagation delay compensation filter is further configured to generate low-pass filtered speed signals from the speed signals, and calculate acceleration signals from the low-pass filtered speed signals. The propagation delay compensation filter is further configured to generate low-pass filtered acceleration signals from the acceleration signals. The propagation delay compensation filter is also configured to produce compensated angular position signals from the low-pass filtered speed and acceleration signals.
G01B 7/00 - Measuring arrangements characterised by the use of electric or magnetic techniques
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
G01D 5/14 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage
A power converter includes an input coupled to an inductor, a first switch coupled to a first comparator, and a second switch coupled to a second comparator. The power converter also includes a pulse comparison counter coupled to the first comparator and the second comparator and a synchronous rectifier (SR) calculator coupled to the pulse comparison counter. The synchronous rectifier calculator is operable to modify a conduction time of the first switch during a first AC half-cycle and modify a conduction time of the second switch during a second AC half-cycle.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
32.
METHODS FOR MANUFACTURING POWER SEMICONDUCTOR DEVICES AND POWER SEMICONDUDCTOR STRUCTURES
A method of manufacturing a semiconductor device includes providing a body of semiconductor material including a substrate and a semiconductor region over the substrate. The method includes providing a spacer over the semiconductor region. The method includes providing a first feature as part of the body of semiconductor material self-aligned to a first side wall of the spacer and providing a second feature as part of the body of semiconductor material self-aligned to a second side wall of the pacer. A portion of the semiconductor region is laterally interposed between the first feature and the second feature, the first feature and the second feature can be doped regions or recesses, and the portion of the semiconductor region laterally interposed between the first feature and the second feature comprises a channel region of a JFET semiconductor device or a JFET region of an insulated gate field effect transistor device.
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
An image sensor may include an image sensor pixel array. The image sensor pixel array may include active image sensor pixels that generate image data based on incident light and reference pixels that are optically black for generating reference data for noise compensation. Sets of reference pixels in the same row may be coupled to respective shared readout paths in a source follower binning configuration. The shared readout path may be could to downstream readout circuits. The use of shared readout paths for the reference pixels can reduce the number of reference pixel readout paths. If desired, pixel circuitry may be implemented on a first die, while readout circuitry and at least a portion of the reference pixel readout paths may be implemented on a second die mounted to the first die.
H04N 25/671 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
35.
Backside Illumination Global Shutter Image Sensor with Trench Storage Gate
An image sensor may include an array of global shutter image pixels arranged in rows and columns. Each global shutter image pixel may include a storage gate implemented as a trench transistor. The storage gate may be at least partially covered by a corresponding backside deep trench isolation structure. The deep trench isolation structure can be filled with light-shielding material. Configured in this way, the global shutter image pixel exhibits improved global shutter efficiency.
In a general aspect, a package includes a semiconductor die disposed between a first high voltage isolation carrier and a second high voltage isolation carrier. The semiconductor die is thermally coupled to the first high voltage isolation carrier. The package also includes a molding material disposed in a space between the semiconductor die and the first high voltage isolation carrier, and a conductive spacer disposed between the semiconductor die and the second high voltage isolation carrier. The conductive spacer is thermally coupled to semiconductor die and to the second high voltage isolation carrier. A longitudinal dimension of the conductive spacer is greater than a longitudinal dimension of the semiconductor die. The molding material encapsulates the semiconductor die and the conductive spacer.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
An inductive sensor may track an angle of a movable element. In some cases, it is desirable to operate the inductive sensor using battery power so that turns are tracked properly even when power is lost. The disclosed inductive sensor includes circuitry to conserve power, such as a non-resonant driver that allows for fast measurements without wasting energy and a difference encoder that can estimate the angle within a range without the need for digitization and complicated processing.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
G01P 3/44 - Devices characterised by the use of electric or magnetic means for measuring angular speed
One illustrative integrated circuit manufacturing method includes: a sequence of process operations to provide bipolar devices, CMOS (complementary metal oxide semiconductor) devices, and DMOS (double-diffused metal oxide semiconductor) devices on a monolithic integrated circuit substrate; and further operations to provide nonvolatile memory cells on the monolithic integrated circuit substrate with no additional thermal budget, with no additional implant operations, and with only a single additional mask, relative to the sequence of process operations. The sequence of process operations includes one or more ion implantation operations to form wells and/or buried layers for the bipolar devices, the CMOS devices, and the DMOS devices, on a shared integrated circuit substrate; an annealing operation to heal damage from the one or more ion implantation operations before forming sources and drains for the CMOS and DMOS devices; and gate formation operations to form gates for the CMOS devices and the DMOS devices.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H10B 69/00 - Erasable-and-programmable ROM [EPROM] devices not provided for in groups , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Implementations of a method of making a silicon-on-insulator (SOI) die may include forming a plurality of grooves in a second side of a silicon substrate, depositing an insulative layer directly to the second side of the silicon substrate, the insulative layer filling the plurality of grooves, the silicon substrate comprising a first side opposite the second side, and singulating the silicon substrate through the plurality of grooves into a plurality of SOI die. The insulative layer may be coupled to silicon only through the second side of the silicon substrate.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H10D 89/00 - Aspects of integrated devices not covered by groups
An oversampling analog-to-digital converter (ADC) may include a quantizer that adds an offset error to each oversampling sample. If not reduced, the offset error may limit the performance of the ADC. The existing methods to eliminate the offset may increase a circuit size and slow the operation of the ADC. An oversampling ADC that can reduce, or remove, the offset error is disclosed. The disclosed ADC can be small and fast and still remove the offset. Accordingly, the disclosed ADC may be used in high performance applications, such as a high-speed image sensor.
Implementations of a method of making a silicon-on-insulator (SOI) die may include forming a plurality of grooves in a second side of a silicon substrate, depositing an insulative layer directly to the second side of the silicon substrate, the insulative layer filling the plurality of grooves, the silicon substrate comprising a first side opposite the second side, and singulating the silicon substrate through the plurality of grooves into a plurality of SOI die. The insulative layer may be coupled to silicon only through the second side of the silicon substrate.
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
42.
NONLINEAR, DISCRETE TIME CONTROL OF POWER FACTOR CORRECTION POWER CONVERTER
An apparatus for controlling a power converter operable to receive a cyclically varying input signal includes a discrete-time, on-time generator coupled to the power converter and operable to regulate an output voltage of the power converter and a controller operable to compare the output voltage of the power converter against a voltage range or threshold to: obtain a comparison result in synchronization with the cyclically varying input signal and select one of a plurality of operation levels of the discrete-time, on-time generator in response to the comparison result. The plurality of operation levels may include a linear, discrete-time operation level and a nonlinear, discrete-time operation level. The nonlinear, discrete-time operation level may include determining a power deficiency of a bulk capacitor and adjusting a width of an on-time pulse accordingly.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 7/5388 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with asymmetrical configuration of switches
43.
FREQUENCY CONTROLLED MULTIPHASE CURRENT SOURCE SYSTEM
A voltage regulator is described for use in high power delivery applications, including notebook computers, ultra-book computers, and electric vehicles. The voltage regulator is configured with multiphase current and constant on-time (COT) control. The voltage regulator can be configured with adaptive on-time control with zero undershoot in the output voltage signal, in response to a dynamic load. The multiphase current source can be configured with adjustable current share gain to provide a democratic current balance method. A method of operating the voltage regulator can be compatible with analog, digital, and hybrid implementations.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/084 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters using a control circuit common to several phases of a multi-phase system
An optical sensor module includes a glass lid that protects the sensor die, and a perimeter frame to secure the glass lid. The perimeter frame can hold the glass lid in a position suspended above the sensor die and spaced apart from the sensor die by an air gap. An epoxy seals the glass lid between the perimeter frame and the package. The addition of the perimeter frame creates a longer path length for moisture and gas penetration, preventing moisture from reaching the sensor die, while allowing light to enter the sensor die.
A package includes a semiconductor die attached to a die attach pad by a first sinter bond. The package further includes a clip having a first end and a second end. The first end of the clip is attached to a device contact pad on the semiconductor die by a second sinter bond and the second end of the clip is attached to a post of a lead by a joint. The package further includes a mold body encapsulating the semiconductor die.
Implementations of semiconductor packages may include: a substrate having a first side and a second side and a die having an active area on a second side of the die. A first side of the die may be coupled to the second side of the substrate. The semiconductor package may also include a glass lid having a first side and a second side. The glass lid may be coupled over a second side of the die. The semiconductor package may include a first and a second molding compound and one or more cushions positioned between a first side of the glass lid and a portion of the first molding compound. The second molding compound may be coupled to the substrate and the around the die and the glass lid.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
47.
STRUCTURE AND METHOD OF FORMING LOW-COST THICK SOI WAFER
A semiconductor substrate includes a handle wafer, an oxide layer formed on the handle wafer, and a device layer formed or disposed on the oxide layer. The device layer includes a first epitaxial silicon layer bonded to the oxide layer formed on the handle wafer, a layer of compensated silicon crystalline material formed or disposed on the first epitaxial silicon layer, and a second epitaxial silicon layer formed on the layer of compensated silicon crystalline material. The compensated silicon crystalline material includes a Czochralski silicon substrate.
Image sensors, imaging systems, and methods for eliminating blooming artifacts in high dynamic range imaging. The image sensor includes a pixel array and a controller. The controller is configured to detect that a first pixel signal is at or below a barrier value. The first pixel signal is generated during a first exposure. The controller is also configured to compare neighboring pixel signals to the barrier value. The controller is further configured to determine a first image value for the center pixel based on a second pixel signal when at least one of the neighboring pixel signals is above the barrier value. The second pixel signal is generated during a second exposure that is shorter than the first exposure. The controller is also configured to set the first image value to the first pixel signal when each of the neighboring pixel signals is at or below the barrier value.
H04N 25/589 - Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields with different integration times, e.g. short and long exposures
H04N 23/73 - Circuitry for compensating brightness variation in the scene by influencing the exposure time
H04N 23/741 - Circuitry for compensating brightness variation in the scene by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
H04N 25/59 - Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
H04N 25/621 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/00 - Details of semiconductor or other solid state devices
Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/00 - Details of semiconductor or other solid state devices
51.
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRANSISTOR STRUCTURE
In an aspect, an electronic device can include a substrate, a semiconductor layer overlying the substrate and including a mesa adjacent to a trench, and a doped region within the semiconductor layer. The doped region extends across an entire width of the mesa and contacts the lowermost point of the trench. A charge pocket can be located between an elevation of the peak concentration of the doped region and an elevation of the upper surface of the substrate. In another aspect, a process includes patterning a semiconductor layer to define a trench, forming a sacrificial layer within the trench, removing the sacrificial layer from a bottom of the trench, doping a portion of the semiconductor layer that is along the bottom of the trench while a remaining portion of the sacrificial layer is along a sidewall of the trench.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
H10D 64/00 - Electrodes of devices having potential barriers
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
53.
HOUSINGS FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS
A casing for semiconductor packages that includes a plurality of press-fit pins is disclosed. Specific implementations include a shaft including a first end and a second end. The first end may include a head. The press-fit pin may include a bonding portion included at the second end. The bonding portion may include a first section extending substantially perpendicular from a longest length of the shaft. The bonding portion may also include an angled section coupled to a bonding foot. The bonding foot may be configured to be ultrasonically welded to a substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01R 12/58 - Fixed connections for rigid printed circuits or like structures characterised by the terminals terminals for insertion into holes
H01R 43/02 - Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for soldered or welded connections
Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/051 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
55.
IMMERSION DIRECT COOLING MODULES AND RELATED METHODS
Implementations of a semiconductor package may include one or more semiconductor die directly coupled to only a direct leadframe attach (DLA) leadframe including two or more leads; and a coating covering the one or more semiconductor die and the DLA leadframe where when the semiconductor package is coupled into an immersion cooling enclosure, the coating may be in contact with a dielectric coolant while the two or more leads extend out of the immersion cooling enclosure.
H01L 23/44 - Arrangements for cooling, heating, ventilating or temperature compensation the complete device being wholly immersed in a fluid other than air
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
Implementations of methods of forming a plurality of semiconductor die may include forming a damage layer beneath a surface of a die street in a semiconductor substrate, singulating the semiconductor substrate along the die street into a plurality of semiconductor die, and removing one or more particulates in the die street after singulating through applying sonic energy to the plurality of semiconductor die.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
B23K 26/00 - Working by laser beam, e.g. welding, cutting or boring
B23K 26/53 - Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
57.
METHOD AND SYSTEM FOR CONTROL OF SIDEWALL ORIENTATION IN VERTICAL GALLIUM NITRIDE FIELD EFFECT TRANSISTORS
A III-N-based vertical transistor includes a III-N substrate, a source, a drain, and a channel comprising a III-N crystal material and extending between the source and the drain. The channel includes at least one sidewall surface aligned ±0.3° with respect to an m-plane of the III-N crystal material. The III-N-based vertical transistor also includes a gate electrically coupled to the at least one sidewall surface of the channel.
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
58.
HARMONIC DISTORTION REDUCTION IN INDUCTIVE POSITION SENSORS
An inductive position sensor can include a first target coil, included in a target, and including a first outer lobe that has a size based on a first shift ratio of a harmonic period of a receiver coil, and a first inner lobe having a size based on a second shift ratio of the harmonic period where the harmonic period corresponds with a harmonic and the first shift ratio is different from the second shift ratio. The inductive position sensor also include a second target coil including a second outer lobe having a size based on the second shift ratio, and a second inner lobe having a size based on the first shift ratio.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
59.
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO INTERCONNECT STRUCTURES
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
H10F 99/00 - Subject matter not provided for in other groups of this subclass
60.
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO INTERCONNECT STRUCTURES
A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
H10F 99/00 - Subject matter not provided for in other groups of this subclass
61.
LEADLESS SEMICONDUCTOR PACKAGES, LEADFRAMES THEREFOR, AND METHODS OF MAKING
A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
63.
SLOTTED CLIPS FOR REDUCTION OF MOLDING COMPOUND DELAMINATION
In a general aspect, a semiconductor device assembly includes a substrate, a semiconductor die coupled to the substrate, and a conductive clip coupled to the semiconductor die. The conductive clip is arranged along a longitudinal axis and a transverse axis. The conductive clip has a length along the longitudinal axis, a width along the transverse axis, and a slot defined therethrough. The slot has a length along the longitudinal axis that is greater than or equal to seventy percent of the length of the conductive clip along the longitudinal axis. The slot has a width along the transverse axis that is greater than or equal to thirty percent of the width of the conductive clip along the transverse axis.
An image sensor pixel is provided that includes a single-photon avalanche diode (SPAD), an analog counter coupled to a cathode terminal of the SPAD, and a comparator having a first input coupled to a floating diffusion node in the analog counter, a second input configured to receive a reference voltage, and a clock input configured to receive a comparator clock signal from the analog counter. The image sensor pixel can further include an analog memory circuit selectively coupled to an output of the comparator. The analog memory circuit can include a read enable switch coupled between the output of the comparator and a storage node and a plurality of capacitors coupled to the storage node via respective switches.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors
A semiconductor device may include a first chip with a first wafer and a first dielectric layer, and a second chip that includes a second wafer and a second dielectric layer, the second chip having a backside surface and a frontside surface opposed to the backside surface and bonded to the first chip at the frontside surface to define a bond line between the first dielectric layer and the second dielectric layer. The semiconductor device may include a die seal layer on the backside surface having a die seal ground contact in contact with the second wafer, and an electrostatic discharge path that includes the die seal layer, the die seal ground contact, a first die seal in the first dielectric layer, a second die seal in the second dielectric layer, and a hybrid bond connecting the first die seal and the second die seal through the bond line.
Implementations of semiconductor packages may include a substrate, a first die coupled on the substrate, and a lead frame coupled over the substrate. The lead frame may include a die attach pad. Implementations of semiconductor packages may also include a second die coupled on the die attach pad. The second die may overlap the first die.
Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
In a general aspect, a method includes forming, in a semiconductor device layer disposed on a semiconductor substrate, an opening between a first semiconductor device stack included in the semiconductor device layer and a second semiconductor device stack included in the semiconductor device layer. The method also includes forming a trench in the semiconductor substrate between the first semiconductor device stack and the second semiconductor device stack, the trench corresponding with the opening. The method further includes filling the trench with a first dielectric material, thinning the semiconductor substrate to expose the first dielectric material and separate the semiconductor substrate into a first substrate portion and a second substrate portion, and forming a layer of a second dielectric material on the first substrate portion, the second substrate portion and the exposed first dielectric material.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
High Electron Mobility Transistors (HEMTs) are described with a circular gate. with a drain region disposed within the circular gates and circular source region disposed around the circular gates. The circular gate and the circular source region may form complete circles.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
70.
METHODS AND APPARATUS FOR A TIME-TO-DIGITAL CONVERTER
Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.
An image sensor may include an array of imaging pixels arranged in rows and columns. Each column of pixels can be coupled to a column analog-to-digital converter (ADC) via a pixel output line. The column ADC can include a first low noise single-ended comparison stage, a second low noise single-ended comparison stage, a latch circuit, and a counter. The first low noise single-ended comparison stage may include one or more current source transistors, a voltage ramp generator, a common source amplifier transistor, one or more autozero components, one or more capacitors such as a noise filtering capacitor, and a voltage clamping circuit. The voltage ramp generator can output an increasing voltage ramp or a decreasing voltage ramp.
A semiconductor device (10) includes a substrate (12), a first semiconductor region (14A) of a first conductivity type over the substrate and a second semiconductor region (14B) of the first conductivity type over the first semiconductor region. A trench gate structure (280) is in the second semiconductor region. A first doped region (22) of a second conductivity type is in the first semiconductor region, wherein the first doped region and the first semiconductor region provide a first charge-balance region (142). A second doped region (23) of the second conductivity type is in the second semiconductor region and interposed between the trench gate structure and the first doped region. The second doped region and the second semiconductor region provide a second charge-balance region (143). The second doped region is self-aligned with the trench gate structure.
A method includes applying a sintering precursor material layer to each of a first surface and a second surface of a base layer, and assembling a precursor assembly of a substrate by coupling a first electrically conductive layer on the sinter precursor material layer on the first surface of the base layer and a second electrically conductive layer on the second surface of the sinter precursor material layer on a second surface of the base layer such that the base layer is disposed between the first leadframe and the second leadframe. The method further includes sinter bonding the first electrically conductive layer and the second electrically conductive layer to the base layer to form a sinter bonded substrate.
H01L 23/373 - Cooling facilitated by selection of materials for the device
B22F 7/06 - Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting of composite workpieces or articles from parts, e.g. to form tipped tools
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
75.
MULTIPLE SUBSTRATE PACKAGE SYSTEMS AND RELATED METHODS
Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/24 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel, at the normal operating temperature of the device
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
76.
WIRE-IN-DAM PACKAGES AND RELATED SYSTEMS AND METHODS
An electromagnetic irradiation system may include a bulb assembly and a light emitting diode panel. The bulb assembly and light emitting diode panel may be coupled over a package tray conveyor and the bulb assembly and the light emitting diode panel may be configured so that a package tray including a plurality of image sensor packages encounters irradiation from the light emitting diode panel prior to encountering irradiation from the bulb assembly.
A static charge handling system may include an array of photodiodes, a metal grid coupled to the array of photodiodes, and a set of metal projections extending away from the metal grid. The set of metal projections may be configured to direct charge from one of electrostatic discharge or static charge into the metal grid.
A semiconductor device includes a substrate, a first semiconductor region of a first conductivity type over the substrate and a second semiconductor region of the first conductivity type over the first semiconductor region. A trench gate structure includes a trench in the second semiconductor region, a gate conductor, and a gate dielectric separating the gate conductor from the second semiconductor region. A first doped region of a second conductivity type is in the first semiconductor region, wherein the first doped region and the first semiconductor region provide a first charge-balance region. A second doped region of the second conductivity type is in the second semiconductor region and interposed between the trench gate structure and the first doped region, wherein the second doped region and the second semiconductor region provide a second charge-balance region. The second doped region is self-aligned with the trench gate structure.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A transceiver circuit that includes circuits for cleaning oxidation from input and output pins is disclosed. During a first phase of a cleaning operation, a first cleaner circuit may maintain floating input pins at a voltage level less than a cleaning voltage that is greater than an operating supply voltage. During a second phase of the cleaning operation, the first cleaner circuit may couple the input pins to a ground supply node. A second cleaner circuit may, during the first phase of the cleaning operation, couple the output pins to the cleaning voltage. During the second phase of the cleaning operation, the second cleaner circuit may source respective currents to the output pins.
H01R 43/00 - Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors
B08B 13/00 - Accessories or details of general applicability for machines or apparatus for cleaning
80.
PACKAGE TRAYS FOR SEMICONDUCTOR PACKAGES AND RELATED METHODS
Implementations of a package tray may include a base and a grid of electromagnetic radiation reflectors coupled to a largest planar side of the base; wherein sidewalls of the grid of electromagnetic radiation reflectors may be configured to direct electromagnetic radiation toward sides of a plurality of semiconductor packages located within the grid. The electromagnetic radiation may be configured to assist in curing a component of the plurality of semiconductor packages.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
illustrative vehicles, systems, and methods adapt ultrasonic sensing arrays for close-range communication with, e.g., smart devices, parking infrastructure, and other vehicles. As one example, an illustrative vehicle includes: one or more ultrasonic sensors configured for proximity sensing; and a controller configured to use the one or more ultrasonic sensors to receive an acoustic signal from a smart device. As another example, an illustrative vehicle includes one or more microphones configured for at least one of noise cancellation, voice control, emergency vehicle detection, and proximity sensing; and a controller configured to use the one or more microphones to receive an acoustic signal from a smart device, the acoustic signal being in the frequency range between 18 kHz and 25 kHz, inclusive.
G01S 15/931 - Sonar systems specially adapted for specific applications for anti-collision purposes of land vehicles
H04B 11/00 - Transmission systems employing ultrasonic, sonic or infrasonic waves
H04R 1/40 - Arrangements for obtaining desired frequency or directional characteristics for obtaining desired directional characteristic only by combining a number of identical transducers
In a general aspect, a semiconductor device assembly includes a first substrate including a first dielectric layer, and a first patterned metal layer disposed on a surface of the first dielectric layer. The assembly also includes a pre-molded semiconductor device module having a first side disposed on and electrically coupled with the first patterned metal layer, and a second substrate including a second dielectric layer, a second patterned metal layer disposed on a first surface of the second dielectric layer. The second patterned metal layer being is disposed on and electrically coupled with a second side of the module opposite the first side. The second substrate also includes a conductive via defined through the second dielectric layer. The conductive via electrically couples a signal terminal of the module with a patterned metal layer disposed on a second surface of the second dielectric layer opposite the first surface.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
A power module includes a substrate, a plurality of semiconductor dies coupled to the substrate, and a clip substrate member having a first surface and a second surface. The first surface is coupled to the plurality of semiconductor dies. The clip substrate member includes a first conductive clip, and a second conductive clip, and a dielectric material portion disposed between the first conductive clip and the second conductive clip. The second surface includes a first contact region and a second contact region. The first contact region includes a portion of the first conductive clip. The second contact region includes a portion of the second conductive clip.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
84.
HIDDEN ULTRASONIC SENSING SYSTEMS SUITABLE FOR ADVANCED DRIVER ASSISTANCE
Illustrative sensor controllers, sensors, sensing systems, and sensing methods, may enable cost-efficient implementation of ADAS (advanced driver-assistance system) features with hidden sensors. As one example, an illustrative sensing method includes: transmitting an acoustic burst through a surface over an ultrasonic transducer; receiving an acoustic signal with a MEMS (micro-electromechanical systems) microphone, the MEMS microphone representing the acoustic signal as an electrical receive signal; and processing the electrical receive signal to detect a reflection of the acoustic burst.
An obstacle monitoring system includes a transducer that receives an ultrasonic echo from an obstacle and generates a signal based on the echo. The system further includes a controller coupled to the transducer that is calibrated based on a frequency response of the transducer and a coupling circuit. The system further includes circuitry generating a damping current, controlled by the controller, that reduces or eliminates reverberation of the transducer.
G10K 11/178 - Methods or devices for protecting against, or for damping, noise or other acoustic waves in general using interference effectsMasking sound by electro-acoustically regenerating the original acoustic waves in anti-phase
86.
LEADFRAME-LESS SEMICONDUCTOR DEVICE ASSEMBLIES WITH DUAL-SIDED COOLING
In a general aspect, a semiconductor device assembly (200) includes a first substrate (220) and a second substrate (210). Patterned metal layers (224, 214) respectively included with the first and second substrates are electrically coupled, respectively, with opposite sides of a pre-molded semiconductor device module (230a). A conductive via (216) is defined through the second substrate. The conductive via electrically couples a signal terminal of the module with another patterned metal layer (217) disposed on a surface of the second substrate opposite the first patterned metal layer.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
87.
THERMAL PERFORMANCE IMPROVEMENT AND STRESS REDUCTION IN SEMICONDUCTOR DEVICE MODULES
In a general aspect, a method of producing a signal distribution assembly includes forming a first metal layer having a first, planar side and a second, non-planar side opposite the first side. The second side includes a first base portion, a first post extending from the first base portion; and a second post extending from the first base portion. The method also includes molding the first metal layer such that a molding compound is disposed on the second side of the first metal layer with respective upper surfaces of the first and second posts being exposed through the molding compound. The method further includes coupling the first side of the first metal layer to a first surface of a thermally conductive insulator layer and coupling a second metal layer with a second surface of the thermally conductive insulator layer opposite the first surface of the thermally conductive insulator layer.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
In a general aspect, a circuit includes a metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a source, and a drain. The MOSFET has a first breakdown voltage. The circuit also includes a clamping circuit coupled between the drain and the source. The clamping circuit including a diode having a second breakdown voltage that is less than the first breakdown voltage. A cathode of the diode is coupled with the drain of the MOSFET. The clamping circuit further includes an inductor having a first terminal coupled with an anode of the diode, and a second terminal coupled with the source of the MOSFET.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
89.
Built-in self test with current measurement for analog circuit verification
Illustrative integrated circuit devices are provided with built-in self test circuit designs and verification methods. One disclosed integrated circuit device includes: an analog circuit block configured to be powered by a current flow from a first power rail and an intermediate node; a current sensor configured to provide digital measurements of the current flow; a built-in self test circuit configured to set the analog circuit block in a sequence of operating modes and coupled to the current sensor to capture for each operating mode a corresponding one of the digital measurements.
A reference buffer circuit for buffering a reference voltage is disclosed. The reference buffer circuit includes an input circuit that may generate a replica of the reference voltage. A feedback circuit may generate a charging current using a current mirror circuit and a bias current. A value of the charging current may be greater than a value of the bias current. The feedback circuit may provide a buffered version of the reference voltage at a reference node using the charging current and the replica voltage. An output stage circuit may sink a compensation current from the reference node.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
A power system including a gate driver configured with test circuitry to detect faults is disclosed. The power system may be configured to test the fault detection circuitry in order to confirm its ability to detect faults. Various methods and circuit implementations are disclosed to determine the ability of the system to detect faults. The testing may include different configurations and protocols in order to make conclusions about which components are likely responsible for a failure. These components may include components included in the gate driver or externally coupled to the gate driver. The disclose approach does not significantly add complexity because a test input to initiate a test may be communicated from a low voltage side to a high voltage side over a shared communication channel.
H02H 7/20 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
H02H 1/00 - Details of emergency protective circuit arrangements
Illustrative surge protectors and surge protection methods provide accurate clamp level control during voltage transients and surge events. One illustrative surge protector includes: a shunt transistor having a source coupled to ground and a drain coupled to a conductor at a supply voltage; and an operational amplifier having: an output coupled to a gate of the shunt transistor, an inverting input coupled to a reference voltage Vref, and a noninverting input coupled to receive a sense voltage, the sense voltage being a fixed fraction f of the supply voltage, the operational amplifier being configured to drive the shunt transistor to shunt any excess current when the supply voltage reaches a clamp voltage Vc=Vref/f.
A protection circuit is disclosed for use in automotive or industrial high power integrated circuits equipped with reverse battery protection and reverse current protection. The protection circuit prevents formation of parasitic devices that could cause the high power integrated circuit to malfunction or fail to turn on. The protection circuit features asynchronous operation of a pair of MOSFETs coupled between a power supply and a load. The protection circuit can be engaged at start-up or in response to transient conditions associated with a fault.
H02H 3/05 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection Details with means for increasing reliability, e.g. redundancy arrangements
H02H 3/16 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to fault current to earth, frame or mass
H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
Implementations of an image sensor package may include an optically transmissive cover including a groove along an entire perimeter of the optically transmissive cover; an image sensor die; an adhesive material coupling the optically transmissive cover to the image sensor die; and a mold compound contacting sidewalls of the image sensor die, contacting the adhesive material, and extending into the groove.
Signal converters, systems for power conversion, and methods for adaptive pulse control. The signal converter includes a pulse generator, a level shifter, and a controller. The pulse generator is configured to receive an input control signal for a switch driver. The pulse generator is also configured to generate a set control signal based on the input control signal. The level shifter is configured to generate, based on the set control signal, an output control signal having a first amplitude greater than a second amplitude of the input control signal. The level shifter is also configured to send the output control signal to the switch driver. The controller is configured to detect a common mode transient at a node coupled to the switch driver. The pulse generator is further configured to increase a pulse width of the set control signal when the controller detects the common mode transient.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
A receiver coil of an inductive angular position sensor can have circuit features that become smaller than reasonable for high resolution measurement designs. This is especially true when multiple receiver coils are used, such as in a three-phase configuration, and when each of the multiple receiver coils is in a twisted loop configuration. The disclosed inductive angular position sensor utilizes different spatial frequencies for a rotor coil and the receiver coils. For example, the spatial frequency of the receiver coils may be kept smaller than the rotor coil. In this condition, the fundamental frequency of the angular position sensor is shifted to the least common multiple of the spatial frequencies, making the angular resolution of the inductive angular position sensor high, while the circuit features of the receiver coils are maintained at a reasonable size.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
A receiver coil of an inductive angular position sensor can have circuit features that become smaller than reasonable for high resolution measurement designs. This is especially true when multiple receiver coils are used, such as in a three-phase configuration, and when each of the multiple receiver coils is in a twisted loop configuration. The disclosed inductive angular position sensor utilizes different spatial frequencies for a rotor coil and the receiver coils. For example, the spatial frequency of the receiver coils may be kept smaller than the rotor coil. In this condition, the fundamental frequency of the angular position sensor is shifted to the least common multiple of the spatial frequencies, making the angular resolution of the inductive angular position sensor high, while the circuit features of the receiver coils are maintained at a reasonable size.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
An illustrative controller includes: a transmitter to drive an acoustic transducer to generate a first acoustic burst and a second acoustic burst; a receiver coupled to the acoustic transducer to sense a first response to the first acoustic burst and a second response to the second acoustic burst; and a processing circuit to derive output data from the first and second responses in part by determining an offset frequency difference between the first and second responses, wherein the first acoustic burst has a first characteristic frequency and the second acoustic burst has a second characteristic frequency different from the first characteristic frequency.
A method for attaching a terminal pin to a circuit trace on an electronic substrate. The method includes disposing the electronic substrate on a stage, placing a terminal pin on the circuit trace on the electronic substrate, and directing ultrasound energy generated by a sonotrode to a base region of the terminal pin placed on the circuit trace. The ultrasound energy couples the base region to the circuit trace.
H01R 12/73 - Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
An electrical circuit includes positive and negative voltage rails, a reference voltage rail, a non-trimmable bandgap core configured to output a voltage reference on the reference voltage rail, and a trimming element in an auxiliary section located external to the bandgap core. A current source is coupled to the non-trimmable bandgap core and the positive voltage rail. An auxiliary diode arranged in an auxiliary section outside of the bandgap core is coupled to the current source and negative voltage rail. The trimming element is coupled to the current source external to the non-trimmable bandgap core and has an adjustable set point. The adjustable set point is adjusted to inject a corresponding bias current to the auxiliary section during a trimming process and thereby change the voltage reference.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
