An image sensor is disclosed. The image sensor includes a plurality of image pixels. Each image pixel includes a semiconductor region having a photodiode and a light-sensitive electrical element. Each image pixel further includes a primary metalens. The primary metalens includes a dielectric layer and a plurality of nanostructures arranged within the dielectric layer. Each of the plurality of nanostructures has a first refractive index that is greater than a second refractive index of the dielectric layer. The plurality of nanostructures is patterned within the dielectric layer to direct light received by the image pixel away from the light-sensitive electrical element.
H04N 25/531 - Control of the integration time by controlling rolling shutters in CMOS SSIS
H04N 25/62 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
2.
INTELLIGENT POWER MANAGEMENT SYSTEM, INCLUDING AUTONOMOUS BATTERY SELF-CHARACTERIZATION
A system for characterizing a battery of a battery electric system includes a sensor array, processor, and memory. The sensor array measures a temperature-specific battery voltage and battery current of the battery as battery parameters. The processor executes instructions from memory to provide or create a baseline open circuit voltage to state of charge (OCV-SOC) characteristic relationship during a sequence of charging and discharging modes of the battery. After creating or accessing the baseline OCV-SOC characteristic relationship, the processor determines if the battery is in an open mode during which the battery is not connected to a load. In open mode, the battery parameters are measured via the sensor array. An adjusted OCV-SOC characteristic relationship is created by adjusting an SOC quantity of the baseline OCV-SOC characteristic relationship using the battery parameters. The battery is controlled using the adjusted OCV-SOC characteristic relationship.
G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
G01R 31/378 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] specially adapted for the type of battery or accumulator
G01R 31/3842 - Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
G01R 31/389 - Measuring internal impedance, internal conductance or related variables
G01R 31/392 - Determining battery ageing or deterioration, e.g. state of health
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
H01M 10/0525 - Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodesLithium-ion batteries
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
A multi-phase controller is disclosed. The multi-phase controller includes a current-mode regulation circuit and a pulse distributor configured to distribute a first set of pulses to a first power stage and a second set of pulses to a second power stage, and to selectively enable or disable the second set of pulses to the second power stage based on the load condition. The multi-phase controller further includes a current-sense circuit coupled to receive a plurality of current-monitor signals from the plurality of power stages and configured to provide a summation signal to the current-mode regulation circuit based on the plurality of current-monitor signals, utilize a first current-monitor signal from the first power stage in place of a second current-monitor signal from the second power stage for a replacement period following a resumption of the second set of pulses to the second power stage.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An image sensor package may include an optically transmissive cover including a first layer coupled to a largest planar surface of the optically transmissive cover; and a plurality of nanostructures in the first layer located adjacent a perimeter of the optically transmissive cover. The plurality of nanostructures may form a substantially solar-blind ultraviolet light pass filter.
Circuit implementations may include a sensing field effect transistor, a gate of the sensing field effect transistor coupled with a gate of a silicon carbide transistor; and a driver integrated circuit including a differential amplifier coupled with a drain of the sensing field effect transistor and configured to output a gate reference voltage in response to receiving a drain current from the sensing field effect transistor. A first transistor may be included where a gate of the first transistor may be coupled to the gate reference voltage and a collector is coupled to a reference current source forming a current mirror. A first comparator may be coupled to the collector and configured to output a detected voltage signal when the gate reference voltage reaches a predetermined voltage level and the driver integrated circuit receives the detected voltage signal identifying a first fault condition and shuts down the silicon carbide transistor.
H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
H03K 17/18 - Modifications for indicating state of switch
6.
SEMICONDUCTOR DEVICE ASSEMBLIES WITH DIE ADHESIVE OUTFLOW BARRIERS
In a general aspect, a semiconductor device assembly (200) includes a conductive member (210), a conductive adhesive (240a, 240b) disposed on the conductive member, and a semiconductor die (250a, 250b) disposed on the conductive adhesive. The conductive adhesive couples the semiconductor die with the conductive member. The device assembly further includes a barrier (220) included in the conductive member. The barrier is proximate to an edge of the semiconductor die and configured to inhibit outflow of the conductive adhesive.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/373 - Cooling facilitated by selection of materials for the device
Implementations of a substrate may include a semiconductor material; a redistribution layer coupled to a first largest planar surface of the semiconductor material; and a hollow via extending from a second largest planar surface of the semiconductor material completely through a thickness of the semiconductor material, the hollow via directly coupled with the redistribution layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
Implementations of a system configured for operation of a field effect transistor may include a gate driver coupled with a memory and a microcontroller unit and a plurality of analog to digital converters, the gate driver configured to be coupled with a gate of a field effect transistor where the gate driver may be configured to generate a drive signal with at least two levels for the gate of the field effect transistor. The drive signal with at least two levels may be generated using a deep reinforcement learning agent and data associated with one or more parameters of the field effect transistor.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
In a general aspect, a semiconductor device assembly includes a conductive member, a conductive adhesive disposed on the conductive member, and a semiconductor die disposed on the conductive adhesive. The conductive adhesive couples the semiconductor die with the conductive member. The device assembly further includes a barrier included in the conductive member. The barrier is proximate to an edge of the semiconductor die and configured to inhibit outflow of the conductive adhesive.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
Implementations of a method of forming an image sensor package may include providing an image sensor substrate including image sensor die; bonding an optically transmissive substrate to the image sensor substrate; forming a plurality of electrical interconnects on the image sensor substrate; and, after forming the plurality of electrical interconnects, thinning the optically transmissive substrate to a desired thickness.
A semiconductor package may include a semiconductor die disposed on a first substrate and having at least a first contact on a first side and at least a second contact on a second side that is opposed to the first side. An insulator, such as a dielectric, may encapsulate the semiconductor die. A second substrate may be disposed on the first substrate with the semiconductor die therebetween. Either of the first or second substrate may have a cavity formed therein, and the semiconductor die may be disposed in one or both of the cavities. Vias through the first substrate, the dielectric, and/or the second substrate may be used to connect to the semiconductor die, enabling formation of a redistribution layer. Magnetic elements and associated windings may also be used in place of the semiconductor die and associated contacts.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
12.
SEMICONDUCTOR MODULE WITH POWER BRIDGE FOR INTEGRATED DIE INTERCONNECTION
A semiconductor module may include a first substrate having a first substrate surface that includes an area, a first semiconductor die disposed within the area on the first substrate surface, and a second semiconductor die disposed within the area on the first substrate surface. The semiconductor module may further include a second substrate that has a second substrate surface that spans the area and faces the first semiconductor die, the second semiconductor die, and the area, with the second substrate surface having a dielectric layer formed thereon with a metallization layer formed on the dielectric layer that includes patterned metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface that is outside of the area.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
13.
INTELLIGENT POWER MANAGEMENT SYSTEM AND METHOD FOR MONITORING BATTERY DEGRADATION
A battery monitoring system for a battery includes a sensor array, a processor, and memory. The sensor array measures battery parameters, including an ambient temperature and a battery voltage, a battery current, and a battery temperature of the battery. The memory includes instructions. Execution of the instructions causes the processor to record the battery parameters from the sensor array during a charging mode and a discharging mode of the battery, respectively. An accumulated temperature history of the battery is also determined using the ambient temperature and the battery temperature. The processor calculates a total energy loss level of the battery using the battery voltage and current, and then generates a degradation alert in response to the total energy loss level exceeding a loss threshold and the accumulated temperature history exceeding a temperature threshold.
G01R 31/392 - Determining battery ageing or deterioration, e.g. state of health
G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
G01R 31/371 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with remote indication, e.g. on external chargers
G01R 31/3842 - Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
14.
METHOD AND SYSTEM FOR ROUTING OF ELECTRICAL CONDUCTORS OVER NEUTRALIZED POWER FETS
A vertical, FinFET device includes an array of FinFETs comprising a plurality of rows and columns of fins. Each of the fins has a fin length and a fin width, a first fin tip, a second fin tip, and a central region disposed between the first fin tip of a first row of the plurality of rows and the second fin tip of a second row of the plurality of rows. The central region is characterized by an electrical conductivity. The FinFET device also includes a neutralized region including the first fin tip, a region between the first row of the plurality of rows and the second row of the plurality of rows, and the second fin tip. The neutralized region is characterized by a second electrical conductivity less than the electrical conductivity of the central region. The FinFET device further includes an electrical conductor disposed over the neutralized region.
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Implementations of a semiconductor package may include a metal containing substrate including a solder preform coupled thereto and a laminated substrate including an opening. The laminated substrate may be fixedly coupled to the metal containing substrate through the solder preform.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
16.
SEMICONDUCTOR DEVICE WITH OPTICAL STRUCTURE FOR ENHANCING BLUE LIGHT DETECTION
A semiconductor device is disclosed. The semiconductor device includes a plurality of image pixels. Each image pixel includes a semiconductor region and a single-photon avalanche diode formed in the semiconductor region. Each image pixel also includes an optical structure disposed in the semiconductor region and extending from an upper surface of the semiconductor region into an interior of the semiconductor region. Each image pixel further includes a microlens configured to focus light received by the image pixel into the optical structure.
Receivers, control systems, and methods for receiving a signal. The method includes receiving a differential communication signal including a first component and a second component. The method also includes generating, with a comparator, a comparison signal by comparing the first component and the second component. The method further includes generating a single-ended communication signal by applying a debouncing time to the comparison signal. The method also includes inverting a voltage offset of the comparator based on the single-ended communication signal.
An imaging system may include an image sensor with an array of pixels arranged in rows and columns. Row driver circuitry may be coupled to the pixels and may address a given row of the pixels based on a row address. Row randomization circuitry may be coupled to the row driver circuitry to dither the row address and therefore randomize the order in which rows of a given column are read out over column lines to sample and hold circuitry that includes a plurality of capacitors for each column. The imaging system may include a multiplexer that de-randomizes the order of the rows after passing through the sample and hold circuitry. Alternatively or additionally, the order in which the plurality of capacitors is used to store the signals from each column may be randomized. In this way, fixed pattern noise in an output image may be reduced or eliminated.
H04N 25/677 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
A transistor is disclosed. The transistor includes a source region and a drain region having a first conductivity type. The transistor also includes a channel region located adjacent to the source region and having a second conductivity type. The transistor further includes a drift region located between the drain region and the channel region, the drift region having a drift-region width that is less than a drain-region width of the drain region. In addition, the transistor includes a trench region located adjacent to the drift region on a first side and on a second side of the drift region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
An audio device is disclosed. The audio device includes a microphone and an input filter bank configured to decompose a microphone input signal into a plurality of sub-band input signals. The audio device further includes a plurality of sub-band channels configured to process the plurality of sub-band input signals to generate a plurality of sub-band output signals, wherein each of the plurality of sub-band channels are configured to subtract a respective one of a plurality of sub-band estimated acoustic-feedback signals from a respective one of the plurality of sub-band input signals, and wherein each of a subset of the plurality of sub-band channels are configured to frequency shift a respective sub-band output signal relative to a corresponding sub-band input signal. Further, the audio device includes an output filter bank configured to construct an output signal based on the sub-band output signals, and a speaker configured to output an audible signal.
Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.
Implementations of a method of providing wettable flanks on leads of a semiconductor package may include applying mold compound around a plurality of leads included in a leadframe; electroplating exposed portions of the plurality of leads; cutting at least one lead of the plurality of leads to expose a flank of the least one lead; applying an electrically conductive layer over the plurality of leads; electroplating the flank of the at least one lead to render the flank wettable; removing the electrically conductive layer from the plurality of leads; and singulating to form a semiconductor package.
A package includes an inorganic substrate with a first inter-metal dielectric layer disposed on a first surface of the inorganic substrate. An optical sensor die is attached to and electrically connected to a pad in the first inter-metal dielectric layer by a connector. A molding material layer is disposed on the first inter-metal dielectric layer encapsulating the optical sensor die. A second inter-metal dielectric layer is disposed on the molding material layer. An opening extends through the molding material layer between the first inter-metal dielectric layer and the second inter-metal dielectric layer. The opening is filled or lined with conductive material electrically connecting the first inter-metal dielectric layer and the second inter-metal dielectric layer.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
Systems, devices, and methods are described for locating a contact for single-photon avalanche diode (SPAD) in an isolation trench structure of a SPAD-based imager. Systems, devices, and methods may include a frontside isolation trench structure disposed between neighboring SPAD pixels, where the trench is lined with a continuous passivation layer having an opening that allows a conductive material filling the trench to contact the substrate and form a buried contact for one or more neighboring SPADs. The trench may include a stepped trench having the opening in the passivation layer proximate to the stepped region. The trench may include the opening in the passivation layer toward the bottom of the frontside trench. The trench may include a backside trench having a hi-k material. The backside trench may be continuous, or segmented and/or overlapping. Buried SPAD contacts as described herein may allow for reduced pixel size.
A battery monitoring system for a battery of a battery electric system includes a sensor array, a processor, and memory. Execution of the instructions by a processor according to a method causes the processor to receive parameters of the battery from the sensor array, calculate a rate of increase of an internal resistance (ΔR ratio) of the battery across multiple states of charge of the battery, compare the ΔR ratio to one or more degradation thresholds, and record a corresponding degradation level of the battery in the memory when the ΔR ratio exceeds the degradation threshold(s). A state of health notice may be transmitted to a remote device.
G01R 31/392 - Determining battery ageing or deterioration, e.g. state of health
G01R 31/371 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with remote indication, e.g. on external chargers
G01R 31/3842 - Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
G01R 31/389 - Measuring internal impedance, internal conductance or related variables
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
27.
DEVICE PACKAGE WITH FLEXIBLY-ALIGNED LEAD FRAME CLIP
A package includes a semiconductor die disposed on a lead frame. A source contact pad is disposed on the semiconductor die. The package further includes a lead post shared by a plurality of leads that form external terminals of the package. The lead post has a clip-locking feature. A clip connects the source contact pad to the lead post. The clip has a key structure coupled to the clip-locking feature in the lead post.
Systems, devices, and methods are described to provide an improved current mirror operational transconductance amplifier (OTA). Improved OTAs may include an input circuit arranged to receive a differential voltage input, a load circuit arranged to measure a positive branch current and negative branch current from the input circuit, a bias circuit arranged to determine a bias voltage based on the negative branch current, a folded current branch circuit arranged to generate an adaptive bias current and a pass transistor configured to adjust an amount of the adaptive bias current based on the bias voltage, and a push-pull output circuit configured to sink current based on the adjusted adaptive bias current. The folded current branch circuit may generate the adaptive bias current based on the measured negative branch current. The output circuit may source current based on the measured positive branch current. Advantageously, most transistors may be of minimum size.
Visible and short-wave infrared (SWIR) hybrid sensors and methods for constructing such sensors. The method includes forming a first deep trench isolation (DTI), a second DTI, and a third DTI in a silicon substrate. A portion of the silicon substrate positioned between the second and third DTIs forms a silicon photodetector for detecting visible light. The method also includes etching a trench in the silicon substrate between the second and third DTIs. The trench is etched such that another portion of the silicon substrate remains between the second and thirds DTIs. The method further includes forming a SWIR photodetector within the trench for detecting SWIR light. The method also includes removing another portion of the silicon substrate such that the first, second, and third DTIs are exposed on a side of the silicon substrate. The method further includes forming a high-K dielectric layer on the silicon substrate.
A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.
Ultrasonic sensors, sensor controllers, and sensing methods may employ adaptive data compression to improve important aspects of measurement signal fidelity while retaining the main benefits of data compression. One illustrative sensor includes: a piezoelectric transducer; and a sensor controller. The sensor controller includes: a receiver coupled to an ultrasonic transducer to obtain a receive signal having one or more reflections of an acoustic burst within a measurement interval associated with the acoustic burst; a correlator configured to produce an output signal having a peak for each of the one or more reflections; and a compressor configured to determine a digital representation of the output signal for communication via a bus using at least one encoding parameter that varies within the measurement interval.
The cooling of power modules used in high-power systems, such as three-phase inverters, may require a cooling apparatus that is heavier than desired for some applications, such as electric vehicles. A cooling apparatus is disclosed that can provide sufficient cooling in a weight-reduced package. Additionally, assembly methods are disclosed that make the cooling apparatus more robust to shocks and vibrations, which may be experienced by electric vehicles.
Devices and methods are disclosed for facilitating faster switching of silicon-based and silicon carbide-based power transistors suitable for use in electric vehicles. The disclosed techniques can minimize the impact on turn-on and turn-off losses, while reducing gate voltage and drain voltage spikes during device switching. A fast/slow cell design incorporating shielded gate MOSFETs controls gate-to-drain capacitance and gate resistances to optimize suppression of voltage overshoot.
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
An electronic power module is disclosed that forms external electrical connections without the use of a lead frame. Instead, various types of external connectors can be used, such as a press-fit pin assembly and an integrated connection post and power tap. Different methods of securing the external connectors to a multilayer substrate are also disclosed.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01R 12/58 - Fixed connections for rigid printed circuits or like structures characterised by the terminals terminals for insertion into holes
Systems, devices, and methods are provided for an improved voltage buffer. Improved voltage buffers may include an output circuit operating in a first voltage domain, and an input circuit operating in a second voltage domain and receiving a reference voltage and feedback signal. The second voltage domain may have a lower voltage than the first voltage domain. A bias circuit coupled between the input and output circuits may bias operation of the output circuit. An error signal from the input circuit may adjust the bias of the output circuit. A level shifting circuit may translate the adjusted bias signal from the second to the first voltage domain. The bias circuit may be controlled according to transistors having opposite VGS temperature curves. Advantageously, a reduced portion of the voltage buffer may be exposed to over-voltage stress, and the voltage buffer may be more resistant to temperature-based fluctuations in output voltage.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A package includes an inorganic substrate, and an optical sensor die disposed on a first portion of a top surface of the inorganic substrate. The package further includes a first inter-metal dielectric layer disposed on a second portion of the top surface and a second inter-metal dielectric layer disposed on a bottom surface of the inorganic substrate. At least one through-substrate via filled or lined with a conductive material electrically connects the first inter-metal dielectric layer and the second inter-metal dielectric layer.
An actuator comprises an output stage configured to alternately couple an output node to a first supply voltage and a second supply voltage, and to isolate the output node when an inhibit signal is asserted. A piezoelectric element has two terminals coupled by a parasitic capacitance CP, with one terminal coupled to the output node. A switched inductance path between the two terminals includes an inductor in series with a switch. A control circuit is configured to close the switch as needed to substantially invert a charge on the parasitic capacitance before the output stage couples the first or second supply voltage to the output node. The second terminal may be coupled to ground, with the supply voltages having equal magnitude but opposite polarity.
In a general aspect, an electronic device assembly includes a substrate arranged in a plane. The substrate has a first side and a second side, the second side being opposite the first side. The assembly also includes a plurality of semiconductor die disposed on the first side of the substrate and at least one signal pin. The at least one signal pin includes a proximal end portion coupled with the first side of the substrate, a distal end portion, and a medial portion disposed between the proximal end portion and the distal end portion. The medial portion is pre-molded in a molding compound, the proximal end portion and the distal end portion exclude the molding compound. The at least one signal pin is arranged along a longitudinal axis that is orthogonal to the plane of the substrate.
H01R 12/58 - Fixed connections for rigid printed circuits or like structures characterised by the terminals terminals for insertion into holes
H01R 43/16 - Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for manufacturing contact members, e.g. by punching and by bending
H01R 43/26 - Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current collectors or for joining electric conductors for engaging or disengaging the two parts of a coupling device
39.
CLOSE-RANGE COMMUNICATIONS WITH A VEHICLE'S ULTRASONIC PROXIMITY SENSORS
illustrative vehicles, systems, and methods adapt ultrasonic sensing arrays for close-range communication with, e.g., smart devices, parking infrastructure, and other vehicles. As one example, an illustrative vehicle includes: one or more ultrasonic sensors configured for proximity sensing; and a controller configured to use the one or more ultrasonic sensors to receive an acoustic signal from a smart device by: detecting a trigger; generating with the one or more ultrasonic transducers an acoustic signal representing a beacon; upon receiving an acoustic signal representing a connection request, using the one or more ultrasonic transducers to send an acoustic signal representing a response to the connection request; and upon receiving an acoustic signal representing a command to the vehicle, executing the command and using the one or more ultrasonic transducers to send an acoustic response message acknowledging the command and communicating a result.
G01S 15/931 - Sonar systems specially adapted for specific applications for anti-collision purposes of land vehicles
H04B 11/00 - Transmission systems employing ultrasonic, sonic or infrasonic waves
H04R 1/40 - Arrangements for obtaining desired frequency or directional characteristics for obtaining desired directional characteristic only by combining a number of identical transducers
Implementations of a leadframe may include a substrate attach portion including a first largest planar surface and a second largest planar surface on a side opposing the first largest planar surface; and a substrate opening formed in a material of the first largest planar surface of the substrate attach portion. The substrate opening may be configured to receive a perimeter of a substrate therein.
A system-in-package includes an interposer substrate having a first side and a second side opposite the first side, and a redistribution layer disposed on the first side. The redistribution layer includes a plurality of contact pads and a plurality of interconnections disposed on the first side. The plurality of interconnections is electrically connected to a plurality of terminals disposed on the second side opposite the first side. A first semiconductor die is disposed on the first side and electrically coupled to a first of the plurality of contact pads and a first of the plurality of interconnections disposed on the first side of the interposer substrate. A second semiconductor die is disposed on the first side. The second semiconductor die is electrically coupled to a second of the plurality of contact pads and a second of the plurality of interconnections disposed on the first side of the interposer substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A power device includes a silicon carbide substrate. A gate is provided on a first side of the silicon carbide substrate. A graded channel includes a first region having a first dopant concentration and a second region having a second dopant concentration, the second dopant concentration being greater than the first dopant concentration.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
43.
SHIELDED GATE TRENCH POWER MOSFET WITH HIGH-K SHIELD DIELECTRIC
In one general aspect, an apparatus can include a substrate having a semiconductor region, and a trench defined in the semiconductor region and having a sidewall. The apparatus can include a shield electrode disposed in the trench and insulated from the sidewall of the trench by a shield dielectric, the shield dielectric having a low-k dielectric portion and a high-k dielectric portion. The apparatus can include a gate electrode disposed in the trench and at least partially surrounded by a gate dielectric, and an inter-electrode dielectric disposed between the shield electrode and the gate electrode.
Implementations of a substrate may include a first side coupled with a first plurality of leads, the first side including a first set of spaced apart through holes therein; and a second side coupled with a second plurality of leads, the second side including a second set of spaced apart through holes therein. The first side may oppose the second side where a portion of a first set of edges of the first set of spaced apart through holes form a first set of wettable flanks for the first plurality of leads; and a portion of a second set of edges of the second set of spaced apart through holes form a second set of wettable flanks for the second plurality of leads.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
The technology involves providing illumination via an illumination module, which is perceivable by a person when the illumination module is operating in a first mode. The technology also involves the illumination module emitting a coded pattern when operating in a second mode. This can be done concurrently so that the person cannot perceive the coded pattern. This can involve coordinating a light emitting diode (LED) on/off frequency of the illumination module, along with an image sensor capture rate and exposure time. The coded pattern may be used to complement the information displayed to the person, aid in autonomous operation of a vehicle, identify environmental or other conditions to a computing device, or provide other technical benefits.
G06K 7/10 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation
G06K 7/14 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation using light without selection of wavelength, e.g. sensing reflected white light
46.
SHARED DIGITAL COMMUNICATIONS BUS SUITABLE FOR AUTOMOTIVE APPLICATIONS
An illustrative network includes: n nodes coupled to a signal conductor, n being an integer greater than one; and a bus controller configured to transmit periodic pulses via the signal conductor, each pulse initiating a data transmission slot. Each of the multiple nodes has a node ID and is configured to determine which of the data transmission slots correspond to that node ID by: driving the signal conductor with a pulse representing a resynchronization request if n-1 consecutive data transmission slots are empty; and upon driving or detecting a pulse representing a resynchronization request, tracking a data transmission slot count that treats a first data transmission slot after a resynchronization request as the first data transmission slot in a series of frames each having n data transmission slots, each data transmission slot in the frame having a slot count that matches a respective one of the node IDs.
An image sensor device may include a semiconductor substrate, first and second image sensor pixels in the substrate, and a gradient-doped deep trench isolation (DTI) structure between the first and second image sensor pixels. The gradient-doped DTI structure may include at least two doped regions that extend from a rear surface of the semiconductor substrate to form a backside DTI structure. Light scattering structures may be formed in the rear surface and may be doped. The at least two doped regions may be etched and doped sequentially when the image sensor device is fabricated. Alternatively or additionally, a trench may be etched from a front surface of a semiconductor substrate, doped, and etched further into the semiconductor substrate to form a frontside DTI structure. The semiconductor substrate may be etched at the front surface, and the additional etching of the trench may eliminate or reduce pitting of the semiconductor substrate.
A semiconductor device includes a first termination trench at a first edge region and a second termination trench at a second edge region. A first active trench extends from the first termination trench towards the second termination trench and terminates with a first tip region separated from the second termination trench by the termination mesa region. A second active trench extends from the second termination trench towards the first termination trench and terminates with a second tip region separated from the first termination trench by the termination mesa region. A first gate contact trench is connected to the first termination trench within the first edge region. A coupling trench is at a third edge region and is connected to the second termination trench, The coupling trench includes a corner portion that couples the coupling trench to the first gate contact trench.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
In a general aspect, a method of sintering a semiconductor device assembly having a surface projection includes applying sintering material to a die attach surface. The method also includes disposing a semiconductor die on the sintering material, the semiconductor die having a surface including a substantially planar portion and at least one projection extending from the substantially planar portion in a direction orthogonal to the surface. The method also includes disposing a film on the surface of the semiconductor die, the film including at least one spacer, where the film is disposed such that the at least one spacer contacts the substantially planar portion. The method also includes applying pressure to the film. The method also includes applying thermal energy at a first sintering temperature to sinter the semiconductor die to the die attach surface. The method also includes removing the film.
In general aspect, a module can include a substrate having a semiconductor circuit implemented thereon, and a negative power supply terminal electrically coupled with the semiconductor circuit via the substrate. The negative power supply terminal includes a connection tab arranged in a first plane. The module also includes a first positive power supply terminal electrically and a second positive power supply terminal that are coupled with the semiconductor circuit via the substrate. The first positive power supply terminal being laterally disposed from the negative power supply terminal, and including a connection tab arranged in the first plane. The second positive power supply terminal is laterally disposed from the negative power supply terminal and arranged in the first plane, such that the negative power supply terminal is disposed between the first positive power supply terminal and the second positive power supply terminal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
51.
SYSTEMS AND METHODS FOR DESIGNING A MODULE PRODUCT
Implementations of a method of designing a semiconductor device product may include selecting of at least one discrete device die at least one test condition; generating a product die and package configuration using a predictive modeling module and the at least one discrete device die; generating a graphic design system file with the product die configuration; generating a package bonding diagram with the graphic design system file; generating a product SPICE model corresponding with the product die configuration; generating one or more datasheet characteristics of a discrete device product with the product SPICE model; generating a product datasheet for the discrete device product using the graphic design system file, the package bonding diagram, and the one or more datasheet characteristics; and providing access to the graphic design system file, the package bonding diagram, the product SPICE model, and the product datasheet.
G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 111/02 - CAD in a network environment, e.g. collaborative CAD or distributed simulation
G06F 117/12 - Sizing, e.g. of transistors or gates
G06F 119/08 - Thermal analysis or thermal optimisation
G06N 3/04 - Architecture, e.g. interconnection topology
A vertical fin-based field effect transistor (FinFET) device includes an array of FinFETs comprising a plurality of rows and columns of separated fins. Each of the separated fins has a length and a width measured laterally with respect to the length and includes a first fin tip disposed at a first end of the separated fin, a second fin tip disposed at a second end of the separated fin opposing the first end, a central region disposed between the first fin tip and the second fin tip and characterized by a first electrical conductivity, and a source contact electrically coupled to the central region. The first fin tip and the second fin tip are characterized by a second electrical conductivity less than the first electrical conductivity. The FinFET further includes a first gate region surrounding the first fin tip and a second gate region surrounding the second fin tip.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 30/62 - Fin field-effect transistors [FinFET]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
53.
LIDAR SENSORS WITH NANOPHOTONIC POLARIZATION ROUTERS
Light detection and ranging (LIDAR) sensors, LIDAR systems, and methods for performing LIDAR. The LIDAR sensing includes a pixel array and a spectral router. The pixel array includes first, second, third, and fourth pixels arranged in a two-by-two grid. The spectral router is configured to route a first light with a first polarization to the first pixel. The spectral router is also configured to route a second light with a second polarization to the second pixel. The second polarization is about forty-five degrees greater than the first polarization. The spectral router is further configured to route a third light with a third polarization to the third pixel. The third polarization is orthogonal to the second polarization. The spectral router is also configured to route a fourth light with a fourth polarization to the fourth pixel. The fourth polarization is orthogonal to the first polarization.
G01S 7/499 - Details of systems according to groups , , of systems according to group using polarisation effects
G01S 7/48 - Details of systems according to groups , , of systems according to group
G01S 17/32 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
G01S 17/931 - Lidar systems, specially adapted for specific applications for anti-collision purposes of land vehicles
A system may include a capacitor. The capacitor may include a first electrode, a second electrode, and an insulator between the first and second electrodes. The first electrode may have a peripheral edge that is laterally offset from a peripheral edge of the second electrode. The laterally offset peripheral edges of the first and second electrodes may be formed using a single-mask-based etch process.
A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and QRR may be achieved, leading to lower switching losses.
In a general aspect, mechanisms for dual coupling of a semiconductor package assembly to a component includes a thermal dissipation appliance; a semiconductor package assembly bonded to the thermal dissipation appliance by a thermally conductive adhesive material; and at least one clamping tool mechanically coupled to the semiconductor package assembly and to the thermal dissipation appliance, the at least one clamping tool exerting a compressive force on the semiconductor package assembly to maintain an interface between the semiconductor package assembly and the thermal dissipation appliance.
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
57.
SYSTEM AND METHOD FOR CONTROLLING SILICON CARBIDE CRYSTAL GROWTH
A growth system is disclosed. The growth system may include a crucible at least partially enclosed by an insulation layer, a growth region located within the crucible and configured to hold a silicon carbide (SiC) seed crystal, a source-material region located within the crucible and configured to hold an SiC source material. The growth system may further include a barrier located within the crucible and configured to separate the source-material region and the growth region. In addition, the growth system may include a heating element located around the crucible and configured together with an opening in the insulation layer to provide a temperature gradient with a decreasing temperature in a direction from the source material toward the growth region. The growth system may also include a vent extending through the barrier from the source-material region to the growth region.
Implementations of a substrate may include a first set of tie bars; a second set of tie bars; and a plurality of leads coupled between the first set of tie bars and the second set of tie bars. The first set of tie bars may intersect with the second set of tie bars. Each intersection of the first set of tie bars and the second set of tie bars may be downset from the plurality of leads.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
Sensors may incorporate ultrasonic cleaning device controllers and methods to keep their exposed surfaces free from water, ice, and other adherent substances. One illustrative controller includes a driver configured to drive a transducer with a periodic waveform having voltage pulses and high impedance intervals repeating at a drive frequency. The controller may also include a receiver configured to measure a high impedance voltage of the transducer during the high impedance intervals. The controller may further include control logic configured to adjust the drive frequency using the high impedance voltage to track a resonance frequency of the transducer. Some implementations may use diagnostic bursts with lower voltage pulse magnitudes for tracking and cleaning bursts with higher voltage pulse magnitudes for cleaning. Duty cycle fading may be employed to prevent voltage overshoots after each burst.
G02B 27/00 - Optical systems or apparatus not provided for by any of the groups ,
B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
B06B 1/06 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy operating with piezoelectric effect or with electrostriction
B08B 3/12 - Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration by sonic or ultrasonic vibrations
Systems, devices, and methods are described to protect isolation trench structures from charge damage during plasma-based BEOL deposition and etching steps. Devices and methods may include image sensors having array isolation trenches in an array portion of the image sensor substrate including a pixel array. A periphery portion of the substrate may include isolation trenches coupled with a metallization layer at a frontside of the substrate. The periphery portion may also include contacts between substrate segments and the metallization layer. The substrate and periphery trenches remain at the same potential during BEOL processing, reducing the risk of charge damage to the isolation trenches. In some embodiments, the periphery trenches may remain isolated from the array trenches until BEOL processing is complete, for example being coupled by conductive material after backside thinning. The array trenches may be coupled, through the periphery portion, for biasing in the completed image sensor.
A measurement circuit is disclosed. The measurement circuit may include a current source configured to provide a current to a drain terminal of a transistor. The measurement circuit may also include a voltage-measure circuit configured to measure a drain-to-source voltage of the transistor. The measurement circuit may further include a regulator circuit. The regulator circuit may be configured to receive from the voltage-measure circuit a voltage-measure signal indicative of the drain-to-source voltage of the transistor, and to regulate the gate-to-source voltage of the transistor based on the drain-to-source voltage of the transistor.
G01R 31/26 - Testing of individual semiconductor devices
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 7/5387 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
H02P 27/00 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
A non-volatile memory (NVM) bit cell is disclosed. The NVM bit cell includes a first well region and a second well region. The NVM bit cell also includes an isolation trench between the first well region and the second well region. The isolation trench has a trench depth that is greater than a well depth of the first well region and the second well region. The NVM bit cell further includes a control gate formed in the first well region. In addition, the NVM bit cell includes a state transistor formed in the second well region. The state transistor has a floating-gate terminal coupled to a floating terminal of the control gate. The NVM bit cell also includes an access transistor formed in the second well region and coupled in series with the state transistor.
Sensors may incorporate ultrasonic cleaning device controllers and methods to keep their exposed surfaces free from water, ice, and other adherent substances. One illustrative controller includes a driver configured to drive a transducer with a periodic waveform having voltage pulses. The illustrative controller further includes control logic that performs a diagnostic operation using the periodic waveform to determine a resonance frequency of the transducer and performs a cleaning operation using the periodic waveform with a voltage pulse magnitude that is larger than a voltage pulse magnitude used for the diagnostic operation. Some implementations may use high impedance voltage measurements to enable drive frequency adaptation during driving. Duty cycle fading may be employed to prevent voltage overshoots after each burst.
B08B 7/02 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass by distortion, beating, or vibration of the surface to be cleaned
G01N 29/12 - Analysing solids by measuring frequency or resonance of acoustic waves
65.
ULTRASONIC CLEANING DEVICE CONTROLLER AND METHOD HAVING DUTY CYCLE FADING
Sensors may incorporate ultrasonic cleaning device controllers and methods to keep their exposed surfaces free from water, ice, and other adherent substances. One illustrative controller includes a driver configured to drive a transducer with a periodic waveform having voltage pulses and high impedance intervals at a duty cycle having an initial value. The illustrative controller further includes control logic configured to reduce the duty cycle of the periodic waveform to a pre-termination value before terminating the periodic waveform with a high impedance state. Some implementations may use diagnostic bursts with lower voltage pulse magnitudes for tracking and cleaning bursts with higher voltage pulse magnitudes for cleaning. Drive frequency adaptation may be performed based on high impedance voltage measurements during excitation of the transducer.
B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
B08B 7/02 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass by distortion, beating, or vibration of the surface to be cleaned
B60S 1/56 - Cleaning windscreens, windows, or optical devices specially adapted for cleaning other parts or devices than front windows or windscreens
66.
SEMICONDUCTOR PACKAGE ELECTRICAL CONTACT STRUCTURES AND RELATED METHODS
Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Image sensor, imaging systems, and methods for imaging low energy photons. The image sensor includes an upconversion layer, an energy emitter, and a plurality of silicon photodetectors. The upconversion layer is configured to emit visible light in response to infrared light when electrons in the upconversion layer are charged to a metastable state. The energy emitter is configured to charge the electrons in the upconversion layer to the metastable state. The plurality of silicon photodetectors are positioned behind the upconversion layer and configured to detect the visible light emitted by the upconversion layer.
A memory cell is disclosed. The memory cell comprises a transistor. The transistor includes a gate, a drain region coupled to a drain terminal by one or more drain contacts, and a source region coupled to a source terminal by a source contact. A cumulative drain-contact area of the one or more drain contacts of the transistor is greater than a source-contact area of the transistor. Further a source-contact silicide is located between the source contact and the source region, and the source-contact silicide is configured to migrate into the source region in response to a programming current conducted through the drain region and the source region.
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
69.
SWITCHING POWER CONVERTERS, AND METHODS AND CONTROL MODULES FOR OPERATING SAME
Switching power converters, and methods and control modules for operating same. At least one example is a method of operating a switching power converter, the method comprising: generating, by a regulator, a drive signal that is periodic, each period defining an on-time and an off-time; passing unchanged, by a transition controller, the drive signal to an electrically-controlled switch; and then responsive to a mode controller changing conduction modes of an inductor of the switching power converter, conveying with adjustments, by the transition controller, the drive signal to the electrically-controlled switch.
Implementations of a semiconductor package may include one or more leads operatively coupled with one or more semiconductor devices; and a mold compound coupled to the one or more leads and exposing a flank of the one or more leads through a surface of the mold compound that may be oriented substantially perpendicularly to a longest length of the one or more leads. An exposed surface of the flank may be recessed into the surface of the mold compound. The exposed surface of the flank may include at least one curve.
Implementations of a semiconductor package may include a semiconductor die including a first side and a second side, the first side of the semiconductor die including one or more electrical contacts; and an organic material covering at least the first side of the semiconductor die. Implementations may include where the one or more electrical contacts extend through one or more openings in the organic material; a metal-containing layer coupled to the one or more electrical contacts; and one or more slugs coupled to one of a first side of the semiconductor die, a second side of the semiconductor die, or both the first side of the semiconductor die and the second side of the semiconductor die.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Wake-up systems and wake-up methods for an external power source and interfaces for angular position sensors. The system includes a rotatable sensor and an interface circuit. The rotatable sensor is configured to generate a plurality of phase signals. The interface circuit is configured to generate a first rectified signal by rectifying a first phase signal of the plurality of phase signals. The interface circuit is also configured to generate a first integrated signal by integrating the first rectified signal. The interface circuit is further configured to generate a wake-up signal for the external power source based on the first integrated signal.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
A cascode switching circuit is disclosed. The cascode switching circuit includes a cascode device comprising a JFET and a MOSFET coupled in a cascode topology. The cascode switching circuit further includes a gate driver having a gate-driver input configured to receive a switching input signal and a gate-driver output coupled to a gate of the MOSFET and configured to switch the MOSFET between a MOSFET ON-state and a MOSFET OFF-state based on the switching input signal. In addition, the cascode switching circuit includes a current source coupled between the gate-driver output and the gate of the JFET and configured to forward bias a gate-source junction of the JFET when the cascode device is in an ON-state.
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
H03K 17/12 - Modifications for increasing the maximum permissible switched current
74.
SILICON-ON-INSULATOR DIE SUPPORT STRUCTURES AND RELATED METHODS
Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
75.
SEMICONDUCTOR PACKAGES USING PACKAGE IN PACKAGE SYSTEMS AND RELATED METHODS
Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.
A substrate includes a base plate made of an insulating material, a first electrically conductive layer disposed on a first side of the base plate, and a second electrically conductive layer disposed on a second side of the base plate. The first electrically conductive layer has a stepped surface, the stepped surface including a plurality of steps at different heights above the base plate.
A power detector is disclosed. The power detector includes a primary-side sense circuit configured to generate a sense signal representative of an output voltage of a flyback converter. The power detector also includes a primary-side reference generator configured to generate a reference signal representative of an average output current of the flyback converter. The power detector further includes a primary-side power calculation circuit configured to generate an output-power signal in response to the sense signal and the reference signal.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
G01R 21/127 - Arrangements for measuring electric power or power factor by using pulse modulation
Global shutter image sensors, imaging systems, and methods for operating global shutter image sensor. The global shutter image sensor includes a pixel array and a controller. The pixel array includes a correction pixel and a plurality of image pixels positioned around the correction pixel. The correction pixel and each of the plurality of image pixels include a photodetector, a storage diode, and a frame transfer transistor. The photodetector is configured to accumulate charge in response to incident light. The frame transfer transistor is coupled between the photodetector and the storage diode. The first row driver coupled to the frame transfer transistor in each of the plurality of image pixels. The second row driver coupled to the frame transfer transistor in the correction pixel.
H04N 25/532 - Control of the integration time by controlling global shutters in CMOS SSIS
H04N 25/621 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
79.
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
A method of making a semiconductor device includes providing semiconductor region of a first conductivity type. A first region comprising the first conductivity type and a second dopant concentration greater than the first dopant concentration is provided within the region. The first region provides a JFET channel region for a JFET device. A second region comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion and a second portion below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
80.
SHORT-CIRCUIT DETECTOR FOR ELECTRONIC FUSE CIRCUIT
An electronic fuse that includes a clamp circuit to enhance the protection provided by the electronic fuse. The clamp circuit can detect a short circuit condition quickly and transmit a trigger signal to a controller so that a power transistor of the electronic fuse can be turned-OFF before the current through the power transistor causes overheating or damage. The clamp circuit is a dedicated circuit for short-circuit detection that can work with other current control circuits of the electronic fuse. The clamp circuit does not increase the power consumed by the electronic fuse while not in the short circuit condition. The clamp circuit is small and fast because it can use low-voltage devices, even as high voltages are present at the input and output of the electronic fuse.
H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for DC applications
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
81.
SILICON PHOTOMULTIPLIER LINEARITY IMPROVEMENT USING BIAS CURRENT
Silicon photomultiplier linearity using bias current. A silicon photomultiplier (SiPM) device includes: a single photon avalanche detector (SPAD) configured to selectively conduct an output current in response to detecting a photon; a current source defining a microcell supply node and configured to supply the output current to the microcell supply node; and at least one active device connected between the microcell supply node and the SPAD and configured to selectively conduct the output current therebetween. The current source has a first load capacitance at the microcell supply node, and the at least one active device has a second load capacitance. The SiPM device also includes a current regulator configured to conduct a precharge current from the microcell supply node to precharge each of the first load capacitance and the second load capacitance.
G01S 7/481 - Constructional features, e.g. arrangements of optical elements
G01S 17/931 - Lidar systems, specially adapted for specific applications for anti-collision purposes of land vehicles
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A sensor package may include a radiation transmitting substrate. A sensor package may include a sensor module coupled to the radiation transmitting substrate via a material that positions the radiation transmitting substrate away from an active region of the radiation transmitting substrate. The sensor module includes an integrated circuit embedded into the sensor module. The sensor module includes a fan-out structure including a first end portion and a second end portion. The first end portion is coupled to the integrated circuit. The second end portion is coupled to a conductive component. A sensor package may include a substrate coupled to the sensor module.
An illustrative die may include a first region and a second region that overlap in an overlap region, as well as an array of circuit elements arranged in a grid spanning the first region and the second region. An overlap set of circuit elements may include circuit elements from the array that are disposed in the overlap region. A first subset of this overlap set may receive a lithographic deposition of a first layer as the first layer is deposited to the first region using a first reticle aligned with the first region. A second subset of the overlap set may receive the lithographic deposition of the first layer as the first layer is deposited to the second region using a second reticle aligned with the second region. Corresponding methods, reticle sets, and systems are also disclosed.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
84.
METHOD AND SYSTEM FOR CONCEALING PACKET LOSS IN A COMMUNICATION SYSTEM
A method is disclosed. The method includes receiving a sequence of encoded data packets, storing valid packets from the sequence of encoded data packets in a history buffer, and detecting an invalid packet in the sequence of encoded data packets. The method further includes comparing a template-data block preceding the invalid packet to a plurality of data blocks stored in the history buffer to identify a closest-matching data block in the history buffer. In addition, the method includes generating a replacement block based on a first data block following the closest-matching data block and storing the replacement block in place of the invalid packet in the history buffer. The method further includes decoding data, including the valid packets and the replacement block, with a decoder.
A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.
The technology involves imaging devices, such as image sensors and imaging systems, providing methods of performing parallel readout of two or more rows of image pixels of such devices. This includes a deinterleaving approach that exploits both row read interleaving and memory deinterleaving in order to reduce the memory requirement to convert the row read parallelism to a serialized row stream. Parallel readout can be applied to non-contiguous rows of pixels, including when subsampling or when two contiguous rows share floating diffusion. The process may include parallel row read deinterleaving of a stored image by performing time division multiplexing partial deinterleaving of selected rows when reading selected rows in parallel from a pixel array to order even rows of the selected rows sequentially and odd rows of the selected rows sequentially. A memory store can time-shift either the even or odd rows of the partially deinterleaved selected rows.
H04N 25/767 - Horizontal readout lines, multiplexers or registers
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
87.
IMAGE SENSORS WITH INTEGRATED VISIBLE AND INFRARED LIGHT PIXELS
Image sensors, imaging systems, and methods for constructing image sensors. The image sensor includes a pixel array. The pixel array includes a first photosensitive region, a second photosensitive region, a spectral router, and a spectral filter. The first photosensitive region is configured to detect visible light within a color wavelength range. The second photosensitive region includes a plurality of light scattering structures. The second photosensitive region is configured to detect infrared light. The spectral router is positioned over at least the first photosensitive region. The spectral router is configured to route the visible light within the color wavelength range to the first photosensitive region. The spectral router is also configured to route the infrared light to the second photosensitive region. The spectral filter is positioned over the spectral router. The spectral filter is configured to block visible light outside of the color wavelength range.
H04N 25/131 - Arrangement of colour filter arrays [CFA]Filter mosaics characterised by the spectral characteristics of the filter elements including elements passing infrared wavelengths
H04N 23/11 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from different wavelengths for generating image signals from visible and infrared light wavelengths
88.
Colloidal Quantum Dots on a Matrix of Silicon Photomultiplier Microcells
The technology employs colloidal quantum dots (CQDs), in which a CQD layer is arranged over an array of SiPM microcells of an image sensor for an imaging module. Separate biases are applied to the CQD layer and to the microcell array. A method includes biasing the CQD layer of an imaging module at a first voltage, and biasing an array of photomultiplier microcells at a second voltage. Upon receiving a photon, the CQD layer generates a charge in response. The charge moves from the CQD layer into the array, where at least one photomultiplier microcell amplifies the charge. A signal from the imaging module is then output according to the amplified charge. This approach can significantly increase photon detection efficiency of an imaging element, which can be employed in a wide variety of applications such as lidar, medical imaging, and night vision or for other low-light imaging situations.
An assembly includes a conductive surface. The conductive surface includes an area with a hydrophilic surface. The hydrophilic surface is prepared by plasma cleaning. A semiconductor die is disposed on the hydrophilic surface. A coupling layer made of an adhesive material bonds the semiconductor die to the hydrophilic surface. The coupling layer fills a gap between the semiconductor die and the hydrophilic surface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
A circuit module includes a substrate with a patterned metal surface. The patterned metal surface includes a conductive terminal pad, a first conductive pad, and a second conductive pad that is non-adjacent to the conductive terminal pad. A first circuit portion is assembled on the first conductive pad and a second circuit portion is assembled on the second conductive pad. A conductive bridge electrically couples the conductive terminal pad and the second conductive pad. The conductive bridge includes an elevated span extending above and across the first conductive pad.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
92.
STACKED POWER TERMINALS IN A POWER ELECTRONICS MODULE
A module includes a power circuit enclosed in a casing. A first power terminal and a second power terminal of the power circuit each extend to an exterior of the casing. The first power terminal and the second power terminal separated by a gap are disposed in a stack on the exterior of the casing.
An illustrative apparatus includes a substrate (102) having a first portion (104-1) and a second portion (104-2) electrically isolated from one another. The apparatus also includes a leadless discrete component (106) with a first surface (108-1) and a second surface (108-2), and a semiconductor die (110). The first surface (108-1) of the leadless discrete component (106) is physically and electrically coupled to the first portion (104-1) of the substrate (102), while the semiconductor die (110) is physically and electrically coupled to the second portion (104-2) of the substrate (102). The apparatus further includes a first lead (112-1) electrically coupled to the first portion (104-1) of the substrate (102), a second lead (112-2) electrically coupled to the second portion (104-2) of the substrate (102), and a third lead (112-3) electrically coupled to the second surface (108-2) of the leadless discrete component (106). Corresponding apparatuses and methods are also disclosed.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
SiC substrates are in demand for high power applications such as electric vehicles, solar panels, and industrial electronics. A physical vapor transport (PVT) apparatus for growth of silicon carbide (SiC) ingots can be improved by incorporating a moveable source. During growth of the ingot, the shape of the growth interface can be maintained as a convex shape by keeping a substantially constant distance between the growth interface and the source material. It is shown that temperature gradients during the growth phase are also influenced by the shape of the growth interface. By moving the source during crystal growth, the resulting SiC ingot can be taller with fewer defects, and can be less likely to crack during subsequent grinding or polishing operations.
A battery monitoring system (BMS) for a battery of a battery electric system includes a sensor array, a processor, and memory. Execution of the instructions causes the processor to receive battery parameters from the sensor array during respective charging and discharging modes of the battery, including at least a voltage, current, and temperature of the battery. Separate charge-side and discharge-side resistances of the battery are determined during charging and discharging modes, followed by calculation of a degradation level of the battery using the charge-side and discharge-side resistances. The processor may also perform a preventive action in response to the degradation level exceeding a calibrated threshold.
An illustrative cooler assembly (100) may include an inlet (104), an outlet (106), a cooling channel (122), and a distribution channel (124). The cooling channel (122) may include an array of protrusions (114) configured to transfer heat from a plurality of electronic modules (110) to fluid (116) flowing through the array of protrusions (114). The plurality of electronic modules (110) may be disposed along a longitudinal axis (112) extending between the inlet (104) and the outlet (106). The distribution channel (124) may be in fluid communication with the cooling channel (122) via a venting system. The distribution channel (124) may be configured to direct fluid (116) entering at the inlet (104) to flow through the cooling channel (122) in a transverse direction substantially perpendicular to the longitudinal axis (112) before exiting at the outlet (106). Corresponding systems, assemblies, and methods are also disclosed.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
97.
SIC MOSFET SEMICONDUCTOR PACKAGES AND RELATED METHODS
A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
98.
DIODES WITH SCHOTTKY CONTACT INCLUDING LOCALIZED SURFACE REGIONS
In some aspects, the techniques described herein relate to a diode including: a substrate of a first conductivity type; a semiconductor layer of the first conductivity type disposed on the substrate, the semiconductor layer including a drift region; a shield region of a second conductivity type disposed in the semiconductor layer adjacent to the drift region; a surface region of the first conductivity type disposed in a first portion of the drift region adjacent to the shield region, the surface region having a doping concentration that is greater than a doping concentration of a second portion of the drift region adjacent to the surface region, the second portion of the drift region excluding the surface region; and a Schottky material disposed on: at least a portion of the shield region; the surface region in the first portion of the drift region; and the second portion of the drift region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
99.
COMPACT SEMICONDUCTOR PACKAGING USING A LEADLESS DISCRETE COMPONENT
An illustrative apparatus may include a substrate having a first portion and a second portion that is electrically isolated from the first portion. The apparatus may further include a leadless discrete component and a semiconductor die. The leadless discrete component may have a first surface and a second surface opposite the first surface, the first surface being physically coupled and electrically coupled to the first portion of the substrate, and the semiconductor die may be physically coupled and electrically coupled to the second portion of the substrate. The apparatus may further include a plurality of leads including a first lead electrically coupled to the first portion of the substrate, a second lead electrically coupled to the second portion of the substrate, and a third lead electrically coupled to the second surface of the leadless discrete component. Corresponding apparatuses and methods are also disclosed.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
An illustrative cooler assembly may include an inlet, an outlet, a cooling channel, and a distribution channel. The cooling channel may include an array of protrusions configured to transfer heat from a plurality of electronic modules to fluid flowing through the array of protrusions. The plurality of electronic modules may be disposed along a longitudinal axis extending between the inlet and the outlet. The distribution channel may be in fluid communication with the cooling channel via a venting system. The distribution channel may be configured to direct fluid entering at the inlet to flow through the cooling channel in a transverse direction substantially perpendicular to the longitudinal axis before exiting at the outlet. Corresponding systems, assemblies, and methods are also disclosed.
