ASM Japan K.K.

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IPC Class
C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes 15
H05H 1/24 - Generating plasma 15
H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers 12
H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers 10
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching 7
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Status
Pending 1
Registered / In Force 87
Found results for  patents

1.

Method of forming metal oxide hardmask

      
Application Number 14505290
Grant Number 09171716
Status In Force
Filing Date 2014-10-02
First Publication Date 2015-02-26
Grant Date 2015-10-27
Owner ASM JAPAN K.K. (Japan)
Inventor Fukuda, Hideaki

Abstract

y wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.

IPC Classes  ?

  • H01L 21/228 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a liquid phase, e.g. alloy diffusion processes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • G03F 1/00 - Originals for photomechanical production of textured or patterned surfaces, e.g. masks, photo-masks or reticlesMask blanks or pellicles thereforContainers specially adapted thereforPreparation thereof

2.

Method for forming single-phase multi-element film by PEALD

      
Application Number 13250721
Grant Number 08569184
Status In Force
Filing Date 2011-09-30
First Publication Date 2013-04-04
Grant Date 2013-10-29
Owner ASM Japan K.K. (Japan)
Inventor
  • Oka, Takahiro
  • Shimizu, Akira

Abstract

A method for forming a single-phase multi-element film on a substrate in a reaction zone by PEALD repeating a single deposition cycle. The single deposition cycle includes: adsorbing a precursor on the substrate in the absence of reactant and plasma; decomposing the precursor adsorbed on the substrate by an inert gas plasma; and reacting the decomposed precursor with a reactant gas plasma in the presence of the inert gas plasma. The multi-element film contains silicon and at least two non-metal elements constituting a matrix of the film, the precursor contains silicon and optionally at least one non-metal element to be incorporated in the matrix, and the reactant gas contains at least one non-metal element to be incorporated in the matrix.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers

3.

Method for reducing dielectric constant of film using direct plasma of hydrogen

      
Application Number 13191762
Grant Number 08551892
Status In Force
Filing Date 2011-07-27
First Publication Date 2013-01-31
Grant Date 2013-10-08
Owner ASM Japan K.K. (Japan)
Inventor Nakano, Akinori

Abstract

A method for reducing a dielectric constant of a film includes (i) forming a dielectric film on a substrate; (ii) treating a surface of the film without film formation, and (III) curing the film. Step (i) includes providing a dielectric film containing a porous matrix and a porogen on a substrate, step (ii) includes, prior to or subsequent to step (iii), treating the dielectric film with charged species of hydrogen generated by capacitively-coupled plasma without film deposition to reduce a dielectric constant of the dielectric film, and step (iii) includes UV-curing the dielectric film to remove at least partially the porogen from the film.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof
  • H05C 1/00 - Circuits or apparatus for generating electric shock effects
  • H05H 1/00 - Generating plasmaHandling plasma
  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

4.

Method for positioning wafers in multiple wafer transport

      
Application Number 13166367
Grant Number 09793148
Status In Force
Filing Date 2011-06-22
First Publication Date 2012-12-27
Grant Date 2017-10-17
Owner ASM Japan K.K. (Japan)
Inventor
  • Yamagishi, Takayuki
  • Suwada, Masaei
  • Tanaka, Hiroyuki

Abstract

A method for positioning wafers in dual wafer transport, includes: simultaneously moving first and second wafers placed on first and second end-effectors to positions over lift pins protruding from first and second susceptors, respectively; and correcting the positions of the first and second wafers without moving any of the lift pins relative to the respective susceptors or without moving the lift pins relative to each other, wherein when the first and second wafers are moved to the respective positions, the distance between the first wafer and tips of the lift pins of the first susceptor is substantially smaller than the distance between the second wafer and tips of the lift pins of the second susceptor.

IPC Classes  ?

  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

5.

High-throughput semiconductor-processing apparatus equipped with multiple dual-chamber modules

      
Application Number 13154271
Grant Number 09312155
Status In Force
Filing Date 2011-06-06
First Publication Date 2012-12-06
Grant Date 2016-04-12
Owner ASM Japan K.K. (Japan)
Inventor
  • Mori, Yukihiro
  • Yamagishi, Takayuki

Abstract

A wafer-processing apparatus includes: eight or ten reactors with identical capacity for processing wafers on the same plane, constituting four or five discrete units, each unit having two reactors arranged side by side with their fronts aligned in a line; a wafer-handling chamber including two wafer-handling robot arms each having at least two end-effectors; a load lock chamber; and a sequencer for performing, using the two wafer-handling robot arms, steps of unloading/loading processed/unprocessed wafers from/to any one of the units, and steps of unloading/loading processed/unprocessed wafers from/to all the other respective units in sequence while the wafers are in the one of the units.

IPC Classes  ?

  • B05C 11/10 - Storage, supply or control of liquid or other fluent materialRecovery of excess liquid or other fluent material
  • B32B 41/00 - Arrangements for controlling or monitoring lamination processesSafety arrangements
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

6.

Method of depositing dielectric film by ALD using precursor containing silicon, hydrocarbon, and halogen

      
Application Number 13566069
Grant Number 08563443
Status In Force
Filing Date 2012-08-03
First Publication Date 2012-11-22
Grant Date 2013-10-22
Owner ASM Japan K.K. (Japan)
Inventor Fukazawa, Atsuki

Abstract

A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: supplying a precursor in a pulse to adsorb the precursor on a surface of a substrate; supplying a reactant gas in a pulse over the surface without overlapping the supply of the precursor; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least two halogens attached to silicon in its molecule.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
  • H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers

7.

Atomic layer deposition for controlling vertical film growth

      
Application Number 13094402
Grant Number 08592005
Status In Force
Filing Date 2011-04-26
First Publication Date 2012-11-01
Grant Date 2013-11-26
Owner ASM Japan K.K. (Japan)
Inventor Ueda, Shintaro

Abstract

A method for forming a film by atomic layer deposition wherein vertical growth of a film is controlled, includes: (i) adsorbing a metal-containing precursor for film formation on a concave or convex surface pattern of a substrate; (ii) oxidizing the adsorbed precursor to form a metal oxide sub-layer; (iii) adsorbing a metal-free inhibitor on the metal oxide sub-layer more on a top/bottom portion than on side walls of the concave or convex surface pattern; and (iv) repeating steps (i) to (iii) to form a film constituted by multiple metal oxide sub-layers while controlling vertical growth of the film by step (iii). The adsorption of the inhibitor is antagonistic to next adsorption of the precursor on the metal oxide sub-layer.

IPC Classes  ?

  • H05H 1/24 - Generating plasma
  • B05D 1/36 - Successively applying liquids or other fluent materials, e.g. without intermediate treatment
  • B05D 3/00 - Pretreatment of surfaces to which liquids or other fluent materials are to be appliedAfter-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials
  • B05D 1/32 - Processes for applying liquids or other fluent materials using means for protecting parts of a surface not to be coated, e.g. using stencils, resists
  • B05D 5/00 - Processes for applying liquids or other fluent materials to surfaces to obtain special surface effects, finishes or structures

8.

Footing reduction using etch-selective layer

      
Application Number 13085698
Grant Number 08298951
Status In Force
Filing Date 2011-04-13
First Publication Date 2012-10-18
Grant Date 2012-10-30
Owner ASM Japan K.K. (Japan)
Inventor Nakano, Ryu

Abstract

A method of forming side spacers upwardly extending from a substrate, includes: providing a template constituted by a photoresist formed on and in contact with an etch-selective layer laminated on a substrate; anisotropically etching the template in a thickness direction with an oxygen-containing plasma to remove a footing of the photoresist and an exposed portion of the underlying layer; depositing a spacer film on the template by atomic layer deposition (ALD); and forming side spacers using the spacer film by etching. The etch-selective layer has a substantially lower etch rate than that of the photoresist.

IPC Classes  ?

9.

Calibration method of UV sensor for UV curing

      
Application Number 13040013
Grant Number 08466411
Status In Force
Filing Date 2011-03-03
First Publication Date 2012-09-06
Grant Date 2013-06-18
Owner ASM Japan K.K. (Japan)
Inventor Arai, Hirofumi

Abstract

A method for managing UV irradiation for treating substrates in the course of treating multiple substrates consecutively with UV light, includes: exposing a first UV sensor to the UV light at first intervals to measure illumination intensity of the UV light so as to adjust the illumination intensity to a desired level based on the measured illumination intensity; and exposing a second UV sensor to the UV light at second intervals to measure illumination intensity of the UV light so as to calibrate the first UV sensor by equalizing the illumination intensity measured by the first UV sensor substantially with the illumination intensity measured by the second UV sensor, wherein each second interval is longer than each first interval.

IPC Classes  ?

  • G01D 18/00 - Testing or calibrating apparatus or arrangements provided for in groups
  • G01R 31/26 - Testing of individual semiconductor devices

10.

Method of depositing dielectric film by modified PEALD method

      
Application Number 13410970
Grant Number 08415259
Status In Force
Filing Date 2012-03-02
First Publication Date 2012-08-30
Grant Date 2013-04-09
Owner ASM Japan K.K. (Japan)
Inventor
  • Lee, Woo Jin
  • Hong, Kuo-Wei
  • Shimizu, Akira
  • Jeong, Daekyun

Abstract

A method of forming a film on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers

11.

Method of depositing dielectric film by ALD using precursor containing silicon, hydrocarbon, and halogen

      
Application Number 13030438
Grant Number 08329599
Status In Force
Filing Date 2011-02-18
First Publication Date 2012-08-23
Grant Date 2012-12-11
Owner ASM Japan K.K. (Japan)
Inventor
  • Fukazawa, Atsuki
  • Takamure, Noboru

Abstract

A method of forming a dielectric film having at least Si—N, Si—C, or Si—B bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: adsorbing a precursor on a surface of a substrate; supplying a reactant gas over the surface; reacting the precursor and the reactant gas on the surface; and repeating the above steps to form a dielectric film having at least Si—N, Si—C, or Si—B bonds on the substrate. The precursor has at least one Si—C or Si—N bond, at least one hydrocarbon, and at least one halogen attached to silicon in its molecule.

IPC Classes  ?

  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

12.

Method of depositing film by atomic layer deposition with pulse-time-modulated plasma

      
Application Number 13016735
Grant Number 08465811
Status In Force
Filing Date 2011-01-28
First Publication Date 2012-08-02
Grant Date 2013-06-18
Owner ASM Japan K.K. (Japan)
Inventor Ueda, Shintaro

Abstract

A thin film is formed by alternating multiple times, respectively, a process of adsorbing a precursor onto a substrate and a process of treating the adsorbed surface using a reactant gas and a plasma, wherein the reactant gas is supplied substantially uniformly over the substrate, and the plasma is pulse-time-modulated and applied in the process of supplying the reactant gas.

IPC Classes  ?

  • C23C 16/56 - After-treatment
  • C23C 16/515 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using pulsed discharges

13.

Method of forming metal oxide hardmask

      
Application Number 13333420
Grant Number 08901016
Status In Force
Filing Date 2011-12-21
First Publication Date 2012-06-28
Grant Date 2014-12-02
Owner ASM Japan K.K. (Japan)
Inventor
  • Ha, Jeongseok
  • Fukuda, Hideaki
  • Kaido, Shintaro

Abstract

y wherein M represents at least one metal element, x is less than one including zero, and y is approximately two or a stoichiometrically-determined number.

IPC Classes  ?

  • H01L 21/228 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a liquid phase, e.g. alloy diffusion processes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

14.

Method of depositing film with tailored comformality

      
Application Number 12940906
Grant Number 08470187
Status In Force
Filing Date 2010-11-05
First Publication Date 2012-05-10
Grant Date 2013-06-25
Owner ASM Japan K.K. (Japan)
Inventor Ha, Jeongseok

Abstract

A method of depositing a film with a target conformality on a patterned substrate, includes: depositing a first film on a convex pattern and a bottom surface; and depositing a second film on the first film, thereby forming an integrated film having a target conformality, wherein one of the first and second films is a conformal film which is non-flowable when being deposited and has a conformality of about 80% to about 100%, and the other of the first and second films is a flowable film which is flowable when being deposited.

IPC Classes  ?

  • B44C 1/22 - Removing surface-material, e.g. by engraving, by etching

15.

Shower plate having different aperture dimensions and/or distributions

      
Application Number 12910607
Grant Number 08845806
Status In Force
Filing Date 2010-10-22
First Publication Date 2012-04-26
Grant Date 2014-09-30
Owner ASM Japan K.K. (Japan)
Inventor
  • Aida, Koei
  • Baba, Tomoyuki

Abstract

A shower plate is adapted to be attached to the showerhead and includes a front surface adapted to face the susceptor; and a rear surface opposite to the front surface. The shower plate has multiple apertures each extending from the rear surface to the front surface for passing gas therethrough in this direction, and the shower plate has at least one quadrant section defined by radii, wherein the one quadrant section has an opening ratio of a total volume of openings of all the apertures distributed in the section to a total volume of the one quadrant section, which opening ratio is substantially smaller than an opening ratio of another quadrant section of the shower plate.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23F 1/00 - Etching metallic material by chemical means
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/503 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using DC or AC discharges
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
  • C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes

16.

Method of forming conformal film having si-N bonds on high-aspect ratio pattern

      
Application Number 12875889
Grant Number 08394466
Status In Force
Filing Date 2010-09-03
First Publication Date 2012-03-08
Grant Date 2013-03-12
Owner ASM Japan K.K. (Japan)
Inventor
  • Hong, Kuo-Wei
  • Shimizu, Akira
  • Namba, Kunitoshi
  • Lee, Woo-Jin

Abstract

A method of forming a conformal dielectric film having Si—N bonds on a substrate having a patterned surface includes: introducing a reactant gas into a reaction space; introducing a silicon precursor in pulses of less than 5-second duration into the reaction space; applying a first RF power to the reaction space during the pulse of the silicon precursor; applying a second RF power to the reaction space during the interval of the silicon precursor pulse, wherein an average intensity of the second RF power during the interval of the silicon precursor pulse is greater than that of the first RF power during the pulse of the silicon precursor; and repeating the cycle to form a conformal dielectric film having Si—N bonds with a desired thickness on the patterned surface of the substrate.

IPC Classes  ?

17.

Method of tailoring conformality of Si-containing film

      
Application Number 12847848
Grant Number 08669185
Status In Force
Filing Date 2010-07-30
First Publication Date 2012-02-02
Grant Date 2014-03-11
Owner ASM Japan K.K. (Japan)
Inventor
  • Onizawa, Shigeyuki
  • Lee, Woo-Jin
  • Fukuda, Hideaki
  • Namba, Kunitoshi

Abstract

A method of tailoring conformality of a film deposited on a patterned surface includes: (I) depositing a film by PEALD or pulsed PECVD on the patterned surface; (II) etching the film, wherein the etching is conducted in a pulse or pulses, wherein a ratio of an etching rate of the film on a top surface and that of the film on side walls of the patterns is controlled as a function of the etching pulse duration and the number of etching pulses to increase a conformality of the film; and (III) repeating (I) and (II) to satisfy a target film thickness.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes

18.

Method for forming interconnect structure having airgap

      
Application Number 12718731
Grant Number 08241991
Status In Force
Filing Date 2010-03-05
First Publication Date 2011-09-08
Grant Date 2012-08-14
Owner ASM Japan K.K. (Japan)
Inventor
  • Hsieh, Julian J.
  • Kobayashi, Nobuyoshi
  • Shimizu, Akira
  • Matsushita, Kiyohiro
  • Fukazawa, Atsuki

Abstract

A method for forming an interconnect structure with airgaps, includes: providing a structure having a trench formed on a substrate; depositing a spacer oxide layer on sidewalls of the trench as sidewall spacers by plasma enhanced atomic layer deposition; filling the trench having the sidewall spacers with copper; removing the sidewall spacers to form an airgap structure; and encapsulating the airgap structure, wherein airgaps are formed between the filled copper and the sidewalls of the trench.

IPC Classes  ?

  • H01L 21/76 - Making of isolation regions between components

19.

Heater block for use in a semiconductor processing tool

      
Application Number 29324405
Grant Number D0643055
Status In Force
Filing Date 2008-09-11
First Publication Date 2011-08-09
Grant Date 2011-08-09
Owner ASM Japan K.K. (Japan)
Inventor Takahashi, Satoshi

20.

Method of depositing dielectric film having Si-N bonds by modified peald method

      
Application Number 12901323
Grant Number 08173554
Status In Force
Filing Date 2010-10-08
First Publication Date 2011-04-14
Grant Date 2012-05-08
Owner ASM Japan K.K. (Japan)
Inventor
  • Lee, Woo Jin
  • Hong, Kuo-Wei
  • Shimizu, Akira
  • Jeong, Deakyun

Abstract

A method of forming dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which the semiconductor substrate is placed; introducing a hydrogen-containing silicon precursor in pulses of less than 1.0-second duration into the reaction space wherein the reactive gas and the rare gas are introduced; exiting a plasma in pulses of less than 1.0-second duration immediately after the silicon precursor is shut off; and maintaining the reactive gas and the rare gas as a purge of less than 2.0-second duration.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
  • H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers

21.

Method of forming stress-tuned dielectric film having Si-N bonds by modified PEALD

      
Application Number 12832739
Grant Number 08334219
Status In Force
Filing Date 2010-07-08
First Publication Date 2011-01-20
Grant Date 2012-12-18
Owner ASM Japan K.K. (Japan)
Inventor
  • Lee, Woo-Jin
  • Hong, Kuo-Wei
  • Shimuzu, Akira

Abstract

A method of forming stress-tuned dielectric films having Si—N bonds on a semiconductor substrate by modified plasma enhanced atomic layer deposition (PEALD), includes: introducing a nitrogen-and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space using a high frequency RF power source and a low frequency RF power source; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a stress-tuned dielectric film having Si—N bonds on the substrate.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers

22.

Method of forming highly conformal amorphous carbon layer

      
Application Number 12467017
Grant Number 07842622
Status In Force
Filing Date 2009-05-15
First Publication Date 2010-11-18
Grant Date 2010-11-30
Owner ASM Japan K.K. (Japan)
Inventor
  • Lee, Woo-Jin
  • Fukazawa, Atsuki

Abstract

A method of forming a conformal amorphous hydrogenated carbon layer on an irregular surface of a semiconductor substrate includes: vaporizing a hydrocarbon-containing precursor; introducing the vaporized precursor and an argon gas into a CVD reaction chamber inside which the semiconductor substrate is placed; depositing a conformal amorphous hydrogenated carbon layer on the irregular surface of the semiconductor substrate by plasma CVD; and controlling the deposition of the conformal ratio of the depositing conformal amorphous hydrogenated carbon layer. The controlling includes (a) adjusting a step coverage of the conformal amorphous hydrogenated carbon layer to about 30% or higher as a function of substrate temperature, and (b) adjusting a conformal ratio of the conformal amorphous hydrogenated carbon layer to about 0.9 to about 1.1 as a function of RF power and/or argon gas flow rate.

IPC Classes  ?

23.

Method for depositing flowable material using alkoxysilane or aminosilane precursor

      
Application Number 12489252
Grant Number 07825040
Status In Force
Filing Date 2009-06-22
First Publication Date 2010-11-02
Grant Date 2010-11-02
Owner ASM Japan K.K. (Japan)
Inventor
  • Fukazawa, Atsuki
  • Tazawa, Hisashi
  • Ha, Jeongseok
  • Ueda, Shintaro

Abstract

A method of filling a recess with an insulation film includes: introducing an alkoxysilane or aminosilane precursor containing neither a Si—C bond nor a C—C bond into a reaction chamber where a substrate having an irregular surface including a recess is placed; and depositing a flowable Si-containing insulation film on the irregular surface of the substrate to fill the recess therewith by plasma reaction at −50° C. to 100° C.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers

24.

Method of depositing silicon oxide film by plasma enhanced atomic layer deposition at low temperature

      
Application Number 12416809
Grant Number 08197915
Status In Force
Filing Date 2009-04-01
First Publication Date 2010-10-07
Grant Date 2012-06-12
Owner ASM Japan K.K. (Japan)
Inventor
  • Oka, Takahiro
  • Shimizu, Akira

Abstract

A method of depositing a silicon oxide film on a resist pattern or etched lines formed on a substrate by plasma enhanced atomic layer deposition (PEALD) includes: providing a substrate on which a resist pattern or etched lines are formed in a PEALD reactor; controlling a temperature of a susceptor on which the substrate is placed at less than 50° C. as a deposition temperature; introducing a silicon-containing precursor and an oxygen-supplying reactant to the PEALD reactor and applying RF power therein in a cycle, while the deposition temperature is controlled substantially or nearly at a constant temperature of less than 50° C., thereby depositing a silicon oxide atomic layer on the resist pattern or etched lines; and repeating the cycle multiple times substantially or nearly at the constant temperature to deposit a silicon oxide atomic film on the resist pattern or etched lines.

IPC Classes  ?

  • H05H 1/24 - Generating plasma
  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes

25.

Method of forming conformal dielectric film having Si-N bonds by PECVD

      
Application Number 12778808
Grant Number 07972980
Status In Force
Filing Date 2010-05-12
First Publication Date 2010-09-02
Grant Date 2011-07-05
Owner ASM Japan K.K. (Japan)
Inventor
  • Lee, Woo Jin
  • Shimizu, Akira

Abstract

A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and a rare gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor as a first precursor and a hydrocarbon gas as a second precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film doped with carbon and having Si—N bonds on the substrate.

IPC Classes  ?

  • H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers

26.

Method of forming conformal dielectric film having Si-N bonds by PECVD

      
Application Number 12357174
Grant Number 07919416
Status In Force
Filing Date 2009-01-21
First Publication Date 2010-07-22
Grant Date 2011-04-05
Owner ASM Japan K.K. (Japan)
Inventor
  • Lee, Woo-Jin
  • Shimizu, Akira
  • Fukazawa, Atsuki

Abstract

A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.

IPC Classes  ?

  • H01L 21/337 - Field-effect transistors with a PN junction gate

27.

Method for controlling flow and concentration of liquid precursor

      
Application Number 12353076
Grant Number 08151814
Status In Force
Filing Date 2009-01-13
First Publication Date 2010-07-15
Grant Date 2012-04-10
Owner ASM Japan K.K. (Japan)
Inventor
  • Shimizu, Akira
  • Kobayashi, Akiko
  • Kanayama, Hiroki

Abstract

A method for controlling flow and concentration of a liquid precursor includes: supplying a carrier gas to a first auto-pressure regulator and outputting therefrom the carrier gas at a first pressure to a precursor reservoir; outputting the mixture of the vaporized precursor and the carrier gas from the precursor reservoir; and supplying the mixture to a second auto-pressure regulator and outputting therefrom the mixture at a second pressure to a reactor via an orifice.

IPC Classes  ?

  • F17D 1/17 - Facilitating the conveyance of liquids or effecting the conveyance of viscous products by modification of their viscosity by mixing with another liquid
  • C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials

28.

Semiconductor-processing apparatus equipped with robot diagnostic module

      
Application Number 12341869
Grant Number 08666551
Status In Force
Filing Date 2008-12-22
First Publication Date 2010-06-24
Grant Date 2014-03-04
Owner ASM Japan K.K. (Japan)
Inventor
  • Takizawa, Masahiro
  • Nishino, Teruhide

Abstract

A semiconductor wafer manufacturing apparatus is equipped with a diagnostic module for diagnosing integrity of a transfer robot. The diagnostic module is attached to one side of a semiconductor wafer transfer chamber provided with the transfer robot, which side is also used for the purpose of maintenance, for example. One or more sensors are installed in the diagnostic module so that when the transfer robot is inserted into the diagnostic module, the position or shape of each end effector of the transfer robot is detected and compared against a pre-registered normal condition, thereby diagnosing the integrity of the end effector of the transfer robot, while performing wafer processing.

IPC Classes  ?

  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices

29.

Method of forming conformal dielectric film having Si-N bonds by PECVD

      
Application Number 12553759
Grant Number 08142862
Status In Force
Filing Date 2009-09-03
First Publication Date 2010-06-10
Grant Date 2012-03-27
Owner ASM Japan K.K. (Japan)
Inventor
  • Lee, Woo Jin
  • Shimizu, Akira

Abstract

A method of forming a conformal dielectric film having Si—N bonds on a semiconductor substrate by plasma enhanced chemical vapor deposition (PECVD) includes: introducing a nitrogen- and hydrogen-containing reactive gas and an additive gas into a reaction space inside which a semiconductor substrate is placed; applying RF power to the reaction space; and introducing a hydrogen-containing silicon precursor in pulses into the reaction space wherein a plasma is excited, thereby forming a conformal dielectric film having Si—N bonds on the substrate.

IPC Classes  ?

  • C23C 8/00 - Solid state diffusion of only non-metal elements into metallic material surfacesChemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals
  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • H05H 1/24 - Generating plasma

30.

Method for forming low-carbon CVD film for filling trenches

      
Application Number 12331309
Grant Number 08765233
Status In Force
Filing Date 2008-12-09
First Publication Date 2010-06-10
Grant Date 2014-07-01
Owner ASM Japan K.K. (Japan)
Inventor
  • Fukazawa, Atsuki
  • Tazawa, Hisashi
  • Onizawa, Shigeyuki

Abstract

A method of forming a low-carbon silicon-containing film by CVD on a substrate having trenches includes: introducing a silicon-containing compound having three or less hydrocarbon units in its molecule and having a boiling temperature of 35° C. to 220° C.; applying RF power to the gas; and depositing a film on a substrate having trenches wherein the substrate is controlled at a temperature such that components of the silicon-containing compound are at least partially liquidified on the substrate, thereby filling the trenches with the film.

IPC Classes  ?

  • C23C 16/22 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material

31.

Method of forming insulation film using plasma treatment cycles

      
Application Number 12618419
Grant Number 08647722
Status In Force
Filing Date 2009-11-13
First Publication Date 2010-05-20
Grant Date 2014-02-11
Owner ASM Japan K.K. (Japan)
Inventor
  • Kobayashi, Akiko
  • Shimizu, Akira
  • Hong, Kuo-Wei
  • Kobayashi, Nobuyoshi
  • Fukazawa, Atsuki

Abstract

A film forming cycle based on pulse CVD or ALD is repeated multiple times to form a single layer of insulation film, while a reforming cycle is implemented in the aforementioned process, either once or multiple times per each film forming cycle, by treating the surface of formed film using a treating gas that has been activated by a plasma.

IPC Classes  ?

32.

Purge step-controlled sequence of processing semiconductor wafers

      
Application Number 12248741
Grant Number 07972961
Status In Force
Filing Date 2008-10-09
First Publication Date 2010-04-15
Grant Date 2011-07-05
Owner ASM Japan K.K. (Japan)
Inventor
  • Sugiyama, Toru
  • Nakano, Ryu

Abstract

A method of processing semiconductor substrates includes: depositing a film on a substrate in a reaction chamber; evacuating the reaction chamber without purging the reaction chamber; opening a gate valve and replacing the substrate with a next substrate via the transfer chamber wherein the pressure of the transfer chamber is controlled to be higher than that of the reaction chamber before and while the gate valve is opened; repeating the above steps and removing the substrate from the reaction chamber; and purging and evacuating the reaction chamber, and cleaning the reaction chamber with a cleaning gas.

IPC Classes  ?

  • H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes

33.

Method for forming metal film by ALD using beta-diketone metal complex

      
Application Number 12251343
Grant Number 08133555
Status In Force
Filing Date 2008-10-14
First Publication Date 2010-04-15
Grant Date 2012-03-13
Owner ASM Japan K.K. (Japan)
Inventor
  • Shinriki, Hiroshi
  • Namba, Kunitoshi
  • Jeong, Daekyun

Abstract

A method of forming a single-metal film on a substrate by plasma ALD includes: contacting a surface of a substrate with a β-diketone metal complex in a gas phase; exposing molecule-attached surface to a nitrogen-hydrogen mixed plasma; and repeating the above steps, thereby accumulating atomic layers to form a single-metal film on the substrate.

IPC Classes  ?

  • H05H 1/24 - Generating plasma
  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds

34.

Atomic composition controlled ruthenium alloy film formed by plasma-enhanced atomic layer deposition

      
Application Number 12201434
Grant Number 08084104
Status In Force
Filing Date 2008-08-29
First Publication Date 2010-03-04
Grant Date 2011-12-27
Owner ASM Japan K.K. (Japan)
Inventor
  • Shinriki, Hiroshi
  • Namba, Kunitoshi
  • Jeong, Daekyun

Abstract

(y2)) is more than zero but less than 15, and z2 is 0.10 or greater.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes

35.

Semiconductor manufacturing apparatus equipped with wafer inspection device and inspection techniques

      
Application Number 12198004
Grant Number 07832353
Status In Force
Filing Date 2008-08-25
First Publication Date 2010-02-25
Grant Date 2010-11-16
Owner ASM Japan K.K. (Japan)
Inventor
  • Takizawa, Masahiro
  • Nishino, Teruhide

Abstract

A semiconductor manufacturing apparatus includes a processing unit for processing at least one wafer; a loading/unloading unit for loading/unloading at least wafer; an input/output chamber for taking in a processed wafer from the processing unit and taking out the processed wafer to the loading/unloading unit, and taking in a unprocessed wafer from the loading/unloading unit and taking out the unprocessed wafer to the reaction unit; and a wafer inspection device for inspecting the processed wafer through a light transmittable top portion of the input/output chamber, through which light is transmittable, while the processed wafer is temporarily placed in the input/output chamber.

IPC Classes  ?

  • B05C 11/00 - Component parts, details or accessories not specifically provided for in groups

36.

Semiconductor manufacturing apparatus

      
Application Number 12187249
Grant Number 07945345
Status In Force
Filing Date 2008-08-06
First Publication Date 2010-02-11
Grant Date 2011-05-17
Owner ASM Japan K.K. (Japan)
Inventor
  • Takizawa, Masahiro
  • Makino, Tsutomu

Abstract

A semiconductor manufacturing apparatus includes a first program on a controller and a second program on an interface board between the controller and controlled devices. Both of the programs update their own counters and exchange their counter values with each other, serving as bi-directional software watchdog timers (WDT). If a counter value of the first program on the controller sent to the second program on the interface board is determined to be abnormal by the second program, the second program on the interface board sends commands to the controlled devices to terminate output so that the apparatus is navigated to a safe mode. The first program similarly monitors the counter values of the second program for anomalies. This bi-directional software WDT can be implemented as add-on to software programs that already exist in the controller and the interface board, therefore, this implementation does not incur extra cost of hardware of the apparatus.

IPC Classes  ?

  • G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
  • G06F 11/00 - Error detectionError correctionMonitoring

37.

Method for designing shower plate for plasma CVD apparatus

      
Application Number 12039699
Grant Number 08053036
Status In Force
Filing Date 2008-06-02
First Publication Date 2009-12-03
Grant Date 2011-11-08
Owner ASM Japan K.K. (Japan)
Inventor Takahashi, Satoshi

Abstract

A method of designing a shower plate for a plasma CVD apparatus includes (a) providing a shower plate having a convex surface configured by a convex equation; (b) forming a film on a wafer using the shower plate in the plasma CVD apparatus; (c) determining a distribution of thickness of the film formed on the wafer by dividing a diametrical cross section of the film into multiple regions; (d) determining at least one secondary equation; and (e) designing a surface configuration of the shower plate by overlaying the secondary equation on the convex equation.

IPC Classes  ?

  • H05H 1/24 - Generating plasma
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes

38.

Device isolation technology on semiconductor substrate

      
Application Number 12130522
Grant Number 07622369
Status In Force
Filing Date 2008-05-30
First Publication Date 2009-11-24
Grant Date 2009-11-24
Owner ASM JAPAN K.K. (Japan)
Inventor
  • Lee, Woo Jin
  • Fukazawa, Atsuki
  • Matsuki, Nobuo

Abstract

A method of forming device isolation regions on a trench-formed silicon substrate and removing residual carbon therefrom includes providing a flowable, insulative material constituted by silicon, carbon, nitrogen, hydrogen, oxygen or any combination of two or more thereof; forming a thin insulative layer, by using the flowable, insulative material, in a trench located on a semiconductor substrate wherein the flowable, insulative material forms a conformal coating in a silicon and nitrogen rich condition whereas in a carbon rich condition, the flowable, insulative material vertically grows from the bottom of the trenches; and removing the residual carbon deposits from the flowable, insulative material by multi-step curing, such as O2 thermal annealing, ozone UV curing followed by N2 thermal annealing.

IPC Classes  ?

  • H01L 21/76 - Making of isolation regions between components
  • H01L 21/36 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
  • H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
  • H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
  • H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers

39.

Method of forming a high transparent carbon film

      
Application Number 12115386
Grant Number 07632549
Status In Force
Filing Date 2008-05-05
First Publication Date 2009-11-05
Grant Date 2009-12-15
Owner ASM Japan K.K. (Japan)
Inventor Goundar, Kamal Kishore

Abstract

β/inert gas of 0.25 or less into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-based polymer film on the substrate by plasma polymerization of the gas at a processing temperature (T) wherein T≦(−800R+500).

IPC Classes  ?

  • H05H 1/24 - Generating plasma
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating

40.

Wafer processing apparatus with wafer alignment device

      
Application Number 12062419
Grant Number 07963736
Status In Force
Filing Date 2008-04-03
First Publication Date 2009-10-08
Grant Date 2011-06-21
Owner ASM Japan K.K. (Japan)
Inventor
  • Takizawa, Masahiro
  • Suwada, Masaei
  • Akagawa, Masayuki

Abstract

A semiconductor-processing apparatus includes: a wafer handling chamber; a wafer processing chamber; a wafer handling device; a first photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer partially blocks light received by the first photosensor at a ready-to-load position and substantially entirely blocks light received by the first photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction; and a second photosensor disposed in the wafer handling chamber in front of the wafer processing chamber at a position where the wafer does not block light received by the second photosensor at the ready-to-load position and partially blocks light received by the second photosensor when the wafer moves from the ready-to-load position toward the wafer processing chamber in the x-axis direction.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

41.

Substrate-supporting device having continuous concavity

      
Application Number 12051769
Grant Number 07993462
Status In Force
Filing Date 2008-03-19
First Publication Date 2009-09-24
Grant Date 2011-08-09
Owner ASM Japan K.K. (Japan)
Inventor Takahashi, Satoshi

Abstract

A substrate-supporting device has a top surface for placing a substrate thereon composed of a plurality of surfaces separated from each other and defined by a continuous concavity being in gas communication with at least one through-hole passing through the substrate-supporting device in its thickness direction. The continuous concavity is adapted to allow gas to flow in the continuous concavity and through the through-hole under a substrate placed on the top surface.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
  • C23F 1/00 - Etching metallic material by chemical means
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

42.

Ruthenium alloy film for copper interconnects

      
Application Number 12129345
Grant Number 07799674
Status In Force
Filing Date 2008-05-29
First Publication Date 2009-08-20
Grant Date 2010-09-21
Owner ASM Japan K.K. (Japan)
Inventor
  • Shinriki, Hiroshi
  • Inoue, Hiroaki

Abstract

A method for forming interconnect wiring, includes: (i) covering a surface of a connection hole penetrating through interconnect dielectric layers formed on a substrate for interconnect wiring, with an underlying alloy layer selected from the group consisting of an alloy film containing ruthenium (Ru) and at least one other metal atom (M), a nitride film thereof, a carbide film thereof, and an nitride-carbide film thereof, and (ii) filling copper or a copper compound in the connection hole covered with the underlying layer.

IPC Classes  ?

  • H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layersAfter-treatment of these layers
  • H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
  • H01L 21/461 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L 29/40 - Electrodes
  • H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

43.

Clamping mechanism for semiconductor device

      
Application Number 12027767
Grant Number 08118940
Status In Force
Filing Date 2008-02-07
First Publication Date 2009-08-13
Grant Date 2012-02-21
Owner ASM Japan K.K. (Japan)
Inventor
  • Shimizu, Akira
  • Watanabe, Akira

Abstract

A clamping mechanism for a semiconductor substrate includes: a C-shaped pickup plate; a susceptor top plate having a periphery adapted to receive and support an inner periphery portion of the C-shaped pickup plate thereon; and a clamp comprising (i) a top ring portion for clamping the substrate by sandwiching a periphery of the substrate between the top ring portion and the susceptor top plate and (ii) a pickup plate supporting portion adapted to support an outer periphery portion of the C-shaped pickup plate, wherein the C-shaped pickup plate is movable between the top ring portion and the pickup plate supporting portion, and the clamp is movable upward together with the C-shaped pickup plate and the susceptor top plate.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23F 1/00 - Etching metallic material by chemical means
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

44.

Method for forming Ta-Ru liner layer for Cu wiring

      
Application Number 11955275
Grant Number 07655564
Status In Force
Filing Date 2007-12-12
First Publication Date 2009-06-18
Grant Date 2010-02-02
Owner ASM Japan, K.K. (Japan)
Inventor
  • Shinriki, Hiroshi
  • Jeong, Daekyun

Abstract

A method of forming a Ta—Ru metal liner layer for Cu wiring includes: (i) conducting atomic deposition of Ta X times, each atomic deposition of Ta being accomplished by a pulse of hydrogen plasma, wherein X is an integer such that a surface of an underlying layer is not covered with Ta particles; (ii) after step (i), conducting atomic deposition of Ru Y times, each atomic deposition of Ru being accomplished by a pulse of hydrogen plasma, wherein Y is an integer such that the Ta particles are not covered with Ru particles; and (iii) repeating steps (i) and (ii) Z times, thereby forming a Ta—Ru metal liner layer on a Cu wiring substrate.

IPC Classes  ?

  • H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups

45.

Method for forming dielectric film using siloxane-silazane mixture

      
Application Number 11955766
Grant Number 08003174
Status In Force
Filing Date 2007-12-13
First Publication Date 2009-06-18
Grant Date 2011-08-23
Owner ASM Japan K.K. (Japan)
Inventor
  • Fukazawa, Atsuki
  • Lee, Woo Jin
  • Matsuki, Nobuo

Abstract

A method of forming a dielectric film, includes: introducing a siloxane gas essentially constituted by Si, O, C, and H and a silazane gas essentially constituted by Si, N, H, and optionally C into a reaction chamber where a substrate is placed; depositing a siloxane-based film including Si—N bonds on the substrate by plasma reaction; and annealing the siloxane-based film on the substrate in an annealing chamber to remove Si—N bonds from the film.

IPC Classes  ?

46.

Method for forming dielectric SiOCH film having chemical stability

      
Application Number 11952891
Grant Number 07807566
Status In Force
Filing Date 2007-12-07
First Publication Date 2009-06-11
Grant Date 2010-10-05
Owner ASM Japan K.K. (Japan)
Inventor
  • Tsuji, Naoto
  • Matsushita, Kiyohiro
  • Kato, Manabu
  • Takamure, Noboru

Abstract

A method for determining conditions for forming a dielectric SiOCH film, includes: (i) forming a dielectric SiOCH film on a substrate under conditions; (ii) evaluating the conditions using a ratio of Si—CH3 bonding strength to Si—O bonding strength of the film as formed in step (i); (iii) if the ratio is 2.50 % or higher, confirming the conditions, and if the ratio is less than 2.50 %, changing the conditions by changing at least one of the susceptor temperature, the distance between upper and lower electrodes, the RF power, and the curing time; and (iv) repeating steps (i) to (iii) until the ratio is 2.50 % or higher.

IPC Classes  ?

  • H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layersAfter-treatment of these layers

47.

Method for forming silazane-based dielectric film

      
Application Number 11949701
Grant Number 07651959
Status In Force
Filing Date 2007-12-03
First Publication Date 2009-06-04
Grant Date 2010-01-26
Owner ASM Japan K.K. (Japan)
Inventor
  • Fukazawa, Atsuki
  • Ha, Jeongseok
  • Matsuki, Nobuo

Abstract

A method of forming a dielectric film includes: introducing a source gas essentially constituted by Si, N, H, and optionally C and having at least one bond selected from Si—N, Si—Si, and Si—H into a reaction chamber where a substrate is placed; depositing a silazane-based film essentially constituted by Si, N, H, and optionally C on the substrate by plasma reaction at −50° C. to 50° C., wherein the film is free of exposure of a solvent constituted essentially by C, H, and optionally O; and heat-treating the silazane-based film on the substrate in a heat-treating chamber while introducing an oxygen-supplying source into the heat-treating chamber to release C from the film and increase Si—O bonds in the film.

IPC Classes  ?

  • H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers

48.

Method of plasma treatment using amplitude-modulated RF power

      
Application Number 11946022
Grant Number 08021723
Status In Force
Filing Date 2007-11-27
First Publication Date 2009-05-28
Grant Date 2011-09-20
Owner ASM Japan K.K. (Japan)
Inventor
  • Fukasawa, Yasushi
  • Shuto, Mitsutoshi
  • Suzuki, Yasuaki

Abstract

A method for processing a substrate by plasma CVD includes: (i) forming a film on a substrate placed on a susceptor by applying RF power between the susceptor and a shower plate in the presence of a film-forming gas in a reactor; and (ii) upon completion of step (i), without unloading the substrate, applying amplitude-modulated RF power between the susceptor and the shower plate in the absence of a film-forming gas but in the presence of a non-film-forming gas to reduce a floating potential of the substrate.

IPC Classes  ?

  • H05H 1/30 - Plasma torches using applied electromagnetic fields, e.g. high-frequency or microwave energy
  • H05H 1/32 - Plasma torches using an arc
  • H05H 1/24 - Generating plasma
  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C 14/02 - Pretreatment of the material to be coated
  • B05D 3/00 - Pretreatment of surfaces to which liquids or other fluent materials are to be appliedAfter-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials

49.

Position sensor system for substrate transfer robot

      
Application Number 11867525
Grant Number 08041450
Status In Force
Filing Date 2007-10-04
First Publication Date 2009-04-09
Grant Date 2011-10-18
Owner ASM Japan K.K. (Japan)
Inventor
  • Takizawa, Masahiro
  • Suwada, Masaei

Abstract

A substrate processing apparatus comprises a substrate handling chamber, a pair of position sensors, and a substrate transfer robot. Each of the sensors comprises an emitter configured to emit a beam of light, and a receiver configured to receive the light beam. The substrate transfer robot comprises an end effector and a robot actuator. The end effector is configured to hold a substrate such that the substrate has a same expected position with respect to the end effector every time the substrate is held. The robot actuator is configured to move the end effector within the handling chamber to transfer substrates among a plurality of substrate stations. An edge of a substrate held in the expected position by the end effector can partially block a light beam of one of the position sensors, while another end of the end effector partially blocks a light beam of the other position sensor.

IPC Classes  ?

  • G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)
  • G05B 15/02 - Systems controlled by a computer electric

50.

Method of forming a carbon polymer film using plasma CVD

      
Application Number 11853273
Grant Number 07638441
Status In Force
Filing Date 2007-09-11
First Publication Date 2009-03-12
Grant Date 2009-12-29
Owner ASM Japan K.K. (Japan)
Inventor
  • Morisada, Yoshinori
  • Matsuki, Nobuo
  • Goundar, Kamal Kishore

Abstract

γ, wherein α and β are natural numbers of 5 or more; γ is an integer including zero; X is O, N or F) having a boiling point of about 20° C. to about 350° C.; introducing the vaporized gas into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-containing polymer film on the substrate by plasma polymerization of the gas. The liquid monomer is unsaturated and has no benzene structure.

IPC Classes  ?

  • H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

51.

Method for managing UV irradiation for curing semiconductor substrate

      
Application Number 11780021
Grant Number 07501292
Status In Force
Filing Date 2007-07-19
First Publication Date 2009-01-22
Grant Date 2009-03-10
Owner ASM Japan K.K. (Japan)
Inventor
  • Matsushita, Kiyohiro
  • Kagami, Kenichi

Abstract

A method for managing UV irradiation for curing a semiconductor substrate, includes: passing UV light through a transmission glass window provided in a chamber for curing a semiconductor substrate placed in the chamber; monitoring an illuminance upstream of the transmission glass window and an illuminance downstream of the transmission glass window; determining a timing and/or duration of cleaning of the transmission glass window, a timing of replacing the transmission glass window, a timing of replacing a UV lamp, and/or an output of the UV light based on the monitored illuminances.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment

52.

Method for forming inorganic silazane-based dielectric film

      
Application Number 11759159
Grant Number 07781352
Status In Force
Filing Date 2007-06-06
First Publication Date 2008-12-11
Grant Date 2010-08-24
Owner ASM Japan K.K. (Japan)
Inventor
  • Fukazawa, Atsuki
  • Matsuki, Nobuo
  • Ha, Jeongseok

Abstract

A method of forming an inorganic silazane-based dielectric film includes: introducing a gas constituted by Si and H and a gas constituted by N and optionally H into a reaction chamber where an object is placed; controlling a temperature of the object at −50° C. to 50° C.; and depositing by plasma reaction a film constituted by Si, N, and H containing inorganic silazane bonds.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
  • H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers

53.

Method for forming dielectric film using porogen gas

      
Application Number 11759439
Grant Number 07955650
Status In Force
Filing Date 2007-06-07
First Publication Date 2008-12-11
Grant Date 2011-06-07
Owner ASM Japan K.K. (Japan)
Inventor Tsuji, Naoto

Abstract

A method for reducing a dielectric constant of a cured film, includes: introducing a source gas at a flow rate of A, a porogen gas at a flow rate of B, an oxidizing gas at a flow rate of C, and an inert gas into a reaction space in which a substrate is place; increasing a ratio of B/(A+B) used as a parameter for controlling a dielectric constant of a cured film, by a degree substantially or nearly in proportion to a target decrease of dielectric constant of a cured film; applying RF power to the reaction space, thereby depositing a film on the substrate by plasma CVD; and curing the film to remove the porogen material, thereby forming pores in the cured film.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes

54.

UV light irradiating apparatus with liquid filter

      
Application Number 11690614
Grant Number 07763869
Status In Force
Filing Date 2007-03-23
First Publication Date 2008-09-25
Grant Date 2010-07-27
Owner ASM Japan K.K. (Japan)
Inventor
  • Matsushita, Kiyohiro
  • Kagami, Kenichi

Abstract

A UV light irradiating apparatus for irradiating a semiconductor substrate with UV light includes: a reactor in which a substrate-supporting table is provided; a UV light irradiation unit connected to the reactor for irradiating a semiconductor substrate placed on the substrate-supporting table with UV light through a light transmission window; and a liquid layer forming channel disposed between the light transmission window and at least one UV lamp for forming a liquid layer through which the UV light is transmitted. The liquid layer is formed by a liquid flowing through the liquid layer forming channel.

IPC Classes  ?

  • G21K 5/02 - Irradiation devices having no beam-forming means

55.

Cluster type semiconductor processing apparatus

      
Application Number 11681668
Grant Number 08758514
Status In Force
Filing Date 2007-03-02
First Publication Date 2008-09-04
Grant Date 2014-06-24
Owner ASM Japan K.K. (Japan)
Inventor
  • Takizawa, Masahiro
  • Suwada, Masaei
  • Hagino, Takashi

Abstract

A cluster type semiconductor processing apparatus includes a wafer handling chamber having a polygonal base including multiple sides for wafer processing chambers and two adjacent sides for wafer loading/unloading chambers as viewed in a direction of an axis of the wafer handling chamber. An angle A between two adjacent sides of the multiple sides for wafer processing chambers is greater than an angle B which is calculated by dividing 360° by the number of the total sides consisting of the multiple sides for wafer processing chambers and the two adjacent sides for wafer loading/unloading chambers.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • H01L 21/00 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid-state devices, or of parts thereof

56.

Liquid material vaporization apparatus for semiconductor processing apparatus

      
Application Number 11626777
Grant Number 07833353
Status In Force
Filing Date 2007-01-24
First Publication Date 2008-07-24
Grant Date 2010-11-16
Owner ASM Japan K.K. (Japan)
Inventor
  • Furukawahara, Kazunori
  • Fukuda, Hideaki

Abstract

A liquid material vaporization apparatus for a semiconductor processing apparatus includes: a vaporization tank; an inner partition wall disposed in the tank for dividing the interior of the tank into a charging compartment and a vaporization compartment which are liquid-communicatable with each other over an upper edge of the inner partition wall. A liquid material charged in the charging compartment overflows over the upper edge of the inner partition wall toward the vaporization compartment to store and vaporize the liquid material in the vaporization compartment.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • B01D 1/14 - Evaporating with heated gases or vapours in contact with the liquid

57.

Method of detecting occurrence of sticking of substrate

      
Application Number 11615784
Grant Number 07712370
Status In Force
Filing Date 2006-12-22
First Publication Date 2008-06-26
Grant Date 2010-05-11
Owner ASM Japan K.K. (Japan)
Inventor
  • Furukawahara, Kazunori
  • Ishigami, Katsutoshi

Abstract

Sticking of a substrate occurs in a reaction chamber for processing the substrate placed on a surface of a substrate-supporting device provided with lift pins for moving the substrate up and down with respect to the surface of the substrate-supporting device. A method of detecting the occurrence of the sticking of the substrate includes: monitoring a vibration propagating in or through the reaction chamber by a sensor, which vibration is indicative of or specific to sticking of the substrate on the surface of the substrate-supporting device when being moved up from the surface of the substrate-supporting device with the lift pins; and initiating a pre-designated sequence if the vibration is detected while processing the substrate in the reaction chamber.

IPC Classes  ?

  • G01N 29/00 - Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic wavesVisualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object

58.

Method of forming ultra-thin SiN film by plasma CVD

      
Application Number 11940253
Grant Number 07638443
Status In Force
Filing Date 2007-11-14
First Publication Date 2008-05-15
Grant Date 2009-12-29
Owner ASM Japan K.K. (Japan)
Inventor
  • Tanaka, Rei
  • Hitomi, Taku

Abstract

A method of forming an ultra-thin SiN film includes: supplying a Si source gas into a reactor in which a substrate is placed on a susceptor; supplying an N source gas into the reactor at a flow rate which is at least 300 times that of the Si source gas; applying an RF power between an upper electrode and the susceptor in the reactor; and depositing an ultra-thin SiN film on the substrate.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
  • H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers

59.

Method for forming insulation film having high density

      
Application Number 11525147
Grant Number 07718553
Status In Force
Filing Date 2006-09-21
First Publication Date 2008-03-27
Grant Date 2010-05-18
Owner ASM Japan K.K. (Japan)
Inventor
  • Fukazawa, Atsuki
  • Matsuki, Nobuo

Abstract

3 as a result of the heat treatment.

IPC Classes  ?

  • H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers

60.

Method of cleaning UV irradiation chamber

      
Application Number 11857639
Grant Number 07789965
Status In Force
Filing Date 2007-09-19
First Publication Date 2008-03-20
Grant Date 2010-09-07
Owner ASM Japan K.K. (Japan)
Inventor
  • Matsushita, Kiyohiro
  • Fukuda, Hideaki
  • Kagami, Kenichi

Abstract

A method of cleaning a UV irradiation chamber includes steps of: (i) after completion of irradiating a substrate with UV light transmitted through an optical transmitted window provided in the UV irradiation chamber, generating radical species of a cleaning gas outside the UV irradiation chamber; and (ii) introducing the radical species from the outside of the UV irradiation chamber into the UV irradiation chamber, thereby cleaning the optical transmitted window.

IPC Classes  ?

  • B08B 7/04 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass by a combination of operations

61.

Substrate-processing apparatus with buffer mechanism and substrate-transferring apparatus

      
Application Number 11512637
Grant Number 07690881
Status In Force
Filing Date 2006-08-30
First Publication Date 2008-03-06
Grant Date 2010-04-06
Owner ASM Japan K.K. (Japan)
Inventor
  • Yamagishi, Takayuki
  • Kobayashi, Tamihiro
  • Watanabe, Akira
  • Kaneuchi, Kunihiro

Abstract

A substrate transfer apparatus for loading and unloading substrates in a reaction chamber, includes: an arm having a distal end which is laterally movable in a straight line direction; and end-effectors for loading and unloading substrates in a reaction chamber, which include a lower end-effector and an upper end-effector. One of the lower end-effector or the upper end-effector is movably coupled to the arm at a distal end of the arm, and the other end-effector is fixed to the movably coupled end-effector. The fixed end-effector is fixed to the movably coupled end-effector.

IPC Classes  ?

  • B65G 49/07 - Conveying systems characterised by their application for specified purposes not otherwise provided for for fragile or damageable materials or articles for semiconductor wafers

62.

Ruthenium thin film-formed structure

      
Application Number 11469828
Grant Number 07435484
Status In Force
Filing Date 2006-09-01
First Publication Date 2008-03-06
Grant Date 2008-10-14
Owner ASM Japan K.K. (Japan)
Inventor
  • Shinriki, Hiroshi
  • Inoue, Hiroaki

Abstract

A method of depositing a ruthenium(Ru) thin film on a substrate in a reaction chamber, includes: (i) supplying a gas of a ruthenium precursor into the reaction chamber so that the gas of the ruthenium precursor is adsorbed onto the substrate, wherein the ruthenium precursor a ruthenium complex contains a non-cyclic dienyl; (ii) supplying an excited reducing gas into the reaction chamber to activate the ruthenium precursor adsorbed onto the substrate; and (iii) repeating steps (i) and (ii), thereby forming a ruthenium thin film on the substrate.

IPC Classes  ?

  • B32B 15/01 - Layered products essentially comprising metal all layers being exclusively metallic
  • B32B 15/04 - Layered products essentially comprising metal comprising metal as the main or only constituent of a layer, next to another layer of a specific substance
  • B32B 15/20 - Layered products essentially comprising metal comprising aluminium or copper

63.

Method for forming silicon carbide film containing oxygen

      
Application Number 11463247
Grant Number 08080282
Status In Force
Filing Date 2006-08-08
First Publication Date 2008-02-14
Grant Date 2011-12-20
Owner ASM Japan K.K. (Japan)
Inventor
  • Fukazawa, Atsuki
  • Kato, Manabu
  • Matsuki, Nobuo

Abstract

2) is controlled at 30-850; and thereby depositing on the substrate a silicon carbide film containing Si, C, O, H, and optionally N.

IPC Classes  ?

  • H05H 1/24 - Generating plasma
  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes

64.

Ignition control of remote plasma unit

      
Application Number 11390832
Grant Number 07571732
Status In Force
Filing Date 2006-03-28
First Publication Date 2007-10-11
Grant Date 2009-08-11
Owner ASM Japan K.K. (Japan)
Inventor
  • Takizawa, Masahiro
  • Wada, Takashi
  • Noguchi, Satoru

Abstract

A method of maintaining a remote plasma unit for cleaning a semiconductor-processing apparatus includes: (i) detecting if the semiconductor-processing apparatus is in an idle state; (ii) if the idle state is detected, igniting the remote plasma unit for cleaning the semiconductor-processing apparatus after a lapse of a given time period; (iii) detecting if the remote plasma unit is ignited in step (ii); and (iv) if the remote plasma unit is not ignited in step (ii), retrying ignition of the remote plasma unit.

IPC Classes  ?

  • B08B 6/00 - Cleaning by electrostatic means

65.

Method of forming carbon polymer film using plasma CVD

      
Application Number 11387527
Grant Number 07410915
Status In Force
Filing Date 2006-03-23
First Publication Date 2007-09-27
Grant Date 2008-08-12
Owner
  • ASM Japan K.K. (Japan)
  • Samsung Electronic Co., Ltd. (Republic of Korea)
Inventor
  • Morisada, Yoshinori
  • Goundar, Kamal Kishore
  • Yamaguchi, Masashi
  • Matsuki, Nobuo
  • Na, Kyu Tae
  • Baek, Eun Kyung

Abstract

2 gas into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-containing polymer film on the substrate by plasma polymerization of the gas, thereby reducing extinction coefficient (k) at 193 nm and increasing mechanical hardness.

IPC Classes  ?

  • H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers
  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

66.

Method of forming a carbon polymer film using plasma CVD

      
Application Number 11524037
Grant Number 07470633
Status In Force
Filing Date 2006-09-20
First Publication Date 2007-09-20
Grant Date 2008-12-30
Owner ASM Japan K.K. (Japan)
Inventor
  • Matsuki, Nobuo
  • Morisada, Yoshinori
  • Umemoto, Seijiro
  • Lee, Jea Sik

Abstract

γ, wherein α and β are natural numbers of 5 or more; γ is an integer including zero; X is O, N or F) having a boiling point of about 20° C. to about 350° C.; introducing the vaporized gas into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-containing polymer film on the substrate by plasma polymerization of the gas.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers

67.

Semiconductor processing apparatus with lift pin structure

      
Application Number 11330662
Grant Number 07638003
Status In Force
Filing Date 2006-01-12
First Publication Date 2007-07-12
Grant Date 2009-12-29
Owner ASM Japan K.K. (Japan)
Inventor
  • Satoh, Kiyoshi
  • Yamagishi, Takayuki

Abstract

A semiconductor processing apparatus includes: a reaction chamber; a susceptor disposed in the reaction chamber for placing a substrate thereon and having through-holes in an axial direction of the susceptor; lift pins slidably disposed in the respective through-holes for lifting the substrate over the susceptor; and a means for reducing contact resistance between the lift pins and the respective through-holes.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23F 1/00 - Etching metallic material by chemical means
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

68.

Method for forming porous insulation film

      
Application Number 11559797
Grant Number 08105661
Status In Force
Filing Date 2006-11-14
First Publication Date 2007-07-12
Grant Date 2012-01-31
Owner
  • ASM JAPAN K.K. (Japan)
  • ULVAC, INC. (Japan)
Inventor
  • Hyodo, Yasuyoshi
  • Kohmura, Kazuo
  • Fujii, Nobutoshi
  • Kunimi, Nobutaka
  • Kinoshita, Keizo

Abstract

A method of forming a porous film on a processing target includes: forming fine organic particles by polymerizing an organic compound in a gaseous phase; mixing the fine organic particles with a silicon compound containing a Si—O bond in a gaseous phase, thereby depositing a film containing the fine particles on the processing target; and removing the fine organic particles from the film.

IPC Classes  ?

69.

Method for forming porous insulation film

      
Application Number 11604598
Grant Number 07585789
Status In Force
Filing Date 2006-11-27
First Publication Date 2007-07-12
Grant Date 2009-09-08
Owner
  • ASM Japan K.K. (Japan)
  • Ulvac, Inc. (Japan)
  • NEC Corporation (Japan)
Inventor
  • Hyodo, Yasuyoshi
  • Kohmura, Kazuo
  • Fujii, Nobutoshi
  • Kunimi, Nobutaka
  • Kinoshita, Keizo

Abstract

A method of forming a porous film on a semiconductor substrate includes: supplying a silicon compound containing at least one Si—O bond in its molecule in a gaseous phase into a reaction chamber; forming a siloxane oligomer through plasma reaction of the silicon compound; and supplying an organic amine in a gaseous phase into the reaction chamber and reacting the organic amine with the siloxane oligomer, thereby forming a porous film on the semiconductor substrate.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers
  • H01L 21/469 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layers

70.

Method of forming organosilicon oxide film and multilayer resist structure

      
Application Number 11325167
Grant Number 07829159
Status In Force
Filing Date 2006-01-04
First Publication Date 2007-06-21
Grant Date 2010-11-09
Owner ASM Japan K.K. (Japan)
Inventor Nakano, Ryu

Abstract

A method of forming an organosilicon oxide film by plasma CVD includes: (i) adjusting a temperature of a susceptor on which a substrate is placed to lower than 300° C.; (ii) introducing at least tetraethylorthosilicate (TEOS) and oxygen into a reactor in which the susceptor is disposed; (iii) applying high-frequency RF power and low-frequency RF power; and (iv) thereby depositing an organosilicon oxide film on the substrate.

IPC Classes  ?

  • H05H 1/24 - Generating plasma
  • C23C 28/00 - Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups , or by combinations of methods provided for in subclasses and
  • H05K 3/00 - Apparatus or processes for manufacturing printed circuits

71.

Semiconductor substrate transfer apparatus and semiconductor substrate processing apparatus equipped with the same

      
Application Number 11445035
Grant Number 07618226
Status In Force
Filing Date 2006-06-01
First Publication Date 2007-06-21
Grant Date 2009-11-17
Owner ASM Japan K.K. (Japan)
Inventor
  • Takizawa, Masahiro
  • Suwada, Masaei
  • Wada, Takashi

Abstract

A semiconductor substrate transfer apparatus for transferring semiconductor substrates from a first container to a second container, includes: multiple end effectors; at least one robot arm with which the multiple end effectors are independently rotatably joined; and a controller storing software including instructions to judge which end effector or end effectors in the multiple end effectors are to be selected based on a distribution status of substrates stored in the first and second containers and to rotate the selected end effector(s) for unloading a substrate or substrates from the first container and loading the substrate or substrates to the second container.

IPC Classes  ?

  • B65B 69/00 - Unpacking of articles or materials, not otherwise provided for

72.

Substrate-supporting device

      
Application Number 11252918
Grant Number 07691205
Status In Force
Filing Date 2005-10-18
First Publication Date 2007-04-26
Grant Date 2010-04-06
Owner ASM Japan K.K. (Japan)
Inventor Ikedo, Yozo

Abstract

A substrate-supporting device for CVD having a substrate-supporting region includes: a substrate-supporting surface which is a continuous surface defining a reference plane on which a substrate is placed; and multiple dimples having bottom surfaces lower than the reference plane. The respective dimples are isolated from each other by a portion of the substrate-supporting surface.

IPC Classes  ?

  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

73.

Method for forming metal wiring structure

      
Application Number 11367177
Grant Number 07785658
Status In Force
Filing Date 2006-03-03
First Publication Date 2007-04-12
Grant Date 2010-08-31
Owner ASM Japan K.K. (Japan)
Inventor
  • Shinriki, Hiroshi
  • Shimizu, Akira

Abstract

A method for forming a metal wiring structure includes: (i) providing a multi-layer structure including an exposed wiring layer and an exposed insulating layer in a reaction space; (ii) introducing an —NH2 or >NH terminal at least on an exposed surface of the insulating layer in a reducing atmosphere; (iii) introducing a reducing compound to the reaction space and then purging a reaction space; (iv) introducing a metal halide compound to the reaction space and then purging the reaction space; (v) introducing a gas containing N and H and then purging the reaction space; (vi) repeating steps (iii) to (v) in sequence to produce a metal-containing barrier layer; and (vii) forming a metal film on the metal-containing barrier layer.

IPC Classes  ?

  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
  • C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides

74.

Plasma CVD apparatus for forming uniform film

      
Application Number 11202492
Grant Number 07418921
Status In Force
Filing Date 2005-08-12
First Publication Date 2007-02-15
Grant Date 2008-09-02
Owner ASM Japan K.K. (Japan)
Inventor
  • Tsuji, Naoto
  • Takahashi, Satoshi

Abstract

A plasma CVD film formation apparatus includes: a reaction chamber; a shower plate installed inside the reaction chamber; and a susceptor for placing a wafer thereon installed substantially parallel to and facing the shower plate. The shower plate has a surface facing the susceptor, which is configured using a convex shape toward a center as a basic shape and overlaying at least one equation thereon, and the susceptor supports the wafer at a peripheral portion and at a position between a central portion and the peripheral portion.

IPC Classes  ?

  • C23C 16/00 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes

75.

VACUUM SYSTEM AND METHOD FOR OPERATING SAME

      
Application Number JP2006314056
Publication Number 2007/010851
Status In Force
Filing Date 2006-07-14
Publication Date 2007-01-25
Owner
  • NABTESCO CORPORATION (Japan)
  • ASM JAPAN K.K. (Japan)
Inventor
  • Tanaka, Hiroyuki
  • Ando, Kiyoshi

Abstract

Provided is a vacuum system wherein the rotating speed of a vacuum pump can be suitably adjusted at the time of performing prescribed process in a vacuum chamber to contribute to energy saving. A vacuum pump controller (33) in a semiconductor manufacturing system (10) is provided with gas flow mode and auto-tuning mode. In the auto-tuning mode, the rotating speed of a vacuum pump unit (30) is determined so that an operation quantity of an APC valve (22) is at a target value within a range which is less than the full operation quantity by a prescribed quantity, in a status where the inside of a process chamber (21) is in a vacuum required in the gas flow mode. The vacuum pump controller is provided with a means for judging whether the operation quantity of the APC valve (22) reached the target value or not, by reducing the rotating speed of the vacuum pump unit (30) from a rated speed, in a status where the inside of the process chamber (21) is in the vacuum required in the gas flow mode, for operation in the auto-tuning mode; and a means for storing the rotating speed of the vacuum pump unit (30) as a rotating speed in the gas flow mode when it is judged that the operation quantity reached the target value.

IPC Classes  ?

76.

Apparatus, precursors and deposition methods for silicon-containing materials

      
Application Number 11117988
Grant Number 07425350
Status In Force
Filing Date 2005-04-29
First Publication Date 2006-11-02
Grant Date 2008-09-16
Owner ASM Japan K.K. (Japan)
Inventor Todd, Michael A.

Abstract

A method for making a Si-containing material comprises transporting a pyrolyzed Si-precursor to a substrate and polymerizing the pyrolyzed Si-precursor on the substrate to form a Si-containing film. Polymerization of the pyrolyzed Si-precursor may be carried out in the presence of a porogen to thereby form a porogen-containing Si-containing film. The porogen may be removed from the porogen-containing Si-containing film to thereby form a porous Si-containing film. Preferred porous Si-containing films have low dielectric constants and thus are suitable for various low-k applications such as in microelectronics and microelectromechanical systems.

IPC Classes  ?

  • B05D 3/02 - Pretreatment of surfaces to which liquids or other fluent materials are to be appliedAfter-treatment of applied coatings, e.g. intermediate treating of an applied coating preparatory to subsequent applications of liquids or other fluent materials by baking
  • C23C 16/40 - Oxides
  • C23C 16/56 - After-treatment

77.

Method of recipe control operation

      
Application Number 11105052
Grant Number 07340320
Status In Force
Filing Date 2005-04-13
First Publication Date 2006-10-19
Grant Date 2008-03-04
Owner ASM Japan K.K. (Japan)
Inventor
  • Takizawa, Masahiro
  • Wada, Takashi
  • Noguchi, Satoru

Abstract

An operation method of a recipe control process in which multiple processing targets are processed continuously in a processing apparatus using recipes that specify a set of control parameters specifying the processing conditions of processing targets. The method comprises the steps of: (I) specifying correction coefficients to correct at least one of the parameters' values for each processing target, separately from the recipes, and (II) performing the recipe control process for multiple processing targets and applying the correction coefficients to each processing target to adjust the parameters' values.

IPC Classes  ?

  • G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)

78.

Input signal analyzing system and control apparatus using same

      
Application Number 11069599
Grant Number 07899557
Status In Force
Filing Date 2005-03-01
First Publication Date 2006-09-28
Grant Date 2011-03-01
Owner ASM Japan K.K. (Japan)
Inventor
  • Takizawa, Masahiro
  • Ishigaya, Kazuyoshi
  • Ootani, Kunio

Abstract

For example, by providing MMF software 10, 11 transferring data using a memory-mapped file respectively in a semiconductor manufacturing apparatus 1 and in an input signal analyzing system 8, data transfer load placed on control software 4 and analyzing software 9 is reduced. Additionally, in the MMF software 10, by inserting counter information in the memory-mapped file and by observing the information by the MMF software 11, communication abnormality is detected.

IPC Classes  ?

  • G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)

79.

Method of stabilizing film quality of low-dielectric constant film

      
Application Number 11086598
Grant Number 07560144
Status In Force
Filing Date 2005-03-22
First Publication Date 2006-09-28
Grant Date 2009-07-14
Owner ASM Japan K.K. (Japan)
Inventor
  • Fukazawa, Atsuki
  • Itoh, Kiyoto
  • Kimura, Tsunayuki
  • Matsuki, Nobuo

Abstract

A method of forming a film having a low dielectric constant, comprises the steps of: placing a substrate between an upper electrode and a lower electrode inside a reaction chamber, introducing a silicon-containing hydrocarbon compound source gas, an additive gas, and an inert gas into a space between the upper and lower electrodes by controlling a gas flow ratio, generating a plasma by applying RF power to the space between the upper and lower electrodes in a state in which an interval between the upper electrode and the substrate is narrower in the vicinity of a center of the substrate than that in the vicinity of its periphery, and forming a film having a low dielectric constant on the substrate at a deposition rate of less than approx. 790 nm/min by controlling a flow rate of the process gas.

IPC Classes  ?

80.

Semiconductor-manufacturing apparatus equipped with cooling stage and semiconductor-manufacturing method using same

      
Application Number 11074820
Grant Number 07467916
Status In Force
Filing Date 2005-03-08
First Publication Date 2006-09-14
Grant Date 2008-12-23
Owner ASM Japan K.K. (Japan)
Inventor
  • Yamagishi, Takayuki
  • Watanabe, Takeshi

Abstract

A wafer transfer apparatus includes: (A) a mini environment that connects to a wafer storage part and a load lock chamber and is equipped with a transfer robot inside, in order to transfer wafers between the wafer storage part and load lock chamber in the presence of air flows; and (B) a cooling stage that opens and connects to the mini environment from the outside of the mini environment in the vicinity of the connection port of the load lock chamber, in order to temporarily hold a wafer so that the wafer is cooled by the air taken in from the mini environment.

IPC Classes  ?

  • B65G 49/07 - Conveying systems characterised by their application for specified purposes not otherwise provided for for fragile or damageable materials or articles for semiconductor wafers

81.

Method of forming silicon-containing insulation film having low dielectric constant and low diffusion coefficient

      
Application Number 11382512
Grant Number 07718544
Status In Force
Filing Date 2006-05-10
First Publication Date 2006-08-17
Grant Date 2010-05-18
Owner ASM Japan K.K. (Japan)
Inventor
  • Tsuji, Naoto
  • Matsushita, Kiyohiro
  • Takahashi, Satoshi
  • Kameling, Nathan

Abstract

2/min or less as measured using isopropyl alcohol, by plasma reaction using a reaction gas comprising (i) a source gas comprising a silicon-containing hydrocarbon compound containing plural cross-linkable groups, (ii) a cross-linking gas, (iii) an inert gas, and optionally (iv) an oxygen-supplying gas, wherein a flow rate of the oxygen-supplying gas is no more than 25% of that of the source gas; and subjecting the insulation film to an integration process to fabricate a semiconductor device.

IPC Classes  ?

  • H01L 21/31 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers

82.

Method of forming interconnection in semiconductor device

      
Application Number 11292820
Grant Number 07354852
Status In Force
Filing Date 2005-12-02
First Publication Date 2006-07-20
Grant Date 2008-04-08
Owner ASM Japan K.K. (Japan)
Inventor
  • Matsushita, Kiyohiro
  • Ohara, Naoki
  • Kemeling, Nathan R. C.

Abstract

A multilayer interconnection structure is formed by a method comprising the steps of: Forming a low dielectric constant film on a substrate, curing the low dielectric constant film by irradiating it with UV light, laminating a UV blocking film, laminating a next low dielectric constant film, and curing the next low dielectric constant film by irradiating it with UV light.

IPC Classes  ?

  • H01L 21/4763 - Deposition of non-insulating-, e.g. conductive-, resistive-, layers on insulating layersAfter-treatment of these layers

83.

Method of CVD chamber cleaning

      
Application Number 11022083
Status Pending
Filing Date 2004-12-22
First Publication Date 2006-07-13
Owner ASM JAPAN K.K. (Japan)

Abstract

A method for cleaning a plasma CVD reactor includes, during a cleaning cycle, (i) providing cleaning active species derived from a cleaning gas in the plasma CVD reactor, and (ii) generating a hydrogen plasma in an interior of the plasma CVD reactor to clean the interior of the reactor.

IPC Classes  ?

  • B08B 6/00 - Cleaning by electrostatic means
  • B08B 9/00 - Cleaning hollow articles by methods or apparatus specially adapted thereto
  • H05H 1/24 - Generating plasma

84.

Plasma processing apparatus with insulated gas inlet pore

      
Application Number 11237997
Grant Number 07712435
Status In Force
Filing Date 2005-09-28
First Publication Date 2006-06-29
Grant Date 2010-05-11
Owner ASM Japan K.K. (Japan)
Inventor
  • Yoshizaki, Yu
  • Nakano, Ryu

Abstract

A plasma processing apparatus includes: a reaction chamber; two electrodes provided inside the reaction chamber for generating a plasma therebetween, wherein at least one of the electrodes has at least one gas inlet pore through which a gas is introduced into the reaction chamber; and a gas inlet pipe coupled to the gas inlet pore for introducing the gas into the reaction chamber. The gas inlet pipe is grounded and insulated from the gas inlet pore, wherein an insulation member is placed inside the gas inlet pipe and the gas inlet pore.

IPC Classes  ?

  • C23C 16/507 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using external electrodes, e.g. in tunnel type reactors
  • C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
  • C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
  • C23F 1/00 - Etching metallic material by chemical means
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • C23C 16/22 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material

85.

Selective formation of metal layers in an integrated circuit

      
Application Number 11254071
Grant Number 07476618
Status In Force
Filing Date 2005-10-18
First Publication Date 2006-06-08
Grant Date 2009-01-13
Owner ASM Japan K.K. (Japan)
Inventor
  • Kilpelä, Olli V.
  • Koh, Wonyong
  • Huotari, Hannu A.
  • Tuominen, Marko
  • Leinikka, Miika

Abstract

A method for enhancing the reliability of copper interconnects and/or contacts, such as the bottom of vias exposing top surfaces of buried copper, or at the top of copper lines just after CMP. The method comprises contacting the exposed copper surface with a vapor phase compound of a noble metal and selectively forming a layer of the noble metal on the exposed copper surface, either by a copper replacement reaction or selective deposition (e.g., ALD or CVD) of the noble metal.

IPC Classes  ?

  • H01L 21/44 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups

86.

Gas-introducing system and plasma CVD apparatus

      
Application Number 11262103
Grant Number 07718004
Status In Force
Filing Date 2005-10-28
First Publication Date 2006-05-04
Grant Date 2010-05-18
Owner ASM Japan K.K. (Japan)
Inventor
  • Satoh, Kiyoshi
  • Fukasawa, Yasushi
  • Matsumoto, Kazuya

Abstract

A gas-introducing system for plasma CVD and cleaning includes: a showerhead including a top plate with a gas inlet port and a shower plate; a rectifying plate installed in the interior space of the showerhead and dividing the interior space into an upper space and a lower space; a structure for inhibiting inactivation of active species of the activated cleaning gas at the rectifying plate; and a piping unit for connecting the gas inlet port of the showerhead to a remote plasma unit and a reaction gas introduction port.

IPC Classes  ?

  • C23C 16/452 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials by activating reactive gas streams before introduction into the reaction chamber, e.g. by ionization or by addition of reactive species
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

87.

Method of forming a carbon polymer film using plasma CVD

      
Application Number 11172031
Grant Number 07504344
Status In Force
Filing Date 2005-06-30
First Publication Date 2006-04-20
Grant Date 2009-03-17
Owner ASM Japan K.K. (Japan)
Inventor
  • Matsuki, Nobuo
  • Morisada, Yoshinori
  • Umemoto, Seijiro
  • Lee, Jea Sik

Abstract

γ, wherein α and β are natural numbers of 5 or more; γ is an integer including zero; X is O, N or F) having a boiling point of about 20° C. to about 350° C. which is not substituted by a vinyl group or an acetylene group; introducing the vaporized gas into a CVD reaction chamber inside which a substrate is placed; and forming a hydrocarbon-containing polymer film on the substrate by plasma polymerization of the gas.

IPC Classes  ?

  • H01L 21/30 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups

88.

Apparatus and method for forming thin film using upstream and downstream exhaust mechanisms

      
Application Number 10960600
Grant Number 07408225
Status In Force
Filing Date 2004-10-07
First Publication Date 2005-09-22
Grant Date 2008-08-05
Owner ASM Japan K.K. (Japan)
Inventor
  • Shinriki, Hiroshi
  • Kawano, Baiei
  • Shimizu, Akira

Abstract

A thin-film formation apparatus possesses a reaction chamber to be evacuated, a placing portion on which a substrate is placed inside the reaction chamber, a gas-dispersion guide installed over the placing portion for supplying a gas onto a substrate surface, a gas-supply port for introducing the gas into the gas-dispersion guide, a gas-dispersion plate disposed on the side of the substrate of the gas-dispersion guide and having multiple gas-discharge pores, a first exhaust port for exhausting, downstream of the gas-dispersion plate, the gas supplied onto the substrate surface from the gas-dispersion plate, and a second exhaust port for exhausting, upstream of the gas-dispersion plate, a gas inside the gas-dispersion guide via a space between the gas-dispersion guide and the gas-dispersion plate.

IPC Classes  ?

  • H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts