Abrégé

A manufacturing method of a capacitor includes forming a dielectric layer stack over a substrate, forming an opening through the dielectric layer stack, forming a bottom electrode layer lining the opening, forming a protective layer sealing the opening, in which forming the protective layer includes performing a first deposition process to form a first dielectric layer by using a nitrogen plasma, and performing a second deposition process to form a second dielectric layer by using an oxygen plasma, removing the hard mask layer and the protective layer until the top surface of the dielectric layer stack is exposed, and a portion of the protective layer remains in place, forming a high-k dielectric layer along a sidewall of the bottom electrode layer and a sidewall of the protective layer, and forming a top electrode layer along a sidewall of the high-k dielectric layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a semiconductor device including a source/drain structure, a dielectric layer, first contact structures, a polysilicon stack, and a second contact structure. The source/drain structure is disposed over a semiconductor substrate. The dielectric layer is disposed over the source/drain structure. The first contact structures penetrates through the dielectric layer and the source/drain structure. The second contact structure is disposed over the polysilicon stack. The polysilicon stack and the second contact structure are disposed between two of the plurality of first contact structures. Each of the first contact structures includes a first liner and a first conductive layer surrounding by the first liner.

Classes IPC  ?

• H10D 64/62 - Électrodes couplées de manière ohmique à un semi-conducteur
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
• H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles

Abrégé

In accordance with an aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure includes a substrate, a cell capacitor, a lower dielectric layer, a channel layer, a word line structure, a barrier layer, an upper dielectric layer and a spacer. The cell capacitor is embedded in the substrate. The lower dielectric layer is located on the substrate. The channel layer is located on the cell capacitor, wherein the channel layer is in direct contact with the cell capacitor and the channel layer comprises indium gallium zinc oxide (IGZO). The word line structure surrounds the channel layer. The barrier layer is located between the channel layer and the word line structure. The upper dielectric layer is located on the word line structure. The spacer is located on the sidewall of the upper dielectric layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A method of fabricating a semiconductor device includes forming a substrate layer and a pad layer over the substrate layer; forming an isolation layer in the substrate layer and the pad layer, in which the isolation layer separates the substrate layer and the pad layer into a first substrate layer and a first pad layer over the first substrate layer, and a second substrate layer and a second pad layer over the second substrate layer; removing the second pad layer; lowering a top surface of the second substrate layer; and forming a semiconductor layer on the second substrate layer, in which a top surface of the semiconductor layer is substantially level with a top surface of the first substrate layer.

Classes IPC  ?

• H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
• H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
• H10D 84/01 - Fabrication ou traitement
• H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS

Abrégé

A semiconductor device includes an interposer and a plurality of memory dies. The interposer has a first surface and a second surface opposite to the first surface. The interposer includes first bonding pads adjacent to the first surface. The plurality of memory dies are arranged in an array on the first surface of the interposer. Each of the plurality of memory dies includes second bonding pads, and the second bonding pads are in direct contact with the corresponding first bonding pads.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

A forming method of a semiconductor device includes forming multiple first patterns extending along a first direction in a first hard mask layer on a substrate, forming multiple second patterns extending along a second direction in a second hard mask layer on the substrate, forming a hole pattern in a third hard mask layer by using the first patterns and the second patterns, forming a resist layer covering the first center sections of the first patterns, and the second center sections of the second patterns, and removing the end sections of the first patterns and the end sections of the second patterns. Each of the first patterns and the second patterns includes a first center section and two first end sections.

Classes IPC  ?

• H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou

Abrégé

The present disclosure provides a semiconductor device including a source/drain structure, a dielectric layer, first contact structures, a polysilicon stack, and a second contact structure. The source/drain structure is disposed over a semiconductor substrate. The dielectric layer is disposed over the source/drain structure. The first contact structures penetrates through the dielectric layer and the source/drain structure. The second contact structure is disposed over the polysilicon stack. The polysilicon stack and the second contact structure are disposed between two of the plurality of first contact structures. Each of the first contact structures includes a first liner and a first conductive layer surrounding by the first liner.

Classes IPC  ?

• H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles

Abrégé

The present disclosure provides a semiconductor device including a source/drain structure, a dielectric layer, first contact structures, a polysilicon stack, and a second contact structure. The source/drain structure is disposed over a semiconductor substrate. The dielectric layer is disposed over the source/drain structure. The first contact structures penetrates through the dielectric layer and the source/drain structure. The second contact structure is disposed over the polysilicon stack. The polysilicon stack and the second contact structure are disposed between two of the plurality of first contact structures. Each of the first contact structures includes a first liner and a first conductive layer surrounding by the first liner.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor memory device manufacturing method includes the following steps. A bit line structure is formed in a memory array area of a substrate. A gate structure is formed in a periphery area of the substrate. A dielectric layer is formed over the bit line structure and the gate structure. A lower hard mask layer is formed over the dielectric layer. An etch process diagnostic signal layer is formed over the lower hard mask layer. An upper hard mask layer is formed over the etch process diagnostic signal layer. A main etching step is performed to form a first via hole towards the bit line structure and a second via hole towards the gate structure until the upper hard mask layer is removed to expose the etch process diagnostic signal layer.

Classes IPC  ?

• H10P 76/40 -
• H10P 50/00 -
• H10W 20/00 -

Abrégé

This invention provides a memory-paired system for multiple stacked semiconductor devices and its repair method. The memory-paired system has a paired unit having at least two chips that are identical design. Each of the at least two chips of the paired unit has a memory resources module configured for deploying memory resources for repair and a paired control module configured for executing allocation of memory resources by sending a request to another one chip of the at least two chips of the paired unit when memory resource of the memory resource module that the request points have been allocated, or providing spare memory resource of the memory resource module to one chip of the paired unit based on a request from the one chip that has a failed unit existing, so the spare memory resource of the memory resource module repairs the failed unit of the one chip.

Classes IPC  ?

• G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne

Abrégé

A defect detection apparatus configured to detect a sample including a periodical structure. The defect detection apparatus includes a light source, an image detector, and a controller. The light source is configured to provide a light beam incident on the periodical structure, wherein the periodical structure converts the light beam into an interference beam. The image detector is disposed on a path of the interference beam, wherein the interference beam forms an interference intensity distribution on the image detector. The controller is electrically connected to the image detector and configured to determine whether the periodical structure has a defect by determining whether the interference intensity distribution has a normal waveform. A defect detection method is also provided.

Classes IPC  ?

• G01N 21/88 - Recherche de la présence de criques, de défauts ou de souillures
• G01N 21/45 - RéfringencePropriétés liées à la phase, p. ex. longueur du chemin optique en utilisant des méthodes interférométriquesRéfringencePropriétés liées à la phase, p. ex. longueur du chemin optique en utilisant les méthodes de Schlieren

Abrégé

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate, a gate structure, a spacer structure, and a sealing layer. The gate structure is positioned on the substrate. The spacer structure includes a first spacer, a second spacer, a third spacer, and an air gap. The first spacer is disposed on a sidewall of the gate structure, and the air gap is located between the first spacer and the second spacer. The air gap is enclosed by the first spacer, the second spacer, the third spacer, and the sealing layer.

Classes IPC  ?

• H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
• H10D 30/01 - Fabrication ou traitement
• H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
• H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a landing pad positioned over the substrate; and an electrode layer positioned on the landing pad. A bottom surface of the electrode layer is substantially flat. The semiconductor device further includes a top dielectric layer having a cavity and a filling layer positioned on the top dielectric layer and filling the cavity.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A manufacturing method of a semiconductor structure is provided. The method includes the following steps. A conductive layer is formed on a substrate. A protection layer is formed on the conductive, wherein the protection layer includes a plurality of first pores, and the first pores expose portions of the conductive layer. A nitridation treatment is performed on the exposed portions of the conductive layer through the first pores to form nitride portions at a top surface of the conductive layer. A dielectric layer is formed on the protection layer, wherein the dielectric layer includes a plurality of second pores. A clean treatment is performed on the dielectric layer.

Classes IPC  ?

• H01L 21/321 - Post-traitement
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a landing pad positioned over the substrate; and an electrode layer positioned on the landing pad, wherein no residual bump is present between the landing pad and the electrode layer. A bottom surface of the electrode layer is substantially flat.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device comprises a substrate, a gate structure, a spacer structure, and a sealing layer. The gate structure is positioned on the substrate. The spacer structure includes a first spacer, a second spacer, a third spacer, and an air gap. The first spacer is disposed on a sidewall of the gate structure, and the air gap is located between the first spacer and the second spacer. The air gap is enclosed by the first spacer, the second spacer, the third spacer, and the sealing layer.

Classes IPC  ?

• H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
• H10D 30/01 - Fabrication ou traitement
• H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
• H10D 64/01 - Fabrication ou traitement
• H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
• H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille

Abrégé

A method for fabricating a semiconductor device includes providing a substrate and forming a layer of pad material over the substrate; forming a second mask layer on the layer of pad material; performing a first planarization process to the second mask layer and patterning the second mask layer; performing a pad-forming etching process using the second mask layer as a hard mask to form a valley and turning the layer of pad material into a landing pad; forming a top dielectric layer that covers the landing pad and partially fills the valley; forming a filling layer on the top dielectric layer and filling the valley; performing a second planarization process to the filling layer; performing a pad-exposing etching process to expose the landing pad; and forming an electrode layer on the landing pad; wherein a bottom surface of the electrode layer is substantially flat.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device comprises a substrate, a gate structure, a spacer structure, and a sealing layer. The gate structure is positioned on the substrate. The spacer structure includes a first spacer, a second spacer, a third spacer, and an air gap. The first spacer is disposed on a sidewall of the gate structure, and the air gap is located between the first spacer and the second spacer. The air gap is enclosed by the first spacer, the second spacer, the third spacer, and the sealing layer.

Classes IPC  ?

• H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
• H10D 30/01 - Fabrication ou traitement
• H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
• H10D 64/01 - Fabrication ou traitement
• H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
• H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille

Abrégé

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a patterned circuit structure, a capacitor structure and a vertical transistor. The patterned circuit structure is disposed over the base structure. The capacitor structure is disposed over the patterned circuit structure. The vertical transistor is disposed over the capacitor structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a patterned circuit structure, a capacitor structure and a vertical transistor. The patterned circuit structure is disposed over the base structure. The capacitor structure is disposed over the patterned circuit structure. The vertical transistor is disposed over the capacitor structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A method for manufacturing a semiconductor structure is provided. A substrate is recessed from an upper surface toward a lower surface to form a trench. A semiconductor material is filled in the trench. A patterned metal layer is formed on the semiconductor material and a patterned hard mask is formed on the patterned metal layer. A portion of the semiconductor material is etched by using the patterned metal layer as a mask, in which a remaining portion of the semiconductor material includes a first portion and a second portion below the first portion, and the second portion is wider than the first portion. A passivation layer is formed on a sidewall of the first portion. The passivation layer is removed and the second portion of the remaining portion of the semiconductor material is etched by using the patterned metal layer as a mask, thereby forming a semiconductor layer.

Classes IPC  ?

• H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/321 - Post-traitement

Abrégé

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a patterned circuit structure, a capacitor structure and a vertical transistor. The patterned circuit structure is disposed over the base structure. The capacitor structure is disposed over the patterned circuit structure. The vertical transistor is disposed over the capacitor structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A wafer handling apparatus includes a housing, a load port, a robotic arm, a sensor group and a processing unit. The load port is mounted on a side of the housing and configured to receive a wafer container which accommodates at least one wafer. The robotic arm is disposed inside the housing and configured to transfer the wafer into or out of the wafer container. The robotic arm includes a handling portion and a moving portion. The handling portion is configured to hold the wafer. The moving portion is connected with the handling portion and configured to move the handling portion relative to the load port. The sensor group is disposed on the load port. The sensor group includes at least one first sensor configured to obtain a first height level of the handling portion. The processing unit is signally connected with the sensor group.

Classes IPC  ?

• B25J 9/16 - Commandes à programme
• B25J 11/00 - Manipulateurs non prévus ailleurs
• B25J 13/08 - Commandes pour manipulateurs au moyens de dispositifs sensibles, p. ex. à la vue ou au toucher
• H01L 21/677 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le transport, p. ex. entre différents postes de travail
• H01L 21/68 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le positionnement, l'orientation ou l'alignement
• H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces

Abrégé

A method of fabricating a semiconductor device that includes forming a dummy channel structure, forming a gate electrode surrounding the dummy channel structure, forming a word line surrounding the gate electrode, removing the dummy channel structure to form an opening, forming a gate dielectric in the opening, and forming a channel structure in the opening.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A duty cycle correction device and a duty cycle correction method thereof are disclosed. A duty cycle adjustment circuit adjusts a duty cycle of an input clock signal to output an output clock signal. An integrator circuit generates an integral signal according to the output clock signal. A correction control circuit periodically controls the duty cycle adjustment circuit to adjust an adjustment amount of the duty cycle according to a change of a logic level of the integral signal.

Classes IPC  ?

• H03K 5/156 - Dispositions dans lesquelles un train d'impulsions est transformé en un train ayant une caractéristique désirée
• H03K 5/13 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés

Abrégé

A capacitor structure and a manufacturing method thereof are provided. The capacitor structure includes a bottom electrode, an insulation layer, a top electrode and an interfacial layer. The insulation layer is disposed on the bottom electrode. The top electrode is disposed over the insulation layer. The interfacial layer is disposed between the insulation layer and the top electrode. A composition of the interfacial layer has at least one element in common with elements containing in the insulation layer and at least one element in common with elements containing in the top electrode.

Classes IPC  ?

• H01G 4/33 - Condensateurs à film mince ou à film épais
• H01G 2/06 - Dispositifs de montage spécialement adaptés pour le montage sur un support de circuit imprimé
• H01G 4/008 - Emploi de matériaux spécifiés
• H01G 4/12 - Diélectriques céramiques

Abrégé

A manufacturing method of a semiconductor device includes forming a plurality of photoresist strips on a substrate, in which an opening is formed in each of the photoresist strips; forming a plurality of contacts in the openings of the photoresist strips, in which an outer contour of each of the contacts is a string shape; and using the photoresist strips to form a plurality of bit lines.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 29/40 - Electrodes

Abrégé

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a bit line structure and a cell contact structure. The bit line structure is disposed over the base structure. The cell contact structure is disposed around the bit line structure, and has a first surface and a second surface facing the bit line structure. A first distance between the first surface of the cell contact structure and the bit line structure is different from a second distance between the second surface of the cell contact structure and the bit line structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device includes two active areas, an isolation structure between the active areas, two word lines, and protection pillars covering the word lines and in direct contact with the isolation structure. Each of the word lines is between one of the active areas and the isolation structure, and the protection pillars are rhombus-shaped.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a pad structure positioned above the substrate and including a bottom portion and two side portions, wherein the bottom portion is positioned parallel to a top surface of the substrate, and the two side portions are positioned on two sides of the bottom portion and extending along a direction parallel to a normal of the top surface of the substrate; and an insulator film surrounding the pad structure. A top surface of the insulator film is at a vertical level greater than a vertical level of a top surface of the pad structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a bit line structure and a cell contact structure. The bit line structure is disposed over the base structure. The cell contact structure is disposed around the bit line structure, and has a first surface and a second surface facing the bit line structure. A first distance between the first surface of the cell contact structure and the bit line structure is different from a second distance between the second surface of the cell contact structure and the bit line structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a bit line structure and a cell contact structure. The bit line structure is disposed over the base structure. The cell contact structure is disposed around the bit line structure, and has a first surface and a second surface facing the bit line structure. A first distance between the first surface of the cell contact structure and the bit line structure is different from a second distance between the second surface of the cell contact structure and the bit line structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application provides a semiconductor structure including a first die, a second die and a first via. The first die includes a first substrate, a first interconnect structure having a first conductive pad, and a first bonding layer over the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second interconnect structure. The first via extends through the second die and the first bonding layer and coupled to the first conductive pad. The first via includes a first portion having a first width and a second portion coupled to the first portion and having a second width different from the first width, wherein the first portion is surrounded by the first bonding layer and adjacent to the second interconnect structure, and the second portion is surrounded by the second substrate.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

The present application provides a semiconductor structure including a first die, a second die and a first via. The first die includes a first substrate, a first interconnect structure having a first conductive pad, and a first bonding layer over the first conductive pad. The second die includes a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second interconnect structure. The first via extends through the second die and the first bonding layer and coupled to the first conductive pad. The first via includes a first portion having a first width and a second portion coupled to the first portion and having a second width different from the first width, wherein the first portion is surrounded by the first bonding layer and adjacent to the second interconnect structure, and the second portion is surrounded by the second substrate.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a supporting substrate; and a channel layer positioned parallel to a top surface of the supporting substrate, extending along a first direction, and including, in a sequence along the first direction, a drain, a channel, and a source. A top surface of the channel deviates less than three times its root mean square roughness.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a supporting substrate; and a channel layer positioned parallel to a top surface of the supporting substrate, extending along a first direction, and including, in a sequence along the first direction, a drain, a channel, and a source. A top surface of the channel deviates less than three times its root mean square roughness.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a channel layer including a channel extending along a first direction and including a first region and a second region in sequence along the first direction, a source extending from the second region along the first direction, and a drain extending from the first region in inverse of the first direction; and a word line structure including an inner word line dielectric layer surrounding the first region of the channel, an outer word line dielectric layer surrounding the second region of the channel and the inner word line dielectric layer, and a word line conductive layer surrounding the outer word line dielectric layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a channel layer including a channel extending along a first direction and including a first region and a second region in sequence along the first direction, a source extending from the second region along the first direction, and a drain extending from the first region in inverse of the first direction; and a word line structure including an inner word line dielectric layer surrounding the first region of the channel, an outer word line dielectric layer surrounding the second region of the channel and the inner word line dielectric layer, and a word line conductive layer surrounding the outer word line dielectric layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses an expandable negative photoresist and a method for adjusting a profile of a spacer oxide using the expandable negative photoresist. The expandable negative photoresist includes a polymer material, a suspension material and a photoacid generator. The suspension material contains a plurality of expandable molecules. An expansion coefficient of the suspension material is greater than that of the polymer material

Classes IPC  ?

• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
• G03F 7/38 - Traitement avant le dépouillement selon l'image, p. ex. préchauffage

Abrégé

The present application discloses an etching system. The etching system includes a process chamber, an image and temperature control device, and an artificial intelligence control module. The process chamber is configured to execute an etching process based on a first etching recipe on a first wafer. The image and temperature control device is configured to generate a thermal image of the first wafer during the etching process. The artificial intelligence control module is configured to determine whether the thermal image is compliant with a predetermined requirement. When the thermal image is not compliant with the predetermine requirement, the artificial intelligence control module is configured to update the first etching recipe according to the plurality of parameters so as to generate a second etching recipe.

Classes IPC  ?

• H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
• G05B 13/02 - Systèmes de commande adaptatifs, c.-à-d. systèmes se réglant eux-mêmes automatiquement pour obtenir un rendement optimal suivant un critère prédéterminé électriques
• H01J 37/32 - Tubes à décharge en atmosphère gazeuse
• H01L 21/3065 - Gravure par plasmaGravure au moyen d'ions réactifs
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension

Abrégé

The present application discloses an etching system. The etching system includes a process chamber, an image and temperature control device, and an artificial intelligence control module. The process chamber is configured to execute an etching process based on a first etching recipe on a first wafer. The image and temperature control device is configured to generate a thermal image of the first wafer during the etching process. The artificial intelligence control module is configured to determine whether the thermal image is compliant with a predetermined requirement. When the thermal image is not compliant with the predetermine requirement, the artificial intelligence control module is configured to update the first etching recipe according to the plurality of parameters so as to generate a second etching recipe.

Classes IPC  ?

• H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
• G05B 13/02 - Systèmes de commande adaptatifs, c.-à-d. systèmes se réglant eux-mêmes automatiquement pour obtenir un rendement optimal suivant un critère prédéterminé électriques
• H01J 37/32 - Tubes à décharge en atmosphère gazeuse
• H01L 21/3065 - Gravure par plasmaGravure au moyen d'ions réactifs
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension

Abrégé

The present application discloses an expandable negative photoresist and a method for adjusting a profile of a spacer oxide using the expandable negative photoresist. The expandable negative photoresist includes a polymer material, a suspension material and a photoacid generator. The suspension material contains a plurality of expandable molecules. An expansion coefficient of the suspension material is greater than that of the polymer material.

Classes IPC  ?

• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
• G03F 7/38 - Traitement avant le dépouillement selon l'image, p. ex. préchauffage

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a channel layer positioned over the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoid cross-sectional profile; and a word line including a word-line dielectric layer conformally and laterally surrounding the channel layer, and a word-line conductive layer laterally and partially surrounding the word-line dielectric layer, extending along a second direction parallel to the top surface of the substrate, and including an inverted trapezoid cross-sectional profile.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

An operation method of the overhead hoist transport device includes acquiring a first image of a first car by an image acquisition device on a second car; calculating a regression distance between the first car and the second car by using the first image as an input of a CNN model; adjusting a real distance between the first car and the second car based on the regression distance; and performing a CNN regression to adjusting a focus of the image acquisition device on the second car based on the regression distance.

Classes IPC  ?

• B66C 15/04 - Mécanismes de sécurité pour empêcher les collisions, p. ex. entre les grues ou les chariots à treuil travaillant sur la même voie
• B66C 19/00 - Ponts roulants ou portiques fixes ou mobiles, portant un chariot ou un treuil mobile

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a channel layer positioned over the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoid cross-sectional profile; and a word line including a word-line dielectric layer conformally and laterally surrounding the channel layer, and a word-line conductive layer laterally and partially surrounding the word-line dielectric layer, extending along a second direction parallel to the top surface of the substrate, and including an inverted trapezoid cross-sectional profile.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a channel layer positioned over the substrate, extending along a first direction perpendicular to a top surface of the substrate, and including an inverted trapezoid cross-sectional profile; and a word line including a word-line dielectric layer conformally and laterally surrounding the channel layer, and a word-line conductive layer laterally and partially surrounding the word-line dielectric layer, extending along a second direction parallel to the top surface of the substrate, and including an inverted trapezoid cross-sectional profile.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

An electronic device, an assembly structure and a manufacturing method are provided. The electronic device includes a base portion, a circuit structure, an insulation structure, a first conductive layer, a via structure, a first outer layer and a second outer layer. The circuit structure is disposed on a first surface of the base portion. The insulation structure is disposed on the circuit structure. The first conductive layer is disposed on the insulation structure. The via structure extends through the insulation structure, and electrically connects the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material so as to improve a coplanarity of an outermost surface of the second outer layer.

Classes IPC  ?

• H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés

Abrégé

A manufacturing method of a semiconductor structure is provided. The method includes the following steps. A target layer and a hardmask layer are sequentially formed on a substrate. A part of the hardmask layer is removed to form a recess. A plurality of first patterns are formed on a top surface of the hardmask layer and a plurality of second patterns are formed in the recess simultaneously. A pattern density of the plurality of first patterns is smaller than that of the plurality of second patterns. The hardmask layer and the target layer are patterned using the first patterns and the second patterns as a mask to form a plurality of first target patterns corresponding to the plurality of first patterns and a plurality of second target patterns corresponding to the plurality of second patterns in the target layer. The first and second patterns and the hardmask layer are removed.

Classes IPC  ?

• H01L 21/311 - Gravure des couches isolantes
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
• H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable

Abrégé

An electronic device, an assembly structure and a manufacturing method are provided. The electronic device includes a base portion, a circuit structure, an insulation structure, a first conductive layer, a via structure, a first outer layer and a second outer layer. The circuit structure is disposed on a first surface of the base portion. The insulation structure is disposed on the circuit structure. The first conductive layer is disposed on the insulation structure. The via structure extends through the insulation structure, and electrically connects the first conductive layer and the circuit structure. The first outer layer is disposed on the first conductive layer. The second outer layer is disposed on the first outer layer. The second outer layer includes an oxide material so as to improve a coplanarity of an outermost surface of the second outer layer.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

A signal receiver includes a data receiver and a data strobe signal receiver. The data receiver includes a plurality of current mode logic circuits and a plurality of data latches. A first stage current mode logic circuit receives a data signal, and a final stage current mode logic circuit outputs an amplified data signal. The plurality of data latches receive the amplified data signal, wherein each of the data latches sums the amplified data signal and a plurality of feedback data to obtain a summing data, and latches the summing data to output an output data according to one of a plurality of amplified data strobe signals. The data strobe signal receiver receives a data strobe signal, and generates the plurality of amplified data strobe signals by dividing a frequency of the data strobe signal.

Classes IPC  ?

• G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
• G11C 11/4076 - Circuits de synchronisation
• H03K 3/037 - Circuits bistables
• H03K 17/56 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs
• H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs

Abrégé

A method of fabricating a semiconductor structure includes depositing a first dielectric layer on a substrate; depositing a second dielectric layer on the first dielectric layer; forming a capacitor in the first dielectric layer and the second dielectric layer; depositing a first insulating layer on the second dielectric layer and the capacitor; forming a word line structure on the first insulating layer; depositing a second insulating layer on the word line structure; forming a channel hole in the second insulating layer, the word line structure, and the first insulating layer, wherein the channel hole includes a first section with a trumpet shape opening and a second section below the first section; forming a vertical channel in the second section of the channel hole; and forming a landing pad in the first section of the channel hole. A semiconductor structure is also disclosed.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A detection method of an overhead hoist transport device includes obtaining a position information of a car at a rail and a vibration information corresponding to the position information. A vibration peak data is generated based on the position information and the vibration information. An analyzing operation is performed on the vibration peak data to generate an analyzed result. Whether the analyzed result indicates a critical gap position at the rail is determined.

Classes IPC  ?

• B61K 9/08 - Installations de mesure pour surveiller la voie

Abrégé

A method of manufacturing a semiconductor structure includes the following steps. A substrate is received with a top electrode of an embedded capacitor exposed from the substrate. An oxide layer is formed on the substrate. A patterned sacrificial layer is formed on the oxide layer and a portion of the oxide layer is exposed. A metal layer is formed to cover the portion of the oxide layer. A patterned dielectric layer is formed on the metal layer. A spacer is formed on a sidewall of the patterned dielectric layer. The metal layer is patterned by using the spacer and the patterned dielectric layer as a mask to form a gap. The gap is filled with a filler. The patterned sacrificial layer is removed to expose the top electrode of the embedded capacitor. A gate structure is formed on the top electrode of the embedded capacitor.

Classes IPC  ?

• H01L 29/40 - Electrodes

Abrégé

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an electronic component, and an encapsulant. The substrate has a lower surface and an upper surface opposite to the lower surface. The electronic component is disposed on the upper surface of the substrate. The encapsulant is disposed on the upper surface of the substrate. The encapsulant includes a first portion penetrating the substrate at a central region of the substrate and a second portion penetrating the substrate at a peripheral region of the substrate.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H05K 1/02 - Circuits imprimés Détails
• H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés

Abrégé

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/764 - Espaces d'air
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an electronic component, and an encapsulant. The substrate has a lower surface and an upper surface opposite to the lower surface. The electronic component is disposed on the upper surface of the substrate. The encapsulant is disposed on the upper surface of the substrate. The encapsulant includes a first portion penetrating the substrate at a central region of the substrate and a second portion penetrating the substrate at a peripheral region of the substrate.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H05K 1/02 - Circuits imprimés Détails
• H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés

Abrégé

A label dispensing device includes a housing having a label outlet, a collection reel, a feeding reel, a driving mechanism and a peeling mechanism. The collection reel and the feeding reel are rotatably disposed in the housing. The driving mechanism drives one of the feeding reel and the collection reel for conveying a label strip from the feeding reel to the collection reel. The peeling mechanism is disposed in the housing and used to change a conveying direction of the label strip being pulled from the feeding reel towards the label outlet into a recycled direction intersected with the conveying direction from the peeling mechanism downwardly for peeling off one of label stickers from the label strip when the label sticker is passing the peeling mechanism.

Classes IPC  ?

• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition

Abrégé

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/764 - Espaces d'air
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/764 - Espaces d'air
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a conductive layer, a landing pad, and an air gap protection structure. The substrate includes a plurality of liners disposed on side surfaces of a trench in the substrate. The bit line is disposed on the substrate. The isolation spacer is disposed on a sidewall of the bit line. The isolation spacer includes an air gap. The conductive layer is disposed over the substrate and next to the isolation spacer. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure includes an upper portion above a top surface of the landing pad and a lower portion below the upper portion.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/764 - Espaces d'air
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A manufacturing method of a semiconductor structure is provided. The method includes following steps. A substrate is provided, and the substrate has a first array region, a second array region, and a periphery region. A first lower conductive layer is formed on the substrate, the first lower conductive layer continuously has a first portion in the first array region, a second portion in the second array region, and a third portion in the periphery region. The first portion of the first lower conductive layer and the second portion of the first lower conductive layer are removed. A second lower conductive layer is formed on the substrate. The second lower conductive and the first lower conductive layer comprise the same material such that the second lower conductive and the first lower conductive layer form a lower conductive layer collectively.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A method for manufacturing a semiconductor structure includes the following steps. A substrate is received, in which the substrate has a functional area and a dummy area surrounding the functional area. A functional pattern is formed on the functional area and a dummy pattern is formed on the dummy area in a same process step. A closet distance between the dummy pattern and the functional pattern is from 15 nm to about 50 nm. The dummy pattern is removed.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate comprising a front side and a back side parallel to the front side; a bonding dielectric positioned on the front side of the first substrate; a redistribution layer positioned between the bonding dielectric and the front side of the first substrate; a first dielectric layer positioned between the front side of the first substrate and the redistribution layer; a capping layer positioned between the redistribution layer and the bonding layer; a first conductive pad positioned between the capping layer and the bonding layer; a second dielectric layer positioned between the capping layer and the bonding layer, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad; and a conductive feature positioned in the bonding dielectric and the first conductive pad.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

The present application discloses a semiconductor device and a method for fabricating the same. The semiconductor device includes a first substrate comprising a front side and a back side parallel to the front side; a bonding dielectric positioned on the front side of the first substrate; a redistribution layer positioned between the bonding dielectric and the front side of the first substrate; a first dielectric layer positioned between the front side of the first substrate and the redistribution layer; a capping layer positioned between the redistribution layer and the bonding layer; a first conductive pad positioned between the capping layer and the bonding layer; a second dielectric layer positioned between the capping layer and the bonding layer, wherein a surface of the second dielectric layer is coplanar with a surface of the first conductive pad; and a conductive feature positioned in the bonding dielectric and the first conductive pad.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device with a protruding contact and a method of fabricating the semiconductor device. The semiconductor device includes a substrate, a bit line structure on the substrate, a capacitor contact structure next to the bit line structure, and a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a method of forming a semiconductor structure. The method includes the following operations. A first hard mask stack is formed on a dielectric layer, in which the dielectric layer includes an array region. The first hard mask stack is etched to form a second hard mask stack and a first trench extending along a first direction above the array region and in the second hard mask stack. A second trench is formed in the second hard mask stack extending along a second direction different from the first direction, in which the first trench and the second trench cross each other to form an intersection. The second hard mask stack and the dielectric layer directly below the intersection are etched to form a through-hole. A first landing pad is formed in the through-hole.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/311 - Gravure des couches isolantes

Abrégé

A temperature detection apparatus and method are provided. The apparatus captures an image and a thermal image of an object. The apparatus determines a first contour of the object in the image based on the image. The apparatus overlaps the first contour in the image onto the thermal image to generate a second contour in the thermal image. The apparatus generates a temperature record of the object based on a plurality of temperature values among the second contour in the thermal image.

Classes IPC  ?

• G06T 7/564 - Récupération de la profondeur ou de la forme à partir de plusieurs images à partir des contours
• G06T 1/00 - Traitement de données d'image, d'application générale
• G06T 7/62 - Analyse des attributs géométriques de la superficie, du périmètre, du diamètre ou du volume

Abrégé

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an electronic component, an encapsulant, and a dam structure. The substrate has a lower surface and an upper surface opposite to the first surface. The electronic component is disposed on the upper surface of the substrate. The encapsulant is disposed on the upper surface of the substrate and has a portion penetrating the substrate. The dam structure vertically overlaps the portion of the encapsulant.

Classes IPC  ?

• H01L 23/16 - Matériaux de remplissage ou pièces auxiliaires dans le conteneur, p. ex. anneaux de centrage
• H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
• H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H01L 23/498 - Connexions électriques sur des substrats isolants

Abrégé

A manufacturing method of a memory device, including forming a hard mask layer over a substrate, in which the hard mask layer is made of an oxide-based material, and the hard mask layer has a first width, forming a trench in the substrate through the hard mask layer, performing a first cleaning process to the substrate, in which the first width of the hard mask layer is reduced to a second width after the first cleaning process is complete, forming a first dielectric layer lining the trench, forming a first word line layer in the trench, forming a second word line layer in the trench and over the first word line layer, forming a cap layer in the trench and over the second word line layer, removing the hard mask layer, and forming a gate contact layer over the cap layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A dynamic random-access memory (DRAM) device is provided. The DRAM device includes a slave DRAM chip and a master DRAM chip. The slave DRAM chip includes a slave control circuit and a slave power circuit. The slave control circuit generates a slave control signal according to a slave category signal and a setting signal. The slave power circuit stops generating at least one of slave voltages in response to a first value of the slave control signal and generates the slave voltages in response to a second value of the slave control signal. The master DRAM chip includes a master control circuit. The master control circuit generates a master control signal according to a master category signal and the setting signal, and controls the master DRAM chip to generate master voltages according to the master control signal. The slave category signal is different from the master category signal.

Classes IPC  ?

• G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
• G11C 11/4099 - Traitement de cellules facticesGénérateurs de tension de référence

Abrégé

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an electronic component, an encapsulant, and a dam structure. The substrate has a lower surface and an upper surface opposite to the first surface. The electronic component is disposed on the upper surface of the substrate. The encapsulant is disposed on the upper surface of the substrate and has a portion penetrating the substrate. The dam structure vertically overlaps the portion of the encapsulant.

Classes IPC  ?

• H01L 23/16 - Matériaux de remplissage ou pièces auxiliaires dans le conteneur, p. ex. anneaux de centrage
• H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
• H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H01L 23/498 - Connexions électriques sur des substrats isolants

Abrégé

A delay locked loop device is provided, which includes a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generate a reference clock signal based on the input clock signal. The delay line delays the first signal to generate a second signal based on a delay control signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate an enable signal. The phase detector detects, in response to the enable signal, a phase difference between the reference clock signal and a feedback clock signal to generate a phase detection result. The delay control circuit is configured to generate the delay control signal for the delay line based on the phase detection result.

Classes IPC  ?

• H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
• G11C 11/4076 - Circuits de synchronisation
• H03L 7/085 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie
• H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle

Abrégé

A delay locked loop device is provided, which includes a receiver, a delay line, a frequency detection and control circuit, a phase detector, and a delay control circuit. The receiver compares an input clock signal and a reference voltage to generate a first signal, and generate a reference clock signal based on the input clock signal. The delay line delays the first signal to generate a second signal based on a delay control signal. The frequency detection and control circuit detects an operating frequency of the reference clock signal to generate an enable signal. The phase detector detects, in response to the enable signal, a phase difference between the reference clock signal and a feedback clock signal to generate a phase detection result. The delay control circuit is configured to generate the delay control signal for the delay line based on the phase detection result.

Classes IPC  ?

• H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
• G11C 11/4076 - Circuits de synchronisation
• H03L 7/085 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie
• H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle

Abrégé

A manufacturing method of a semiconductor device includes stacking a first hard mask layer on an active area layer; coating a photoresist on the first hard mask layer, in which the photoresist covers a first peripheral portion of the first hard mask layer; partially etching the first hard mask layer; side etching the photoresist to expose a second peripheral portion of the first hard mask layer; etching the first hard mask layer and the active area layer, in which after the etching, the active area layer has a ladder-shaped upper surface; and depositing a dielectric layer on the ladder-shaped upper surface.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a method of forming a semiconductor structure. The method includes the following operations. A diamond-like carbon hard mask layer is formed on a substrate, in which an absorbance of the diamond-like carbon hard mask layer is smaller than or equal to 0.5. A dielectric anti-reflective coating layer is formed on the diamond-like carbon hard mask layer. A bottom anti-reflective coating layer is formed on the dielectric anti-reflective coating layer.

Classes IPC  ?

• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
• H01L 21/311 - Gravure des couches isolantes

Abrégé

The present application discloses a photoresist structure, a semiconductor device including the photoresist structure, and a method for fabricating the semiconductor device including the photoresist structure. The photoresist structure includes a bottom photoresist layer; a top photoresist layer positioned on the bottom photoresist layer. A coefficient of thermal expansion of the top photoresist layer is greater than a coefficient of thermal expansion of the bottom photoresist layer.

Classes IPC  ?

• G03F 7/09 - Matériaux photosensibles caractérisés par des détails de structure, p. ex. supports, couches auxiliaires
• G03F 7/033 - Composés photopolymérisables non macromoléculaires contenant des doubles liaisons carbone-carbone, p. ex. composés éthyléniques avec des liants les liants étant des polymères obtenus par des réactions faisant intervenir uniquement des liaisons non saturées carbone-carbone, p. ex. polymères vinyliques

Abrégé

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, a fourth semiconductor and a fifth semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The fourth semiconductor chip is stacked on the third semiconductor chip, and is electrically connected to the third semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps. The fifth semiconductor chip disposed below the first semiconductor chip, and is electrically connected to the first semiconductor chip through a plurality of electrical connectors.

Classes IPC  ?

• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

The present application discloses a photoresist structure, a semiconductor device including the photoresist structure, and a method for fabricating the semiconductor device including the photoresist structure. The photoresist structure includes a bottom photoresist layer and a top photoresist layer positioned on the bottom photoresist layer. A coefficient of thermal expansion of the top photoresist layer is greater than a coefficient of thermal expansion of the bottom photoresist layer.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• G03F 7/38 - Traitement avant le dépouillement selon l'image, p. ex. préchauffage
• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
• H01L 21/311 - Gravure des couches isolantes

Abrégé

An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip, a third semiconductor chip, a fourth semiconductor and a fifth semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The fourth semiconductor chip is stacked on the third semiconductor chip, and is electrically connected to the third semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps. The fifth semiconductor chip disposed below the first semiconductor chip, and is electrically connected to the first semiconductor chip through a plurality of electrical connectors.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
• H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

The present application discloses a capacitor structure and a method for fabricating the capacitor structure. The capacitor structure includes a first electrode including carbon nanotubes; a second electrode including graphene and vanadium oxide; a separator separating the first electrode and the second electrode; and a first type electrolyte surrounding the first electrode, the second electrode, and the separator.

Classes IPC  ?

• H01G 11/04 - Condensateurs hybrides
• H01G 11/28 - Électrodes caractérisées par leur structure, p. ex. multicouches, selon la porosité ou les caractéristiques de surface agencées ou disposées sur un collecteur de courantCouches ou phases entre les électrodes et les collecteurs de courant, p. ex. adhésifs
• H01G 11/36 - Nanostructures, p. ex. nanofibres, nanotubes ou fullerènes
• H01G 11/46 - Oxydes métalliques
• H01G 11/52 - Séparateurs
• H01G 11/70 - Collecteurs de courant caractérisés par leur structure

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first bottom conductive layer positioned in the substrate; a bottom porous dielectric layer positioned on the substrate; a top porous dielectric layer positioned on the bottom porous dielectric layer; a middle porous dielectric layer positioned between the bottom porous dielectric layer and the top porous dielectric layer; and a mixing-area conductive structure positioned along the top porous dielectric layer, the middle porous dielectric layer, and the bottom porous dielectric layer, and positioned on the first bottom conductive layer. A porosity of the top porous dielectric layer is greater than a porosity of the middle porous dielectric layer. The porosity of the middle porous dielectric layer is greater than a porosity of the bottom porous dielectric layer.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées

Abrégé

The present application provides a memory device having an ultra-lightly doped region and a manufacturing method of the memory device. The memory device includes a semiconductor substrate including a word line extending into the semiconductor substrate, wherein the semiconductor substrate is defined with a source region, a drain region and an ultra-lightly doped region under the drain region, the word line is disposed between the source region and the drain region, and the ultra-lightly doped region is disposed at a sidewall of the word line.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A label dispensing device includes a housing having a label outlet, a collection reel, a feeding reel, a driving mechanism and a peeling mechanism. The collection reel and the feeding reel are rotatably disposed in the housing. The driving mechanism drives one of the feeding reel and the collection reel for conveying a label strip from the feeding reel to the collection reel. The peeling mechanism is disposed in the housing and used to change a conveying direction of the label strip being pulled from the feeding reel towards the label outlet into a recycled direction intersected with the conveying direction from the peeling mechanism downwardly for peeling off one of label stickers from the label strip when the label sticker is passing the peeling mechanism.

Classes IPC  ?

• B65C 9/18 - Alimentation en étiquettes à partir de bandes, p. ex. de rouleaux
• B65C 9/00 - Parties constitutives ou détails des machines ou appareils à étiqueter
• B65C 11/02 - Distributeurs d'étiquettes à commande manuelle, p. ex. modifiés pour permettre l'application d'étiquettes sur des objets avec équipement pour impression

Abrégé

The present application discloses a capacitor structure and a method for fabricating the capacitor structure. The capacitor structure includes a first electrode including carbon nanotubes; a second electrode including graphene and vanadium oxide; a separator separating the first electrode and the second electrode; and a first type electrolyte surrounding the first electrode, the second electrode, and the separator.

Classes IPC  ?

• H01G 11/04 - Condensateurs hybrides
• H01G 11/28 - Électrodes caractérisées par leur structure, p. ex. multicouches, selon la porosité ou les caractéristiques de surface agencées ou disposées sur un collecteur de courantCouches ou phases entre les électrodes et les collecteurs de courant, p. ex. adhésifs
• H01G 11/36 - Nanostructures, p. ex. nanofibres, nanotubes ou fullerènes
• H01G 11/46 - Oxydes métalliques
• H01G 11/52 - Séparateurs
• H01G 11/70 - Collecteurs de courant caractérisés par leur structure

Abrégé

The present disclosure provides a capacitor structure. The capacitor structure includes a bottom electrode, a first dielectric layer, and a first top electrode. The bottom electrode includes a bottom portion and a side portion, in which the side portion extends upward from an edge of the bottom portion, the side portion includes a first portion and a second portion on the first portion, in which a first width of the first portion is smaller than a second width of the second portion. The first dielectric layer is on the bottom electrode. The first top electrode is on the first dielectric layer.

Classes IPC  ?

• H10D 1/00 - Résistances, Condensateurs, Inducteurs
• H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel

Abrégé

The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate and a word line. The word line is embedded in the substrate and includes a high work function layer and a low work function layer on the high work function layer, in which an average work function of the high work function layer is larger than an average work function of the low work function layer, the low work function layer includes a lower portion and an upper portion on the lower portion, and an average grain size of the lower portion is smaller than an average grain size of the upper portion.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor structure includes a semiconductor substrate, a bit-line structure, and a bit-line spacer. The bit-line structure is disposed on the semiconductor substrate. The bit-line spacer covers the bit-line structure, in which the bit-line spacer includes a SiCO layer, an insulating oxide layer, and an insulating nitride layer. The SiCO layer covers the bit-line structure, in which an oxygen concentration of the SiCO layer is equal to or greater than 55 at %. The insulating oxide layer covers the SiCO layer. The insulating nitride layer covers the insulating oxide layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A wafer transfer device detection system includes detectors, a filling device, a wafer transfer device and a control center. Detectors are disposed between a plurality of process equipment in a process. Filling device performs a filling procedure. Wafer transfer device includes body and sensor disposed in body. Wafer transfer device transmits wafer of process. Sensor detects a gas concentration inside wafer transfer device during a transportation stage of the process. If gas concentration is higher than a preset gas concentration, sensor generates a wireless communication signal. Control center is coupled to detectors and filling device. If detectors receive the wireless communication signal. Detectors notify control center so that the control center transmits wafer transfer device to filling device from process. Control center controls the filling device to perform filling procedure so as to adjust gas concentration to a target gas concentration to retransmit wafer transfer device back to process.

Classes IPC  ?

• H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
• G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes
• H01L 21/673 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants utilisant des supports spécialement adaptés

Abrégé

A method for fabricating a capacitor is provided. The method includes following steps. A mold is formed on an interconnect layer. A recess is formed in the mold. A bottom electrode layer is deposited on the mold and into the recess. A metal oxide layer is disposed on the bottom electrode layer and into the recess. A surface oxide layer is formed on the metal oxide layer. A non-O2 wet etching process is performed to remove the surface oxide layer, the metal oxide layer, and the mold from the bottom electrode layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A method of manufacturing a patterned photoresist layer over a base material and a method of manufacturing a plurality of openings in a base layer are provided. The method includes: providing a base material; forming a photoresist layer over the base material, wherein the photoresist layer includes a negative expansion coefficient material; patterning the photoresist layer to form a first actual pattern having a first critical dimension; and applying an energy to the photoresist layer so that the first actual pattern becomes a second actual pattern, wherein the second actual pattern has a second critical dimension different from the first critical dimension of the first actual pattern.

Classes IPC  ?

• G03F 7/40 - Traitement après le dépouillement selon l'image, p. ex. émaillage

Abrégé

This invention provides a method for forming conductors and their contacts which carry signals for advanced semiconductor memory devices with self-aligned STI support beams, during the method process a patterning layer including a sub shallow trench isolation pattern in a first direction and a sub support beam pattern in a second direction perpendicular to the first direction is provided over a substrate, a STI etching is performed in a way that an anisotropic STI etching is executed in the second direction and a STI tilt etching is executed in the first direction simultaneously, whereby shallow trenches in the second direction with the support beams inside them hanging underneath the sub support beam pattern and adjoining the substrate underneath the sub shallow trench isolation pattern are provided. The support beams mechanically support the shallow trenches during the whole STI manufacturing to suppress the bending, deforming, or tilting of STI.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a method of forming a patterned structure. The method includes the following operations. A photoresist layer on a target layer is patterned to form a first opening in a patterned photoresist layer. A directed self-assembly layer is formed on the patterned photoresist layer and in the first opening, in which a directed self-assembly material in the directed self-assembly layer separates into a first phase on the patterned photoresist layer and a second phase in the first opening by the first phase being attracted by a polarity of the patterned photoresist layer. The second phase is removed to form a second opening through the directed self-assembly layer. The target layer is etched through the second opening.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
• H01L 21/311 - Gravure des couches isolantes

Abrégé

A method of forming a memory device includes forming a trench in a substrate, forming a first dielectric layer lining the trench, forming a first conductive layer into the trench, etching back the first conductive layer, resulting in a native oxide layer being formed over the first conductive layer, performing an etching process to remove the native oxide layer to expose the first conductive layer and to trim a portion of the first dielectric layer exposed by the first conductive layer, and forming a second conductive layer into the trench and in contact with the first conductive layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Embodiments of this disclosure provide a semiconductor structure, including an active device layer disposed over a substrate and a capacitor structure disposed on the active device layer. The capacitor structure includes a first conductive layer disposed on the active device layer, an insulating layer disposed on the first conductive layer, a second conductive layer disposed on the insulating layer, a third conductive layer disposed on the second conductive layer, a bottom inner insulating layer surrounding the first conductive layer in a top view, a second inner conductive layer surrounding the bottom inner insulating layer in the top view, and a third inner conductive layer surrounding the second inner conductive layer in the top view. Additionally, a method of manufacturing a semiconductor structure is also disclosed in this disclosure.

Classes IPC  ?

• H10D 1/00 - Résistances, Condensateurs, Inducteurs
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel

Abrégé

A semiconductor device includes a substrate including a source region and a drain region; a word line structure including a word line dielectric layer in the substrate, a word line conductive layer on the word line dielectric layer and within the substrate, and a word line capping layer on the word line conductive layer; a top thickening layer between the word line conductive layer and the word line capping layer, and between the word line dielectric layer and the word line capping layer; a bottom capping layer on the substrate and adjacent to the word line dielectric layer; a top capping layer covering the bottom capping layer and the word line structure; a bit line penetrating through the top and bottom capping layers and extending into the source region; and a cell contact penetrating through the top and bottom capping layers and extending into the drain region.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A method of manufacturing a patterned photoresist layer over a base material and a method of manufacturing a plurality of openings in a base layer are provided. The method includes: providing a base material; forming a photoresist layer over the base material, wherein the photoresist layer includes a negative expansion coefficient material; patterning the photoresist layer to form a first actual pattern having a first critical dimension; and applying an energy to the photoresist layer so that the first actual pattern becomes a second actual pattern, wherein the second actual pattern has a second critical dimension different from the first critical dimension of the first actual pattern.

Classes IPC  ?

• G03F 7/40 - Traitement après le dépouillement selon l'image, p. ex. émaillage

Abrégé

The present disclosure provides a method of testing a semiconductor device. The method includes: providing a wafer on a chuck; moving the chuck to a first expected position under a probe card; moving the chuck from the first expected position to a second expected position so that a plurality of dies of the wafer contact a plurality of pins of the probe card; testing a first portion of the dies of the wafer; moving the chuck to the second expected position so that the dies of the wafer abut against the pins of the probe card; and testing a second portion of the dies of the wafer.

Classes IPC  ?

• G01R 1/073 - Sondes multiples
• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux