Abrégé

A memory device and a control method of the memory device are provided. The memory device includes a memory array and a control logic circuit. The memory array includes a plurality of memory cell rows. The control logic circuit perform an access on the memory array. The control logic circuit counts a number of the access performed on the memory cell rows to generate a plurality of count values corresponding to the memory cell rows. When a count value corresponding to an accessed memory cell row among the memory cell rows is larger than or equal to a threshold value generated with random number corresponding to the accessed memory cell row, the control logic circuit arranges the memory cell rows nearby the accessed memory cell row into a mitigation operation.

Classes IPC  ?

• G06F 21/56 - Détection ou gestion de programmes malveillants, p.ex. dispositions anti-virus
• G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures

Abrégé

A semiconductor device structure and a method of manufacturing the same are provided. The semiconductor device structure includes a substrate, a fuse structure, and a first word line. The fuse structure includes a fuse electrode disposed within the substrate. The first word line is electrically coupled to the fuse structure. The first word line is disposed within the substrate and spaced apart from the fuse electrode of the fuse structure. The fuse electrode has a lateral surface protruding toward the first word line.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p.ex. utilisant des jonctions électriquement fusibles
• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables

Abrégé

The present application discloses a method for fabricating a semiconductor device including providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer and the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening.

Classes IPC  ?

• H01L 21/311 - Gravure des couches isolantes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées

Abrégé

A method for preparing a semiconductor device structure includes forming a nitrogen-containing pattern over a semiconductor substrate. The method also includes performing an energy treating process to form a transformed portion in the semiconductor substrate and covered by the nitrogen-containing pattern. The method further includes etching the semiconductor substrate such that the transformed portion is surrounded by an opening structure.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/308 - Traitement chimique ou électrique, p.ex. gravure électrolytique en utilisant des masques
• H01L 21/3105 - Post-traitement

Abrégé

A manufacturing method of a semiconductor structure includes forming a dielectric layer stack including a first oxide layer and a second oxide layer over the first oxide layer. An opening is formed in the dielectric layer stack, and includes a first portion exposing sidewalls of the first oxide layer and a second portion exposing sidewalls of the second oxide layer. A sacrificial layer is formed over the dielectric layer stack and along the sidewalls of the first oxide layer and the second oxide layer in the opening. A first etching is performed to remove the sacrificial layer along the sidewalls of the first oxide layer. A second etching is performed to widen the first portion of the opening. The sacrificial layer along the sidewalls of the second oxide layer and over the dielectric layer stack is removed. A capacitor is formed in the opening after removing the sacrificial layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A method for preparing a semiconductor device structure with features at different levels. The method includes forming a target layer over a semiconductor substrate; forming a plurality of first energy-sensitive patterns over the target layer; performing an energy treating process to transform at least a portion of each of the first energy-sensitive patterns into a first treated portion; forming a lining layer conformally covering the first energy-sensitive patterns, wherein a first opening is formed over the lining layer and between the first energy-sensitive patterns; filling the first opening with a second energy-sensitive pattern; and performing an etching process to form a plurality of second openings and a third opening in the target layer, wherein the third opening is between the second openings, and the second openings and the third opening have different depths.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/311 - Gravure des couches isolantes

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and positioned on the bottom portion; and an in-recess spacer positioned in the substrate, surrounding the bottom portion, and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur

Abrégé

A semiconductor device structure and a method of manufacturing the same are provided. The semiconductor device structure includes a substrate, a fuse structure, and a first word line. The fuse structure includes a fuse electrode disposed within the substrate. The first word line is electrically coupled to the fuse structure. The first word line is disposed within the substrate and spaced apart from the fuse electrode of the fuse structure. The fuse electrode has a lateral surface protruding toward the first word line.

Classes IPC  ?

• H10B 20/25 - Dispositifs ROM programmable une seule fois, p.ex. utilisant des jonctions électriquement fusibles
• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables

Abrégé

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a device and at least one recess transistor. The device includes a substrate and a plurality of word lines. The substrate includes an array portion and a periphery portion surrounding the array portion. The plurality of word lines are disposed in the array portion. The periphery portion is free of word lines. The periphery portion of the substrate defines at least one recess. The at least one recess transistor is disposed in the at least one recess of the periphery portion of the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and on opposite sides of the word line. The memory device further includes a bit line contact disposed over and electrically connected to the first source/drain region. The bit line contact has a tapered profile. In addition, the memory device includes a capacitor contact disposed over and electrically connected to the second source/drain region.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a buried conductive layer including a bottom portion positioned in the substrate, and a top portion positioned in the substrate and positioned on the bottom portion; and an in-recess spacer positioned in the substrate, surrounding the bottom portion, and covered by the top portion. A top surface of the top portion and a top surface of the substrate are substantially coplanar. A bottom surface of the in-recess spacer and a bottom surface of the bottom portion are substantially coplanar. A sidewall of the in-recess spacer and a sidewall of the top portion are substantially coplanar.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur

Abrégé

A capacitor structure includes a contact layer having first, second, third, fourth and fifth portions arranged from periphery to center, an insulating layer over the contact layer and having an opening exposing the contact layer, a bottom conductive plate in the opening, a dielectric layer conformally on the bottom conductive plate and contacting the second and fourth portions of the contact layer, and a top conductive plate on the dielectric layer. The bottom conductive plate includes first, second and third portions extending along a depth direction of the opening, separated from each other, and contacting the first, third and fifth portions of the contact layer, respectively. The first portion of the bottom conductive plate surrounds the second portion of the bottom conductive plate, and the second portion of the bottom conductive plate surrounds the third portion of the bottom conductive plate.

Classes IPC  ?

• H01G 4/228 - Bornes
• H01G 13/00 - Appareils spécialement adaptés à la fabrication de condensateurs; Procédés spécialement adaptés à la fabrication de condensateurs non prévus dans les groupes
• H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a device and at least one recess transistor. The device includes a substrate and a plurality of word lines. The substrate includes an array portion and a periphery portion surrounding the array portion. The plurality of word lines are disposed in the array portion. The periphery portion is free of word lines. The periphery portion of the substrate defines at least one recess. The at least one recess transistor is disposed in the at least one recess of the periphery portion of the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and on opposite sides of the word line. The memory device further includes a bit line contact disposed over and electrically connected to the first source/drain region. The bit line contact has a tapered profile. In addition, the memory device includes a capacitor contact disposed over and electrically connected to the second source/drain region.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A memory device and a control method of the memory device are provided. The memory device includes a memory array and a control logic circuit. The memory array includes memory cell rows. The control logic circuit includes a counter and a reset circuit. The counter counts a number of an access performed on the memory cell rows to generate a count value corresponding to the accessed memory cell row among the memory cell rows, and sets the count value to a random value when the count value is equal to the predetermined value and when the access is performed. The reset circuit resets the count value to a predetermined value in responses to a refresh command. When the count value reaches to the threshold value, the control logic circuit arranges memory cell rows nearby the accessed memory cell row into a mitigation operation.

Classes IPC  ?

• G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire

Abrégé

A manufacturing method of a semiconductor structure includes forming an active area in a substrate, in which the substrate has an array region and a peripheral region adjacent to the array region. A word line structure is formed in the array region of the substrate. A first protection layer is formed covering the active area and the word line structure. A hard mask stack is formed on the first protection layer. A bit line feature is formed in the first protection layer. After forming the bit line feature, a gate dielectric layer is formed on the active area in the peripheral region of the substrate. A gate electrode layer is formed on the gate dielectric layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A wafer carrier dry cleaner includes a receiver, a tool and a movable nozzle. The receiver includes a clean room. The clean room includes a port used to load a wafer carrier. The wafer carrier comprises a box and a door closing an opening of the box. The tool is located in the clean room and configured to separate the door from the box. The movable nozzle is located in the clean room. The movable nozzle is configured to purge clean gas towards the box and the door at a first position between the box and the door when the box and the door are separated.

Classes IPC  ?

• H01L 21/673 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants utilisant des supports spécialement adaptés
• B08B 5/00 - Nettoyage par des procédés impliquant l'utilisation d'un courant d'air ou de gaz
• H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having plurality of contacts, a plurality of composite plugs positioned above the plurality of contacts, a plurality of metal spacers positioned above the substrate; and a plurality of air gaps positioned above the substrate. At least one of the plurality of composite plugs includes a protection liner having a U-shaped profile and a metal plug in the protection liner, and the protection liner is in direct contact with one of the plurality of contacts.

Classes IPC  ?

• H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The present disclosure provides a memory device and the forming method thereof. The memory device includes a gate structure on a substrate, a source/drain region in a substrate, a dielectric layer covering the substrate and the gate structure, and a cell contact adjacent to the gate structure. The cell contact includes a conductive layer, a first barrier layer on a sidewall of the conductive layer, and a second barrier layer on a bottom surface of the conductive layer. The second barrier layer directly contacts the first barrier layer and the source/drain region. A second resistivity of the second barrier layer is lower than a first resistivity of the first barrier layer.

Classes IPC  ?

• H01L 29/45 - Electrodes à contact ohmique
• H01L 29/40 - Electrodes

Abrégé

This invention provides an asymmetric pads structure using at a scribe line of a wafer, comprising a test element device electrically connected to a first pad and a second pad separately, wherein a first spacing between the second pad and the test element device is sufficient to accommodate the second pad of an another asymmetric pads structure. So, two neighboring asymmetric pads structures may cross to each other to form a cross configuration.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement

Abrégé

A semiconductor device includes a first top selection structure and a second top selection structure at a same vertical level as and separated from a main signal pad, and respectively extending along different directions; a first ground layer at the same vertical level as and separated from the main signal pad and the top selection structures; a first bottom selection structure at a vertical level lower than the main signal pad and partially overlapped with the top selection structures and the first ground layer in a top-view perspective; a first top via between the first ground layer and the first bottom selection structure; second top vias between the top selection structures and the first bottom selection structure; first insulating layers between the second top vias and the first bottom selection structure; and a wiring pad on the main signal pad and the top selection structures.

Classes IPC  ?

• H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
• H01L 23/498 - Connexions électriques sur des substrats isolants

Abrégé

A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a system comprising a memory device and a processor. The memory device operates with a supply voltage having a first value. The processor is operatively coupled to the memory device and executes: generating a write command for writing a first datum to the memory device; generating a first read command for reading a second datum from the memory device and comparing the first datum and the second datum; adjusting the supply voltage to have a second value different from the first value; and generating a second read command for reading a third datum from the memory device and comparing the first datum and the third datum for a test result.

Classes IPC  ?

• G11C 29/12 - Dispositions intégrées pour les tests, p.ex. auto-test intégré [BIST]
• G11C 29/10 - Algorithmes de test, p.ex. algorithmes par balayage de mémoire [MScan]; Configurations de test, p.ex. configurations en damier

Abrégé

A semiconductor device includes a first top selection structure and a second top selection structure at a same vertical level as and separated from a main signal pad, and respectively extending along different directions; a first ground layer at the same vertical level as and separated from the main signal pad and the top selection structures; a first bottom selection structure at a vertical level lower than the main signal pad and partially overlapped with the top selection structures and the first ground layer in a top-view perspective; a first top via between the first ground layer and the first bottom selection structure; second top vias between the top selection structures and the first bottom selection structure; first insulating layers between the second top vias and the first bottom selection structure; and a wiring pad on the main signal pad and the top selection structures.

Classes IPC  ?

• H05K 1/11 - Eléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
• H01L 23/498 - Connexions électriques sur des substrats isolants

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain positioned in the substrate; a top dielectric layer positioned on the substrate; a cell contact structure including a cell contact bottom conductive layer positioned in the top dielectric layer and on the drain, a cell contact top conductive layer positioned in the top dielectric layer and on the cell contact bottom conductive layer, and a cell contact top sealing layer positioned in the top dielectric layer, on the cell contact bottom conductive layer, and surrounding the cell contact top conductive layer; and a first air gap positioned in the top dielectric layer and surrounding the cell contact bottom conductive layer.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A system is provided. The system comprises a memory device and a test device. The test device that is operatively coupled to the memory device and transmits a plurality of glitch signals and a plurality of control signals after the plurality of glitch signals for a write operation of the memory device according to a data signal. The test device determines, based on write data of the data signal, whether read data outputted in a read operation of the memory device are bitwise shifted to generate a test result indicating a disturbance to the write operation induced by the plurality of glitch signals.

Classes IPC  ?

• G11C 29/38 - Dispositifs de vérification de réponse
• G11C 29/12 - Dispositions intégrées pour les tests, p.ex. auto-test intégré [BIST]

Abrégé

An anti-fuse device by ferroelectric characteristic is provided, which comprises an active area including a source region, a drain region laterally spaced from the source region and a channel between the source region and drain region, and a gate structure including a ferroelectric layer formed on the channel as well as a gate electrode formed on the ferroelectric layer. A programming operation of the anti-fuse device is performed by application of power to the gate electrode and at least one of the source region and drain region to cause a permanent electric field polarization in the ferroelectric layer to induce a conduction path along the channel. After the programming operation, the anti-fuse device will much easily turn on as the threshold voltage decreases even the operating voltage applied to the gate electrode is zero bias.

Classes IPC  ?

• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor device manufacturing method includes the following steps. A well implant process is performed on a region of a substrate. A source/drain implant process is performed on the region of the substrate. An active area is defined on the region of the substrate. Shallow trench isolations are formed in the active area. An annealing process is performed to the region of the substrate.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p.ex. recuit, frittage
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a drain positioned in the substrate; a top dielectric layer positioned on the substrate; a cell contact structure including a cell contact bottom conductive layer positioned in the top dielectric layer and on the drain, a cell contact top conductive layer positioned in the top dielectric layer and on the cell contact bottom conductive layer, and a cell contact top sealing layer positioned in the top dielectric layer, on the cell contact bottom conductive layer, and surrounding the cell contact top conductive layer; and a first air gap positioned in the top dielectric layer and surrounding the cell contact bottom conductive layer.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The present disclosure provides a method of manufacturing a semiconductor device. The method includes: providing a semiconductor structure, in which the semiconductor structure comprises a silicon substrate having a plurality of trenches and an oxide material filled in the trenches and covering the silicon substrate, and the trenches define a plurality of island structures; forming a pad oxide layer on a top portion of the oxide material, in which the pad oxide layer is located over the silicon substrate; and removing the pad oxide layer, so that a top surface of the oxide material and a top surface of the island structures are coplanar.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/3105 - Post-traitement
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/3115 - Dopage des couches isolantes

Abrégé

The present disclosure provides a method of manufacturing semiconductor chips. The method includes performing a first dry etching process to remove a top metalization layer such that a portion of an interconnect structure is exposed by a scribe line opening after the top metalization layer is removed, wherein the interconnect structure is embedded in a dielectric layer. Next, a first wet etching process using a first etchant is performed to remove a filling layer of the interconnect structure. After performing the first wet etching process, a second wet etching process using a second etchant is performed to remove a glue layer of the interconnect structure. After performing a second wet etching process, a back side stealth dicing process is performed to induce cracks in a substrate from a back side to a front side so as to separate a semiconductor wafer into the semiconductor chips.

Classes IPC  ?

• H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A semiconductor wafer includes a scribe line and a probe pad. The scribe line extends along a first direction. The probe pad is disposed on the scribe line and is configured to contact a probe needle. The probe pad includes a first metal layer, a dielectric layer, and a second metal layer. The dielectric layer is disposed on the first metal layer, in which the dielectric layer includes a first recess and a second recess. The second metal layer is configured to connect to the first metal layer, in which the second metal layer includes a first portion and a second portion, and the first portion and the second portion are separated by a distance in a second direction perpendicular to the first direction.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p.ex. à l'aide d'un traceur de signaux
• G01R 1/067 - Sondes de mesure
• G01R 1/073 - Sondes multiples

Abrégé

The present disclosure provides a method of manufacturing a semiconductor device. The method includes: forming a dummy via in a trench of a stacking structure with a bottom anti-reflection coated material, in which the stacking structure includes a low-k material layer and a cap layer, and the trench runs through the low-k material layer and the cap layer; and removing a portion of the dummy via by performing a first etching process and a second etching process, and in which the first etching process and the second etching process are performed such that a top surface of the dummy via is lower than a top surface of the low-k material layer and higher than a bottom surface of the low-k material layer.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques

Abrégé

A semiconductor memory device includes a substrate, a memory cell contact formed over the substrate, a bit line conductive structure formed over the substrate and a dielectric spacer located between the memory cell contact and the bit line conductive structure. The dielectric spacer includes an air gap having a rectangular cross-section, and the rectangular cross-section has a height H and a width W, wherein a H/W ratio is equal to or greater than 40.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor memory device includes a substrate with an active area, a bit line contact in contact with the active area, and a bit line having an end portion in contact with the bit line contact, wherein the end portion has a first trapezoidal profile. A semiconductor memory device manufacturing method is also disclosed to utilize a vertical etching process which has an etching recipe to have higher conductive material/barrier layer selectivity, thereby enlarging bit line contact to active area landing area and improving a contact resistance of the bit line contact.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A test system is provided, including an assessment subsystem, a neural network subsystem and a process control processor. The assessment subsystem receives a test image of a tested wafer from a probe apparatus. The process control processor controls, in response to the probe apparatus obtaining the test image, the assessment subsystem to perform an assessment operation to transmit the test image to the neural network subsystem in an automation mode. The neural network subsystem identifies an image specification of probe marks in the test image and generates an analyzed data of the test image to the assessment subsystem. The assessment subsystem further generates a first probe mark inspection result based on the analyzed data to the process control processor for generating a test result.

Classes IPC  ?

• G06T 7/00 - Analyse d'image

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom conductive region positioned in the substrate; a first gate structure positioned on the substrate; a first drain region positioned in the substrate and adjacent to one sidewall of the first gate structure; and a first extended conductive region positioned in the substrate, under the first drain region, contacting a bottom surface of the first drain region, and distant from the bottom conductive region. A top surface of the first drain region and a top surface of the substrate are substantially coplanar. The bottom conductive region and the first extended conductive region include the same electrical type. The first drain region and the first extended conductive region include different electrical types.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

Abrégé

An optical semiconductor device with cascade vias is disclosed. The semiconductor device a logic die having a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and having a memory cell area and a memory peripheral area; a first inter-die via positioned in the memory peripheral area; a landing pad positioned on the first inter-die via; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area. The first inter-die via and the first intra-die via are electrically coupled through the landing pad in a cascade manner.

Classes IPC  ?

• H01L 31/0216 - Revêtements
• H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
• H01L 31/0232 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails - Détails Éléments ou dispositions optiques associés au dispositif
• H01L 31/102 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface
• H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe

Abrégé

A manufacturing method of a semiconductor device including providing a substrate, forming a hard mask over the substrate, etching the substrate by using the hard mask as an etch mask to form a first protrusion region and a plurality of second protrusion regions, wherein the first protrusion region is separated from a closest one of the second protrusion regions by a first trench, and neighboring two of the second protrusion regions are separated by a second trench, forming a first dielectric layer lining the first trench and the second trench, forming a second dielectric layer in the first trench, in which the second dielectric layer is along the first dielectric layer in the first trench, etching back the second dielectric layer to form a blocking structure, and filling the first trench with a filling material, in which the filling material covers the blocking structure.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/321 - Post-traitement
• H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
• H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique

Abrégé

The present disclosure provides a memory device and the forming method thereof. The memory device includes a bit line on a substrate, a multilayer spacer covering the bit line, a low-k dielectric layer and an air gap interposed in the multilayer spacer, and a cell contact adjacent to the multilayer spacer. The multilayer spacer, the low-k dielectric layer, and the air gap are disposed between the bit line and the cell contact. The top surface of the low-k dielectric layer is lower than a top surface of the bit line. The air gap is above the low-k dielectric layer, and an orthogonal projection of the air gap onto the substrate is partially overlapped with that of the low-k dielectric layer onto the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.

Classes IPC  ?

• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

A semiconductor device is provided, which includes a semiconductor die and a redistribution layer. The redistribution layer is formed on the semiconductor die, and includes a plurality of center pads, a plurality of edge pads, and a plurality of conductive wires electrically connecting the plurality of center pads to the plurality of edge pads. Each of the plurality of conductive wires comprises at least two turning points, and an inner angle at each turning point is greater than a predetermined angle.

Classes IPC  ?

• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

The present disclosure provides a method of plasma etching. The method includes the following operations. An etching plasma is sprayed onto a nitride layer through a plasma inlet. A protecting gas is sprayed onto an edge portion of the nitride layer through a gas inlet, in which the gas inlet surrounds the plasma inlet, and the protecting gas reacts with the etching plasma to form a polymer.

Classes IPC  ?

• H01L 21/311 - Gravure des couches isolantes
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants

Abrégé

An impedance adjusting circuit is provided. The impedance adjusting circuit of the disclosure includes a sensing node, a pull-up impedance generator, a zero quotient (ZQ) calibrating circuit and a controller. The pull-up impedance generator is coupled between an external voltage and the sensing node. The controller enables a detecting mode in response to a detecting command, and detect a sensing voltage on the sensing node in the detecting mode. When the sensing voltage is in a default voltage range, the controller controls the ZQ calibrating circuit to perform a ZQ calibrating operation on the pull-up impedance generator. When the sensing voltage is out of the default voltage range in the detecting mode, the controller provides a trimming command to the ZQ calibrating circuit. The ZQ calibrating circuit provides a build-in trim code to the pull-up impedance generator in response to the trimming command.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion

Abrégé

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first spacer on a bit line, wherein the first spacer includes low-k material doped with carbon. An oxidation process is performed to the first spacer such that a surface portion of the first spacer is transformed to an oxide spacer. The first spacer has a remaining first spacer that is not oxidized by the oxidation process. Then, a second spacer is formed on the oxide spacer, wherein the second spacer includes nitride. The oxide spacer is removed to form a gap between the remaining first spacer and the second spacer. A cover layer is formed to cover the bit line, the remaining first spacer, and the second spacer such that an air gap is sealed by the cover layer, the remaining first spacer, and the second spacer.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/764 - Espaces d'air

Abrégé

The present disclosure provides a manufacturing method of a semiconductor structure including the following steps. A trench is formed between bit lines. A seed layer is deposited in the trench, and a first contact layer is deposited on the seed layer in the trench. A second contact layer is deposited on the first contact layer to fill the trench, in which a second doping concentration of the second contact layer is lower than a first doping concentration of the first contact layer. An annealing process is performed on the first contact layer and the second contact layer, such that dopants in the first contact layer diffuse into the second contact layer to form a contact plug including the first contact layer and the second contact layer.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A semiconductor device includes a substrate, a first film stack, a second film stack, a first gate spacer, a buffer layer, and a second gate spacer. The first and second film stacks are located on the substrate, and are respectively located in an array area and a periphery area. The first gate spacer includes a first portion on a sidewall of the first film stack and a second portion on a sidewall of the second film stack. The buffer layer includes a first portion on a sidewall of the first portion of the first gate spacer and a second portion on a sidewall of the second portion of the first gate spacer. The second gate spacer includes a first portion on a sidewall of the first portion of the buffer layer and a second portion on a sidewall the second portion of the buffer layer.

Classes IPC  ?

• H10B 41/42 - Fabrication simultanée de périphérie et de cellules de mémoire

Abrégé

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a first word line, a bit line, and a first capacitor. The substrate has a first surface and a second surface opposite to the first surface. The first word line is disposed within the substrate. The bit line is disposed on the first surface of the substrate. The first capacitor is disposed on the second surface of the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

An interconnect structure includes a barrier layer, an oxide glue layer, and an ultra low-k dielectric layer. The oxide glue layer is located on the barrier layer. The ultra low-k dielectric layer is located on the oxide glue layer, wherein the oxide glue layer is located between the barrier layer and the ultra low-k dielectric layer, and the ultra low-k dielectric layer has porosity less than 40%.

Classes IPC  ?

• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a first word line, a bit line, and a first capacitor. The substrate has a first surface and a second surface opposite to the first surface. The first word line is disposed within the substrate. The bit line is disposed on the first surface of the substrate. The first capacitor is disposed on the second surface of the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A method of manufacturing a semiconductor structure is provided by embodiments of this disclosure, and the method includes the following steps. An insulating area and an active area are formed in a substrate. A first word line trench is formed in the active are. A first dielectric layer is deposited in the first word line trench and on the active area and the insulating area. A second word line trench is formed through etching the first dielectric layer. Besides, the second word line trench is linear and extends through the insulating area and the active area of the substrate, and a portion of the first dielectric layer is remained in a bottom of the second word line trench. Then, a word line structure is formed in the second word line trench. Moreover, a semiconductor structure is provided in this disclosure.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/311 - Gravure des couches isolantes
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

A wafer structure includes a plurality of chips and a plurality of dummy connectors. The chips are separated from each other. Each of the chips includes a body and a plurality of conductive pads. The conductive pads are respectively and at least partially disposed on the body. The dummy connectors are connected with each other. Each of the dummy connectors is connected between adjacent two of the bodies. Each of the conductive pads is further at least partially disposed on a corresponding one of the dummy connectors.

Classes IPC  ?

• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• G01R 1/067 - Sondes de mesure
• H01L 23/498 - Connexions électriques sur des substrats isolants

Abrégé

A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first semiconductor structure disposed over the second dielectric layer. The first semiconductor structure has a first portion and a second portion separated from each other by an opening. The semiconductor device structure further includes a second semiconductor structure disposed over the second dielectric layer and in the opening. The second semiconductor structure has a first portion and a second portion separated from each other. Moreover, the first portion of the second semiconductor structure is in direct contact with the first portion of the first semiconductor structure, and the second portion of the second semiconductor structure is in direct contact with the second portion of the first semiconductor structure.

Classes IPC  ?

• H01L 21/311 - Gravure des couches isolantes

Abrégé

A semiconductor device structure includes an isolation structure disposed in a semiconductor substrate. The semiconductor device structure also includes a fuse and a resistor electrode disposed in the semiconductor substrate. The isolation structure is disposed between the fuse and the resistor electrode, and the isolation structure is closer to the resistor electrode than the fuse. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the fuse and the isolation structure. The S/D region is electrically connected to the resistor electrode.

Classes IPC  ?

• H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/64 - Dispositions relatives à l'impédance

Abrégé

A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first semiconductor structure disposed over the second dielectric layer. The first semiconductor structure has a first portion and a second portion separated from each other by an opening. The semiconductor device structure further includes a second semiconductor structure disposed over the second dielectric layer and in the opening. The second semiconductor structure has a first portion and a second portion separated from each other. Moreover, the first portion of the second semiconductor structure is in direct contact with the first portion of the first semiconductor structure, and the second portion of the second semiconductor structure is in direct contact with the second portion of the first semiconductor structure.

Classes IPC  ?

• H01L 21/311 - Gravure des couches isolantes

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first bottom conductive layer positioned in the substrate; a bottom porous dielectric layer positioned on the substrate; a top porous dielectric layer positioned on the bottom porous dielectric layer; a middle porous dielectric layer positioned between the bottom porous dielectric layer and the top porous dielectric layer; and a mixing-area conductive structure positioned along the top porous dielectric layer, the middle porous dielectric layer, and the bottom porous dielectric layer, and positioned on the first bottom conductive layer. A porosity of the top porous dielectric layer is greater than a porosity of the middle porous dielectric layer. The porosity of the middle porous dielectric layer is greater than a porosity of the bottom porous dielectric layer.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées

Abrégé

A semiconductor device structure includes an isolation structure disposed in a semiconductor substrate. The semiconductor device structure also includes a fuse and a resistor electrode disposed in the semiconductor substrate. The isolation structure is disposed between the fuse and the resistor electrode, and the isolation structure is closer to the resistor electrode than the fuse. The semiconductor device structure further includes a source/drain (S/D) region disposed in the semiconductor substrate and between the fuse and the isolation structure. The S/D region is electrically connected to the resistor electrode.

Classes IPC  ?

• H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/64 - Dispositions relatives à l'impédance

Abrégé

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first bottom conductive layer positioned in the substrate; a bottom porous dielectric layer positioned on the substrate; a top porous dielectric layer positioned on the bottom porous dielectric layer; a middle porous dielectric layer positioned between the bottom porous dielectric layer and the top porous dielectric layer; and a mixing-area conductive structure positioned along the top porous dielectric layer, the middle porous dielectric layer, and the bottom porous dielectric layer, and positioned on the first bottom conductive layer. A porosity of the top porous dielectric layer is greater than a porosity of the middle porous dielectric layer. The porosity of the middle porous dielectric layer is greater than a porosity of the bottom porous dielectric layer.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées

Abrégé

A semiconductor device includes a substrate and a bit line structure disposed on the substrate. The bit line structure includes a first conductive structure and a second conductive structure, in which a material of the first conductive structure includes polysilicon. The second conductive structure is disposed in direct contact on the first conductive structure, in which a reactivity of a material of the second conductive structure to oxygen is larger than a reactivity of tungsten to oxygen.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The present application discloses a semiconductor device and a semiconductor device. The method includes providing a substrate including an array area and a peripheral area adjacent to the array area, forming word line structures and source/drain regions in the array area, and a word line protection layer on the array area, forming a first hard mask layer over the substrate and having a step height adjacent to a border between the array area and the peripheral area, forming a bit line contact in the array area and between the word line structures by using the first hard mask layer as a pattern guide, and forming a gate electrode layer on the peripheral area.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 29/40 - Electrodes
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/51 - Matériaux isolants associés à ces électrodes

Abrégé

A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric conformally formed on the first groove and the first slot.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/762 - Régions diélectriques
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices

Abrégé

A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a first energy-sensitive pattern over the target layer. The method also includes performing an energy treating process to transform an upper portion of the first energy-sensitive pattern into a treated portion, forming a lining layer covering the first energy-sensitive pattern, and forming a second energy-sensitive pattern over the lining layer. The first energy-sensitive pattern and the second energy-sensitive pattern are staggered. The method further includes performing an etching process to form a first opening and a second opening in the target layer. The first opening and the second opening have different depths.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/311 - Gravure des couches isolantes

Abrégé

A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• G01R 31/28 - Test de circuits électroniques, p.ex. à l'aide d'un traceur de signaux
• H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

The present disclosure provides a semiconductor device. The semiconductor device includes a die stack, an intervening bonding layer, and a carrier structure. The intervening bonding layer is positioned on the die stack. The carrier structure is disposed on the intervening bonding layer opposite to the die stack. The carrier structure includes a heat dissipation unit configured to transfer heat generated from the die stack. The heat dissipation unit includes composite vias and conductive plates. Each of the composite vias includes a first through semiconductor via and a second through semiconductor via. The conductive plates are couple to the composite vias.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The present application provides a memory device and a method of manufacturing the memory device. The method includes steps of providing a semiconductor substrate including an active area disposed over or in the semiconductor substrate, a first dielectric layer over the semiconductor substrate, a second dielectric layer over the first dielectric layer, and a patterned photoresist layer over the second dielectric layer; removing first portions of the semiconductor substrate, the first dielectric layer and the second dielectric layer exposed through the patterned photoresist layer to form a trench; removing the patterned photoresist layer; disposing an isolation member within the trench; disposing a sacrificial pillar over the second dielectric layer; disposing a first spacer surrounding the sacrificial pillar; removing the sacrificial pillar; disposing a second spacer surrounding the first spacer; and removing second portions of the first dielectric layer and the second dielectric layer exposed through the second spacer.

Classes IPC  ?

• H10B 20/20 - Dispositifs ROM programmable électriquement [PROM] comprenant des composants à effet de champ

Abrégé

This disclosure provides methods of patterning a semiconductor structure. A first resist layer is patterned to form a first opening in the first resist layer. A second resist layer under the first resist layer is patterned to extend the first opening into the second resist layer, where a top surface of an oxide in the second resist layer is higher than a bottom surface of the first opening. The oxide and the second resist layer are simultaneously etched by a first etching process, where a first etching rate of the oxide is close to a second etching rate of the second resist layer. The oxide and a silicon-containing layer under the oxide are etched by a second etching process to form a second opening below the first opening, where a third etching rate of the oxide is higher than a fourth etching rate of the silicon-containing layer.

Classes IPC  ?

• H01L 21/311 - Gravure des couches isolantes
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou

Abrégé

A scribe line structure is provided. The scribe line structure includes a die region, a scribe line region, and one or more circuit probing pads. The die region is disposed on a semiconductor wafer. The scribe line region surrounds the die region. The one or more circuit probing pads are disposed on a first top surface of the die region and a second top surface of the scribe line region.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• G01R 31/28 - Test de circuits électroniques, p.ex. à l'aide d'un traceur de signaux
• H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

An impedance adjusting circuit and an impedance adjusting method for zero quotient (ZQ) calibration. The impedance adjusting circuit includes a reference resistor, a pull-up impedance generator, a controller and a detection circuit. The reference resistor is coupled between a sensing node and a low reference voltage. The pull-up impedance generator is coupled to an external voltage. The controller connects the pull-up impedance generator to the sensing node and compares a reference voltage and a sensing voltage on the sensing node to generate the calibration signal in a ZQ calibrating operation. When the sensing voltage is out of a specification range in the ZQ calibrating operation, the detection circuit notifies the controller to perform a compensation operation on the pull-up impedance generator, and modify the calibration signal to an adjusted calibration signal.

Classes IPC  ?

• H03H 11/28 - Réseaux d'adaptation d'impédance

Abrégé

The present disclosure provides a method of manufacturing a semiconductor device. The method includes: providing a semiconductor structure, in which the semiconductor structure includes alternatively disposed first nitride portions and second nitride portions wrapping portions of an oxide layer, a dielectric layer disposed between one of the first nitride portions and one of the second nitride portions, a top nitride surrounded by the one of the first nitride portions or the one of the second nitride portions, a filling material, and a cap layer disposed on the filling material; forming a plurality of trenches to expose the portions of the oxide layer wrapped by the first nitride portions and the second nitride portions; forming air gaps by removing the portions of the oxide layer; and conformally forming an encapsulating layer on inner sidewalls of the trenches to encapsulate the air gaps.

Classes IPC  ?

• H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable

Abrégé

A method for fabricating a semiconductor device includes forming a trench extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a gate dielectric layer lining the trench. The method also includes forming a gate electrode layer in the trench and over the top surface of the semiconductor substrate, and forming a bit line structure over a S/D region of the semiconductor structure. The bit line structure includes a protection liner having a U-shaped profile and in direct contact with an upper portion of the gate dielectric layer. The formation of the gate electrode layer includes performing a first deposition process, performing a first etching process after the first deposition process, and performing a second deposition process after the first etching process.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 21/3213 - Gravure physique ou chimique des couches, p.ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
• H01L 29/40 - Electrodes
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a vertical memory structure including a semiconductor stack, a contact plug, gate electrodes and air gap structures. The semiconductor stack includes a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate. The contact plug is disposed over the lower semiconductor pattern structure. The contact plug includes a lower portion and a middle portion over the lower portion. A width of the middle portion is less than a width of the lower portion. The gate electrodes are surrounding a sidewall of the semiconductor stack. The air gap structures are disposed at outer sides of the plurality of gate electrode respectively.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The semiconductor structure includes a substrate, a plurality of bitline structures on the substrate, a spacer structure on side walls of each of the plurality of bitline structures, a plurality of conductive structures on the substrate, and a dielectric layer between the plurality of bitline structures and the plurality of conductive structures. The spacer structure includes an inner sub-spacer, an outer sub-spacer, and an air gap between the inner sub-spacer and the outer sub-spacer. Each of the plurality of conductive structures is separated from the other by the plurality of bitline structures. A first portion of the dielectric layer in direct contact with the plurality of bitline structures has a first maximum height, a second portion of the dielectric layer in direct contact with the plurality of conductive structures has a second maximum height, and the first maximum height is larger than the second maximum height.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.

Classes IPC  ?

• H01G 4/30 - Condensateurs à empilement
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes: a data storage unit in a first dielectric layer; a word line disposed over the data storage unit; an array of conductive pads disposed over the word line; a hard mask layer disposed over the array of conductive pads; and a second dielectric layer laterally surrounding the hard mask layer and the array of conductive pads, the second dielectric layer is leveled with the hard mask layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate, a residual nitrogen, a first dielectric layer, a plurality of first contacts, and a plurality of second contacts. The substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. The residual nitrogen is partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars. The first dielectric layer surrounds each of the pillars. The plurality of first contacts extends from the top surfaces of the pillars into the pillars. The plurality of second contacts extends from the top surface of the first dielectric layer into the first dielectric layer.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

An interconnection structure and a method of manufacturing an interconnection structure are provided. The interconnection structure includes a first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first conductive layer disposed in the first dielectric layer. The interconnection structure also includes a conductive via electrically connected with the first conductive layer and extending through the first dielectric layer and the second dielectric layer. The conductive via has a first lateral surface surrounded by the first dielectric layer and a second lateral surface surrounded by the second dielectric layer. The first lateral surface and the second lateral surface have different slopes.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées

Abrégé

A semiconductor device structure and method of manufacturing the same are provided. The semiconductor device structure includes an interposer and a first electronic component. The interposer includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first cache memory and a first memory control circuit. The second semiconductor die includes a second cache memory and a second memory control circuit. The first electronic component is disposed on the interposer and in communication with the first semiconductor die and the second semiconductor die.

Classes IPC  ?

• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

The present disclosure provides a semiconductor structure and a method of manufacturing a semiconductor structure. The semiconductor structure includes: a data storage unit in a first dielectric layer; a word line disposed over the data storage unit; an array of conductive pads disposed over the word line; a hard mask layer disposed over the array of conductive pads; and a second dielectric layer laterally surrounding the hard mask layer and the array of conductive pads, the second dielectric layer is leveled with the hard mask layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. A substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. A first oxide layer is formed over the substrate conformal to the pillars, wherein the formation of the first oxide layer includes oxidizing top corners of the pillars, thereby causing the top surface of each of the plurality of pillars to become a convex surface. A first dielectric layer is formed among the pillars, wherein the first oxide layer above the plurality of pillars is partially exposed through the first dielectric layer. A planarization is performed on the pillars to partially or entirely remove the convex surface.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

An interconnection structure and a method of manufacturing an interconnection structure are provided. The interconnection structure includes a first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first conductive layer disposed in the first dielectric layer. The interconnection structure also includes a conductive via electrically connected with the first conductive layer and extending through the first dielectric layer and the second dielectric layer. The conductive via has a first lateral surface surrounded by the first dielectric layer and a second lateral surface surrounded by the second dielectric layer. The first lateral surface and the second lateral surface have different slopes.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées

Abrégé

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure. The substrate has a cell region and a peripheral region. The first isolation structure is disposed in the cell region of the substrate. The first isolation structure includes a first dielectric layer and a second dielectric layer. The second dielectric layer is spaced apart from the substrate by the first dielectric layer. The second dielectric layer is doped with an impurity.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H10B 20/25 - Dispositifs ROM programmable une seule fois, p.ex. utilisant des jonctions électriquement fusibles

Abrégé

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate having an active region and a shallow trench isolation (STI) adjacent to the active region of the substrate. The STI includes a charge trapping layer and a liner disposed between the charge trapping layer and the active region of the substrate, wherein the charge trapping layer is doped with an impurity.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques

Abrégé

A preheating control system comprising a testing device and a processor is provided in present disclosure. The testing device is configured to perform a wafer testing on a wafer lot and perform a device preheating on the testing device. The processor is coupled to the testing device and comprises a timing circuit and a controlling circuit. The timing circuit is configured to calculate a lot-changing time, wherein the lot-changing time is a difference between a time corresponding to removal of a previous wafer lot from the testing device and a time corresponding to insertion of the wafer lot into the testing device. The controlling circuit is configured to control the testing device to perform the wafer testing, and configured to control the testing device to perform the device preheating according to the lot-changing time and a standard lot-changing time.

Classes IPC  ?

• G01R 1/44 - Modifications des instruments pour la compensation des variations de température
• G01R 31/28 - Test de circuits électroniques, p.ex. à l'aide d'un traceur de signaux

Abrégé

The present disclosure provides a method of manufacturing a semiconductor structure having fins. The method includes providing a semiconductor substrate including a plurality of initial fin structures. The method also includes forming an isolation material covering the plurality of initial fin structures. The method further includes performing an anisotropic etching operation on the isolation material and the plurality of initial fin structures to form a plurality of fins. The method also includes performing an isotropic etching operation on the isolation material to form an isolation structure surrounding the plurality of fins.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/3065 - Gravure par plasma; Gravure au moyen d'ions réactifs
• H01L 21/311 - Gravure des couches isolantes
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A method of manufacturing a semiconductor structure includes a number of operations. A first oxide layer is provided on a semiconductor integrated circuit. A conductive layer of the semiconductor integrated circuit is exposed from a top surface of the first oxide layer. An etch stop layer is formed on the top surface of the first oxide layer. A second oxide layer is formed on the etch stop layer. A through via is formed extending through the second oxide layer and the etch stop layer to expose the conductive layer. Acid is provided on the conductive layer to form a protective layer on the conductive layer. The protective layer includes a compound of the acid and material of the conductive layer. A fence of the second oxide layer at an edge on the through via is removed at the through via by a hydrofluoric acid etching.

Classes IPC  ?

• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées

Abrégé

The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate, a residual nitrogen, an oxide layer, a plurality of first contacts, and a plurality of second contacts. The substrate includes a plurality of pillars in an array region of the substrate, wherein a top surface of each of the plurality of pillars is a substantially planar surface. The residual nitrogen is partially disposed on sidewalls of the pillars proximal to the top surfaces of the pillars. The oxide layer surrounds each of the pillars. The plurality of first contacts extends from the top surfaces of the pillars into the pillars. The plurality of second contacts extends from the top surface of the first dielectric layer into the first dielectric layer.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A semiconductor device includes a first insulating layer inwardly positioned in a substrate and including a U-shaped cross-sectional profile; a first assisting layer conformally positioned on the first insulating layer and the substrate; a first filler layer positioned on the first assisting layer; and a capping dielectric layer positioned on the substrate and covering the first assisting layer and the first filler layer. A top surface of the first insulating layer is at a vertical level lower than a top surface of the substrate. The first assisting layer includes a first step portion and a second step portion, the first step portion of the first assisting layer is adjacent to the top surface of the first insulating layer, and the second step portion of the first assisting layer is adjacent to the top surface of the substrate.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A semiconductor device structure and method of manufacturing the same are provided. The semiconductor device structure includes an interposer and a first electronic component. The interposer includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first cache memory and a first memory control circuit. The second semiconductor die includes a second cache memory and a second memory control circuit. The first electronic component is disposed on the interposer and in communication with the first semiconductor die and the second semiconductor die.

Classes IPC  ?

• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

A conductive structure and a capacitor structure and a method of manufacturing a conductive structure are provided. The conductive structure includes a first support layer, a second support layer, a first conductive via, a third support layer and a second conductive via. The second support layer is disposed over the first support layer. The first conductive via is disposed between the first support layer and the second support layer. The third support layer is disposed over the second support layer. The second conductive via is disposed between the second support layer and the third support layer, and electrically connected to the first conductive via. A lateral surface of the first conductive via is discontinuous with a lateral surface of the second conductive via.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A capacitor structure and a method of manufacturing a capacitor structure are provided. The capacitor structure includes a conductive via, an intermediate dielectric layer and a top electrode. The conductive via includes a neck portion located near a middle portion thereof. The intermediate dielectric layer is disposed on the conductive via. The top electrode is disposed on the intermediate dielectric layer.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées

Abrégé

The present application provides a semiconductor structure and a manufacturing method of the semiconductor structure. A substrate is provided, wherein the substrate includes a plurality of pillars, and a top surface of each of the plurality of pillars is a substantially planar surface. A first oxide layer is formed over the substrate conformal to the pillars, wherein the formation of the first oxide layer includes oxidizing top corners of the pillars, thereby causing the top surface of each of the plurality of pillars to become a convex surface. A first dielectric layer is formed among the pillars, wherein the first oxide layer above the plurality of pillars is partially exposed through the first dielectric layer. A planarization is performed on the pillars to partially or entirely remove the convex surface.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

A semiconductor device includes a first insulating layer inwardly positioned in a substrate and including a U-shaped cross-sectional profile; a first assisting layer conformally positioned on the first insulating layer and the substrate; a first filler layer positioned on the first assisting layer; and a capping dielectric layer positioned on the substrate and covering the first assisting layer and the first filler layer. A top surface of the first insulating layer is at a vertical level lower than a top surface of the substrate. The first assisting layer includes a first step portion and a second step portion, the first step portion of the first assisting layer is adjacent to the top surface of the first insulating layer, and the second step portion of the first assisting layer is adjacent to the top surface of the substrate.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

An impedance adjusting circuit and an impedance adjusting method for zero quotient (ZQ) calibration. The impedance adjusting circuit includes a reference resistor, a first pull-up impedance generator and a second pull-up impedance generator. The reference resistor is coupled between a first sensing node and a low reference voltage. In a first ZQ calibrating operation, the impedance adjusting circuit connects the first pull-up impedance generator to the first sensing node, and compares a first reference voltage and a sensing voltage on the first sensing node to generate the first calibration signal. In a second ZQ calibrating operation, the impedance adjusting circuit connects the second pull-up impedance generator to the first sensing node, and compares a second reference voltage and the sensing voltage to generate the second calibration signal.

Classes IPC  ?

• G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S

Abrégé

The present application provides a semiconductor structure having dielectric liner and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate; a first bit line structure, disposed over the substrate, comprising a first conductive layer, a second conductive layer disposed over the first conductive layer, and a first dielectric layer disposed over the second conductive layer; a second bit line structure, disposed over the substrate, comprising a second dielectric layer, a third conductive layer disposed over the second dielectric layer, and a third dielectric layer disposed over the third conductive layer; a polysilicon layer, disposed over the substrate and surrounded by the first bit line structure and the second bit line structure; a dielectric liner, surrounding at least a portion of the polysilicon layer; and a landing pad, disposed over the polysilicon layer, the dielectric liner and the second bit line structure.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

The present application provides a memory device having a memory cell with reduced protrusion protruding from the memory cell. The memory device includes a semiconductor substrate having a fin portion protruding from a surface of the semiconductor substrate; a semiconductive layer disposed conformal to the fin portion; a conductive layer disposed over the semiconductive layer; an insulating layer disposed over the conductive layer; and a protrusion including a first protruding portion laterally protruding from the semiconductive layer and along the surface, a second protruding portion laterally protruding from the conductive layer and over the first protruding portion, and a third protruding portion laterally protruding from the insulating layer and over the second protruding portion, wherein the protrusion has an undercut profile.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device includes a bottom barrier layer disposed over a semiconductor substrate, and a conductive contact disposed over the bottom barrier layer. The semiconductor device also includes a top barrier layer disposed over the conductive contact. The bottom barrier layer, the conductive contact, and the top barrier layer form an I-shaped structure. The semiconductor device further includes an isolation layer disposed adjacent to the I-shaped structure and extending into the semiconductor substrate. An air gap is surrounded by the isolation layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device includes a bottom barrier layer disposed over a semiconductor substrate, and a conductive contact disposed over the bottom barrier layer. The semiconductor device also includes a top barrier layer disposed over the conductive contact. The bottom barrier layer, the conductive contact, and the top barrier layer form an I-shaped structure. The semiconductor device further includes an isolation layer disposed adjacent to the I-shaped structure and extending into the semiconductor substrate. An air gap is surrounded by the isolation layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A contact structure and a manufacturing method are provided. The contact structure includes a recessed structure, a conductive feature, a first functional layer, a second functional layer and an interfacial layer. The conductive feature is filled in a recess of the recessed structure. The first functional layer extends between the conductive feature and the recessed structure. The second functional layer extends between the first functional layer and the conductive feature. The interfacial extends along an interface between the first and second functional layers, and includes a first element from the first functional layer and a second element from the second functional layer.

Classes IPC  ?

• H01L 29/45 - Electrodes à contact ohmique
• H01L 29/40 - Electrodes