A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.
A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 29/18 - Dispositifs pour la génération d'adresses; Dispositifs pour l'accès aux mémoires, p.ex. détails de circuits d'adressage
A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.
Provided herein is a memory controller for controlling a memory device. The memory controller includes a workload detector configured to determine a change in workload based on reception of a changed request from a host or a change in clock received from an external device, a device performance controller configured to determine, if the workload is determined as changed, read performance based on a ratio of a size of data output to the host to a size of data requested from the host every preset period and configured to output a read-look-ahead (RLA) command to the memory device based on the determined read performance, a buffer memory configured to store data read from the memory device in response to the RLA command and a memory size controller configured to control a size of the buffer memory. The RLA command instructs to output data which is frequently requested from the host.
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec pré-lecture
The present disclosure relates to a storage device. The storage device includes a memory device including write-completed blocks storing data and free blocks each containing no data and a memory controller controlling the memory device to perform a garbage collection operation to store valid data stored in a victim block, among the write-completed blocks, in one of the free blocks based on the number of map segments including mapping information between logical addresses and physical addresses of the valid data, and erase counts of the free blocks.
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
6.
Memory, memory system, operation method of the memory, and operation of the memory system
A method for operating a memory includes determining to perform an error correction operation; determining whether to perform an error correction operation; generating an internal address when the error correction operation is performed; reading data from memory cells that are selected based on the internal address and an error correction code corresponding to the data; performing an error correction operation on the data based on the error correction code to produce an error-corrected data; writing the error-corrected data and an error correction code corresponding to the error-corrected data into the memory cells; determining one or more regions among regions in the memory as a repair-requiring region based on an error detected when the error correction operation is performed; receiving a first command; backing up the data and the error correction code into a redundant region in response to the first command; and repairing the repair-requiring region with the redundant region.
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 29/18 - Dispositifs pour la génération d'adresses; Dispositifs pour l'accès aux mémoires, p.ex. détails de circuits d'adressage
Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, the memory system may determine, according to a time period to which the length of the idle time belongs among a plurality of set time periods, a command pattern indicating a command type of a command expected to be received from the host, and may execute an operation corresponding to the command pattern. In this case, the type of command may be a read command, a write command, or an erase command, and the command pattern may be a read pattern, a write pattern, or an erase pattern.
A semiconductor device includes a flag generation circuit configured to receive region fuse data and used fuse data which are generated from a fuse set selected based on a fuse set selection signal among from fuse sets and generate a bank resource flag to control a repair operation for a bank on which a repair operation has not been performed, based on the region fuse data and the used fuse data. The semiconductor device also includes a repair control circuit configured to control the repair operation for banks sharing the fuse sets based on the bank resource flag.
G11C 8/12 - Circuits de sélection de groupe, p.ex. pour la sélection d'un bloc de mémoire, la sélection d'une puce, la sélection d'un réseau de cellules
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
9.
Input/output circuit, operation method of the input/output circuit and data processing system including the input/output circuit
An input/output circuit including: an input circuit configured to load differential input data to setup nodes based on a data strobe clock; an output circuit configured to compare and amplify the data loaded to the setup nodes, and output differential output data; and a voltage retention circuit configured to retain the setup nodes at voltage levels corresponding to the differential output data, based on the data strobe clock and the differential output data.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/06 - Amplificateurs de lecture; Circuits associés
G11C 8/18 - Circuits de synchronisation ou d'horloge; Génération ou gestion de signaux de commande d'adresse, p.ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
A storage device may include a plurality of memory devices and a memory controller in communication with the plurality of memory devices through a plurality of channels. The memory controller may select candidate channels to be activated among the plurality of channels, determine a threshold number of channel activation based on a number of channels in an active state before a first time point, and activate one or more target channels among the candidate channels so that a number of the target channels to be activated at the first time point is within the threshold number.
A memory controller controlling an operation of a memory device including a plurality of memory cells may provide a first suspend command instructing the memory device to suspend performance of the first operation, provide a command requesting information on a target period in which the first operation is suspended among the plurality of periods, provide a command instructing a second operation to the memory device, provide a resume command instructing the memory device to resume the performance of the first operation after the second operation is ended, and provide a second suspend command instructing the memory device to re-suspend the performance of the first operation after a delay elapses from a time at which the resume command is provided, the delay being based on the delay information corresponding to the target period.
An electronic device includes a masking signal generation circuit configured to generate a test masking signal by receiving a fuse data during a period in which a test masking mode is executed; and a test mode signal generation circuit configured to, when a test command for executing a test in an internal circuit is input, execute the test based on the test masking signal.
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 29/14 - Mise en œuvre d'une logique de commande, p.ex. décodeurs de mode de test
G11C 29/36 - Dispositifs de génération de données, p.ex. inverseurs de données
G11C 17/18 - Circuits auxiliaires, p.ex. pour l'écriture dans la mémoire
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
A storage device includes a memory device and a memory controller. The memory device stores a history read table including root bit information, read voltage information, and error bit information on each of a plurality of memory blocks, and performs a read operation of reading data stored in the plurality of memory blocks based on the history read table. When the read operation fails, a memory controller changes a level of a read voltage, and controls the memory device to perform a read retry operation of retrying the read operation by using the changed read voltage. When the read retry operation passes, the memory controller determines whether the history read table is to be updated by comparing the root bit information of the read retry operation with the root bit information of the history read table.
A memory controller includes: a map cache area for storing a map cache lines including mapping information between a logical address and a physical address; a victim map cache line selector for selecting a victim map cache line among the map cache lines, using a victim map cache line selection model trained by using a storage state information as training data, when a physical address corresponding to a logical address of an operation request is absent in the map cache area; and a map data controller for removing the selected victim map cache line from the map cache area, providing the removed victim map cache line to a memory device, receiving a target map cache line including the physical address corresponding to the logical address of the operation request from the memory device, and storing the target map cache line in the map cache area.
G06F 12/0888 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant la mémorisation cache sélective, p.ex. la purge du cache
G06F 12/0873 - Mappage de mémoire de mémoire cache vers des dispositifs ou des parties de dispositifs de stockage
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
Provided herein is a memory controller for controlling a memory device. The memory controller includes a workload detector configured to determine a change in workload based on reception of a changed request from a host or a change in clock received from an external device, a device performance controller configured to determine, if the workload is determined as changed, read performance based on a ratio of a size of data output to the host to a size of data requested from the host every preset period and configured to output a read-look-ahead (RLA) command to the memory device based on the determined read performance, a buffer memory configured to store data read from the memory device in response to the RLA command and a memory size controller configured to control a size of the buffer memory. The RLA command instructs to output data which is frequently requested from the host.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec pré-lecture
16.
Sample-and-hold amplifier and semiconductor device including the same
A sample-and-hold amplification circuit can include a sampling circuit configured to sample first and second input signals in response to first and second control signals to generate first and second sampled signals, an amplification circuit configured to amplify a voltage difference between the first and second sampled signals to generate first and second output signals, and an offset compensation circuit configured to form a first path between input and output terminals of the amplification circuit in response to the first control signal to store an offset of the input terminal and form a second path between the input and output terminals in response to the second control signal to reflect the offset to the output terminal.
G11C 27/02 - Moyens d'échantillonnage et de mémorisation
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p.ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
17.
Memory device and memory system controlling generation of data strobe signal based on executing a test
A memory device includes a data storage circuit configured to store, when a write operation is performed, a first internal write data and a second internal write data in a memory cell array which is accessed by an internal address, and output, when a read operation is performed, data stored in a memory cell array which is accessed by the internal address, as internal read data; and a flag generation circuit configured to generate a flag for controlling generation of a data strobe signal, based on the internal read data.
G11C 29/14 - Mise en œuvre d'une logique de commande, p.ex. décodeurs de mode de test
G11C 29/10 - Algorithmes de test, p.ex. algorithmes par balayage de mémoire [MScan]; Configurations de test, p.ex. configurations en damier
G11C 29/44 - Indication ou identification d'erreurs, p.ex. pour la réparation
G11C 29/56 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne Équipements externes pour test de mémoires statiques, p.ex. équipement de test automatique [ATE]; Interfaces correspondantes
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 8/18 - Circuits de synchronisation ou d'horloge; Génération ou gestion de signaux de commande d'adresse, p.ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
G11C 29/36 - Dispositifs de génération de données, p.ex. inverseurs de données
18.
Calibration circuit and semiconductor device including the same
A semiconductor device which includes a termination circuit coupled to a first pad and suitable for providing a termination resistance according to a first control code and a second control code during a normal operation in which data are input and output through the first pad; a stress replica circuit suitable for replicating a stress applied to the termination circuit during the normal operation and for generating a detection code during a second calibration mode; a first calibration circuit suitable for adjusting the first control code to match an impedance of a resistor part coupled to a second pad to an external resistor during a first calibration mode; and a second calibration circuit suitable for generating the second control code by adjusting the first control code according to the detection code during the second calibration mode.
The present technology relates to a memory controller according to an embodiment includes a map caching controller generating a slot allocation request to allocate a physical slot in which a first map segment is to be stored among a plurality of physical slots, a map buffer manager outputting the first map segment, first physical slot information, and tree slot information, in response to the slot allocation request, and a mapping manager receiving the first map segment, the first physical slot information, and the tree slot information, deleting a second map segment and second physical slot information stored in a tree slot among a plurality of tree slots of a map tree, and storing the first map segment and the first physical slot information in the tree slot. At least one of the second map segment and the second physical slot information stored in the tree slot is invalid.
G06F 12/08 - Adressage ou affectation; Réadressage dans des systèmes de mémoires hiérarchiques, p.ex. des systèmes de mémoire virtuelle
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache
A memory device includes a data storage circuit configured to access a cell array having first data stored therein when an arithmetic active operation is performed, output the first data when a first read operation is performed, access a cell array having second data stored therein when an active operation is performed, and output the second data when a second read operation is performed. The memory device also includes an arithmetic circuit configured to receive latch data generated through the first read operation and read data generated through the second read operation, and perform an arithmetic operation on the latch data and the read data.
G06F 3/00 - Dispositions d'entrée pour le transfert de données destinées à être traitées sous une forme maniable par le calculateur; Dispositions de sortie pour le transfert de données de l'unité de traitement à l'unité de sortie, p.ex. dispositions d'interface
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 7/06 - Amplificateurs de lecture; Circuits associés
G11C 7/12 - Circuits de commande de lignes de bits, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to embodiments of the present disclosure, a memory system may determine whether the memory system is in a read-intensive state; when determined that the memory system is in the read-intensive state, process a write request received from a host using at least one first type memory block among the plurality of memory blocks, and migrate data stored in a second type memory block to the at least one first type memory block; and set a number of bits that can be stored in a memory cell included in the first type memory block to be less than a number of bits that can be stored in a memory cell included in the second type memory block.
An electronic device includes a memory controller and a memory device. The memory controller that controls the memory device includes a write buffer to temporarily store write data received from a host, a write timing controller to receive temperature information indicating a temperature of the memory device and generate write timing information based on the temperature information, the write timing information indicating a write timing at which the write data is transferred to and stored in the memory device, and a write operation controller to control the write buffer and the memory device based on the write timing information such that the write data stored in the write buffer is transferred to and stored in the memory device.
Various embodiments of the present disclosure generally relate to a memory system and an operating method thereof. According to the embodiments of the disclosed technology, the memory system may check first information indicating an execution state of a reference operation on each of the memory blocks during a preset target time period, may determine, based on the first information, at least one target memory block, among the plurality of memory blocks, as a target of a refresh operation of rewriting data stored in the target memory block and may execute a refresh operation on the target memory block.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
Disclosed is a memory system including a controller configured to authenticate a user who inputs a request for discarding the memory system, to verify whether the request is valid when the user is authenticated as a legitimate user, to register discard activation of the memory system when the request is valid, and to transmit the request to a memory device; and the memory device configured to determine whether the transmitted request is valid, and to register the discard activation of the memory system when the request is valid.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p.ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p.ex. les mémoires adressables directement
A memory system includes: a memory block including a plurality of pages each comprising a plurality of memory cells connected to bit lines and a word line of word lines, an address manager configured to output addresses corresponding to the plurality of pages, and a system data manager configured to generate index data corresponding to the each of the addresses, the index data indicating whether user data is inverted, and output the index data and information on a memory cell in which the index data is to be stored, respectively. The system data manager is configured to, determine memory cells connected to different bit lines from among memory cells included in adjacent pages corresponding to consecutive addresses of the addresses, as memory cells in which index data corresponding to the consecutive addresses are to be stored.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/14 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
Disclosed is a memory system including: a memory device including a plurality of memory blocks; an address management component suitable for generating an address map table by sequentially mapping a logical address of write data to physical addresses of the memory blocks, in response to a write command; and a read/write control component suitable for writing the write data to a super memory block including pages of each of the memory blocks, based on the address map table, wherein the address management component maps a logical address of invalidation data which is designated by a host, to a physical address of a first memory block of the memory blocks in the address map table.
A controller for controlling a memory device may include: an end-to-end decoder suitable for correcting an error in the unit user data and the corresponding end-to-end parity; an internal encoder suitable for generating a data chunk by adding a first internal parity to the source word which includes the unit user data and the end-to-end parity from the end-to-end decoder and buffering the source word into a buffer; an integrity checker suitable for determining whether an error is included in the source word, by using the end-to-end parity from the end-to-end decoder; and a parallel parity generator suitable for receiving the source word from the buffer according to a result of the determination, and completing a parallel parity based on a predetermined number of source words received, wherein the internal encoder is further suitable for generating a parity chunk by adding a second internal parity to the completed parallel parity.
A data storage apparatus includes a storage including a plurality of planes, which include a plurality of pages, and a controller configured to control the storage to read data by grouping the plurality of pages as a page group in an interleaving unit, manage pages in which valid data are stored, among the plurality of pages, as a first bitmap table, and manage a second bitmap table generated by compressing the first bitmap table in a page group unit.
An image processing system includes: an image sensor suitable for generating an RYYB (Red Yellow Yellow Blue) bayer image by applying an RYYB color filter array; an interpolation logic suitable for generating a Y image at a position of an R image portion in the RYYB bayer image by interpolating a YY image portion in the RYYB bayer image; and a guided filtering logic suitable for guided-filtering the R image portion in the RYYB bayer image by using, as a guide image, the Y image at the position of the R image portion.
G06K 7/14 - Méthodes ou dispositions pour la lecture de supports d'enregistrement par radiation corpusculaire utilisant la lumière sans sélection des longueurs d'onde, p.ex. lecture de la lumière blanche réfléchie
The present technology includes a controller and a method of operating the same. The controller includes a buffer in which N bits of data are stored, and a cyclic redundancy check controller configured to divide the N bits of data stored in the buffer into m data groups each including K bits of data, generate compressed data including K bits by processing data included in the m data groups, and generate a cyclic redundancy check code using the compressed data.
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may repeatedly execute, when entering a low power mode, iterations of a target operation according to a temperature of the memory system until a stop condition is satisfied. In this case, the target operation may be a garbage collection operation for the plurality of memory blocks or a migration operation of moving data stored in a first area including at least one of the plurality of memory blocks to a second area including at least one of the plurality of memory blocks. The operation speed of the memory block included in the first area may be higher than the operation speed of the memory block included in the second area.
The disclosure relates to an operating method of controller, and memory system having the same, the method controls a semiconductor memory device including a plurality of memory blocks. The method includes: receiving read data output according to a first read operation performed on a selected memory block; selecting a read voltage set group from a read retry table based on a read error related indicator providing an indication that an error correction failure has occurred; and selecting a read voltage set from the selected read voltage set group based on whether the read error related indicator is greater than or equal to a predetermined reference value. The selected read voltage set has a minimum average distance with respect to a read voltage set used for the first read operation, and has a minimum first read voltage distance with respect to the read voltage set used for the first read operation.
A memory system includes: a memory device including a plurality of memory dies including the plurality of planes; and a controller configured to store data in a plurality of stripes each including physical pages of different planes and a plurality of unit regions, the controller comprising: a processor configured to queue write commands in a write queue, and select, among the plurality of stripes, a stripe in which data chunks corresponding to the write commands are to be stored; and a striping engine configured to receive queued orders of the write commands, and output, by referring to a lookup table, addresses of unit regions, in which the data chunks are to be arranged, to the processor, wherein the processor in configured to control the memory device to store the data chunks in the unit regions corresponding to the outputted addresses of the selected stripe.
A data storage device may include a first memory apparatus including a plurality of data blocks having data classified in units of data blocks; a second memory apparatus in communication with the first memory apparatus to store data cached from the first memory apparatus; and a controller in communication with the first memory apparatus and the second memory apparatus. The controller is configured to perform a caching group based caching operation by controlling the first memory apparatus to cache data from the first memory apparatus to the second memory apparatus on a caching group basis. Each caching group includes a first data block requested for caching and one or more other data blocks having the same write count as a write count of the first data block.
G06F 12/0888 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant la mémorisation cache sélective, p.ex. la purge du cache
G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
A controller for controlling a memory device including memory cells, the controller includes: a memory suitable for storing offset level information which is determined based on a sample read level according to characteristics of the memory cells and Gaussian modeling of the memory cells; and a processor suitable for generating an estimated read level based on the Gaussian madding and data read from the memory cells, and applying a compensated read voltage to control the memory device to perform read operations of the memory cells, wherein the compensated read voltage is generated by applying the offset level information to the estimated read level.
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
A memory system may write, when operating in a force unit access mode, first write data requested by the host to a buffer for temporarily storing data to be written the memory device and a first memory block among the plurality of memory blocks, and may write, when the size of the data accumulatively stored in the buffer is greater than or equal to A which is a unit of a size in which data is written to a second memory block among the plurality of memory blocks, second write data of size A among the data stored in the buffer to the second memory block. The operation speed of the first memory block may be set faster than the operation speed of the second memory block and the storage capacity of the first memory block may be set smaller than the storage capacity of the second memory block.
An input/output circuit including: an input circuit configured to load differential input data to setup nodes based on a data strobe clock; an output circuit configured to compare and amplify the data loaded to the setup nodes, and output differential output data; and a voltage retention circuit configured to retain the setup nodes at voltage levels corresponding to the differential output data, based on the data strobe clock and the differential output data.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/06 - Amplificateurs de lecture; Circuits associés
G11C 8/18 - Circuits de synchronisation ou d'horloge; Génération ou gestion de signaux de commande d'adresse, p.ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
38.
Calibration circuit and semiconductor device including the same
A semiconductor device which includes a termination circuit coupled to a first pad and suitable for providing a termination resistance according to a first control code and a second control code during a normal operation in which data are input and output through the first pad; a stress replica circuit suitable for replicating a stress applied to the termination circuit during the normal operation and for generating a detection code during a second calibration mode; a first calibration circuit suitable for adjusting the first control code to match an impedance of a resistor part coupled to a second pad to an external resistor during a first calibration mode; and a second calibration circuit suitable for generating the second control code by adjusting the first control code according to the detection code during the second calibration mode.
A storage device may include a memory device and a memory controller. The memory device may include a plurality of data blocks, a plurality of replacement blocks to replace bad blocks, and a system block configured to store default system information. The memory controller may store, based on a result of comparing a lifetime of the memory device with a reference value, update system information corresponding to an update of the default system information, in a selected replacement block among the plurality of replacement blocks. The memory controller may control the memory device to set the selected replacement block as a target system block. The default system information may include one or more parameters corresponding to at least one operation among a read operation, a program operation, and an erase operation of the memory device.
A storage device may include: a memory device including a plurality of memory blocks; a buffer memory device to store event information; and a memory controller configured to: upon occurrence of the predetermined event while a write operation, store, in the buffer memory device, the event information for the event page, and control the memory device to perform a test read operation to read at least one page in the plurality of memory blocks except the event page, based on the event information; upon failure of the test read operation, control the memory device to perform a migration operation of moving, to a replacement block, data stored in valid pages except a page on which the test read operation has fails among pages included in a memory block on which the test read operation fails.
Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may execute a read operation by setting a command delay time for determining whether to merge and process read commands, for each of a plurality of time periods, and may set a target command delay time, from among the command delay times set for each of the plurality of time periods, to be used for determining whether to merge and process a subsequent read command with one or more prior read commands based on the execution result of the read operation for each of the plurality of time periods.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
42.
Memory controller and method of operating the same
A memory controller and a method of operating the same may provide recovery from a Sudden Power-Off (SPO). The memory controller may control a memory device including a plurality of memory blocks, each memory block having a plurality of pages. The memory controller may include a dummy program controller configured to, after an SPO has occurred while a program operation was being performed on a page of the memory device, control a dummy program operation for recovering from the SPO; a parity data controller configured to control resetting and generation of parity data for chipkill decoding based on pages on which the dummy program operation is determined to be performed; and a valid data controller configured to control movement of valid data based on a number of pages on which the dummy program operation is to be performed.
A memory device, and a method of operating the same, includes a plurality of pages, a peripheral circuit, and control logic. The peripheral circuit is configured to receive a command, an address, and data from an external controller to program a page selected from among the plurality of pages, and to generate internal input data depending on an input mode for the command, the address, and the data. The control logic is configured to determine whether internal input data is to be generated based on the data depending on the input mode and to control the peripheral circuit so that a program operation of programming the internal input data is performed.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 16/10 - Circuits de programmation ou d'entrée de données
44.
Memory device for performing multi program operation and operating method thereof
A memory device includes: a plurality of memory cells grouped into a plurality of planes; page buffer groups corresponding to respective ones of the plurality of planes, the page buffer groups including a plurality of page buffer circuits, each of the plurality of page buffer circuits including cache latches which are configured to receive data to be stored in memory cells in the plurality of planes; and control logic for controlling the page buffer groups to simultaneously initialize cache latches corresponding to at least two planes, among the cache latches, in response to a multi-plane program command, wherein the multi-plane program command instructs a multi-plane program operation of simultaneously storing data in plural planes among the plurality of planes.
A storage device includes: a memory device including a map data block including mapping information between a logical address and a physical address; a buffer memory device for storing a block state table including block state information; and a memory controller for determining valid data of a source block among the plurality of memory blocks based on mapping information and block state information corresponding to the source block, and moving the valid data to open memory block. The memory controller may generate a valid page list in which information of the valid data is arranged in a stripe page unit according to an order of logical addresses, and control the memory device to move the valid data to the open memory block, based on the valid page list.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
The storage device includes: a memory device including a plurality of user blocks and a system block; a buffer memory for storing a physical-to-logical table, and a memory controller for controlling the memory device to update map data stored in the system block, based on the physical-to-logical table, and to store the updated map data in the system block, after logical addresses of the physical-to-logical table are all allocated.
A semiconductor package is described. The semiconductor packager includes a chip stack mounted over a package substrate, a first wire disposed over the package substrate, and a molding layer surrounding the chip stack and the first wire. The first wire has an acute angle.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
48.
Host, data storage device, data processing system and data processing method
A data processing system may include: a host including a command queue including a plurality of command storage areas, and configured to store summary information of a second command among a plurality of commands in a reserved storage area of a command storage area, among the plurality of command storage areas, in which a first command among the plurality of commands being a previous command to the second command is stored, when inserting the second command into the command queue; and a data storage device configured to fetch the first command from the command queue and store the fetched first command, according to a new command notification received from the host.
A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.
A memory system includes a memory device comprising a plurality of pages, and a controller suitable for storing data, inputted in response to a write command received from a host, in corresponding pages among the plurality of pages, wherein the controller generates and manages a bitmap table indicating order information of the inputted data according to the type of the write command.
There are provided a memory controller and an operating method thereof. The memory controller includes: a meta data storage for storing meta data including mapping information of data stored in a memory device and valid data information representing whether the data stored in the memory device is valid data; and a migration controller for controlling the memory device to perform a migration operation of moving, to a target memory block, valid data stored in a plurality of source memory blocks included in the memory device, based on the meta data. The migration controller controls the memory device to read a second valid data stored in the second die before reading a first valid data stored in the first die, based on a comparison result between a reference time and a delay time required until before the first valid data is read.
Disclosed is an image sensing device including a sampling module suitable for generating for each color, a plurality of images having different exposure times, based on a single image generated during a single frame time; a correction module suitable for learning correction parameters of the single image based on the plurality of images using a set learning algorithm, and generating a plurality of corrected images by removing the correction parameters from the plurality of images; and an image processing module suitable for generating a high dynamic range image corresponding to the single image, based on the plurality of corrected images.
A controller including a test manager configured to output a program command for performing a program operation of a memory block and a suspend command for stopping the program operation, and a memory interface configured to transmit the program command to a memory device including the memory block, and transmit the suspend command to the memory device after a set time elapses. The test manager outputs a read command for reading memory cells included in the memory block, the memory interface calculates a count value by counting data output from the memory device in response to the read command, and the test manager generates status information on the memory block according to the count value.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
The present technology relates to an electronic device. For example, the present technology relates to a memory device and a method of operating the memory device. A memory device according to an embodiment includes a memory cell, a page buffer, and a test performer configured to control the page buffer to sequentially apply a first test voltage and a second test voltage of a level lower than a level of the first test voltage to a sensing node of the page buffer through a bit line, and detect a defect of the sensing node according to whether a potential level of the sensing node is changed.
The present technology relates to a memory device. A memory device according to the present technology includes a memory cell array including a backup block and a data block, a data input/output circuit including a plurality of page buffers that buffer data received from a host, a peripheral circuit configured to perform a program operation of storing the data in the data block, and a backup operation controller configured to control the peripheral circuit to perform a reset operation of stopping the program operation and a backup program operation of storing the data in the backup block when a backup command indicating occurrence of a sudden power off is received from an external controller during the program operation, and the reset operation is an operation of maintaining a state in which the data is buffered in the plurality of page buffers and resetting the peripheral circuit.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 1/30 - Moyens pour agir en cas de panne ou d'interruption d'alimentation
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
The present disclosure relates to a storage device and an operating method thereof. The storage device includes a memory device including write-completed blocks storing data and free blocks each containing no data and a memory controller controlling the memory device to perform a garbage collection operation to store valid data stored in a victim block, among the write-completed blocks, in one of the free blocks based on the number of map segments including mapping information between logical addresses and physical addresses of the valid data, and erase counts of the free blocks.
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
57.
Integrated circuit and test operation method thereof
An integrated circuit includes a test counting circuit, a test information storage circuit, a sequence control circuit and a driving circuit. The test counting circuit generates a counting address signal. The test information storage circuit stores a test control value and outputs the test control value based on the counting address signal. The sequence control circuit changes an output sequence of the test control value based on a sequence control signal and outputs a final test control value based on the test control value or a target control value. The driving circuit performs a pre-set test operation based on the final test control value.
G11C 29/20 - Dispositifs pour la génération d'adresses; Dispositifs pour l'accès aux mémoires, p.ex. détails de circuits d'adressage utilisant des compteurs ou des registres à décalage à rétroaction linéaire [LFSR]
A storage device includes a memory device including a plurality of memory blocks including a plurality of memory cells respectively connected to a plurality of word lines which are vertically stacked, and a memory controller configured to control the memory device to determine an attribute of a plurality of write data corresponding to a write request in response to the write request provided from a host, set a program voltage used for a program operation of storing write data having the same attribute of the write data among the plurality of write data in the same memory block based on a lookup table including the attribute of the write data and program information on the program voltage according to positions of the plurality of word lines, and perform the program operation according to the set program voltage.
G11C 11/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
59.
Latch circuit and memory device including the same
A memory device includes a latch circuit suitable for storing an input address as a first latch address in response to a first latch signal, and storing an address, selected between the input address and the first latch address, as a second latch address in response to a second latch signal, a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal corresponding to the determination result, in response to a test mode signal, and a control signal generation circuit suitable for comparing the input address to the first and second latch addresses in response to the detection signal, and selectively enabling the first and second latch signals according to the comparison result.
G11C 11/40 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors
G11C 29/44 - Indication ou identification d'erreurs, p.ex. pour la réparation
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G11C 29/20 - Dispositifs pour la génération d'adresses; Dispositifs pour l'accès aux mémoires, p.ex. détails de circuits d'adressage utilisant des compteurs ou des registres à décalage à rétroaction linéaire [LFSR]
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 29/10 - Algorithmes de test, p.ex. algorithmes par balayage de mémoire [MScan]; Configurations de test, p.ex. configurations en damier
60.
Memory system, memory controller, and method of operating memory system
Disclosed are a memory system, a memory controller, and a method of operating the memory system. The memory system performs an operation of recovering system data lost due to SPO when an SPO recovery operation is performed, and flushes recovered system data into the memory device after a first time point at which the operation of recovering the system data is completed and before a second time point at which a power off preparation request is received from a host.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
61.
Memory device with temperature information controller and operating method of the memory device
A storage device including: a peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from the memory controller, a temperature information controller configured to generate a first temperature code corresponding to an internal temperature at a time at which an internal operation corresponding to a first internal operation command among the plurality of internal operation commands is performed and temperature code generation information representing information that the first temperature code has been generated during a set period and a operation controller configured to control the peripheral circuit to perform an internal operation corresponding to a second internal operation command input after the first internal operation command among the plurality of internal operation commands is input, based on the first temperature code and the temperature code generation information, in response to the second internal operation command.
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
62.
Memory controller and method of ordering sequential data and random data
A memory controller includes a meta data memory configured to store mapping information of data stored in a plurality of memory blocks included in a memory device and valid data information indicating whether the data stored in the plurality of memory blocks is valid data, and a migration controller configured to control the memory device to perform a migration operation of moving a plurality of valid data stored in a source memory block among the plurality of memory blocks from the source memory block to a target memory block based on the mapping information and the valid data information.
A memory system may include: a nonvolatile memory device; a volatile memory suitable for storing write data; and a controller suitable for: allocating a normal write buffer in the volatile memory when normal write data are inputted, allocating a first write buffer in the volatile memory when first write data, which are grouped into a first transaction and first total size information on a total size of the first transaction, are inputted, allocating a second write buffer in the volatile memory when second write data, which are grouped into a second transaction and second total size information on a total size of the second transaction, are inputted, managing sizes of the first and second write buffers to change them in response to the first and second total size information, respectively, and managing a size of the normal write buffer to fix it to a set size.
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
64.
Memory system and method for operating memory controller included therein
A memory system may include: one or more memory devices each including a plurality of memory cells for storing data; a memory for storing meta data associated with the stored data; and a memory controller in communication with the memory and the one or more memory devices and for loading the meta data from the memory, and generating first meta page based on the meta data according to a first layout, and storing the first meta page in the memory device.
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
A memory device includes a system block for storing test information and includes a data block including memory cells connected to a plurality of low bank column lines and a plurality of high bank column lines. The memory device also includes a column repair controller configured to detect, based on the test information, a concurrent repair column line in which a low bank column line among the plurality of low bank column lines and a high bank column line the plurality of high bank column lines corresponding to the same column address are concurrent repaired.
Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including multiple planes, a peripheral circuit configured to perform an operation on the multiple planes, a control memory configured to store control codes for controlling the peripheral circuit, and a plurality of independent control logic configured to, when a command corresponding to each of the planes is received from a memory controller, control the peripheral circuit with reference to a control code corresponding to the command in response to the command. The control memory includes a common memory configured to be accessible in common by the plurality of independent control logic, and a temporary storage including areas respectively corresponding to the planes.
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
67.
Edge-based sharpness strength control circuit, image sensing device and operation method of the same
An edge-based sharpness strength control circuit include a first edge determination unit suitable for determining each of multiple regions in a pixel array to be an edge region having edge information on pixel data of the corresponding region or a flat region having flat information on pixel data of the corresponding region, the pixel array including a plurality of pixels; a second edge determination unit suitable for determining each edge region to be a step edge region having directional information within the corresponding edge region or a texture edge region having non-directional information within the corresponding edge region; and a noise removing unit suitable for removing noise from each step edge region using a first filter and for removing noise from each texture edge region using a second filter having a different gain than that of the first filter.
H04N 5/14 - Circuits de signal d'image pour le domaine des fréquences vidéo
H04N 5/217 - Circuits pour la suppression ou la diminution de perturbations, p.ex. moiré ou halo lors de la production des signaux d'image
H04N 5/21 - Circuits pour la suppression ou la diminution de perturbations, p.ex. moiré ou halo
H04N 5/369 - Transformation d'informations lumineuses ou analogues en informations électriques utilisant des capteurs d'images à l'état solide [capteurs SSIS] circuits associés à cette dernière
68.
Memory system, memory controller, and method for operating memory system performing integrity check operation on target code when voltage drop is detected
Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to embodiments of the present disclosure, a memory system may perform an integrity check operation on target code when information indicating whether a supply voltage supplied to a memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage. Accordingly, the memory system is capable of minimizing the time of operation in the state in which a bit-flip occurs and preventing a problem in which irrecoverable data is recorded in a memory device due to malfunction of firmware.
A controller that controls a memory device, includes: a buffer memory; and a processor suitable for: temporarily storing bridge firmware data in the buffer memory when the bridge firmware data is received together with a previous firmware update request, installing and executing bridge firmware based on the bridge firmware data after approved retention firmware data is received together with a subsequent firmware update request, installing the approved retention firmware after execution of the bridge firmware, and removing the installed bridge firmware.
An operating method of a memory system that includes a memory device including a plurality of blocks and a controller including a memory in which a first open block list and a second open block list are stored, the method comprising receiving a write request and a logical address from a host; converting the logical address into a first virtual address; converting the first virtual address into a physical address; performing a first error checking operation of checking a mapping relationship between the first virtual address and the physical address based on the first open block list; performing a second error checking operation of checking whether the physical address is included in the second open block list; and performing a write operation on an open block corresponding to the physical address when it is determined that the physical address is not allocated more than once.
A semiconductor device includes a voltage comparison circuit and a calibration control circuit. The voltage comparison circuit compares test reference voltages and generates a comparison result signal. The calibration control circuit controls an offset value of the voltage comparison circuit.
The present technology relates to a semiconductor device and a method of operating the same. The semiconductor device includes a sensing voltage generator configured to generate a temperature voltage having a voltage level determined according to an internal temperature of the semiconductor device and a reference voltage having a constant voltage level, a code generator configured to generate a temporary code including a sensing code value corresponding to the internal temperature and a boundary value indicating whether the internal temperature is included in a boundary portion associated with at least one temperature range corresponding to the sensing code value based on the temperature voltage and the reference voltage, and a code correction component configured to generate a correction code for generating an operation voltage of the semiconductor device by correcting the temporary code, based on the temporary code and a previously generated correction code.
G06F 3/00 - Dispositions d'entrée pour le transfert de données destinées à être traitées sous une forme maniable par le calculateur; Dispositions de sortie pour le transfert de données de l'unité de traitement à l'unité de sortie, p.ex. dispositions d'interface
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
The present technology relates to an electronic device. More specifically, the present technology relates to a storage device and a method of operating the same. A memory device according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation, a program verifier configured to calculate difference values, each of which is between a first pass loop count and a second pass loop count of a respective one of program states, when the program operation is completed, and output a pass status or a fail status according to whether at least one of the difference values exceeds a reference value.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
74.
Memory system for accessing data in stripe form and operating method thereof
A memory system includes a plurality of memory devices, a buffer memory, and a controller. The controller generates bitmap information for a plurality of pages to distinguish a first page on which a read operation has succeeded from a second page on which the read operation has failed, and stores the bitmap information in the buffer memory, whenever completing the read operation for each of the plurality of pages. The controller generates parity data by cumulatively performing a parity operation on data of the first page whenever performing the read operation on each of the plurality of pages, and stores the parity data in the buffer memory. The controller checks the bitmap information after the read operations on the plurality of pages are completed, and recovers data of the second page by referring to the parity data when the second page is present among the plurality of pages.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
75.
Memory performing defragmentation operation using data collecting area and method of operating the same
A method of operating a memory comprises reading a first node including first data and a first link; writing the first data to a data collecting area; updating a first collecting link of the first data, which is written in the data collecting area to a position in the data collecting area; reading a second node corresponding to the first link, the second node including second data and a second link; and writing the second data to a position in the data collecting area, which is designated by the first collecting link.
Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method of a memory system. According to embodiments of the present disclosure, the memory system may transmit, to a host, target data, and, upon receiving, from the host, information indicating that at least one bit-flip has occurred in the target data, may perform an error handling operation on the at least one bit-flip in the target data. Accordingly, the memory system is able to reduce resource used in checking the bit-flip and to alleviate the constraints of the algorithms used in checking for the bit-flip.
An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
H01L 29/74 - Dispositifs du type thyristor, p.ex. avec un fonctionnement par régénération à quatre zones
78.
Data storage device for storing boot partition data read from memory device in buffer memory and method of operating the same
Provided herein may be a data storage device and a method of operating the same. The data storage device having improved response speed may include a buffer memory configured to hold data, a memory device including a user area reserved for storing user data from a host and configured to be accessed by a first procedure, and a boot partition area reserved for storing boot partition data and configured to be accessed by a second procedure different from the first procedure and a memory controller coupled to and in communications with the buffer memory and memory device and configured to, upon receipt of power from a power supply, control the buffer memory and the memory device to perform a preloading operation by storing, in the buffer memory, part of boot partition data from the boot partition area before a request from the host is received.
The present technology includes a controller and a memory system including the same. The controller includes a memory interface configured to receive a codeword from a memory device, and an error correction circuit configured to: perform an error correction decoding operation on the codeword received from the memory interface, compare a number of unsatisfied check nodes (UCNs) detected in the error correction decoding operation with a reference number, perform or stop the error correction decoding operation on the codeword according to a result of comparing the number of UCNs and the reference number, and output a retransmission request signal of the codeword to the memory interface in response to the result, wherein the memory interface requests the codeword to the memory device in response to the retransmission request signal.
H03M 13/09 - Détection d'erreurs uniquement, p.ex. utilisant des codes de contrôle à redondance cyclique [CRC] ou un seul bit de parité
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
H01L 29/74 - Dispositifs du type thyristor, p.ex. avec un fonctionnement par régénération à quatre zones
A memory system is provided to include memory devices and a controller including cores controlling the memory devices, respectively. The controller determines whether to perform a global wear-leveling operation based on a write count of the plurality of memory devices corresponding to each of the plurality of cores, performs a barrier operation for a request from a host when the global wear-leveling operation is determined to be performed, updates mapping information for mapping a core to memory device information by swapping the mapping information between different cores based on the write count of each of the plurality of cores and closes an open block assigned to each of the plurality of cores and then assigning a new open block to each of the plurality of cores based on the updated mapping information.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/0873 - Mappage de mémoire de mémoire cache vers des dispositifs ou des parties de dispositifs de stockage
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
82.
Memory controller and method of operating the same
Memory controller devices, memory systems, and operating methods for memory controller devices and memory systems are disclosed. In one aspect, a memory controller having improved wear leveling performance is disclosed. The memory controller may control a first memory area and a second memory area, and include a first software layer configured to control the first memory area based on first logical addresses, a second software layer configured to control the second memory area based on second logical addresses, and a logical address manager configured to compare a logical address received from a host with a reference address selected from among a plurality of logical addresses to be used by the host, and transmit the logical address received from the host to the first software layer or the second software layer according to a criterion selected from between a first criterion and a second criterion based on the comparison.
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/0837 - Protocoles de cohérence de mémoire cache avec commande par logiciel, p.ex. données ne pouvant pas être mises en mémoire cache
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
83.
Image sensing device adjusting comparison precondition for pixel signals
An image sensing device includes first and anterior comparators and first and second posterior comparators. The first anterior comparator generates a first anterior comparison signal based on a first pixel signal and a ramp signal. The first posterior comparator performs a first comparison that compares the first anterior comparison signal with a first reference signal under a first comparison precondition and generates a first posterior comparison signal corresponding to a result of the first comparison. The second anterior comparator generates a second anterior comparison signal based on a second pixel signal and the ramp signal. The second posterior comparator performs a second comparison that compares the second anterior comparison signal with a second reference signal under a second comparison precondition different from the first comparison precondition. The second posterior comparator generates a second posterior comparison signal corresponding to a result of the second comparison.
Embodiments of the present disclosure relate to a memory system, a memory controller, and an operation method of a memory system. According to embodiments of the present disclosure, the memory system, before updating a mapping table which includes mapping information between logical addresses and physical addresses, may assign a portion of a map cache area for caching a plurality of map segments in the mapping table as a map update area for updating the mapping table, and may load a subset of the plurality of map segments to the map update area. Accordingly, it is possible to quickly update a mapping table and to optimize update performance for a mapping table within a limit that guarantees caching performance to a predetermined level or higher.
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mémoire cache dédiée, p.ex. instruction ou pile
A memory device includes: one or more planes each including a plurality of memory blocks; and a control circuit for selectively performing a dummy read operation before a valid read operation on the first memory block, according to whether a read command on the first memory block is firstly received from a host after a program operation is performed on a plane including the first memory block.
G11C 16/28 - Circuits de détection ou de lecture; Circuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p.ex. des cellules factices
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
A data storage device including a memory device and a memory controller is disclosed. The memory controller including a super block includes a parity controller in communication with a memory device including a plurality of pages and configured to generate a first parity using data to be written to a first group of pages among the plurality of pages, and generate a second parity using data to be written to a second group of pages among the plurality of pages, a write operation controller configured to control the memory device to store the first parity and the second parity, and an error correction circuitry coupled to apply the first parity and the second parity to correct at least one of the plurality of pages arranged to belong to the first group of pages and the second group of pages.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G11C 29/44 - Indication ou identification d'erreurs, p.ex. pour la réparation
G11C 29/14 - Mise en œuvre d'une logique de commande, p.ex. décodeurs de mode de test
G11C 29/12 - Dispositions intégrées pour les tests, p.ex. auto-test intégré [BIST]
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
87.
Memory controller for controlling different numbers of memory devices and storage device including the same
A storage device includes first and second memory devices, and a memory controller. The first memory devices correspond to a main data area. The second memory devices correspond to a reserved area. The memory controller is coupled to the first and second memory devices through first and second channels. A number of first memory devices coupled to the memory controller through the first channel is equal to a number of first memory devices coupled to the memory controller through the second channel, and a number of second memory devices coupled to the memory controller through the first channel is different from a number of second memory devices coupled to the memory controller through the second channel. The memory controller selects a memory device on which a write operation is to be performed, based on a memory state of the first and second memory devices.
The controller that controls a memory device includes: a processor suitable for controlling the memory device to perform a first soft read operation by using first soft read voltages; and an error correction code (ECC) codec suitable for performing a first soft decision decoding operation based on first soft read data obtained through the first soft read operation, wherein the processor controls the memory device to perform a second soft read operation with an additional read voltage, of second soft read voltages, that is different than any of the first soft read voltages and which is determined based on the first soft read data, according to whether the first soft decision decoding operation failed, and wherein the ECC codec performs a second soft decision decoding operation based on the first soft read data and second soft read data obtained through the second soft read operation.
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G11C 29/12 - Dispositions intégrées pour les tests, p.ex. auto-test intégré [BIST]
G11C 29/50 - Test marginal, p.ex. test de vitesse, de tension ou de courant
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
89.
Nonvolatile memory device, data storage device including the same and operating method thereof
A nonvolatile memory device may include: a memory cell array operated by a first voltage, and including a plurality of memory cells; a peripheral circuit operated by the first voltage, and configured to store data in the memory cell array or read data from the memory cell array; an operation recorder operated by a second voltage, and configured to record information on an operation being performed in the nonvolatile memory device; and a control logic operated by the first voltage, and configured to control the peripheral circuit such that the nonvolatile memory device performs an operation corresponding to a command received from an external device, and control the operation recorder to store the information on the operation being performed in the nonvolatile memory device.
An error correction circuit includes: a first error correction encoder for generating a plurality of row-codewords by performing first error correction encoding on each of a plurality of messages; a second error correction encoder for generating a plurality of column-codewords; a first error correction decoder for performing first error correction decoding on each of read row-vectors corresponding to the plurality of row-codewords, and outputting a soft information of the first error correction decoding; and a second error correction decoder for determining whether each of m-bit symbols in read column-vectors corresponding to the column-codewords is reliable, based on the soft information corresponding to each of the p-bit symbols, and performing second error correction decoding on the read column-vectors, based on the determination of whether each of the m-bit symbols is reliable.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/39 - Estimation de séquence, c.à d. utilisant des méthodes statistiques pour la reconstitution des codes originaux
H03M 13/45 - Décodage discret, c.à d. utilisant l'information de fiabilité des symboles
H03M 13/21 - Codes non linéaires, p.ex. conversion de mots de données à m bits en mots de code à n bits [mBnB] avec détection ou correction d'erreurs
A data storage device includes a storage including a buffer zone and a data zone and a controller for exchanging data with the storage by allocating at least one zone namespace (ZNS) in the data zone, a ZNS being a data storage region that is physically and logically divided and allocated to each of application programs driven in a host. The controller opens one or more sub buffer zones in the buffer zone, divides write data from the host into one or more segments respectively corresponding to sizes of the one or more sub buffer zones, buffers each of the one or more segments in a corresponding one of the one or more sub buffer zones, opens a ZNS corresponding to a length of the write data in the data zone, and migrates the one or more segments buffered in the sub buffer zones to the opened ZNS.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
92.
Methods, semiconductor devices, and semiconductor systems
A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.
G11C 29/00 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 8/18 - Circuits de synchronisation ou d'horloge; Génération ou gestion de signaux de commande d'adresse, p.ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G11C 29/44 - Indication ou identification d'erreurs, p.ex. pour la réparation
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
A memory system may include a cache memory, a nonvolatile memory, a write back wait queue, and a controller. To evict an eviction cache entry including a target transaction ID from the memory cache to the nonvolatile memory, the controller performs write back operations on cache entries respectively corresponding to waiting entries at a head of the write back wait queue until a waiting entry including the target transaction ID arrives at the head of the write back wait queue, and then performs a write back operation on the eviction cache entry.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
G06F 12/121 - Commande de remplacement utilisant des algorithmes de remplacement
94.
Apparatus and method for controlling input/output throughput of a memory system
A memory system includes a memory device including a plurality of memory units capable of inputting or outputting data individually, and a controller coupled with the plurality of memory units via a plurality of data paths. The controller is configured to perform a correlation operation on two or more read requests among a plurality of read requests input from an external device, so that the plurality of memory units output plural pieces of data corresponding to the plurality of read requests via the plurality of data paths based on an interleaving manner. The controller is configured to determine whether to load map data associated with the plurality of read requests before a count of the plurality of read requests reaches a threshold, to divide the plurality of read request into two groups based on whether to load the map data, and to perform the correlation operation per group.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
G06F 11/07 - Réaction à l'apparition d'un défaut, p.ex. tolérance de certains défauts
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p.ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
G06F 12/0871 - Affectation ou gestion d’espace de mémoire cache
95.
Data processing system, memory controller therefor, and operating method thereof
A data processing system may include a memory module; and a controller configured to exchange data with the memory module in response to a request received from a host. The controller divide a first data into a first data group to error correction and a second data group not to error correction in response to the first data and a first data write request received from the host, generates a first meta data for error correction for the first data group, configures a first data chunk that includes the first data and the first meta data, and transmits the first data chunk to the memory module.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
A memory system includes a memory device, a memory controller configured to control the memory device, and an interface device configured to perform an interfacing operation for transmission of a control signal and data between the memory device and the memory controller. The interface device activates a blocking function for the interfacing operation in response to a configuration command of the memory controller including a blocking activation signal and performs an interface configuration operation in response to an interface configuration command of the memory controller while the blocking function is activated.
Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to program the plurality of memory cells to a plurality of program states, and a control logic configured to control the peripheral circuit so that program operations corresponding to the plurality of program states are performed, wherein the control logic controls the peripheral circuit so that, during a program operation for a target program state, among the plurality of program states, memory cells to be programmed to an immediately higher program state than the target program state are programmed to the target program state.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
An operating method of a low density parity check (LDPC) decoder, the operating method includes: initially updating codewords to variable nodes; determining an update order in which a plurality of variable node groups are updated, which is determined based on reliability of each of the variable node groups; executing local iterations including update of check nodes associated with a select variable node group among the variable node groups and update of the select variable node group based on the updated check nodes until all the variable node groups are updated based on the update order; performing syndrome check to determine whether LDPC decoding is successful, based on an operation of the updated variable nodes and a parity check matrix.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.à d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.à d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
A memory system includes a non-volatile memory device and a controller. The non-volatile memory device includes a plurality of memory regions, each memory region including a plurality of cells commonly coupled to a word line. The controller generates a plurality of candidate data sets based on source data, determines a number of vulnerable cells corresponding to each of the plurality of candidate data sets, and stores a candidate data set having a smallest number of vulnerable cells into a target memory region among the plurality of memory regions.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
100.
Memory system, memory controller, and method for operating memory system for determining read biases for read retry operation
A memory system may perform a first read retry operation using at least one read bias of multiple read biases in a priority read bias group, among a plurality of read biases; and perform, according to a result of the first read retry operation, a second read retry operation using one or more remaining read biases, not in the priority read bias group, in the read retry table. At this time, the read biases in the priority read bias group may be selected prior to the remaining read biases when performing the read retry operation on the target memory area. As a result, the memory system is able to minimize degradation of reading performance due to the read retry operation and reduce the number of unnecessary reads when performing the read retry operation.
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