Aspects of gate voltage level shifting circuits are described. An example power amplifier includes a depletion mode power transistor and a level shift circuit. The level shift circuit is configured to generate a level-shifted gate bias control signal for the depletion mode power transistor based on a gate bias control signal. Among other benefits, the level shift circuit facilitates the replacement of the power transistor in a power amplifier system, particularly in cases where the gate bias control levels generated by the amplifier system are insufficient to completely pinch-off the depletion mode power transistor.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
2.
TRANSISTOR WITH GATE LAYOUT, DEVICE IMPLEMENTING THE TRANSISTOR WITH OUTPUT PRE-MATCHING, AND PROCESS OF IMPLEMENTING THE SAME
A device may include at least one drain pad arranged at a first die side of the transistor die and/or at a second die side of the transistor die, the first die side and the second die side being opposed sides of the transistor die. Also, the device may include drain fingers configured to extend from the at least one drain pad longitudinally toward a central location of the transistor die. Furthermore, the device may include source fingers configured to extend from the at least one drain pad longitudinally toward the central location of the transistor die. In addition, the device may include a gate pad and a gate and the gate is configured to extend along implementations of the drain fingers and/or the source fingers. Moreover, the device may include where the gate pad is arranged on an axis at least semi-orthogonally to an axis of the at least one drain pad.
An architecture for peripheral component interconnect express compliant signals over optical fiber is provided. A method includes, based on a first determination that an impedance level of a receiver device satisfies a defined impedance level, causing a driver to pulse at a first defined frequency and duty cycle level. Further, based on a second determination that a number of pulses received, at a transimpedance amplifier, at the first defined frequency and duty cycle level satisfy a defined number of pulses and at least one defined criterion, the method causes a second impedance level of the driver to match the defined impedance level and causes the driver to enter an electrical idle state. The method also includes facilitating, by a transmitter, transmission of data to the receiver device at a second defined frequency level, via an optical fiber link.
A versatile adaptive voltage scaling control circuit, related apparatus, and related method are provided. A method includes monitoring one or more parameters determined to be associated with performance of a device that is driven by a direct current-to-direct current (DC-DC) converter. The method also includes determining a voltage target based on the one or more parameters and comparing the voltage target to a power supply voltage. Further, the method includes selectively adjusting an output voltage of the DC-DC converter via a feedback loop based on a result of the comparing.
A number of semiconductor die with Group III nitride-based amplifier circuits are described. In one example, the semiconductor die includes a first Group III nitride-based transistor having a first output contact. The semiconductor die includes a second Group III nitride-based transistor having a second output contact. The semiconductor die includes an output combiner inductor on the semiconductor die. The output combiner inductor may be coupled to the first output contact and to the second output contact. The output combiner inductor may further be coupled to a radio frequency (RF) output interface for the semiconductor die.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
6.
GROUP III NITRIDE DOHERTY AMPLIFIER USING DIFFERENT EPITAXIAL STRUCTURES
A Doherty amplifier (10) comprises a main amplifier (18a) and a peaking amplifier (18b). The main amplifier (18a) and the peaking amplifier (18b) are electrically connected to a same input signal source. The main amplifier (18a) and the peaking amplifier (18b) comprise different epitaxial structures of a Group III nitride material. To form the Doherty amplifier (10), the main amplifier (18a) and the peaking amplifier (18b) are formed comprising Group III nitride transistors comprising different epitaxial structures from different epiwafers such that the Group III nitride transistors of the main and peaking amplifiers (18a, 18b) comprise different epitaxial structures. The wafers are diced to produce respective amplifier dies comprising the main amplifier (18a) and peaking amplifier (18b), respectively. The amplifier dies are mounted on a common heat sink, and the main and peaking amplifiers (18a, 18b) are electrically connected to the input signal source.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
7.
PACKAGED DEVICE HAVING AN INTEGRATED PASSIVE DEVICE WITH WAFER LEVEL FORMED CONNECTION TO AT LEAST ONE SEMICONDUCTOR DEVICE AND PROCESSES FOR IMPLEMENTING THE SAME
A device includes at least one integrated passive device having at least one bond pad; at least one semiconductor device having at least one bond pad; and at least one connection structure arranged on the at least one integrated passive device. Additionally, the at least one connection structure includes a solder portion configured to form a solder connection to the at least one bond pad of the at least one semiconductor device.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/16 - Matériaux de remplissage ou pièces auxiliaires dans le conteneur, p. ex. anneaux de centrage
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
8.
BYPASSED GATE TRANSISTORS HAVING IMPROVED STABILITY
A transistor device includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.
H01L 23/482 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
9.
INTEGRATED PASSIVE DEVICES (IPD) HAVING A BASEBAND DAMPING RESISTOR FOR RADIOFREQUENCY POWER DEVICES AND DEVICES AND PROCESSES IMPLEMENTING THE SAME
A transistor device includes a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, and the IPD component having a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, and the second IPD component may include a baseband decoupling capacitor arranged on a thermally conductive dielectric substrate.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
Aspects of the present disclosure describe semiconductor DFB laser structures including both pumped and unpumped regions/sections wherein unpumped regions act as DBR reflector(s) while pumped regions act as DFB gratings. Semiconductor DFB laser devices according to aspects of the present disclosure include an active layer that extends the length of the device that is identical in both pumped and unpumped regions/sections.
Devices and methods including hot via die attach jetting are described. An example integrated circuit device includes a semiconductor substrate, vias extending from a top to a bottom surface of the substrate, and a metal layer on the bottom surface of the substrate. The metal layer includes a metal pad extending around a via opening at the bottom surface of the substrate. The metal pad is electrically isolated from a remainder of the metal layer. The device also includes one or more jet-dispensed dots of a conductive die attach adhesive material on the metal pad. Electrical connections made through the metal pad and jet-dispensed dots may be preferred as compared to wire bonds or flip chip approaches, particularly for RF input and output signals. The use of jet-dispensed dots can facilitate high-volume and automated process techniques.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
12.
ADAPTIVE TEMPERATURE PEAKING CONTROL FOR WIDEBAND AMPLIFIERS
Amplifiers with temperature-adaptive gain and peaking gain control are described. In one example, a temperature-adaptive amplifier includes an amplifier, a temperature sense circuit, and a peaking control level shifter to bias shift the output of the amplifier and adjust a peaking gain of the amplifier based on the temperature control signal. The peaking control level shifter can adjust a peaking gain of the amplifier based on the temperature control signal. The temperature-adaptive control can help to compensate for peaking gain in amplifiers based on the operating temperature of the amplifier. The control can help to compensate for unwanted changes in amplifier peaking gain, over time, resulting in more consistent peaking gain over the full operating frequency range of amplifiers.
H03F 1/30 - Modifications des amplificateurs pour réduire l'influence des variations de la température ou de la tension d'alimentation
13.
SYMMETRICAL COMMON GATE DIRECT CURRENT BIAS NETWORK FOR STACKED FIELD EFFECT TRANSMITTER DISTRIBUTED HIGH-POWER AMPLIFIER, RELATED APPARATUSES AND RELATED METHODS
A symmetrical common gate direct current bias network for stacked field effect transmitter distributed high-power amplifier (400), related apparatus, and related method are provided. An apparatus includes a plurality of amplifier stages (206, 208, 210, 212) connected in parallel between an input port (RF_IN) and an output port (RF OUT). The apparatus can also include a first common gate voltage generator operatively connected at a first side of the plurality of amplifier stages and a second common gate voltage generator operatively connected at a second side of the plurality of amplifier stages (206, 208, 210, 212). The first common gate voltage generator can be operatively connected to the second common gate voltage generator in a symmetrical configuration.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c.-à-d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03F 3/60 - Amplificateurs dans lesquels les réseaux de couplage ont des constantes réparties, p. ex. comportant des résonateurs de guides d'ondes
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
Aspects of the present disclosure describe a voice coil actuated leaf spring prober that advantageously may be operated to probe every individual device (device under test – DUT) comprising a contemporary wafer. The prober according to aspects of the present disclosure includes one or more probe needles attached in an electrically isolated arrangement to an end of a horizontal-U-shaped, recurved, leaf spring arrangement. The prober includes – for example – a voice coil actuator positioned within the horizontal-Ushaped portion of the leaf spring which – when operated – results in leaf spring displacement and probe needle movement such that it may mechanically/electrically contact the DUT.
A transistor amplifier package includes a package substrate comprising conductive patterns exposed by solder mask patterns at a surface thereof, and at least one transistor die comprising a semiconductor structure attached to the surface of the package substrate by a solder material and aligned by the solder mask patterns such that respective gate, drain, and/or source terminals of the at least one transistor die are electrically connected to respective ones of the conductive patterns. Related transistor amplifiers and fabrication methods are also discussed.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H03F 3/189 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
16.
HIGH ELECTRON MOBILITY TRANSISTORS HAVING IMPROVED PASSIVATION STRUCTURES AND REDUCES DRAIN CURRENT DRIFT, AS WELL AS METHODS OF FABRICATING SUCH DEVICES
A high electron mobility transistor comprises a semiconductor layer structure that includes a channel layer (230) and a barrier layer (240) and source (250) and drain (252) contacts on the semiconductor layer structure. A gate contact (254) and a multi-layer passivation structure (262, 264, 266) are provided on the semiconductor layer structure between the gate contact (254) and the drain contact (252). The multi-layer passivation structure comprises at least first (262) and second (264) silicon nitride layers that have different material compositions. A spacer passivation layer (270) is provided at least between the gate contact (254) and the multi-layer passivation structure (262, 264, 266) on sidewalls of the first (262) and second (264) silicon nitride layers. A material composition of the spacer passivation layer (270) is different than a material composition of at least one of the layers of the multi-layer passivation structure (262, 264, 266). For example, the spacer passivation layer (270) may be a silicon nitride layer having a higher silicon content than the layers in the multi-layer passivation structure (262, 264, 266).
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
17.
SEMICONDUCTOR STRUCTURES AND FABRICATION USING SUBLIMATION
Semiconductor structures and methods of fabricating semiconductor structures using sublimation are described. An example method includes forming an opening through a mask layer over a wafer. The wafer includes a substrate, a channel layer over the substrate, a barrier layer over the channel layer, and a cap layer over the barrier layer. The method also includes subliming away a region of the cap layer, within the opening in the mask layer, to form an opening in the cap layer down to a top surface of the barrier layer. The material properties of the cap layer, as compared to the barrier layer, can be relied upon to form the opening in the cap layer down to the top surface of the barrier layer using sublimation, with high selectivity. Sublimation will stop with higher precision and selectivity at the interface between the cap layer and the barrier layer, as compared to etching.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/302 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour changer leurs caractéristiques physiques de surface ou leur forme, p. ex. gravure, polissage, découpage
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
18.
MULTI-STAGE DRIVER CIRCUIT AND METHOD OF DISTRIBUTED DRIVER RESPONSE SHAPING USING PROGRAMMABLE CAPACITORS
A multi-stage driver circuit (116) has a transmission line (119) coupled to an output of the multi-stage driver circuit (116). The transmission line (119) has inductive elements and programmable capacitive elements (130) selected to shape the transmitted data signal. The programmable capacitive elements (130) have a first capacitor with a first terminal coupled to a first power supply conductor, and a first transistor with a first conduction terminal coupled to a second terminal of the first capacitor, and a second conduction terminal coupled to a second power supply conductor. The programmable capacitive elements (130) have a register with a first output coupled to a control terminal of the first transistor. The programmable capacitive elements (130) are selected to shape the transmitted data signal by observing operational dynamics of the multi-stage driver circuit (116).
A distributed driver for an optic signal generator comprising amplifier cells having an amplifier cell input configured to receive the input signal and amplifiers configured to amplify the received signal to create an amplified signal, and an amplifier cell output. The distributed driver also includes an input path connected to the amplifier cell input to receive the input signal and distribute the input signal to the two or more amplifier cells. The input path includes one or more buffers configured to introduce a delay into the input signal. An output path is provided and connects to the amplifier cell outputs of the two or more amplifier cells. The output path is configured to receive the amplified signal and the output path includes one or more inductors that incorporated with the parasitic capacitance from the two or more amplifier cells form the LC segments of an artificial transmission line.
A tracking detector device for use in a free-space optics (FSO) system includes a position sensor and an optical receiver coupled to the bottom surface of the position sensor. The position sensor has an optical aperture configured to allow a portion of incoming light to pass through the position sensor and a plurality of position receivers located adjacent to the optical aperture and configured to sense portions of the incoming light. The tracking detector device may also include a focusing optic disposed adjacent to the bottom surface of the position sensor and configured to focus the portion of the incoming light that passed through the position sensor onto the optical receiver. The tracking detector may advantageously be employed in FSO communications systems and provide fully automated alignment with an incoming light beam under computer control.
G01S 3/781 - Radiogoniomètres pour déterminer la direction d'où proviennent des ondes infrasonores, sonores, ultrasonores ou électromagnétiques ou des émissions de particules sans caractéristiques de direction utilisant des ondes électromagnétiques autres que les ondes radio Détails
H04B 10/11 - Dispositions spécifiques à la transmission en espace libre, c.-à-d. dans l’air ou le vide
21.
MONOLITHIC PIN AND SCHOTTKY DIODE INTEGRATED CIRCUITS
A number of Monolithic Microwave Integrated Circuit (MMIC) devices including combinations of PIN and Schottky diodes, with integrated passive electrical components fabricated and electrically connected among them, are described herein, along with new process techniques for forming the MMIC devices. In one example, a monolithic semiconductor includes a substrate, a plurality of layers of semiconductor materials over the substrate, Schottky and Ohmic contacts on a first subset of the plurality of layers for a Schottky diode, and PIN diode Ohmic contacts on a second subset of the plurality of layers for a PIN diode. The device can also include an etch stop layer between the first subset of the plurality of layers and the second subset of the plurality of layers. The etch stop layer facilitates selective etching and isolation of the Schottky diode from the PIN diode by consecutive etchings.
H01L 21/8252 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie III-V
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
A baseline wander and offset correction system having inputs configured to receive input signals to be transmitted. Also part of the system is a driver circuit configured to receive and amplify the input signals. The driver circuit is configured with one or more transistors having an optional back bias terminal. A replica circuit receives the input signals and responsive thereto, generates back bias signals which are provided to the back bias terminal of the one or more transistors to change the back bias in response to the input signals having consecutive one values or consecutive zero values. This reduces the size of the one or more AC coupling capacitors located between the driver circuit and a channel. An embodiment may store back bias values in a memory. The back bias values are processed by DAC to generate the back bias signals for offset correction.
H04B 1/38 - Émetteurs-récepteurs, c.-à-d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
23.
ACOUSTIC WAVE RESONATOR WITH FRACTAL ACTIVE REGION AND METHOD OF FORMING IT
An acoustic wave resonator has a first conductive layer (210), piezoelectrical material (212) formed over the first conductive layer, and second conductive layer (214) formed over the piezoelectric material. An alignment of the first conductive layer, piezoelectric material and second conductive area defines an active region (226) of the resonator and the active region includes a core area and a plurality of fractals extending from or recessed into the core area. The fractals maximize a perimeter-to-area ratio of the active region of the resonator. The fractals increase electromechanical coupling and a quality factor of the resonator. The fractals can have a star shape, rounded shape, asymmetric shape, or other shape that optimizes the perimeter-to-area ratio of the active region to maximize performance of the resonator. A frame can be disposed over or within the piezoelectric material. The frame is raised above the second conductive layer or recessed below the second conductive layer.
H03H 9/02 - Réseaux comprenant des éléments électromécaniques ou électro-acoustiquesRésonateurs électromécaniques Détails
H03H 9/13 - Moyens d'excitation, p. ex. électrodes, bobines pour réseaux se composant de matériaux piézo-électriques ou électrostrictifs
H03H 9/145 - Moyens d'excitation, p. ex. électrodes, bobines pour réseaux utilisant des ondes acoustiques de surface
H03H 9/17 - Détails de réalisation de résonateurs se composant de matériau piézo-électrique ou électrostrictif ayant un résonateur unique
H03H 3/04 - Appareils ou procédés spécialement adaptés à la fabrication de réseaux d'impédance, de circuits résonnants, de résonateurs pour la fabrication de résonateurs ou de réseaux électromécaniques pour la fabrication de résonateurs ou de réseaux piézo-électriques ou électrostrictifs pour obtenir une fréquence ou un coefficient de température désiré
Microstrip technology boards including microstrip traces matched over a range of different impedances are described. The microstrip boards include impedance-offset openings in ground planes under certain microstrip traces. The openings result in different effective dielectric constants and higher impedances for microstrip traces aligned with the openings, as compared to microstrip traces aligned over metal ground planes. The microstrip boards can also be mounted to conductive heatsinks. The conductive heatsinks act as ground planes for the microstrip traces aligned with the impedance-offset ground plane openings. The conductive heatsinks can include depressions co-located with the ground plane openings. Impedances of microstrip traces aligned with the ground plane openings are thus a function of the dielectric constant of the central core of the boards, the thickness of the central core, and the thickness of the air gap provided by the heatsink depressions.
H03F 1/08 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/189 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence
H03F 3/19 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs
H03F 3/50 - Amplificateurs dans lesquels le signal d'entrée est appliqué — ou le signal de sortie est recueilli — sur une impédance commune aux circuits d'entrée et de sortie de l'élément amplificateur, p. ex. amplificateurs dits "cathodynes"
H03F 1/10 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation d'éléments amplificateurs comportant des connexions d'électrodes multiples
H03F 1/12 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de moyens d'amortissement
H03F 3/193 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
25.
DIAMOND-METAL COMPOSITE HIGH POWER DEVICE PACKAGES
Semiconductor device packages and methods of manufacture are described. In one example, a semiconductor device package includes a flange, a frame secured to a major surface of the flange, with the frame forming an air cavity bounded in part by a surface of the flange, and at least one conductive lead that extends from outside the frame, through a portion of the frame, and is exposed within the air cavity for wire bonding. Other packages without air cavities are also described. The flange can incorporate a composite core material including diamond particles distributed in metal. The flange offers improved thermal conductivity, for greater heat dissipation from and additional performance of semiconductor devices within the packages. The flange exhibits thermal conductivity greater than that of Copper and other materials. The flange also exhibits a coefficient of thermal expansion suitable for bonding semiconductor die including GaN and SiC materials to the flange.
H01L 23/047 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base conductrice qui sert de support et en même temps de connexion électrique pour le corps semi-conducteur les autres connexions étant parallèles à la base
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
26.
TAPERED WAVEGUIDE SEMICONDUCTOR OPTICAL DEVICES WITH INCREASED FACET REFLECTIVITY
A semiconductor optical device (100) includes a first facet (110) bounding a first end of the semiconductor optical device (100). The semiconductor optical device further includes a waveguide (101) having a first end proximate the first facet (110), the first end of the waveguide being tapered towards the first facet (110). The first facet has a curvature to increase modal reflectivity at a first interface at which the first end of the waveguide (101) meets the first facet (110).
G02B 6/122 - Éléments optiques de base, p. ex. voies de guidage de la lumière
G02F 1/00 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire
G02B 6/136 - Circuits optiques intégrés caractérisés par le procédé de fabrication par gravure
H01S 3/00 - Lasers, c.-à-d. dispositifs utilisant l'émission stimulée de rayonnement électromagnétique dans la gamme de l’infrarouge, du visible ou de l’ultraviolet
In various embodiments, the present disclosure includes a system for sending 50 gigabits per second (Gbps), 75 Gbps, and 100 Gbps at 50 gigabaud (GBaud) for passive optical networks (PON) downstream and upstream. The system allows for transmission of three data rates at a single baud-rate while only using 2-bits of information per sample. A motivation for sending three data rates at a single baud-rate is to allow for further granularity in the control of the data-rates for downstream and upstream traffic in a flexible PON system based on the link margin. For example, the system can use non-return-to-zero (NRZ) at 50 GBaud for 50 Gbps and can use four-level pulse-amplitude modulation (PAM-4) at 50 GBaud for 100 Gbps. In addition for 75 Gbps, a double square-8 (DSQ-8) constellation can be used at 50 GBaud.
A semiconductor circuit configured to reduce electromigration. The circuit comprises a power rail and ground rail located on a first layer. A power finger and a ground finger are located on a second layer. Cells are located on the second layer, such that the one or more cells are electrically connected to a power finger and a ground finger. The circuit also includes one or more power vias electrically connecting the power rail to the power finger. The one or more power vias extend from the first layer to the second layer. One or more ground vias electrically connecting the ground rail to the ground finger, such that the one or more ground vias extend from the first layer to the second layer. The placement of the fingers on a different level than the rails establishing the fingers as non-contiguous sections thereby reducing electromigration and overcoming design analysis errors.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
29.
CIRCUIT AND METHOD OF SHUTDOWN FOR BIAS NETWORK IN HIGH VOLTAGE AMPLIFIER
A power amplifier has an amplifier cell (350) with an input terminal (352) receiving an input signal and an output terminal (386) providing an output signal. A bias network (408) is coupled to the output terminal (386) of the amplifier cell to provide a bias signal to the amplifier cell (350). A shutdown circuit (410) is coupled to the bias network to disable the bias network (408) in response to the input signal. The shutdown circuit (410) has a transistor (420, 422) with a first conduction terminal coupled to the bias network (408), a second conduction terminal coupled to a power supply terminal. The shutdown circuit (410) further has a first resistor (412) and a second resistor (414) coupled to the first resistor (412) at a node. The control terminal of the transistor (420, 422) is coupled to the node.
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c.-à-d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03F 1/52 - Circuits pour la protection de ces amplificateurs
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/72 - Amplificateurs commandés, c.-à-d. amplificateurs mis en service ou hors service au moyen d'un signal de commande
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
30.
ATOMIC LAYER DEPOSITION IN ACOUSTIC WAVE RESONATORS
Aspects of acoustic resonators and methods of manufacture of acoustic resonators are described, including acoustic resonators with thinner layers of piezoelectric material. In one example, a method of manufacturing an acoustic resonator includes providing a substrate (41), depositing a layer of piezoelectric material over the substrate (43) by atomic layer deposition, ALD, and forming an electrode (44, 45) in contact with the layer of piezoelectric material. ALD is used to deposit highly uniform and conformal thin films of piezoelectric material and, in some cases, electrodes and encapsulation layers (46). The acoustic resonators described herein are better suited for the demands of new radio frequency (RF) filters, duplexers, transformers, and other components in front-end radio electronics and other applications.
A hybrid diode silicon on insulator front end module and related method are provided. The front end module includes a transmit branch that includes a transmit circuit and a receive branch that includes a receive circuit. The receive circuit includes a low noise amplifier, a pin diode including an anode and a cathode; and a switch. The anode of the pin diode is operatively connected to an antenna switch port and an input voltage source. The cathode of the pin diode is operatively connected to a cathode of the switch. Turning on the switch facilitates a drainage of residual electrical current at the pin diode.
H03F 3/72 - Amplificateurs commandés, c.-à-d. amplificateurs mis en service ou hors service au moyen d'un signal de commande
H03F 3/193 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
H03K 17/76 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p. ex. multiplexeurs, distributeurs
H03K 17/567 - Circuits caractérisés par l'utilisation d'au moins deux types de dispositifs à semi-conducteurs, p. ex. BIMOS, dispositifs composites tels que IGBT
32.
SEMICONDUCTOR DEVICE AND METHOD OF FORMING MONOLITHIC SURGE PROTECTION RESISTOR
A semiconductor device has a substrate and a first semiconductor layer with a high resistivity, such as an epitaxial layer with a resistivity in the range of 3000-5000 ohms/ cm2, formed over the substrate. A second semiconductor layer is formed at least partially in the first semiconductor layer. A capacitor is formed at least partially over the first semiconductor layer. The capacitor has a plurality of trenches extending through the first semiconductor layer and into the substrate, and a first insulating layer formed in the trench. The trenches can be parallel, serpentine, or other geometric shape. The capacitor also has a second insulating layer formed over the first insulating layer, and a polysilicon layer formed over the second insulating layer. A conductive layer is formed over the capacitor. The first semiconductor layer with high resistivity provides a vertical path to discharge high voltage events incident on the capacitor.
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
Aspects of an amplifier with bias stabilization are described. In one example, an amplifier includes an output amplifier stage having an input terminal, a biasing leg having a biasing node coupled to the input terminal, and a bias feedback network coupled between the input terminal of the output amplifier stage and the biasing leg. The bias feedback network can include a difference amplifier, a bypass stage, and a reference voltage generator in one example. The difference amplifier can generate a bias control signal based on a difference between a bias voltage at a base terminal of the output amplifier stage and a voltage reference generated by the reference voltage generator. The bias feedback network generates the bias control signal and controls the bias voltage based on feedback, to keep the bias voltage and bias current constant over process, temperature, gain and other variations for consistent performance.
H03F 3/72 - Amplificateurs commandés, c.-à-d. amplificateurs mis en service ou hors service au moyen d'un signal de commande
H03F 3/16 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs avec dispositifs à effet de champ
H03F 3/18 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs avec dispositifs à semi-conducteurs de types complémentaires
H03F 3/213 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
34.
SEMICONDUCTOR MATERIAL WAFERS OPTIMIZED FOR LINEAR AMPLIFIERS
A number of different types of semiconductor material structures and wafers, including epiwafers, are described herein. The semiconductor material wafers are optimized in certain aspects to form transistor amplifiers for use with new modulation communications systems. A semiconductor material wafer includes a silicon carbide substrate and at least one III-nitride material layer over the silicon carbide substrate. The semiconductor material wafers can include layers consisting of semiconductor materials without dopants such as iron or carbon, formed over the silicon carbide substrate.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
35.
ADJUSTING EYE HEIGHTS AND OPTICAL POWER LEVELS OF A MULTI-LEVEL OPTICAL SIGNAL
A multi-level optical signal is sampled to generate an eye diagram. The signal can be adjusted when eyes in the eye diagram have different heights. More specifically, a first value is determined, and the height of a first eye is adjusted using the first value. The first value is multiplied by a stored factor to produce a second value, and the height of a second eye is adjusted using the second value, and so on for other eyes. As a result, eye heights are the same. Similarly, optical power levels of the signal can be adjusted when the levels are not equally spaced. As a result, the optical power levels are equally spaced.
H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmissionDispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données
A configurable optical driver circuit includes an adjustable current source circuit configurable to drive one of a variety of different types of electrical to optical devices, an adjustable back-termination resistance circuit configurable to provide a back-termination resistance to the one of a variety of different electrical to optical devices, and a programmable memory configured to provide configuration information to the adjustable current source circuit and to the adjustable back- termination resistance circuit to configure the adjustable current source circuit and the adjustable back-termination resistance circuit for operation with the one of a variety of different electrical to optical devices.
122) configured to amplify a received signal to create an amplified signal. The amplifier gain changes over temperature. A gain control circuit adjusts the amplifier gain responsive to a gain control signal. A temperature compensation circuit (108) includes a constant current source (144) that generates a constant current which is used to create a constant voltage, a temperature dependent current source (148) that generates a temperature dependent current which is used to create a temperature dependent voltage, such that the temperature dependent current source (148) has an inverse temperature dependence as compared to the amplifier. An operational amplifier (156) compares the constant voltage to the temperature dependent voltage and generates an offset signal which varies over temperature. A gated buffer (140) is configured to receive the offset signal and selectively modify the gain control signal.
A method and apparatus for adapting an equalizer coefficients to a channel comprising filtering a high frequency error monitor slicer output and a data slicer output to isolate selected high frequency symbol values. Filtering a low frequency error monitor slicer output and the data slicer output to isolate selected low frequency symbol values. Generating a high frequency error monitor slicer threshold signal with a first adaptation module. Generating a low frequency error monitor slicer threshold signal with the first adaptation module or a second adaption module. Combining the high frequency error monitor slicer threshold signal and the low frequency error monitor slicer threshold signal to generate a difference signal. Integrating the difference signal with an accumulator to generate equalizer coefficients to adapt the equalizer to the channel. Providing the high frequency and low frequency error monitor slicer threshold signal to respective slicers.
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
39.
ARRAYED WAVEGUIDE GRATINGS WITH STABILIZED PERFORMANCE UNDER VARYING PARAMETERS
An arrayed waveguide grating device (200) includes an input coupler (202) configured to receive a light signal and split the light signal into a plurality of output light signals. The device also includes a plurality of waveguides (208-1~208-n) optically connected to the input coupler, each waveguide having a plurality of waveguide portions (210-1a~210-1n, 210-a~210-2n) having respective sensitivities to variance in one or more parameters associated with operating of the optical arrayed grating device. Lengths of the respective portions are determined such that each waveguide applies a respective phase shift to the output light signal that propagates through the waveguide and the plurality of waveguides have at least substantially same change in phase shift with respective changes in the one or more parameters associated with operation of the device. An output coupler (204) is optically connected to the plurality of waveguides to map respective light signals output from the plurality of waveguides to respective focal positions.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
40.
3D PRINTING TECHNIQUES FOR FORMING INTERCONNECTS FOR FLIP-CHIP ASSEMBLIES OR TUNING RESONATORS OF A SEMICONDUCTOR DEVICE
In an embodiment, a semiconductor device (100) comprises a three- dimensionally printed flip chip interconnect (102) that includes an electrically conductive ink material that is compatible with a three-dimensional printing technology, the three-dimensionally printed flip chip interconnect (102) being located on a metal surface (chip pad) (104) of a semiconductor chip. The three-dimensional printing technology may be a direct write printing technology, an inkjet printing technology, or an aerosol jet printing technology. The three-dimensionally printed flip chip interconnect (102) may have a cylindrical shape. A distal end (202) of the three-dimensionally printed flip chip interconnect (102) may have a polygon shaped surface. A printing map (700) that defines a location of the chip pad (104) on the semiconductor chip may be generated, wherein the electrically conductive ink material is deposited via the three- dimensional printing technology based on the printing map (700). Example semiconductor devices can include, but are not limited to: a bulk acoustic wave device, a monolithic microwave integrated circuit, an integrated circuit, a passive integrated circuit, a microelectrochemical system, a magnetic material-based circuit, a combination thereof, and/or the like. The chip may further include one or more semiconductor features including, but not limited to: resonators, resistors, capacitors, inductors, a combination thereof, and/or the like. In a further embodiment, a method of processing a semiconductor comprises tuning a resonator (800) of a semiconductor device by depositing an ink material onto a surface of the resonator (800), wherein the depositing is performed via a three-dimensional printing technology. The resonator (800) may comprise an electrode (804) adjacent to a piezoelectric layer (802), wherein the ink material is deposited onto at least one of: the electrode (804) and the piezoelectric layer (802). A printing map (700) that defines a location of the resonator (800) on a semiconductor chip may be generated, wherein the ink material may be deposited via the three-dimensional printing technology based on the printing map (700).
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p. ex. contacts planaires
H03H 3/04 - Appareils ou procédés spécialement adaptés à la fabrication de réseaux d'impédance, de circuits résonnants, de résonateurs pour la fabrication de résonateurs ou de réseaux électromécaniques pour la fabrication de résonateurs ou de réseaux piézo-électriques ou électrostrictifs pour obtenir une fréquence ou un coefficient de température désiré
H03H 3/02 - Appareils ou procédés spécialement adaptés à la fabrication de réseaux d'impédance, de circuits résonnants, de résonateurs pour la fabrication de résonateurs ou de réseaux électromécaniques pour la fabrication de résonateurs ou de réseaux piézo-électriques ou électrostrictifs
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
41.
SEMICONDUCTOR DEVICE WITH SOLDERABLE AND WIRE BONDABLE PART MARKING
A technique for marking semiconductor devices (100) with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark (202) on the terminal (102) as a patterned layer of palladium, which offers good contrast with the base metal of the terminal (102) and maintains the solderability and bondability of the terminal.
A semiconductor device architecture includes a silicon substrate having sidewalls that are passivated by encapsulating the sidewalls in dielectric materials having high electric field strength. Encapsulating all the sidewalls using high field strength dielectric materials eliminates electrical paths in air or vacuum and confines the electric fields in these high field strength materials, increasing the breakdown voltage relative to unencapsulated devices and allowing the device to withstand greater standoff voltages. In some cases, encapsulating the sidewalls in this manner can allow the device to withstand voltages of 500V or greater.
Various aspects of integrated amplifiers, layouts for the integrated amplifiers, and packaged arrangements of the amplifiers are described. In one example, an amplifier includes an amplifier cell, and a biasing network coupled to the common gate transistor in the amplifier cell. The amplifier cell includes a common source transistor and a common gate transistor in a cascode arrangement, where at least one of the common source transistor and the common gate transistor comprises a field plate. Among other advantages, the amplifiers described herein can be biased with relatively high voltages and still operate like a single a common source transistor, without sacrificing reliability, performance, or requiring additional off-chip components, such as biasing networks of resistors and inductors.
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c.-à-d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
Semiconductors lasers are disclosed having an active region having a longitudinal axis, a first facet end, and a second facet end. The second facet end emitting the main output beam of light from of the respective semiconductor laser. The first facet end may have a low- reflection coating. The first facet end may be non-perpendicular to the longitudinal axis of the active region. The semiconductor lasers may be distributed feedback (DFB) lasers having a plurality of diffraction gratings along the longitudinal axis of the active region. The plurality of diffraction grating may include three diffraction gratings. The first diffraction grating may be spaced apart from the third diffraction grating along the longitudinal axis of the active region by a first distance. The second diffraction grating may be spaced apart from the third diffraction grating along the longitudinal axis of the active region by a second distance.
H01S 5/12 - Structure ou forme du résonateur optique le résonateur ayant une structure périodique, p. ex. dans des lasers à rétroaction répartie [lasers DFB]
H01S 5/185 - Lasers à émission de surface [lasers SE], p. ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités horizontales, p. ex. lasers à émission de surface à cavité horizontale [HCSEL]
Systems and methods are provided to align a first optical component carried by a first semiconductor chip with a second optical component carried by a second semiconductor chip. Each of the first semiconductor chip and the second semiconductor chip may include at least one primary semiconductor chip fiducial which assists in the alignment of the first optical component carried by a first semiconductor chip with a second optical component carried by a second semiconductor chip.
A semiconductor laser may include an active region having a longitudinal axis, a rear facet end and a front facet end. The front facet end emitting an output beam of the semiconductor laser. The semiconductor laser may include a plurality of diffraction gratings positioned along the longitudinal axis of the active region. The plurality of diffraction gratings including a first diffraction grating positioned proximate the rear facet end of the active region and at least one additional diffraction grating positioned longitudinally between the first diffraction grating and the front facet. The first diffraction grating having a first kappa value and the at least one additional diffraction grating having at least a second kappa value, the first kappa value being greater than the second kappa value.
A cable equalizer configured as part of a cable comprising a first stage, a second stage, and a third stage. The first stage comprises a first stage bias current circuit configured to generate a bias current and a pre-emphasis module configured to introduce pre-emphasis into a received signal to counter the effects of signal amplification. Also part of the first stage is a bias voltage circuit configured to provide a bias voltage to the first stage. The second stage comprises a buffer configured impedance match the first stage. The third stage comprises a third stage bias current circuit configured to generate a bias current and a tank equalizer circuit configured to perform frequency specific equalization on a second stage signal. An amplifier is configured to amplify the second stage signal to create an amplified signal, which is output from the cable equalizer by an output driver.
Systems and methods for implementing a multimode splitting structure that divides a multimode wide waveguide into multiple narrower waveguides for photodetector connections in an optoelectronic system are disclosed. The optoelectronic system includes an optical filter, a multimode splitter, and a plurality of photodetector. The optical filter is communicatively coupled to a first waveguide to receive an optical signal and configured to demultiplex the optical signal onto a plurality of second waveguides based on different wavelengths. The multimode splitter is adapted to divide each of the plurality of second waveguides into a plurality of third waveguides. Each of the plurality of photodetector is adapted to be connected to each of the plurality of the third waveguide.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/28 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
49.
HIGH SPEED ON DIE SHARED BUS FOR MULTI-CHANNEL COMMUNICATION
A shared bus for inter-channel communication comprising two or more channels having signal processing elements such that each channel is configured to receive and process an incoming channel specific signal. A sequence generator is configured to generate a test sequence suitable for testing the signal processing elements of a channel. An error checker is configured to error check incoming channel specific signals. A shared bus connects to the two or more channels to communicate an incoming channel specific signal to the error checker and communicate the test sequence to the signal processing elements of a channel. One or more pull up resistors and/or termination resistors connect to the shared bus. The bus may comprise a clock signal path and a data signal path. The test sequence may be a pseudo-random bit sequence. The bus interface comprises an open collector current mode logic driver in cascode arrangement.
Active bias circuits for integrated devices are described. In one example, an active bias circuit includes a voltage control element to establish a control voltage, an active bias device to provide a power bias responsive to the control voltage, and a compensation circuit connected to the active bias device. The compensation circuit can be configured to set output impedance and compensate for parasitic capacitance of the active bias device. In another embodiment, the voltage control element can be omitted, and a control voltage can be relied upon to directly control the power bias output provided by the active bias device. The active bias circuit can be used to power a driver of an integrated optical transmitter, in one example, among other possible applications.
Structures for suppressing parasitic acoustic waves in semiconductor structures and integrated circuit devices are described. Such integrated circuit devices can, typically, produce undesirable acoustic wave resonances, and the acoustic waves can degrade the performance of the devices. In that context, some embodiments described herein relate to spoiling a conductive path that participates in the generation of acoustic waves. Some embodiments relate to spoiling acoustic characteristics of an acoustic resonant structure that may be present in the vicinity of the device. Combined embodiments that spoil the conductive path and acoustic characteristics are also possible.
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 31/0328 - Matériaux inorganiques comprenant, à part les matériaux de dopage ou autres impuretés, des matériaux semi-conducteurs couverts par plusieurs des groupes
H01L 31/00 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
Integrated semiconductor devices are described. In one example, an integrated device includes first and second transistors formed on a substrate, where the transistors share a terminal metal feature (220) to reduce a size of the integrated device. The terminal metal feature can include a shared source electrode metalization, for example, although other electrode metalizations can be shared. In other aspects, a first width of a gate of the first transistor can be greater than a second width of a gate of the second transistor, and the shared metalization can taper from the first width to the second width. The integrated device can also include a metal ground plane on a backside of the substrate, and the terminal metal feature can also include an in-source via for the shared source electrode metalization. The in-source via can electrically couple the shared source electrode metalization to the metal ground plane.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/085 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H01L 21/8252 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie III-V
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
53.
IMPROVED LAYOUT TECHNIQUES AND OPTIMIZATION FOR POWER TRANSISTORS
Various embodiments are disclosed for improved and structurally optimized transistors, such as RF power amplifier transistors. A transistor may include a drain metal portion raised from a surface of a substrate, a drain metal having a notched region, a gate manifold body with angled gate tabs extending from the gate manifold, and/or a source-connected shielding. The transistor may include a high-electron-mobility transistor (HEMT), a gallium nitride (GaN)-on-silicon transistor, a GaN-on-silicon-carbide transistor, or other type of transistor.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
54.
CLOSED LOOP LANE SYNCHRONIZATION FOR OPTICAL MODULATION
A system for transmitting signals via serial links includes a plurality of lanes for combining data onto a transmission media, a skew detector configured to detect skew among two of the plurality of lanes, and a variable delay circuit controlled by the skew detector, configured to delay the start of a clock signal to circuitry of one of the plurality of lanes.
A diode semiconductor structure is described. In one example, a diode device includes a substrate, a layer of first semiconductor material of a first doping type, a layer of intrinsic semiconductor material, and a layer of second semiconductor material of a second doping type. The diode device also includes a metal contact formed on the layer of first semiconductor material and a metal via formed from a backside of the substrate, through the substrate, and through the layer of first semiconductor material, where the metal via contacts a bottom surface of the metal contact on the layer of first semiconductor material. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without the need for an additional metal connection, such as a metal air bridge, to the metal contact.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/205 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV comprenant plusieurs composés dans différentes régions semi-conductrices
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
A configurable phased array tile is disclosed including an aperture assembly having a plurality of aperture assembly connectors, a backplane assembly having a plurality of backplane assembly connectors, and a plurality of vertical transmit cards mounted to a corresponding first plurality of aperture assembly connectors and a corresponding first plurality of backplane assembly connectors. The plurality of vertical transmit cards each include a plurality of transmit channels including at least one high power transmit amplifier for powering at least one radiating element mounted to the aperture assembly.
Various integrated circuits formed using gallium nitride and other materials are described. In one example, an integrated circuit includes a first integrated device formed over a first semiconductor structure in a first region of the integrated circuit, a second integrated device formed over a second semiconductor structure in a second region of the integrated circuit, and a passive component formed over a third region of the integrated circuit, between the first region and the second region. The third region comprises an insulating material, which can be glass in some cases. Further, the passive component can be formed over the glass in the third region. The integrated circuit is designed to avoid electromagnetic coupling between the passive component, during operation of the integrated circuit, and interfacial parasitic conductive layers existing in the first and second semiconductor structures, to improve performance.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
H01L 21/8258 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une combinaison de technologies couvertes par les groupes , , ou
58.
OPTICAL MODULATION SKEW ADJUSTMENT SYSTEMS AND METHODS
The present invention facilitates optical modulation skew adjustment. Components of an on chip optical device driver system can cooperatively operate to provide modulated driver signals to drive configuration of optical signals. A serializer is configured to receive parallel data signals and forward corresponding serial data signals. A multiplexing component is configured to selectively output an in-phase component and a quadrature component of the serial data signals, including implementing skew adjustments to aspects of a first output signal and a second output signal. An output stage is configured to output signals that modulate an optical signal, including the first output signal and the second output signal. An on chip skew detector is configured to detect a skew difference between the first output signal and the second output signal. A skew calibration component is configured to direct skew adjustment between the first output signal and the second output signal.
A communication interface comprising a host with non-linear equalizers configured to perform non-linear equalization. Also part of the interface is a host to optic module channel electrically connecting the host to an optic module and the optic module. The optic module comprises a transmitter and a receiver. The transmitter includes a linear equalizer and an electrical to optical module configured to convert the equalized signal from the driver to an optical signal, and transmit the optical signal over a fiber optic cable, such that the transmitter does not perform non-linear processing. The receiver includes a photodetector, configured to convert the received optic signal to a received electrical signal, and a linear amplifier configured to perform linear amplification on the received electrical signal. A driver sends the amplified received signal over an optic module to host channel, such that the receive does not perform non¬ linear processing.
H04B 10/2507 - Dispositions spécifiques à la transmission par fibres pour réduire ou éliminer la distorsion ou la dispersion
H04B 10/58 - Compensation pour sortie d’émetteur non linéaire
H04B 10/2543 - Dispositions spécifiques à la transmission par fibres pour réduire ou éliminer la distorsion ou la dispersion due à des non-linéarités dans les fibres, p. ex. effet Kerr
H04B 10/69 - Dispositions électriques dans le récepteur
Low-load-modulation, broadband power amplifiers and method of use are described. The amplifiers can include multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see low modulation of its load between the fully-on and fully backed-off states of the amplifier. With lower load modulation, the power amplifiers described herein exhibit better power-handling capability and RF fractional bandwidth as compared to conventional amplifiers.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/60 - Amplificateurs dans lesquels les réseaux de couplage ont des constantes réparties, p. ex. comportant des résonateurs de guides d'ondes
H03F 3/213 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
61.
MULTI-TIP WAVEGUIDE COUPLER WITH IMPROVED ALIGNMENT GUIDANCE
Disclosed are various embodiments for a multi-tip laser coupler with improved alignment guidance. A photonic integrated circuit (PIC) includes an input interface, an output interface, and a waveguide array. The waveguide array includes a first waveguide, a second waveguide, and a third waveguide. The first waveguide and the third waveguide are coupled to the input interface and are not coupled to the output interface. The second waveguide is coupled to the input interface and the output interface. Further, the second waveguide is positioned parallel to and between the first waveguide and a third waveguide. The second waveguide includes a tapered body such that an output end of the second waveguide coupled to the output interface is wider than an input end of the second waveguide coupled to the input interface.
An optic reference signal generator comprising a housing forming an enclosed space with one or more air flow openings. Within the housing is an optic signal generator driver configured to generate an optic signal generator drive signal. An optic signal generator generates an optic signal responsive to the optic signal generator drive signal. A polarity control unit adjusts polarization of the optic signal to create a polarization adjusted optic signal and a modulator bias generator and controller generates a modulation signal. A pattern signal input receives a pattern signal and a modulator receives the polarization adjusted optic signal, the pattern signal, and the modulation signal to generate a modulated output signal.
Various aspects provide for a digitally programmable analog duty-cycle correction circuit. For example, a system includes a duty-cycle correction circuit and a duty-cycle distortion detector circuit. The duty-cycle correction circuit adjusts a clock associated with the transmitter. The duty-cycle distortion detector circuit facilitates digital control of a duty-cycle of the clock associated with the duty-cycle correction circuit based on duty-cycle distortion error associated with output of the transmitter.
Efficiency improvements for multi-stage power amplifiers are described. In one example, a power amplifier includes a driver amplifier formed on a first semiconductor die using a first semiconductor fabrication process, an output amplifier formed on a second semiconductor die using a second semiconductor fabrication process, and an inter-stage matching network formed between the driver amplifier and the output amplifier. The first semiconductor fabrication process is a lower voltage process and the second semiconductor fabrication process is a higher voltage process. The use of the two different fabrication processes leads to a number of advantages, including the simplification of the inter-stage matching network, increased radio frequency bandwidth, and improved line-up efficiency among the stages of the power amplifier.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
An improved method and system for locating a slicer threshold and phase is disclosed. A two-dimensional field of coordinates is defined using phase versus eye monitor magnitude. At each coordinate, the number of samples above the eye monitor magnitude are counted. Dividing by the total number of samples considered yields a ratio between 0 and 1. Each eye 0, 1, 2 (bottom, middle, top in a PAM4 system) has an ideal ratio (75%, 50%, 25%) assuming a balanced distribution of PAM4 levels. The rating (third dimension) at each coordinate is calculated to be (0.25 - abs.value (actual_ratio - ideal_ratio)) limited to positive results only. The resulting ratings are summed over phase. The eye center is calculated using weighted average of the sums. The eye center is compared to the calibrated target to determine which way to move the slicer threshold.
H04L 25/06 - Moyens pour rétablir le niveau à courant continuCorrection de distorsion de polarisation
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
H04L 12/26 - Dispositions de surveillance; Dispositions de test
The present disclosure relates to optical phase modulation devices. The optical phase modulation devices may include a heater resistance which induces a phase change and control systems and methods of controlling the induced phase change.
A method and system for reducing power supply noise comprising receiving a primary data stream at a data rate. The primary data stream comprises a stream of bits having logical values of either zero or one. Then, splitting the primary data stream to create a first group of lower rate data streams and a second group of lower rate data streams. Processing the second group of lower rate data streams to invert the logic values of the bits of the lower rate data streams to create processed lower rate data streams. The first group of lower rate data streams are combined with the processed lower rate data streams to create a complementary data stream. Then, processing the primary data stream and the complementary data stream concurrently with a data processing system, the concurrent processing reducing noise on the power supply.
A system for controlling equalization applied to a received signal comprising an equalizer configured to equalize on a received signal to generate an equalized signal, and a clock recovery module configured to recover a clock signal from the equalized signal or the received signal. A clock adjustment system is configured to receive the clock signal, and at least one control signal, to create a sampling clock signal. A filter is configured to filter the equalized signal to create a filtered signal. A sampling unit samples the filtered signal or the equalized signal such that the output of the sampling unit is provided to a controller. The controller is configured to receive and process the output of the sampling unit to generate a boost signal, and the controller is further configured to provide the boost signal to the equalizer to control the amount of equalization performed by the equalizer.
Example polarization splitter and rotator devices are described. In one example, an optical apparatus includes a splitter configured to split a light signal into a first signal having a first polarization and a second signal having a second polarization, a polarization rotator configured to rotate the second polarization of the second signal into a third polarization, and a polarization mode converter configured to convert the third polarization of the second signal into the first polarization. In certain aspects of the embodiments, the splitter can be a curved multi-mode inference (MMI) polarization splitter, and the polarization rotator comprises input and output ports, with the output port being wider than the input port. The polarization mode converter can be an asymmetrical waveguide taper mode converter. The devices described herein can overcome the deficiencies of conventional devices and provide low insertion loss, flat and/or wide wavelength response, high fabrication tolerance, and compact size.
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
G02B 27/28 - Systèmes ou appareils optiques non prévus dans aucun des groupes , pour polariser
A method and apparatus for processing a signal to generate equalizer codes, which are used to control equalization of the signal, that comprises processing the signal to identify the eyes of the signal, and for each eye, calculating an eye height and calculating a noise value. For each eye, squaring the eye height to generate an eye height product and dividing the eye height product by the noise value to generate a Q2value. Using the calculated Q2 values optimizing, through adaptation, the equalizer codes. Calculating the noise values may include calculating an IS I value for each band of the signal and then calculating the eye height for each eye as the difference between the adjacent upper average value and the adjacent lower average value. Then, for each eye, calculating a noise value by summing the IS I value for the band above the eye and the band below the eye.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
H04L 25/06 - Moyens pour rétablir le niveau à courant continuCorrection de distorsion de polarisation
A system for receiving signals transmitted via serial links includes an equalizer for accessing a digitized communications signal and producing an equalized output signal, and a fast equalization module for determining output data corresponding to the communications signal The fast equalization module includes a filter to access an output of the equalizer, a sheer module to access an output, of the filter and produce a data output corresponding to the communications signal, a lookup table to provide filtering coefficients to the filter, and a coefficient, improvement module to improve the coefficients based on an error signal, from the filer. The coefficient improvement module is configured to update the coefficients in. the lookup table.
A number of monolithic multi-throw diode switch structures are described. The monolithic multi-throw diode switches can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a monolithic multi-throw diode switch have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. As one example, for a switch functioning in a dedicated transmit/receive mode, the first transmit PIN diode can have a thicker intrinsic region than the second receive PIN diode to maximize power handling for the transmit arm and maximize receive sensitivity and insertion loss in the receive arm.
A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a diode limiter semiconductor structure have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. The thin intrinsic region PIN diode can be optimized for low level tum on and flat leakage, and the thick intrinsic region PIN diode can be optimized for low capacitance, good isolation, and high incident power levels. This configuration is not limited to two stage solutions, as additional stages can be used for higher incident power handling.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H03G 11/02 - Limitation d'amplitudeLimitation du taux de variation d'amplitude au moyen de diodes
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
A diode structure and a method of fabrication of the diode structure is described. In one example, the diode structure is a PIN diode structure and includes an N-type layer formed on a substrate, an intrinsic layer formed on the N-type layer, and a P-type layer formed on the intrinsic layer. The P-type layer forms an anode of the diode structure, and the anode is formed as a quadrilateral-shaped anode. According to the embodiments, a top surface of the anode can be formed with one or more straight segments, such as a quadrilateral-shaped anode, to reduce at least one of a thermal resistance or an electrical on-resistance. These changes, among others, can improve the overall power handling capability of the PIN diode structure.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/205 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV comprenant plusieurs composés dans différentes régions semi-conductrices
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
75.
GATE METAL FORMATION ON GALLIUM NITRIDE OR ALUMINUM GALLIUM NITRIDE
A method of manufacturing an electrode structure for a device, such as a GaN or AIGaN device is described. In one example, the method includes providing a substrate (212) of GaN or AIGaN with a surface region of the GaN or AIGaN exposed through an opening (216) in a layer of silicon nitride (214) formed on the substrate. The method further includes depositing layers of W (222), in one example, or Ni (220) and W (222), in another example, on the substrate and the layer of silicon nitride using reactive evaporation and photoresist layers (230) having an undercut profile for liftoff. The method further includes removing the photoresist layers having the undercut profile, and depositing layers of WN (224) and Al over the underlying layers of W or Ni and W by sputtering.
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
A monolithic, vertical, planar semiconductor structure with a number diodes having different intrinsic regions is described. The diodes have intrinsic regions of different thicknesses as compared to each other. In one example, the semiconductor structure includes an N-type silicon substrate, an intrinsic layer formed on the N-type silicon substrate, and a dielectric layer formed on the intrinsic layer. A number of openings are formed in the dielectric layer. Multiple anodes are sequentially formed into the intrinsic layer through the openings formed in the dielectric layer. For example, a first P-type region is formed through a first one the openings to a first depth into the intrinsic layer, and a second P-type region is formed through a second one of the openings to a second depth into the intrinsic layer. Additional P-type regions can be formed to other depths.
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
Apparatus and methods for a low-load-modulation power amplifier (500) are described. Low-load-modulation power amplifiers can include multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier (132) in a first amplification class and the remaining amplifiers can operate as peaking amplifiers (538, 539) in a second amplification class. The main amplifier (132) can see low modulation of its load between the power amplifier's fully-on and fully backed-off states. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/42 - Modifications des amplificateurs pour augmenter la bande passante
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/60 - Amplificateurs dans lesquels les réseaux de couplage ont des constantes réparties, p. ex. comportant des résonateurs de guides d'ondes
An adaptive CTLE used in a receiver with its zero and/or pole frequencies automatically and continuously adjustable based on an error signal and post-cursors. The error signal is derived from the sliced equalized signal that is output from the CTLE. A correction control signal can be determined based on one or more delayed and sampled data (corresponding to the post-cursors) and the error signal. As controlled by the correction control signal, the CTLE zero/pole frequency setting is then adapted such that the CTLE transfer function causes the error signal to decrease while the post cursor ISI is reduced or eliminated. As a result, effective equalization can be advantageously accomplished in a consistent and fast manner.
Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.
Extrinsic structure that is formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. Extrinsic structure is described that can reduce gate leakage current in transistors by over four orders of magnitude.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/205 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV comprenant plusieurs composés dans différentes régions semi-conductrices
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
Material structures comprising Ill-nitride material regions (120) (e.g., gallium nitride material regions) are described herein. The material structures also comprise substrates (110) having relatively high electrical conductivities to reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick Ill-nitride material regions and/or relatively small ohmic contacts are employed.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
82.
PARASITIC CAPACITANCE REDUCTION IN GAN-ON-SILICON DEVICES
A method for making a semiconductor structure includes defining one or more device areas and one or more interconnect areas on a silicon substrate, forming trenches in the interconnect areas of the silicon substrate, oxidizing the silicon substrate in the trenches to form silicon dioxide regions, forming a Ill-nitride material layer on the surface of the silicon substrate, forming devices in the device areas of the gallium nitride layer, and forming interconnects in the interconnect areas. The silicon dioxide regions reduce parasitic capacitance between the interconnects and ground.
A coupling system in an integrated circuit to block DC components from an amplifier without large costly external coupling capacitors. An input receives an input signal which has a DC component. A first impedance element receives the input signal and blocks the DC component while a second impedance element connects between the output of the first impedance matching element and a ground node. The second impedance element and the first impedance element form a voltage divider network. The first and second impedance element are integrated elements. The amplifier receives the input signal after the DC component is blocked. The first impedance element and the second impedance element may comprise a resistor in series with a capacitor. In a differential pair configuration, an impedance matching element interconnects between a first path and a second path to impedance match the amplifier to a data source.
A method for establishing the settings in a multichannel optic module that includes connecting the optic module to an optimization module and establishing initial settings in the multichannel optic module for each channel such that the settings include bias voltage, modulation voltage, and crossing voltage. This method then sets the overshoot to a target overshoot value for each channel and adjusting the settings to optimize the eye mask margin and minimize bias voltage. The settings are generated at different temperatures to create and these settings across temperature are stored in a memory of the optic module. The optimization module analyzes an eye diagram created by optic signal from the multichannel optic module and uses PID control determine optimal setting for the multichannel optic module. The target overshoot value may be 20% of voltage amplitude.
H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmissionDispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données
System and method of adapting thresholds for constellation selection based on statistic distributions of received data symbols. An expected ratio of received symbols with values in a certain range is preset based on an expected statistic distribution of data symbols across the multiple constellations. An adapted threshold is then obtained based on the expected ratio. Further, constellation values can be based on statistic distributions of received data symbols. A count ratio of receive symbols falling in a first range to all the symbols in the set is compared with the expected ratio. A first value is repeatedly adjusted to adjust the first range until the count ratio equals the expected ratio. The final fist value is used to determine the optimal adapted constellation.
H03K 5/08 - Mise en forme d'impulsions par limitation, par application d'un seuil, par découpage, c.-à-d. par application combinée d'une limitation et d'un seuil
86.
COMPACT HIGH GAIN AMPLIFIER WITH DC COUPLED STAGES
An amplifier system with high gain, compact size, and extended bandwidth is disclosed. The amplifier system includes one or more inputs configured to receive one or more input signals and a pre-driver configured to receive the one or more input signals. The pre-driver may comprise source connected FETs which create a virtual ground and may include inductors which cancel or counter parasitic capacitance of the FETs. The pre- driver amplifies the one or more input signals to create one or more pre-amplified signals, which are provided to a voltage divider network configured to reduce a DC bias voltage of the one or more pre-amplified signals, while maintaining a wide bandwidth range. An amplifier receives and amplifies the output of the voltage divider network to create amplified signals. The amplifier may comprise mirrored FET pairs in a common source configuration and a common gate arrangement.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/30 - Modifications des amplificateurs pour réduire l'influence des variations de la température ou de la tension d'alimentation
87.
HIGH FREQUENCY DIGITAL-TO-ANALOG CONVERSION BY TIME-INTERLEAVING WITHOUT RETURN-TO-ZERO
Disclosed are various embodiments of a substrate with an embedded copper molybdenum slug or an embedded copper tungsten slug. In one embodiment, among others, a substrate can include a top copper layer and a bottom copper layer. A copper molybdenum slug or a copper tungsten slug is embedded between the top copper layer and the bottom copper layer.
Techniques for providing curved facet semiconductor lasers, are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor laser, comprising a waveguide, wherein the waveguide includes a facet formed at an edge of the semiconductor laser, and the facet has a curvature.
An apparatus includes a drain node, a plurality of source nodes and a gate node. The drain node may be configured to transfer a drain signal along a first axis from a first port to a second port. The source nodes may be (i) distributed along the first axis and (ii) configured to transfer a plurality of source signals along a second axis from the drain node to a ground node. The gate node may be (i) arranged in parallel to the drain node and (ii) configured to control the source signals in response to a gate voltage. The drain node, the source nodes, and the gate node generally form a traveling-wave switch that blocks a slot mode through the source nodes.
H01P 1/15 - Dispositifs commutateurs ou interrupteurs utilisant des dispositifs à semi-conducteurs
H01L 27/085 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
Apparatus and methods for a multiclass, broadband, no-load-modulation power amplifier are described. The power amplifier (500) may include a main amplifier (532) operating in a first amplification class and a plurality of peaking amplifiers (536, 537, 538) operating in a second amplification class. The main amplifier (532) and peaking amplifiers (536, 537, 538) may operate in parallel on portions of signals derived from an input signal to be amplified. The main amplifier (532) may see no modulation of its load impedance between a fully-on state of the power amplifier (all amplifiers amplifying) and a fully backed-off state (peaking amplifiers idle). By avoiding load modulation, the power amplifier (500) can exhibit improved bandwidth and efficiency compared to conventional Doherty amplifiers.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/42 - Modifications des amplificateurs pour augmenter la bande passante
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
H03F 3/60 - Amplificateurs dans lesquels les réseaux de couplage ont des constantes réparties, p. ex. comportant des résonateurs de guides d'ondes
92.
EFFICIENCY IMPROVED DRIVER FOR LASER DIODE IN OPTICAL COMMUNICATION
A circuit and method provide a headroom voltage for a laser driver driving a laser diode such that the laser diode provides signals to an optical communications device. The circuit includes a headroom control circuit receiving the headroom voltage from the laser driver, the headroom control circuit generating a controlled voltage based on the headroom voltage, and a DC-DC converter receiving the controlled voltage from the headroom control circuit generating a voltage Vout based on the controlled voltage, and applying the voltage Vout as an input to the laser diode. The headroom control circuit and the DC-DC converter are connected in a feedback loop with the laser diode to continuously provide the voltage Vout to the laser diode, and the DC-DC converter modifies the voltage Vout to compensate for burn-in characteristics or temperature drift of the laser diode over time to maintain an optimized headroom voltage for the laser driver.
A tunable laser device is described. In one example, the tunable laser device includes an adaptive ring mirror, a gain waveguide, a loop mirror waveguide, and a booster amplifier waveguide. The gain waveguide and the boost amplifier waveguide can be formed in a semiconductor optical amplifier (SOA) region of the tunable laser device, and the adaptive ring mirror and the loop mirror waveguide can be formed in a silicon photonics region of the tunable laser device. The adaptive ring mirror includes a phase shifter optically coupled between a number of MMI couplers. By inducing a phase shift using the phase shifter, the wavelength of the output of the tunable laser device can be altered or adjusted for use in coherent fiber-optic communications, for example, among other applications.
H01S 3/105 - Commande de l'intensité, de la fréquence, de la phase, de la polarisation ou de la direction du rayonnement, p. ex. commutation, ouverture de porte, modulation ou démodulation par commande de la position relative ou des propriétés réfléchissantes des réflecteurs de la cavité
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
H01S 5/02 - Détails ou composants structurels non essentiels au fonctionnement laser
H01S 5/026 - Composants intégrés monolithiques, p. ex. guides d'ondes, photodétecteurs de surveillance ou dispositifs d'attaque
H01S 5/06 - Dispositions pour commander les paramètres de sortie du laser, p. ex. en agissant sur le milieu actif
H01S 5/10 - Structure ou forme du résonateur optique
Thermally-sensitive structure and methods for sensing the temperature in a region of a bipolar junction transistor (BJT) during device operation are described. The region may be at or near a region of highest temperature attained in the BJT. Metal resistance thermometry (MRT) can be implemented to assess a peak operating temperature of a BJT.
G01K 7/16 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments résistifs
G01K 1/14 - SupportsDispositifs de fixationDispositions pour le montage de thermomètres en des endroits particuliers
Apparatus and methods for a no-load-modulation power amplifier are described. No-load-modulation power amplifiers can comprise multiple amplifiers connected in parallel to amplify a signal that has been divided into parallel circuit branches. One of the amplifiers can operate as a main amplifier in a first amplification class and the remaining amplifiers can operate as peaking amplifiers in a second amplification class. The main amplifier can see essentially no modulation of its load between the power amplifier's fully-on and fully backed-off states. The power amplifiers can operate in symmetric and asymmetric modes. Improvements in bandwidth and drain efficiency over conventional Doherty amplifiers are obtained. Further improvements can be obtained by combining signals from the amplifiers with hybrid couplers.
H03F 1/08 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs
H03F 1/42 - Modifications des amplificateurs pour augmenter la bande passante
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
96.
TECHNIQUES FOR HIGH SPEED OPTOELECTRONIC COUPLING BY REDIRECTION OF OPTICAL PATH
Techniques for high speed optoelectronic coupling by redirection of optical path are disclosed. In one particular embodiment, the techniques may be realized as an optoelectronic receiver comprising an optical signal demultiplexer that may be configured to transmit an optical signal along a first axis, and a photodiode that may be configured to convert the optical signal into an electrical signal, wherein the optical signal demultiplexer may include an inclined end surface that may be configured to reflect the optical signal towards a photoactive area of the photodiode at an obtuse angle of reflection with respect to the first axis.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/28 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
G02B 6/43 - Dispositions comprenant une série d'éléments opto-électroniques et d'interconnexions optiques associées
Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.
G01K 7/18 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments résistifs l'élément étant une résistance linéaire, p. ex. un thermomètre à résistance de platine
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
98.
ATHERMAL SILICON PHOTONICS WAVELENGTH LOCKER AND METER
A wavelength locker includes first and second waveguides to guide light. The wavelength locker also includes a multimode interference (MMI) coupler having a number of inputs and outputs. First and second inputs of the MMI coupler are coupled to outputs of the first and second waveguides. The MMI coupler merges light from the first and second waveguides to generate an interference pattern of light. The MMI coupler then outputs a plurality of phase shifted versions of the interference pattern. The wavelength locker also includes an interference pattern selector configured to receive signals corresponding, respectively, to light output from the outputs of the MMI coupler. The interference pattern selector is also configured to select one or more outputs of the MMI coupler based on power levels of the interference patterns output from the MMI coupler and a predetermined frequency of a telecommunications frequency grid.
H04J 14/02 - Systèmes multiplex à division de longueur d'onde
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/28 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux
H01S 5/0687 - Stabilisation de la fréquence du laser
99.
REDUCTION OF WAFER BOW DURING GROWTH OF EPITAXIAL FILMS
Structures and methods for reducing wafer bow during heteroepitaxial growth are described. Micro-trenches may be formed across a surface of a substrate and filled with polycrystalline material. Stress-relieving regions of material can be grown over the polycrystalline material in a layer of semiconductor material during heteroepitaxy.
System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. Upon a good Signal-to-Noise Ratio (SNR) being achieved, a selected set of the tap weights of the equalizer filter are frozen or set to smaller values, while others continue to adapt and the timing recovery loop continues the clock recovery process. Thereby, the adaptation of equalization can be adjusted to attenuate the equalization filter's effect on clock delay correction by limiting the adaptation time or speed relative to those of the entire timing recovery loop.
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