A NAND device comprises a memory array, the memory array including a plurality of blocks of NAND cells and circuitry to perform a touchup program on a portion of programmed NAND cells in a block of NAND cells after all word lines in the block have been programmed. The gap width in a threshold voltage (Vt) distribution for a 3D NAND Flash cell is improved by performing touchup program on a selected portion of the word lines in a block after all of the word lines in the block have been programmed.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
Vertical wordline driver structures and methods. The vertical wordline driver comprises a transistor that is used to drive a wordline in a three-dimensional 3D memory structure. A vertical transistor structure is formed in a semiconductor substrate comprising a gate all around (GAA) structure or a double-gate structure including a gate oxide, an amorphous IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide, and a liner adjacent to the amorphous IGZO channel. The GAA structure may comprise a conical frustrum shape or a cylindrical shape with straight walls. The double-gate structure may have straight or angled walls. An outer wall of the gate oxide is in contact with a polysilicon gate layer. An upper and lower contact is electrically coupled to the amorphous IGZO channel.
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p.ex. NON-ET
G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
3.
EARLY READ OPERATION FOR STORAGE DEVICES WITH INDEPENDENT PLANES AND PLANE GROUPS
A storage device includes a storage array with multiple planes organized as plane groups, where the planes of a plane group receive and process commands in parallel. The storage device includes a storage controller that receives a command from a host controller. In response to receipt of the command the storage controller provides ready information for all planes to the host controller. The multiple planes can optionally have independent multiplane read operation (IMPRO). Each plane group can have a first plane and a second plane, and the storage controller can optionally read data from the first plane of a plane group in response to a virtual ready signal for the first plane, before the second plane of the plane group is ready.
The size of page map memory in a NAND flash device used to store page related information is decreased by embedding page type in a row address. The row address is received by the NAND flash device from the host on the data bus in a six-cycle sequence. The received row address is used to decode a physical page address received during the row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array. A same block segment number is used for each page type in the block segment.
Systems, apparatuses, and methods may provide for technology that simultaneously forms staircase areas and CMOS (complementary metal-oxide-semiconductor) contact areas in three‐dimensional (3D) NAND memory. A 3D NAND memory includes a first CMOS contact area and a first staircase area. The first CMOS contact area is formed through a plurality of sequential chops. The first staircase area is formed through a plurality of sequential staircase chops. The first CMOS contact area is formed through the plurality of sequential chops being performed simultaneous to the plurality of sequential staircase chops.
H01L 27/24 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants à l'état solide pour le redressement, l'amplification ou la commutation, sans barrière de potentiel ni barrière de surface
Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller determines that the program operation can be initiated without loading all pages into the memory. In response, the NAND loads a first page and then executes portions of the program operation in parallel, at least in part, with loading subsequent pages. The NAND behavior is modified to monitor data loading completion times, to copy pages from a cache register to a data register as needed, and to resume program operation if a shutdown occurs. The portions of the program operation include a program prologue operation and a pulse verify loop for the first voltage level (LI) of the MLC memory.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
7.
METHOD AND APPARATUS TO SELECT A PLANE IN A NAND FLASH DIE TO STORE A READ-ONLY RESERVED BLOCK
Manufacturing yield loss of NAND Flash dies is reduced by selecting a plane to store a read-only reserved block and another plane to store a backup read-only reserved block based on the Number of Valid Blocks (NVB) blocks in each plane in the NAND Flash array.
brevets
