A hydrogen detection device (10) comprises a first resistance element (hydrogen sensor (100)), a second resistance element (reference element (100a)), a third resistance element (reference element (100b)), and a fourth resistance element (reference element (100c)) that constitute a bridge circuit. Each of the first to fourth resistance elements is formed on one semiconductor substrate (102), and has: a first electrode (103) and a second electrode (106), the principal surfaces of which are disposed mutually opposing; a metal oxide layer (104) disposed in contact with the principal surface of the first electrode (103) and the principal surface of the second electrode (106); and an insulating film (107b), or the like, covering the second electrode (106). On at least the first resistance element among the first to fourth resistance elements, the insulating film (107b), or the like, is formed with an opening (110) that exposes another surface that opposes the principal surface of the second electrode (106) without being covered by the insulating film (107b) or the like.
G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
An optical sensor package (10) comprises a substrate (20), an optical sensor device (30) mounted on the substrate (20), a resin frame (40) provided on the substrate (20) so as to surround the outer periphery of the optical sensor device (30), and a transparent plate (70) provided on the resin frame (40) so as to cover the optical sensor device (30) via a space. A plurality of recessed regions (50) are provided in a frame top surface (41) of the resin frame (40). When viewed from a direction perpendicular to the substrate (20), the transparent plate (70) is disposed such that the outer side (73) of the transparent plate (70) is positioned inside the outer side (43) of the resin frame (40), and the maximum distance (D1) between the outer side (73) of the transparent plate (70) and the outer side (43) of the resin frame (40), which are adjacent to each other, is equal to or less than the maximum length (L1) of the recessed regions (50).
A ranging device (100) comprises: a light source (10) that emits light in a prescribed range; a light reception unit (20) that has a plurality of pixels for receiving reflected light resulting from the emitted light being reflected within the prescribed range; an image recognition unit (30) that acquires an image in which at least a portion of the prescribed range appears, and that detects a preset recognition target object (OBJ) by subjecting the acquired image to image recognition; a drive control unit (40) that, if the recognition target object (OBJ) is detected by the image recognition unit (30), adjusts an emission condition of the emitted light to be emitted by the light source (10), on the basis of first outputs that are respectively output by one or more pixels corresponding to a region of the recognition target object (OBJ) on the basis of the reflected light of the emitted light emitted under a prescribed emission condition; and a distance calculation unit (50) that calculates the distance to the recognition target object (OBJ) on the basis of second outputs that are respectively output by the plurality of pixels on the basis of the reflected light of the emitted light emitted under the adjusted emission condition.
A semiconductor device (1) includes a vertical MOS transistor (10) having a semiconductor substrate (32) of a first conductivity type containing an impurity of a first concentration, and a low-concentration impurity layer (33) of the first conductivity type formed in contact with the semiconductor substrate (32) and containing an impurity of a second concentration lower than the first concentration. In a plan view, an active region (112) of the vertical MOS transistor (10) is formed of unit cells repeatedly arranged in the plane of the active region (112). The unit cell has a hexagonal shape with the outer periphery at the center position of the width of a gate trench (17). In the unit cell, a body contact region (18a) is exposed on the upper surface of the low-concentration impurity layer (33) in a shape of which the center coincides with the center of the unit cell and that has a rotational symmetry of 60[°] or less in the clockwise direction. When the width of the gate trench (17) is Lxr [μm] and the distance between gate trenches (17) facing each other in parallel is Lxm [μm], the relationship Lxm/3 ≤ Lxr ≤ Lxm is satisfied.
A DC-DC converter (1) for controlling DC output power by controlling the on and off of a high-side switch (11) is provided with a control unit (2) for adjusting the off-time of the high-side switch (11) in order to control output power. The control unit (2) makes the on-time of the high-side switch (11) inversely proportional to an input output voltage difference (Ei-Eo) which is the difference between an input voltage (E1) to the DC-DC converter (1) and an output voltage (Eo) from the DC-DC converter (1).
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
A DC-DC converter (100) includes a high-side switch (11), a low-side switch (12), an inductor (3), an output capacitor (4), and a control unit (2). The control unit (2) comprises: a pre-charge circuit (21) that charges the output capacitor (4); a negative current detection circuit (25) that outputs a negative current detection signal indicating that a current flowing from the inductor (3) to the low-side switch (12) has reached a predetermined value; and a control circuit (26) that performs a switching operation that turns on the high-side switch (11) and the low-side switch (12) alternately. The control circuit (26) starts the switching operation by turning on the low-side switch (12), and turns off the low-side switch (12) after receiving the negative current detection signal.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
7.
BATTERY MONITORING DEVICE AND BATTERY MONITORING METHOD
A battery monitoring device (201) comprises a signal generating unit that generates a control signal for controlling a first measuring circuit (1z) to which a first battery assembly (1) obtained by dividing a plurality of batteries connected in series is connected, and a second measuring circuit (2z) to which a second battery assembly (2) obtained by dividing the plurality of batteries is connected, and an impedance calculating unit (15) that calculates the AC impedance of each of the plurality of batteries on the basis of a measured current value flowing through the first measuring circuit (1z) and the voltage value of each battery included in the first battery assembly (1), and a measured current value flowing through the second measuring circuit (2z) and the voltage value of each battery included in the second battery assembly (2), wherein: the first measuring circuit (1z) includes a first switch; the second measuring circuit (2z) includes a second switch; and the signal generating unit generates a control signal for exclusively turning on the first switch and the second switch.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/382 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge
G01R 31/385 - Dispositions pour mesurer des variables des batteries ou des accumulateurs
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H02J 7/04 - Régulation du courant ou de la tension de charge
H02J 7/10 - Régulation du courant ou de la tension de charge utilisant des tubes à décharge ou des dispositifs à semi-conducteurs utilisant uniquement des dispositifs à semi-conducteurs
A voltage measuring circuit (23) comprises a first switched capacitor filter (9) connected to a first battery cell (C2) constituting a battery pack (50), a second switched capacitor filter (10) connected to a second battery cell (C3) constituting the battery pack (50), and a first amplifier (19) shared by the first switched capacitor filter (9) and the second switched capacitor filter (10), wherein: the first switched capacitor filter (9) includes a first switch group (3), a first capacitance (5), and a third switch group (4); the second switched capacitor filter (10) includes a second switch group (6), a second capacitance (8), and a fourth switch group (7); and the first switch group (3) and the second switch group (6) are electrically insulated from the third switch group (4) and the fourth switch group (7) by means of the first capacitance (5) and the second capacitance (8), respectively.
G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
G01R 31/396 - Acquisition ou traitement de données pour le test ou la surveillance d’éléments particuliers ou de groupes particuliers d’éléments dans une batterie
H02J 7/02 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries pour la charge des batteries par réseaux à courant alternatif au moyen de convertisseurs
9.
BATTERY MONITORING DEVICE AND BATTERY MONITORING METHOD
This battery monitoring device (1) comprises: a storage unit (24) in which relationship data is stored, the relationship data indicating the relationship between the battery state of a secondary battery (5) and a resistance component, which changes depending on the battery state of the secondary battery (5), among a plurality of resistance components that constitute the impedance of the secondary battery (5); an impedance acquisition unit (23a) that acquires the impedance of the secondary battery (5) being monitored; and an arithmetic processing unit (23) that, on the basis of the impedance acquired by the impedance acquisition unit (23a), calculates the value of a resistance component that changes depending on the battery state of the secondary battery (5) being monitored, and estimates the battery state of the secondary battery (5) being monitored on the basis of the value of the resistance component and the relationship data.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/382 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge
G01R 31/385 - Dispositions pour mesurer des variables des batteries ou des accumulateurs
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
10.
BATTERY MONITORING DEVICE AND BATTERY MONITORING METHOD
A battery monitoring device (1D) is provided with: a first temperature acquisition unit (109) that acquires a first temperature (T1), which is the external temperature of a battery pack (101) having a plurality of secondary batteries (Bt); a second temperature acquisition unit (111) that acquires a second temperature (T2), which is an internal temperature of the secondary battery (Bt); a third temperature acquisition unit (112) that acquires a third temperature (T3) including temperature distribution information on the battery pack (101); and a determination unit (113) that compares the first temperature (T1), the second temperature (T2), and the third temperature (T3), and determines whether there is an abnormality in the first temperature (T1), the second temperature (T2), or the third temperature (T3).
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/382 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge
G01R 31/385 - Dispositions pour mesurer des variables des batteries ou des accumulateurs
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
This semiconductor device (1) comprises a semiconductor layer (40) and a first vertical MOS transistor (10) and a second vertical MOS transistor (20) formed on the semiconductor layer (40). In plan view of the semiconductor layer (40), the full length of one side among the outer peripheral sides of a first gate electrode region (G1) and the full length of one side among the outer peripheral sides of a first resistance element region (R1) match a portion of a side which is orthogonal to a boundary line (90) and from which the distance to a first gate pad (119) is the shortest, among the outer peripheral sides of the semiconductor layer (40). In plan view of the semiconductor layer (40), the outer peripheral sides of the first resistance element region (R1) include only one corner among the four corners on the outer periphery of the first gate electrode region (G1), the only one corner being the corner where the distance to the boundary line (90) is the shortest and the distance to the side orthogonal to the boundary line (90) among the outer peripheral sides of the semiconductor layer (40) is the shortest.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
A memory system (100a) comprises: a memory controller (130); and an external memory (140) connected to the memory controller (130). The memory controller (130) transmits, to the external memory (140), a read command or a write command, a data size, an address interval that is an interval between addresses of continuous pieces of data of said data size, and a head address. The external memory (140) performs reading or writing for accessing the data on the basis of the data size, the address interval, and the head address so that the access conforms to the read command or the write command.
A semiconductor integrated circuit (10) for scrambling and transferring data to a transfer destination circuit (90) comprises: a scrambler (50) that generates a scramble key for causing Hamming weight to be B/2, where B denotes the bus width of the data and if B is an even number, generates a scramble key for causing Hamming weight to be (B +1)/2 or (B-1)/2 if B is an odd number, and scrambles the data by using the scramble key; and a transfer control unit (20) that transfers scramble data, which is the scrambled data, to the transfer destination circuit (90).
A nitride-based semiconductor light-emitting element (100) is provided with a semiconductor laminate (100S) and a P-side electrode (113). The semiconductor laminate (100S) has: an N-type first cladding layer (102); an N-side guide layer (104) disposed above the N-type first cladding layer (102); an active layer (105) disposed above the N-side guide layer (104) and having a quantum well structure; a P-side first guide layer (106) disposed above the active layer (105); a P-side second guide layer (107) disposed above the P-side first guide layer (106); and a P-type cladding layer (110) disposed above the P-side second guide layer (107). The band gap energy of the P-side second guide layer (107) is greater than the band gap energy of the N-side guide layer (104), the band gap energy of the N-side guide layer (104) is greater than or equal to the band gap energy of the P-side first guide layer (106), and the P-side electrode (113) includes Ag.
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
The present invention comprises: an n-type cladding layer (402); at least one n-side guide layer disposed above the n-type cladding layer (402); an active layer (405) disposed above the at least one n-side guide layer; a p-side semiconductor layer (400p) disposed above the active layer (405); and a p-side electrode (113) disposed above the p-side semiconductor layer (400p) and in ohmic contact with the p-side semiconductor layer (400p), wherein the active layer (405) has at least one well layer, a second distance between the p-side electrode (113) and a well layer (405b), which is closest to the p-side electrode (113) among the at least one well layer, is smaller than a first distance between the n-type cladding layer (402) and a well layer (405b), which is closest to the n-type cladding layer (402) among the at least one well layer, and the p-side electrode (113) includes at least one among Ag, Al, and Rh.
A wireless communication device (110) comprises: a medium access control (MAC) unit having the function of a media link layer; a physical layer (PHY) unit having the function of a physical layer; and an error correction circuit (ECC) unit that executes processing related to error correction on a passing signal. The ECC unit is connected between the MAC unit and the PHY unit.
A wireless communication device (110) comprises: a first wireless communication subsystem (111) having a first wireless communication circuit; a second wireless communication subsystem (112) having a second wireless communication circuit; and a control system (113) for controlling the first wireless communication subsystem (111) and the second wireless communication subsystem (112). The first wireless communication subsystem (111), the second wireless communication subsystem (112), and the control system (113) are configured in one semiconductor device.
H04W 12/106 - Intégrité des paquets ou des messages
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H04W 4/00 - Services spécialement adaptés aux réseaux de télécommunications sans filLeurs installations
H04W 4/48 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p. ex. communication véhicule-piétons pour la communication dans le véhicule
A wireless communication device (110) comprises a first wireless communication subsystem (111) having a first wireless communication circuit, a second wireless communication subsystem (112) having a second wireless communication circuit, and a control system (113) for controlling the first wireless communication subsystem (111) and the second wireless communication subsystem (112). The first wireless communication subsystem (111) communicates using a first frequency, the second wireless communication subsystem (112) communicates using a second frequency, and the control system (113) controls the first frequency and the second frequency.
H04W 4/00 - Services spécialement adaptés aux réseaux de télécommunications sans filLeurs installations
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H04W 4/48 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p. ex. communication véhicule-piétons pour la communication dans le véhicule
A nitride semiconductor device (1) comprises an active element (10) and a passive element (20), wherein the nitride semiconductor device comprises: a nitride semiconductor layer (120) that is divided into an active region (101) and an inactive region (102) in plan view; and a metal layer (150) that is in contact with the nitride semiconductor layer (120) in the inactive region (102). The active element (10) is provided in the active region (101), and the passive element (20) is provided in the inactive region (102). The metal layer (150) may be in a coherent state or a metamorphic state with respect to the nitride semiconductor layer (120).
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
A control system (100) comprises each of a plurality of sensors (1) in a detection system that detects an object by means of the plurality of sensors (1). The control system (100) comprises: a counter (104); a first acquisition unit (101); a second acquisition unit (102); and a processing unit (103). The counter (104) outputs an operation signal for causing a corresponding sensor (1) to operate in accordance with a counter value. The first acquisition unit (101) acquires time information shared by each of the plurality of sensors (1). The second acquisition unit (102) acquires the counter value of the counter (104) at the point in time at which the first acquisition unit (101) acquires the time information. On the basis of the time information acquired by the first acquisition unit (101) and the counter value acquired by the second acquisition unit (102), the processing unit (103) executes adjustment processing for adjusting the timing at which the operation signal is output.
A semiconductor device (1) comprises: a semiconductor layer (40) that has a semiconductor substrate (32) on the rear surface side and is divided into three regions of a first region (A1), a second region (A2), and a third region (A3) that do not overlap one another in plan view of the semiconductor device (1); a first vertical MOS transistor (10) that is formed in the first region (A1) of the semiconductor layer (40); a second vertical MOS transistor (20) that is formed in the second region (A2) of the semiconductor layer (40); and a drain pad (151) that is connected to the semiconductor substrate (32) at a position included in the third region (A3) in plan view of the semiconductor device (1). Moreover, in plan view of the semiconductor device (1), the third region (A3) is sandwiched between the first region (A1) and the second region (A2), and the surface area of the first region (A1) is greater than the surface area of the second region (A2) in plan view of the semiconductor device (1).
A semiconductor device (1) comprises: a semiconductor layer (40) that is divided into three regions, namely a first region (A1), a second region (A2), and a third region (A3) that do not overlap each other in a plan view; a first vertical MOS transistor (10) that is formed in the first region (A1); a second vertical MOS transistor (20) that is formed in the second region (A2); and a third vertical MOS transistor (30) that is formed in the third region (A3), wherein a first gate wiring (118) of the first vertical MOS transistor (10) and a third gate wiring (138) of the third vertical MOS transistor (30) are electrically connected in series via a first diode (113) having this order as the forward direction, and a second gate wiring (128) of the second vertical MOS transistor (20) and the third gate wiring (138) are electrically connected in series via a second diode (123) having this order as the forward direction.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
A semiconductor light-emitting element (1) is provided with: a laminated structure (2) that has a first end surface (2F) and a second end surface (2R) that face each other to constitute a resonator, and that includes a nitride semiconductor; and a protective film (3) that is disposed on the first end surface (2F). The protective film (3) includes a first protective film (31a). The first protective film (31a) is an oxide film or an oxynitride film of aluminum to which scandium is added.
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
24.
VIDEO SIGNAL PROCESSING DEVICE AND VIDEO SIGNAL PROCESSING METHOD
A video signal processing device (100) addresses failure of wiring (101) for transmitting video signals, the video signal processing device (100) comprising: a signal collection circuit (103) that collects signals transmitted by the wiring (101); a failure diagnosis circuit (104) that creates failure diagnosis information relating to failure of the wiring (101) from the signals collected by the signal collection circuit (103); a switch control circuit (105) that generates, from the failure diagnosis information, switch information for shifting upper bits constituting the video signals to lower bits or for bypassing the upper bits; and a transmission-side switch circuit (106) that is disposed prior to the wiring (101) and switches the path of the bits constituting the video signals in accordance with the switch information.
x11-x1y11-y1x21-x2y21-y2x31-x3y31-y31-y3P (0 ≤ x3 ≤ 1, 0 ≤ y3 ≤ 1). The average band gap energy of each of the first hole barrier layer (41a) and the second hole barrier layer (41b) is greater than the average band gap energy of the first intermediate layer (42a).
H01S 5/323 - Structure ou forme de la région activeMatériaux pour la région active comprenant des jonctions PN, p. ex. hétérostructures ou doubles hétérostructures dans des composés AIIIBV, p. ex. laser AlGaAs
H01L 33/06 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure à effet quantique ou un superréseau, p.ex. jonction tunnel au sein de la région électroluminescente, p.ex. structure de confinement quantique ou barrière tunnel
H01L 33/14 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure contrôlant le transport des charges, p.ex. couche semi-conductrice fortement dopée ou structure bloquant le courant
H01L 33/30 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
26.
NOISE DETECTION DEVICE, NOISE SUPPRESSION DEVICE, NOISE DETECTION METHOD, AND PROGRAM
A noise detection device (100) comprises: a DFT execution unit (10) that executes DFT on an input signal and outputs a conversion result; a carrier wave detection unit (20) that detects a carrier frequency bin in the conversion result; a frequency correction unit (30) that performs correction to reduce any difference between the center frequency of the carrier frequency bin and the frequency of the carrier wave; a phase calculation unit (40) that calculates the phase of each signal component in the post-correction conversion result; a phase inversion unit (50) that inverts the phase of each signal component with reference to the center frequency of the carrier frequency bin in the post-correction conversion result; and an asymmetric component detection unit (60) that detects, as noise, a signal component for which the phase is asymmetric with respect to the carrier frequency bin in the post-correction conversion result, on the basis of the phase before the inversion and the phase after the inversion of each signal component.
H04L 27/02 - Systèmes à courant porteur à modulation d'amplitude, p. ex. utilisant la manipulation par tout ou rienModulation à bande latérale unique ou à bande résiduelle
H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
A semiconductor device (1) includes a vertical MOS transistor (10) having: a plurality of first trenches (17) which are formed so as to pass through a body region (18) from the upper surface of a low-concentration impurity layer (33), and which extend in a first direction; and a plurality of second trenches (27) which are formed so as to pass through the body region (18) from the upper surface of the low-concentration impurity layer (33) and so as to be deeper than the plurality of first trenches (17), and which extend in the first direction. The plurality of first trenches (17) and the plurality of second trenches (27) are alternately disposed in a second direction. A first conductor (15) connected to a gate electrode (19) is formed on the inside of the plurality of first trenches (17) and on the upper side inside the plurality of second trenches (27). A second conductor (25) connected to a source electrode (11) is formed on the lower side inside the plurality of second trenches (27). The interval between the second conductors (25) is twice the interval of the first conductors (15) in the second direction.
This sensor package is provided with: a chip (30) having a surface (31) on which an exposed portion (106e) of a sensor part (100) is provided; a substrate (20) having a surface (21) on which the chip (30) is mounted; and a mold resin part (60) formed so as to cover the surface (31) of the chip (30) excluding the exposed portion (106e) and the surface (21) of the substrate (20). The mold resin part (60) has an opening hole (62) positioned over the exposed portion (106e). The chip (30) has a flat portion (37, 37a, or 47) positioned outside the exposed portion (106e) on the surface (31) of the chip (30). An edge (62e) of the opening hole (62) on the surface (31) side of the chip (30) is formed along the flat portion.
This sensing method, executed by a sensing device provided with a 3D sensor that detects an object on the basis of reflected light of light emitted by a light source, comprises a first control step (step S11) for controlling the light source at a first number of emissions per unit time, a first calculation step (step S12) for calculating a first difference between a sensing result acquired by the sensing device when the light source is controlled at the first number of emissions and a sensing result acquired by the sensing device in a state in which an object is not present, a first determination step (step S13) for determining whether the first difference exists, and a second control step (step S14) for controlling the light source at a second number of emissions larger than the first number of emissions per unit time when it is determined that the first difference exists.
A distance measuring device (10) that outputs one or more pieces of distance information indicating the distance to a subject (500) comprises: a light source (20) that emits illuminating light including one or more bright portions; a light receiving unit (30) including a pixel array (32) in which a plurality of pixels (31) are arranged in a matrix; a distance information calculating unit (110) which, when the light receiving unit (30) receives reflected light, this being the illuminating light reflected by the subject (500), calculates, on the basis of one or more pixel values sequentially output from each pixel (31), for each of the plurality of pixels (31), light intensity information indicating the intensity of the reflected light at the pixel (31), and pixel distance information indicating the distance to the subject (500) at the pixel (31); a distance information selecting unit (120) for selecting one or more pieces of selected distance information from among the plurality of pieces of pixel distance information corresponding to the plurality of pixels (31), on the basis of the plurality of pieces of light intensity information corresponding to the plurality of pixels (31); and an output unit (130) for outputting one or more pieces of distance information on the basis of the one or more pieces of selected distance information.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 21/318 - Couches inorganiques composées de nitrures
32.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device (100) comprises: a first nitride semiconductor layer (103); a second nitride semiconductor layer (104); a p-type third nitride semiconductor layer (106) and a p-type fourth nitride semiconductor layer (107) that are provided on the second nitride semiconductor layer (104) and are separated from one another; a source electrode (301) and a drain electrode (302); a first gate electrode (303) that is provided in contact with the third nitride semiconductor layer (106); and a second gate electrode (304) that is provided on the fourth nitride semiconductor layer (107) with a dielectric layer (201) interposed therebetween, wherein at least one of the following conditions is satisfied: the second gate length (L2) of the fourth nitride semiconductor layer (107) is less than the first gate length (L1) of the third nitride semiconductor layer (106); the fourth nitride semiconductor layer (107) is thinner than the third nitride semiconductor layer (106); and the p-type impurity concentration of the fourth nitride semiconductor layer (107) is lower than the p-type impurity concentration of the third nitride semiconductor layer (106).
A semiconductor device (1) having: an electron travel layer (103); an electron supply layer (104) that is provided on the electron-traveling layer (103); a gate electrode (303) that is provided on the electron-supply layer (104); a contact layer (212) that, at a position where the gate electrode (303) is enclosed on either side, is embedded in a through-recess part (211) passing through the electron supply layer (104); an electron supply auxiliary layer (401) that is provided so as to be in contact with the electron supply layer (104) and the contact layer (212) but not be in contact with the gate electrode (303), the electron supply auxiliary layer (401) being an example of a n-type semiconductor layer composed of a n-type semiconductor that contains Si; an alloy layer (402) that is provided on the electron supply auxiliary layer (401) and that contains Si; a first insulating layer (201) that is provided so as to be in contact with the gate electrode (303) but not be in contact with the contact layer (212); and a source electrode (301) and/or a drain electrode (302) that is provided on the contact layer (212) and the alloy layer (402).
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
34.
OBJECT DETECTING DEVICE, OBJECT DETECTING SYSTEM, AND OBJECT DETECTING METHOD
An object detecting device (10) detects an object (103) present at a distance less than a minimum distance that can be measured, using exposure information or a distance image (D2) obtained by a ranging camera (40) having a function of emitting light onto an object (103) and performing phase shift exposure with respect to reflected light from the object (103), the object detecting device (10) comprising a nearby region presence determining unit (20) that determines whether the object (103) is present in a nearby region, which is a zone closer than the minimum distance that can be measured, and an output unit (30) for outputting information indicating the result determined by the nearby region presence determining unit (20), wherein the nearby region presence determining unit (20) includes a nearby region determining unit (21) that determines whether an exposure condition is satisfied, said exposure condition being that light reception based on the reflected light is performed in only a first exposure period, in which the most recent exposure was performed, among exposure periods performed at a plurality of two or more different timings, constituting the phase shift exposure, and determines that the object (103) is present in the nearby region on the basis of the exposure condition.
A high-frequency power amplifier (100) includes a power amplification transistor (1) and a gate bias circuit (5). The gate bias circuit (5) comprises a VHb terminal (7) that is connected to a bias high-voltage power supply (10), a VLb terminal (8) that is connected to a bias low-voltage power supply (11), an enable terminal (6) that receives an enable signal; an enable transistor (12) and a voltage dividing resistor (13) that are connected in series between the VHb terminal (7) and the VLb terminal (8), a drive unit (14) that outputs voltage to a control terminal of the enable transistor (12), and a gate bias output terminal (9) that outputs, as gate bias voltage, divided voltage generated by the voltage dividing resistor (13). When an OFF signal has been received as the enable signal, the drive unit (14) operates the enable transistor (12) in a first operation region that is not a cut-off region.
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
A high-frequency amplifier (200) is provided with a transistor (1), an input line (1a), an output line (1b), and a shunt circuit (240) connected between the input line (1a) or the output line (1b) and a ground (161). The shunt circuit (240) includes a first series resonance circuit (5) including an inductor (7) and a capacitor (8) connected in series and having a first resonance frequency f1, a second series resonance circuit (6) including an inductor (9) and a capacitor (10) connected in series and having a second resonance frequency f2 different from the first resonance frequency f1, and a resistor (11) connected between a first connection point (5a) between the inductor (7) and the capacitor (8) and a second connection point (6a) between the inductor (9) and the capacitor (10).
This high-frequency electric power amplification device (100) comprises: a sub-mount substrate (1); a semiconductor substrate (4) that is mounted on the sub-mount substrate (1); a plurality of unit amplifiers (5) that are mounted on the semiconductor substrate (4); and a plurality of input wires (18). Each of the plurality of unit amplifiers (5) has an RF transistor (10), a gate bus line (11), an input bonding pad (12), and a shunt circuit (14) that has one end connected to the input bonding pad (12) and the other end connected to a ground potential. The plurality of input wires (18) include, for each of the plurality of unit amplifiers (5), a plurality of input wires that connect a first wiring pattern (2) and the input bonding pad (12) of the unit amplifier (5). The shunt circuit (14) that is included in each of the plurality of unit amplifiers (5) includes a semiconductor inductor (15) and an MIM capacitor (16) that are connected in series.
A semiconductor device (1) is provided with: a substrate (101); a channel layer (103); a nitride semiconductor layer (104) including a barrier layer (105); a source electrode (201); a drain electrode (202); a gate electrode (203); a drain-side insulating layer (300d); and a source-side insulating layer (300s). The gate electrode (203) includes a junction part (203a), a drain-side overhang part (203d), and a source-side overhang part (203s). The overhang length of the source-side overhang part (203s) is longer than the overhang length of the drain-side overhang part (203d). The lower surface (203sa) of the source-side overhang part (203s) has a step. The height Hgs of an end part (203ss) of the lower surface (203sa) of the source-side overhang part (203s) is higher than the height Hgd of an end part (203dd) of the lower surface (203da) of the drain-side overhang part (203d).
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
39.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
A semiconductor device (1) comprises: an electron transit layer (103); an electron supply layer (104) that is provided on the electron transit layer (103) and that has a band gap greater than that of the electron transit layer (103); a gate electrode (303) that is provided on the electron supply layer (104); contact layers (212) that are embedded, at positions between which the gate electrode (303) is sandwiched, in a through-recessed part (211) which passes through the electron supply layer (104); a first insulation layer (201) that is provided on a part of the electron supply layer (104) to which the gate electrode (303) is not provided; and a second insulation layer (202) that is provided on the first insulation layer (201) such that the second insulation layer (202) is in contact with the contact layers (212) but is not in contact with the gate electrode (303), wherein the coefficient of linear thermal expansion of the second insulation layer (202) is higher than the coefficient of linear thermal expansion of the electron supply layer (104).
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A semiconductor device (1) is provided with a rectangular semiconductor chip (2) having a long side extending in a first direction and a short side extending in a second direction. The semiconductor chip (2) is provided with a first vertical MOS transistor (10) provided with a first gate pad (119) and a plurality of first source pads (111), and a second vertical MOS transistor (20) provided with a second gate pad (129) and a plurality of second source pads (121). A plurality of first row-shaped arrangement regions (71) in which the source pads are arranged linearly side by side in the first direction, and a plurality of second row-shaped arrangement regions (72) in which the source pads are arranged linearly side by side in the second direction are formed on the upper surface of the semiconductor chip (2). The semiconductor device (1) further includes a plurality of ball-type bump electrodes (3) connected to the first gate pads (119), the plurality of first source pads (111), the second gate pads (129), and the plurality of second source pads (121), respectively.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
41.
VIDEO MONITORING DEVICE AND VIDEO MONITORING METHOD
A video monitoring device (230) for monitoring video data received from a video display device (120) that receives a video signal from a camera (90) and displays the video comprises: a video extractor (234) that extracts, from the received video data, color information for each pixel constituting an image represented by the video data; a specific color difference calculator (235) that calculates, for each pixel, difference information between a color represented by the extracted color information and a specific color; a histogram calculator (233) that calculates a histogram in which the number of pixels in each of a plurality of difference intervals is the frequency by classifying the difference information calculated for each pixel; and an anomaly detector (240) that generates and outputs a signal indicating that the video data is abnormal when the frequency of pixels in a specific difference interval in the calculated histogram is equal to or greater than a first threshold value.
This method for manufacturing a semiconductor light emitting element comprises: a growth step for growing a semiconductor laminate (1S) on a main surface of a wafer (10M); a ridge groove formation step for forming a plurality of projection sections (P1) and a plurality of ridges (R1) extending in a first direction parallel to the main surface of the wafer (10M) by forming, in the semiconductor laminate (1S), a plurality of ridge grooves (T3) extending in the first direction; a transverse groove formation step for forming, in the semiconductor laminate (1S), a plurality of transverse grooves (T1) that are deeper than the plurality of ridge grooves (T3); a cleavage step for forming a plurality of bar-shaped substrates (10Mb) by cleaving the wafer (10M) at a plurality of cleavage lines (L1) parallel to a second direction that is parallel to the main surface of the wafer (10M) and perpendicular to the first direction; and a separation step for individually dividing the plurality of bar-shaped substrates (10Mb) at a plurality of division lines (L2) parallel to the first direction.
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
43.
IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM
An image processing device (100) is provided with: an acquisition unit (10) that acquires a visible light image and an infrared image that show the same area; a dividing unit (20) that divides the visible light image into a plurality of blocks; a calculation unit (30) that calculates a correction coefficient for correcting contrast for each of the plurality of blocks; and an application unit (50) that applies the calculated correction coefficients to the visible light image. The calculation unit (30) excludes, from each block of the plurality of blocks, high luminance noise pixels having a specific component that is greater than a first threshold value in the corresponding infrared image, and calculates a correction coefficient using a maximum pixel value and a minimum pixel value in the block from which the high luminance noise pixels have been excluded.
G06T 5/94 - Modification de la plage dynamique d'images ou de parties d'images basée sur les propriétés locales des images, p. ex. pour l'amélioration locale du contraste
An in-vehicle warning light fault diagnosis device (240) comprises: a correct-answer icon area memory controller (142) that acquires and stores a correct-answer icon image for reference; an icon image cut-out unit (141) that cuts out an icon image from a synthetic image; an icon correlation calculator (143) that calculates a first correlation value between an icon in the cut-out icon image and an icon in the correct-answer icon image for reference; a background correlation calculator (144) that calculates a second correlation value between a background part except the icon and a predetermined similar color; and an icon fault determiner (245) and a background fault determiner (246) that determine faults in the icon in the cut-out icon image and the background part on the basis of the calculated first correlation value and second correlation value.
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
B60K 35/00 - Instruments spécialement adaptés aux véhiculesAgencement d’instruments dans ou sur des véhicules
B60R 16/02 - Circuits électriques ou circuits de fluides spécialement adaptés aux véhicules et non prévus ailleursAgencement des éléments des circuits électriques ou des circuits de fluides spécialement adapté aux véhicules et non prévu ailleurs électriques
A start control circuit (1) comprises a detection unit (20) that detects the voltage of a power supply (200) that supplies power to a plurality of circuits, a control unit (10) that performs start control for the plurality of circuits, and a storage unit (30) that stores a plurality of combinations each including one or more circuits among the plurality of circuits. The control unit (10) determines whether or not the voltage of the power supply (200) detected by the detection unit (20) is lower than a predetermined voltage value when the control unit (10) has performed the start control on the plurality of circuits. Upon determining that the voltage of the power supply (200) is lower than the predetermined voltage value, the control unit (10) selects, from among the plurality of combinations, a combination in which one or more circuits have been excluded from the circuits, and performs the start control on the combination selected.
G06F 1/28 - Surveillance, p. ex. détection des pannes d'alimentation par franchissement de seuils
G06F 1/3237 - Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
H02J 1/00 - Circuits pour réseaux principaux ou de distribution, à courant continu
46.
SEMICONDUCTOR LASER DEVICE, LIGHT SOURCE MODULE, AND METHOD FOR MANUFACTURING LIGHT SOURCE MODULE
Provided is a semiconductor laser device (1) comprising a semiconductor laser element (200) that emits a laser beam, and a lens unit (100) that includes a first cylindrical lens (110) and an installation plane, wherein: the semiconductor laser element (200) includes an active layer; the first cylindrical lens (110) reduces the spread angle of a laser beam in the fast axis direction when the laser beam enters said lens; the installation plane is fixed to a first installation target plane; the generatrix of the first cylindrical lens (110) is inclined with respect to the first installation target plane, and the angle θ formed between the generatrix and the active layer is such that |θ| < 22.5°.
An image processing device (100) comprising: an acquisition unit (exposure time setting unit (10)) which acquires two types of image obtained by two types of imaging means differ in wavelength from each other and showing the same area; and a determination unit (exposure time setting unit (10)) which determines, on the basis of one of the two types of image, a photometric area which is in the other one of the two types of image and in which photometry is performed.
H04N 23/45 - Caméras ou modules de caméras comprenant des capteurs d'images électroniquesLeur commande pour générer des signaux d'image à partir de plusieurs capteurs d'image de type différent ou fonctionnant dans des modes différents, p. ex. avec un capteur CMOS pour les images en mouvement en combinaison avec un dispositif à couplage de charge [CCD] pour les images fixes
A light source module (10) comprises a plurality of optical units (1-6). The plurality of optical units (1-6) each have a semiconductor laser element (200) that emits laser light, a fast-axis cylindrical lens (FACL) (110), a first fast-axis adjustment lens (first lens) (120), and a slow-axis collimator lens (SACL) (170). α satisfies expression 1: α=F2/F1, and β satisfies expression 2: β=d/F2, when F1 is the effective focal length of the FACL (110), F2 is the effective focal length of the first lens (120), and d is the distance between the principal point of the FACL (110) and the principal point of the first lens (120). When F2>0, α and β satisfy expression 3, expression 4, expression 5, and expression 6. Expression 3: α>1, expression 4: αβ>1, expression 5: β<(1/α)+(1/3), expression 6: β<1
A resistive resistance non-volatile memory device (10a) includes a memory cell (20) and a heater (30) that is thermally coupled to the memory cell (20), each of which can independently operate. The memory cell (20) has a first electrode layer (21), a second electrode layer (22), and a variable resistance layer (23) sandwiched between the first electrode layer (21) and the second electrode layer (22). The heater (30) has a heating element (31) and a third terminal (32) and a fourth terminal (33) that are connected to the heating element (31).
A display video correction device (100) comprises: a feature quantity extraction unit (110) that extracts a feature quantity from a camera video that is obtained from an in-vehicle camera (300); a Hough conversion unit (120) that executes Hough conversion on the extracted feature quantity; a straight line detection unit (130) that detects a plurality of straight lines in the camera video on the basis of the conversion result of the executed Hough conversion; a vanishing point calculation unit (140) that calculates a first coordinate that indicates the coordinate of a vanishing point in the camera video, on the basis of the plurality of detected straight lines; a difference calculation unit (150) that calculates the difference between the calculated first coordinate and a prescribed second coordinate; and a position correction unit (160) that corrects the position of a display region of the camera video that is to be displayed by a display device (310), on the basis of the calculated difference.
An IC card (500) of the present invention comprises: a coil antenna (501) that receives power from a transmission/reception device via non-contact communication; a resonance frequency variable circuit (502) for varying a resonance frequency of the coil antenna (501); a rectification unit (505) that rectifies an antenna output current output from the coil antenna (501); a control unit (508) that consumes a load current; a detection unit (507) that detects an excessive current which is a difference between the load current and a rectified output current output from the rectification unit (505); and a resonance frequency control unit (509) that changes the resonance frequency of the coil antenna (501) by controlling the resonance frequency variable circuit (502) in accordance with a detection signal which indicates a detection result of the excessive current and which is output from the detection unit (507).
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
52.
LIGHT EMITTING DEVICE, LIGHT EMITTING MODULE, METHOD FOR PRODUCING LIGHT EMITTING DEVICE, AND METHOD FOR PRODUCING LIGHT EMITTING MODULE
Disclosed is a light emitting device which is provided with a base material (70), a semiconductor laser element (10) that is bonded to the base material (70), and a first bonding layer (30) that bonds the base material (70) and the semiconductor laser element (10) to each other, wherein: the first bonding layer (30) comprises an element bonding layer (43) that is formed of a single metal element, a metal film (50) that is disposed between the element bonding layer (43) and the base material (70) and is formed of a sintered body of a single metal element, and a base material bonding layer (62) that is disposed between the metal film (50) and the base material (70) and is formed of a single metal element; the metal film (50) is formed of Au, Ag, Cu or Al; and the total thickness of the element bonding layer (43), the metal film (50) and the base material bonding layer (62) is 80% or more of the thickness of the first bonding layer (30).
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
53.
SEMICONDUCTOR LASER DEVICE, SUBMOUNT FOR SEMICONDUCTOR LASER ELEMENTS, SUBMOUNT ASSEMBLY FOR SEMICONDUCTOR LASER ELEMENTS, METHOD FOR PRODUCING LIGHT EMITTING DEVICE, AND METHOD FOR PRODUCING SUBMOUNT FOR LIGHT EMITTING ELEMENTS
This semiconductor laser device (a light emitting device (1)) is provided with: a base material (70) which has a first main surface (70a); a metal film (50) which is disposed on the first main surface (70a) and is formed of a sintered body of metal fine particles; and an end face emission-type semiconductor laser element (a light emitting element (10)) which is bonded to the metal film (50). The semiconductor laser element is disposed such that, in a plan view of the first main surface (70a), a light emission surface (10F) of the semiconductor laser element protrudes from a first edge (70ae) of the first main surface (70a) toward the outside of the first main surface (70a).
A solid-state imaging device (100) comprises: a pixel array (11) in which multiple pixels (1) are arranged in a matrix configuration; and a first power source wire (101). Each of the pixels (1) is equipped with a photoelectric conversion unit (10), a floating diffusion unit (20), a capacitance storage unit (30), a first transfer transistor (40), an overflow transistor (50), a second transfer transistor (60), a first reset transistor (70), and an amplifier transistor (80). This solid-state imaging device (100) is further provided with a reset means (75 and 120) that is for resetting the floating diffusion unit (20) and the capacitance storage unit (30) at voltages different from each other.
A solid-state imaging device (100) comprises a pixel array (110) in which a plurality of pixels (111) are arranged in a matrix, the plurality of pixels (111) each including a photoelectric conversion section (10) for converting received light into signal charge, and capacitive storage sections (21, 22, 23, 24, 25). The plurality of pixels (111) are configured to be able to output M pixel signals having mutually different gains, and are controlled to output N (N is an integer greater than or equal to 2 and less than M) pixel signals among the M pixel signals.
H04N 25/585 - Commande de la gamme dynamique impliquant plusieurs expositions acquises simultanément avec des pixels ayant des sensibilités différentes à l'intérieur du capteur, p. ex. des pixels rapides ou lents ou des pixels ayant des tailles différentes
A semiconductor device (1) comprises: a semiconductor layer (40); a first vertical MOS transistor (10) and a second vertical MOS transistor (20) that are formed in the semiconductor layer (40); a metal layer (30) that is in contact with and connected to the entire back side surface of the semiconductor layer (40); and a support (42) that is bonded to the back side of the metal layer (30) with an adhesive (41) therebetween. In a plan view, the support (42) has a larger area than the semiconductor layer (40) and encompasses the semiconductor layer (40); the thickness of the support (42) is greater than the thickness of the semiconductor layer (40); the height of the adhesive (41) along a side surface of the semiconductor layer (40) is less than that of a top surface of the semiconductor layer (40) in a cross-sectional view of the semiconductor device (1), the cross-sectional view including the center of the semiconductor layer (40) and the outer circumference of the semiconductor layer (40) in a plan view; and in the cross-sectional view, a semiconductor chip (2), which is the portion of the semiconductor device (1) excluding the support (42) and the adhesive (41), has a curved shape that is convex in the direction toward the support (42).
A semiconductor device (1) comprises: a semiconductor layer (40); a first vertical MOS transistor (10) and a second vertical MOS transistor (20), which have been formed in the semiconductor layer (40); a metal layer (30) which is in contact with and connected to the entire back surface of the semiconductor layer (40); and a support (42) bonded to the back surface of the metal layer (30) with an electroconductive adhesive (41) therebetween. In a plan view, the support (42) has a larger area than the semiconductor layer (40) and the semiconductor layer (40) lies within the support (42). The support (42) has a larger thickness than the semiconductor layer (40). In a cross-sectional view of the semiconductor device (1), including the center of the semiconductor layer (40) and the outer periphery of the semiconductor layer (40) in the plan view, a semiconductor chip (2), resulting from excluding the support (42) and the electroconductive adhesive (41) from the semiconductor device (1), has a curved shape such that the semiconductor chip (2) protrudes away from the support (42).
This semiconductor device comprises a filter circuit (104) including resistors (201a, 201b), MOS capacitors (202a, 202b), and a MOM capacitor (203) stacked on the resistors (201a, 201b) or/and MOS capacitors (202a, 202b), wherein where a cutoff frequency of the filter circuit (104) is ft, a resistance area of a resistance formation region (600) where the resistors (201a, 201b) are formed is Mr, a MOS capacitor area of a MOS capacitor formation region (500) where the MOS capacitors (202a, 202b) are formed is Mc, the resistivity of the resistors (201a, 201b) is α, a MOS capacitance ratio of the MOS capacitors (202a, 202b) is β, and a MOM capacitance ratio of the MOM capacitor (203) is γ, Formulas 1 are satisfied.
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01G 4/33 - Condensateurs à film mince ou à film épais
H01G 4/40 - Combinaisons structurales de condensateurs fixes avec d'autres éléments électriques non couverts par la présente sous-classe, la structure étant principalement constituée par un condensateur, p. ex. combinaisons RC
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H03H 7/06 - Réseaux à deux accès sélecteurs de fréquence comprenant des résistances
H03K 5/08 - Mise en forme d'impulsions par limitation, par application d'un seuil, par découpage, c.-à-d. par application combinée d'une limitation et d'un seuil
59.
POWER STORAGE PACK, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This power storage pack (100) comprises: a power storage cell (3); a power storage tab (80AB) connected to the power storage cell (3); a protection circuit substrate (60) that protects the power storage cell (3) from over-charging or over-discharging; a chip-size package-type semiconductor element (2A) that is mounted face down on the protection circuit substrate (60); and a metal plate for joining the power storage tab (70AB) that is connected to the semiconductor element (2A) on a first main surface, and that has a part with a thickness of 0.2 mm or less. The metal plate for joining a power storage tab (70AB) is joined to the power storage tab (80AB) on a second main surface facing away from the first main surface so as to have an overlapping part in which the power storage tab (80AB), the metal plate for joining a power storage tab (70AB), the semiconductor element (2A), and the protection circuit substrate (60) overlap in the plan view of the protection circuit substrate (60), and there is a part in which a region that can become a conduction path between the power storage tab (80AB) and the protection circuit substrate (60) overlaps with the abovementioned overlapping part in the plan view of the protection circuit substrate (60).
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01G 2/16 - Protection contre la surcharge électrique ou thermique avec des éléments fusibles
H01G 11/16 - Agencements ou procédés de réglage ou de protection des condensateurs hybrides ou EDL contre les surcharges électriques, p. ex. comprenant des fusibles
H01G 11/74 - Bornes, p. ex. extensions des collecteurs de courant
H01M 50/284 - MonturesBoîtiers secondaires ou cadresBâtis, modules ou blocsDispositifs de suspensionAmortisseursDispositifs de transport ou de manutentionSupports comprenant l’insertion de cartes de circuits, p. ex. de cartes de circuits imprimés
60.
SEMICONDUCTOR INTEGRATED CIRCUIT, TRANSFER SYSTEM, AND DATA TRANSFER METHOD
A semiconductor integrated circuit (10) comprises: a transmission control unit (20) that transmits transmission data to a transmission destination circuit (90) and that transmits, to the transmission destination circuit (90), a strobe signal for causing the transmission data to be received; a determination unit (30) that, on the basis of scheduled transmission data which is scheduled to be subsequently transmitted by the transmission control unit (20) and an N number (N being a whole number equal to or greater than 1) of pieces of transmitted data among the transmission data pieces transmitted in the past, determines whether to transmit dummy data to the transmission destination circuit (90) before the transmission control unit (20) transmits the scheduled transmission data to the transmission destination circuit (90); and a dummy data generation unit (40) that generates dummy data. When the determination unit (30) makes an affirmative determination, the transmission control unit (20) transmits dummy data to the transmission destination circuit (90) and performs an invalidation process for invalidating the dummy data at the transmission destination circuit (90), before the scheduled transmission data is transmitted to the transmission destination circuit (90).
In the present invention, an impedance detection device (60) comprises an acquisition unit (61) for acquiring measurement data that is the current and/or the voltage at I points in time during a transient response when a prescribed current or a prescribed voltage is fed to a secondary cell, and a calculation unit (60b) for calculating internal impedance on the basis of the measurement data that is the current and/or voltage. The calculation unit (60b) has a first calculation unit (62) for calculating I items of impedance data using the measurement data that is the current and/or voltage, and a second calculation unit (60a) for calculating an element parameter of an equivalent circuit model of the secondary cell on the basis of the I items of impedance data and an Mth-order equation that is obtained from an equivalent circuit model and in which internal impedance is indicated as a linear sum of a plurality of terms. The Mth-order equation is an equation based on a theoretical value that corresponds to a prescribed current or a prescribed voltage.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/367 - Logiciels à cet effet, p. ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
62.
IMAGE SENSING DEVICE, IMAGE SENSING METHOD AND PROGRAM
This image sensing device (100) comprises: a 2D camera (10) that generates a two-dimensional image; a 3D camera (20) that has a light source (21) and generates a distance image on the basis of the reflected light of a light irradiated by the light source (21); an image recognition unit (30) that uses the two-dimensional image or the distance image to perform a recognition of a subject appearing in the two-dimensional image; and a camera control unit (40) that controls the on and off of the operation of the 3D camera (20). When the 3D camera (20) is in a standby state in which the light source (21) is emitting no light after the completion of an initialization process following an activation, the camera control unit (40) turns on the operation of the 3D camera (20) on the basis of the result of the recognition using the two-dimensional image. The 3D camera (20) enters the standby state when the operation of the 3D camera (20) is turned off by the camera control unit (40) after the turning-on of the operation of the 3D camera (20) thereby.
H04N 23/611 - Commande des caméras ou des modules de caméras en fonction des objets reconnus les objets reconnus comprenant des parties du corps humain
63.
IMAGE SENSING DEVICE, IMAGE SENSING METHOD, AND PROGRAM
An image sensing device (100) comprises a microphone (10), a 3D camera (20), a voice recognition unit (31) that implements voice recognition on the basis of an audio signal representing a voice picked up by the microphone (10), and a camera control unit (40) that controls on and off operations of the 3D camera (20). When the 3D camera (20) has completed an initialization process after startup and is in a standby state, the camera control unit (40) turns on the operation of the 3D camera (20) on the basis of the voice recognition result, and the 3D camera (20) is placed in a standby state if operation of the 3D camera (20) has been turned off by the camera control unit (40).
An image sensing device (100) comprises a 3D camera (20), an orientation detection sensor (10) that detects the orientation of the 3D camera (20), and a camera control unit (40) that controls the turning on and off the operation of the 3D camera (20), wherein: the camera control unit (40) acquires a detection result for the orientation of the 3D camera (20) and determines, on the basis of the detection result, whether or not the orientation of the 3D camera (20) is a specific orientation; the camera control unit (40) turns on the operation of the 3D camera (20) when the orientation of the 3D camera (20) is the specific orientation while the 3D camera (20) is in a standby state, with an initialization process after startup being completed; and the 3D camera (20) is in the standby state when the operation is turned off by the camera control unit (40).
An information processing method according to one aspect of the present disclosure involves: using a distance measurement sensor (10) mounted on an object to acquire a first point group (S10); and calculating, on the basis of the first point group, the position and orientation of the distance measurement sensor (10) (S20). For example, in the acquisition of the first point group, the distance measurement sensor (10) acquires the first point group that can be obtained by detecting the road surface. In the calculation of the orientation of the distance measurement sensor (10), the pitch angle and the roll angle of the distance measurement sensor (10) are calculated on the basis of the vector of the second point group that is normal to the road surface. In the calculation of the position of the distance measurement sensor (10), the height of the distance measurement sensor (10) from the road surface is calculated on the basis of the pitch angle and the roll angle of the distance measurement sensor (10).
A motor drive device (10) comprises: an actual speed signal generation unit (4) that generates an actual speed signal; a target speed signal generation unit (5) that generates a target speed signal; a speed comparison unit (6) that compares the actual speed signal and the target speed signal; and a speed command generation unit (7) that generates a speed command signal in accordance with an output from the speed comparison unit (6). The speed command generation unit (7) includes: a step width generation unit (7A) that, in accordance with the output of the speed comparison unit (6), generates a step width signal indicating a step width that includes a size and a plus/minus sign for which one of the actual speed and the target speed serves as a reference and which correspond to the size of the other of the actual speed and the target speed; an update signal generation unit (7B) that generates an update signal; and an integration calculation unit (7C) that adds, at a timing of the update signal, the step width expressed in the step width signal to the speed command signal and outputs the resulting signal.
This pulse wave analysis device (10) comprises an acquisition unit (11) for acquiring a pulse wave waveform, a generation unit (12) for generating an acceleration pulse wave waveform, a detection unit (13) for detecting a feature point included in the acceleration pulse wave waveform, and an output unit (14) for outputting the feature point. The detection unit (13): determines, for one of the maxima present in the acceleration pulse wave waveform, whether an ascending inflection point exists between said maxima and the next minima present after the maxima, and if said ascending inflection point exists, detects the ascending inflection point as a feature point; or determines, for one of the minima present in the acceleration pulse wave waveform, whether a descending inflection point exists between said minima and the next maxima present after the minima, and if said descending inflection point exists, detects the descending inflection point as a feature point.
A61B 5/02 - Détection, mesure ou enregistrement en vue de l'évaluation du système cardio-vasculaire, p. ex. mesure du pouls, du rythme cardiaque, de la pression sanguine ou du débit sanguin
A semiconductor device (1) is provided with, in plan view: a transistor (10) formed in a first region (A1) of a semiconductor layer (40); a transistor (20) formed in a second region (A2) adjacent to the first region (A1) of the semiconductor layer (40); and a drain pad (151) formed in a third region (A3) not overlapping with the first region (A1) or the second region (A2). In plan view, the first region (A1) and the second region (A2) result from bisecting the surface area of a region of the semiconductor layer (40) excluding the third region (A3). In plan view, the transistor (10) and the transistor (20) are lined up in a first direction. The center of the third region (A3) is on a rectilinear center line (90) that bisects the semiconductor layer (40) in the first direction and that is orthogonal to the first direction. In plan view, the drain pad (151) is encompassed by the third region (A3).
A motor drive device (1) comprises: a target speed generation unit (10) that generates a target speed signal (St) indicating a target speed of a motor (2); an actual speed detection unit (14) that generates an actual speed signal (Sr) indicating the actual speed; and a drive unit (30) that drives the motor (2) so that the actual speed indicated by the actual speed signal (Sr) approaches the target speed indicated by the target speed signal (St). The target speed generation unit (10) generates an input speed signal (Si) based on an input instruction and a provisional speed signal that is higher than the actual speed signal (Sr) at the time of startup, and, when the actual speed indicated by the actual speed signal (Sr) at startup is higher than the speed indicated by the input speed signal (Si), outputs the provisional speed signal as the target speed signal (St).
An imaging device (1) comprises an effective area pixel (20) that outputs N pixel signals that have different gains, N×M optical black pixels (30) that output dark current pixel signals, a selection circuit (40) that selects one of the N pixel signals and specifies one of M gains, an AD conversion circuit (50) that performs an AD conversion on the pixel signal selected by the selection circuit (40) on the basis of the gain specified by the selection circuit (40), and a dark current calculation circuit (60) that calculates N×M dark current component signals on the basis of the dark current pixel signals outputted by the N×M optical black pixels (30) and feeds the dark current component signals back to at least one of the selection circuit (40) and the AD conversion circuit (50).
A distance measuring device (100) comprises: a light source unit (10) for emitting emitted light; a light receiving unit (20) including a pixel for generating a pixel signal on the basis of incident light; a drive control unit (30) for controlling the drive of the light source unit (10) and the light receiving unit (20); and a signal processing unit (40) for deriving a distance to a target object on the basis of the pixel signal. The drive control unit (30) drives the light source unit (10) and the pixel using a CW-ToF sequence and a pulse ToF sequence for measuring the distance using mutually different types of indirect ToF schemes, and switches between the CW-ToF sequence and the pulse ToF sequence between frames. The signal processing unit (40) derives the distance to the target object on the basis of a first pixel signal generated by the pixel using the CW-ToF sequence, and a second pixel signal generated by the pixel using the pulse ToF sequence. A distance measurement range of the pulse ToF sequence is greater than the distance measurement range of the CW-ToF sequence.
A semiconductor light-emitting element (1) emits light from a front end surface (1F) and comprises a semiconductor laminate (1S) having a waveguide, a first P-side electrode (71), and a pad electrode (73). The semiconductor light-emitting element (1) has: a front bottom part (L1) that is the upper surface of the semiconductor light-emitting element (1), that extends rearward from the front end surface (1F) above the waveguide of the semiconductor light-emitting element (1), and that does not have the pad electrode (73) disposed thereon; a rear bottom part (L2) disposed rearward of the front bottom part (L1); a front projection part (H1) that is disposed between the front bottom part (L1) and the rear bottom part (L2) and that projects upward relative to the front bottom part (L1) and the rear bottom part (L2); and a rear projection part (H2) that is disposed rearward of the rear bottom part (L2) and that projects upward relative to the front bottom part (L1) and the rear bottom part (L2). The rear projection part (H2) includes at least a portion of the pad electrode (73).
This semiconductor laser device comprises: a semiconductor laser element (11) and a semiconductor laser element (12); a reflecting mirror (71) that reflects first laser light emitted from the semiconductor laser element (11); and a reflecting mirror (72) that reflects second laser light emitted from the semiconductor laser element (12). The semiconductor laser element (11) has a light emitting point (11e). The semiconductor laser element (12) has a light emitting point (12e). When the optical axis of the first laser light entering the reflecting mirror (71) is a first optical axis, the optical axis of the second laser light entering the reflecting mirror (72) is a second optical axis, and a direction passing through the light emitting point (11e) and perpendicular to the first optical axis is a first direction, a first distance from the light emitting point (11e) to the first optical axis in the first direction and a second distance from the light emitting point (11e) to the second optical axis in the first direction are different from each other. A third distance from the light emitting point (12e) to the second optical axis in the first direction is greater than the first distance.
This semiconductor laser device (1) comprises: a housing (2) that has a flat bottom surface (6a); semiconductor laser elements (10–15) that are arranged in the housing (2); fast axis collimator lenses (30–35) that respectively collimate laser beams that are respectively emitted from the semiconductor laser elements (10–15) in a fast axis direction; prisms (40–45) that respectively deflect the laser beams in the fast axis direction; and slow axis collimator lenses (60–65) that respectively collimate the laser beams in a slow axis direction. The prisms (40–45) are arranged between the fast axis collimator lenses (30–35) and the slow axis collimator lenses (60–65), and the laser beams that are respectively emitted from the slow axis collimator lenses (60–65) have different optical axis positions in the fast axis direction from one another.
A nitride-based semiconductor light-emitting device (100) emits light and comprises an N-type cladding layer (104), an N-side light guide layer (106), an active layer (107), an electron barrier layer (109), a P-type intermediate layer (110), a P-side light guide layer (111), and a P-type cladding layer (112). The average band gap energy of the electron barrier layer (109) is greater than the average band gap energy of the P-type cladding layer (112). The average band gap energy of the P-type intermediate layer (110) is greater than the average band gap energy of the P-side light guide layer (111), and less than the average band gap energy of the electron barrier layer (109). The average impurity concentration of the P-type intermediate layer (110) is lower than the average impurity concentration of the electron barrier layer (109) and higher than the average impurity concentration of the P-side light guide layer (111). The peak wavelength of the light emitted is less than 400 nm.
H01S 5/20 - Structure ou forme du corps semi-conducteur pour guider l'onde optique
H01L 33/32 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique contenant de l'azote
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
A semiconductor integrated circuit device (1) includes a plurality of standard cell rows (10) having a plurality of standard cells (11) arranged in the X direction and a plurality of power supply wirings (L1) extending in the X direction and supplying power to the plurality of standard cells (11), a plurality of strap power supply wirings (30) extending in the Y direction, a plurality of sub-strap power supply wirings (40) extending in the Y direction and each connected to each of the plurality of power supply wirings (L1), and a plurality of switch cells (SW) provided at intersections of the plurality of strap power supply wirings (30) and the plurality of power supply wirings (L1). The plurality of standard cell rows (10) have standard cell rows (10b) in which the switch cells (SW) are not arranged at positions corresponding to one or more standard cell columns other than the standard cell columns (21) and (22) at both ends of the plurality of standard cell columns (20).
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
77.
IMAGING DEVICE, DISTANCE MEASUREMENT DEVICE, AND CONTROL METHOD FOR IMAGING DEVICE
An imaging device (100) comprises: a unit cell that includes n pixels (201) (n being a natural number) and a charge storage part for storing the charge generated at the n pixels (201); and first control lines (241, 241v) and second control lines (251, 251v) that are provided to each pixel. Each of the n pixels includes: a photoelectric conversion part (211); a first transfer transistor (221) that has a first control terminal (221g) that is connected to the first control lines (241, 241v), a first input/output terminal that is connected to the photoelectric conversion part (211), and a second input/output terminal that is connected to the charge storage part; and a second transfer transistor (231) that has a second control terminal (231g) that is connected to the second control lines (251, 251v), a third input/output terminal that is connected to the photoelectric conversion part (211), and a fourth input/output terminal that is connected to a power supply line.
An imaging device (100) comprises: a first semiconductor layer (170); a unit cell that includes n (n is a natural number) pixels (201) and a charge storage unit (FD) for storing charge generated by the n pixels; and a drive circuit (130). The n pixels each include a photoelectric conversion unit (211), a first transfer transistor (221) having a first control terminal (221g), and a second transfer transistor (231) having a second control terminal (231g). The drive circuit (130) supplies a voltage corresponding to one operation mode selected from among a plurality of operation modes to the first semiconductor layer (170) and to the first control terminal (221g) or the second control terminal (231g).
This object detection device comprises: an image processing means that processes an image; a model pre-processing means that generates a first position shift image by performing position shifting on a reference image in accordance with a position shift amount; an object detection model that infers an object position, a class identification, and a likelihood from the reference image and the first position shift image for each frame; and an image selection means that compares position information including a detection frame for each detection object of each image as an inference result with the likelihood information to select and output a maximum inference result for each frame. The object detection device further comprises a detection frame correction means that, if the image selection means selects the inference result of the first position shift image, outputs position information including a detection frame obtained by performing position shifting in the opposite direction in accordance with the position shift amount of frame control information.
G06V 10/70 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique
Provided is an object detection method including: acquiring a first image and a second image in which each pixel corresponds one-to-one to each pixel of the first image (step S1); executing a first recognition process for recognizing the type of a first object captured in the first image (step S2); executing a second recognition process for recognizing the position of a second object captured in the second image (step S3), and when a first region based on the first object in the first image and a second region based on the second object in the second image overlap, executing a detection process for detecting the first object and the second object as the same object (step S4).
A semiconductor memory device (1) comprises: a first pull-down N-channel MOS transistor (21) having a drain connected to a word line (20), a source connected to a ground line, and a gate connected to a first node (91); a first series-connected N-channel MOS transistor (22) having a drain connected to a power supply line, and a source connected to the first node (91); and a second series-connected N-channel MOS transistor (23) having drain connected to the first node (91), and a source connected to the ground line. A signal that is an inverted logic of a signal input to the gate of the second series-connected N-channel MOS transistor (23) is inputted to the gate of the first series-connected N-channel MOS transistor (22).
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 8/08 - Circuits de commande de lignes de mots, p. ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
This chip sized package-type semiconductor device (1), which is able to be face-up mounted, comprises: a semiconductor layer (40); a vertical MOS transistor (10) which is formed within the semiconductor layer (40); a protective film (35); a first wiring electrode (12) which is connected to a source electrode (13) of the vertical MOS transistor (10); and a second wiring electrode (52) which is connected to a gate electrode (19) of the vertical MOS transistor (10). With respect to this chip sized package-type semiconductor device (1), a first outer peripheral structure (101), which protrudes upward from the semiconductor device (1) and is obtained by sequentially stacking the source electrode (13), the protective film (35) and the first wiring electrode (12) in this order, is formed on an outer peripheral portion of the first wiring electrode (12) in a plan view of the semiconductor layer (40); and a second outer peripheral structure (102), which protrudes upward from the semiconductor device (1) and is obtained by sequentially stacking the gate electrode (19), the protective film (35) and the second wiring electrode (52) in this order, is formed on an outer peripheral portion of the second wiring electrode (52) in a plan view of the semiconductor layer (40).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
This semiconductor laser element (10) is provided with a first semiconductor layer, an active layer (23), an insulating film (30), a contact electrode (40) and a barrier metal layer (50). A second semiconductor layer has a ridge (24R); the insulating film (30) has an opening part (30a) which is arranged in a position that corresponds to the upper surface (24Rt) of the ridge (24R); the contact electrode (40) is arranged in the opening part (30a); the lateral surface (40s) of the contact electrode (40) is inclined towards the inside of the contact electrode (40); the lateral surface (30s) of the insulating film (30) is inclined towards the outside of the opening part (30a); and the barrier metal layer (50) covers the entirety of the upper surface (40t) of the contact electrode (40), and continuously covers the area from the upper surface (40t) of the contact electrode (40) to the upper surface (30t) of the insulating film (30).
A hydrogen detection element (10) comprises: a first electrode (21) that is planar; a second electrode (23) having a main surface covered by insulating films (protection film (14) and second insulating film (13)) and formed so as to be opposite to the first electrode (21), the second electrode (23) being planar and having a plurality of exposed parts (26) in which portions of the insulating films on the main surface are opened to serve as a plurality of hydrogen gas inlets; a metal oxide layer (22) held between the first electrode (21) and the second electrode (23); and a first terminal (25a) and a second terminal (25b) electrically connected to the second electrode (23) at positions holding the exposed parts (26) therebetween in a plan view of the second electrode (23). When hydrogen gas is introduced into the exposed parts (26), resistance between the first terminal (25a) and the second terminal (25b) changes.
G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
86.
NOISE DETECTION DEVICE, NOISE DETECTION METHOD, AND PROGRAM
A noise detection device (1) for detecting cyclic noise included in an input signal is provided with: a cycle detection unit (10) that detects a cycle of noise; a timing estimation unit (20) that estimates a cyclic occurrence timing of noise in the future on the basis of the detected cycle; a threshold calculation unit (30) that lowers, for each estimated occurrence timing, a first threshold for use in detecting noise to a second threshold; and a noise detection unit (40) that detects noise by comparing, for each estimated occurrence timing, the magnitude of the input signal and the second threshold.
A noise elimination device (1) comprises: a noise detection unit (10) that detects noise having a frequency component spread across a band wider than the bandwidth of a desired signal included in an input signal; an FFT unit (51) that detects the frequency spectrum of a signal corresponding to the detected noise; and a noise elimination unit (60) that determines noise to be eliminated by comparing the frequency spectrum of the input signal and the frequency spectrum of the signal corresponding to the detected noise, and eliminates, from the input signal, the noise to be eliminated which was determined.
This noise removal device (1) comprises: a noise detection unit (10) which detects noise having a frequency component across a band wider than a bandwidth of a desired signal included in an input signal; and an interpolation unit (20) which removes the detected noise from the input signal and interpolates the portion removed together with the noise of the input signal.
An artificial intelligence processing device (200) comprises: one substrate (60) or the like; a computation circuit, such as a sum-of-product computation circuit (215) that is mounted on the one substrate (60) or the like and comprises a first resistance-variable non-volatile storage element (10) and a second resistance-variable non-volatile storage element (20) that each retain a conductance and have the same structure; and a write circuit (260) that overwrites the conductance of the first resistance-variable non-volatile storage element (10) by applying a first voltage pulse having a first voltage to the first resistance-variable non-volatile storage element (10), and overwrites the conductance of the second resistance-variable non-volatile storage element (20) by applying a second voltage pulse having a second voltage different from the first voltage to the second resistance-variable non-volatile storage element (20).
G06G 7/14 - Dispositions pour l'exécution d'opérations de calcul, p. ex. amplificateurs spécialement adaptés à cet effet pour l'addition ou la soustraction
G06G 7/16 - Dispositions pour l'exécution d'opérations de calcul, p. ex. amplificateurs spécialement adaptés à cet effet pour la multiplication ou la division
G06G 7/60 - Calculateurs analogiques pour des procédés, des systèmes ou des dispositifs spécifiques, p. ex. simulateurs d'êtres vivants, p. ex. leur système nerveux
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
A chip-scale package semiconductor device (1) which can be mounted face-down comprises a semiconductor substrate (32), a semiconductor layer (40) formed on the semiconductor substrate (32), a vertical field effect transistor (10) formed on the semiconductor layer (40), ball-type bump electrodes formed on the front surface-side relative to the semiconductor layer (40) and having a height of at least 100 µm, and a metal layer (30) having a multi-layer configuration and being formed in contact with the entire surface of the back surface-side of the semiconductor substrate (32), wherein: a first metal layer (30a) which is the thickest part within the metal layer (30) has a first metal as a main constituent, said first metal having the highest ductility among the metals constituting the metal layer (30); the first metal layer (30a) has a thickness of at least 8 µm; the outer periphery of the metal layer (30) in a planar view of the semiconductor layer (40) is provided with a protrusion (50) which protrudes downward relative to the back surface-side of the semiconductor substrate (32); and in a cross-sectional view of the protrusion (50), there is a section in which the width of the protrusion (50) becomes at least 5 µm.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/301 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour subdiviser un corps semi-conducteur en parties distinctes, p. ex. cloisonnement en zones séparées
91.
BANDGAP REFERENCE CIRCUIT, AND SEMICONDUCTOR DEVICE
A bandgap reference circuit (20) comprises: a diode characteristic element group (22); a dynamic element matching circuit (23) which repeatedly performs an operation to select, from the diode characteristic element group (22), a first diode characteristic element group (22a) configured by connecting in parallel M diode characteristic elements, and a second diode characteristic element group (22b) configured by connecting in parallel N (≥M) diode characteristic elements, within a fixed period, while changing a combination of selected diode characteristic elements; a reference voltage generating circuit (30) for generating a reference voltage (VBG) on the basis of a difference between current densities of currents flowing through the first diode characteristic element group (22a) and the second diode characteristic element group (22b); and a second-order temperature coefficient adjusting circuit (37) for adjusting a second-order temperature coefficient of the generated reference voltage (VBG).
G05F 3/30 - Régulateurs utilisant la différence entre les tensions base-émetteur de deux transistors bipolaires fonctionnant à des densités de courant différentes
92.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device (10) is provided with a semiconductor element (20), a submount (40), and a joining body (60). The semiconductor element (20) comprises an element body (22) and a first base electrode (24) that has a first joining surface (24a). The submount (40) comprises a base (42) and a second base electrode (44) that has a second joining surface (44a). The joining body (60) is an alloy that includes a plurality of metallic elements, is joined with the semiconductor element (20) in a first joining region (24b) of the first joining surface (24a), and is joined with the submount (40) in a second joining region (44b) of the second joining surface (44a). The semiconductor element (20) further includes an unjoined section (36) that is disposed outside the first joining region (24b) and that is formed from at least one metallic element among the plurality of metallic elements. The area of the first joining region (24b) is less than the area of the second joining region (44b).
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
93.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device (1) comprises: a Si substrate (101); a reverse-surface electrode (304) provided to the lower side of the Si substrate (101); an SiC layer (102) provided to the upper side of the Si substrate (101); a nitride semiconductor layer (103) provided to the upper side of the SiC layer (102); a source electrode (201) and a drain electrode (202) that are provided to the upper side of the nitride semiconductor layer (103); a gate electrode (203) in contact with the nitride semiconductor layer (103); an intermediate layer (105) provided to an opening (104), at which the SiC layer (102) and the nitride semiconductor layer (103) are opened; a metal layer (106) provided to the upper side of the opening (104) so as to cover the intermediate layer (105); and a conductor (303) provided inside a through-via (301) passing through the intermediate layer (105) and the Si substrate (101), the conductor (303) being electrically connected to the reverse-surface electrode (304) and the metal layer (106). The intermediate layer (105) is a metal nitride layer or a silicon oxide layer.
A semiconductor device (1) comprises: a semiconductor layer (40) that is rectangular in a plan view; a first vertical MOS transistor (10) formed in a first region (A1) of the semiconductor layer (40); and a second vertical MOS transistor (20) that is formed in a second region (A2) adjacent to the first region (A1) in a plan view. In a plan view, the first and second regions (A1, A2) are the one and the other that divide the area of the semiconductor layer (40) into two equal parts. The shape formed by a first gate wiring (114) and a first gate electrode (19) provided in the first region (A1) and the shape formed by a second gate wiring (124) and a second gate electrode (29) provided in the second region (A2) are not line-symmetrical to each other if the boundary line between the first region (A1) and the second region (A2) is the symmetry axis, and are not point-symmetrical to each other if the center of the semiconductor layer (40) is the symmetry center.
This battery pack is characterized by comprising: an assembled battery in which a plurality of power storage devices (3) are connected; a current application line which applies a current to the assembled battery; a plurality of voltage detection lines which detect the voltages of the plurality of power storage devices (3); and a battery monitoring device which measures the internal impedances of the plurality of power storage devices (3) via the current application line and the plurality of voltage detection lines. The battery pack is further characterized in that each of the plurality of power storage devices (3) has an electrode assembly obtained by alternately stacking positive electrode plates and negative electrode plates, the electrode plate located on one principal surface of the electrode assembly and the electrode plate located on the other principal surface have the same polarity, the direction of a current flowing through the positive electrode plate is opposite to the direction of a current flowing through the negative electrode plate, and the plurality of power storage devices (3) are stacked.
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
H01M 50/129 - Boîtiers primairesFourreaux ou enveloppes caractérisés par le matériau ayant une structure en couches comprenant au moins trois couches dont au moins deux couches de matériaux organiques uniquement
H01M 50/211 - Bâtis, modules ou blocs de multiples batteries ou de multiples cellules caractérisés par leur forme adaptés aux cellules en forme de poche
H01M 50/548 - Bornes caractérisées par la position des terminaux sur les cellules sur des côtés opposés de la cellule
H01M 50/55 - Bornes caractérisées par la position des terminaux sur les cellules sur le même côté de la cellule
H01M 50/569 - Détails de construction des connexions conductrices de courant pour détecter les conditions à l'intérieur des cellules ou des batteries, p. ex. détails des bornes de détection de tension
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
This ranging device (100) comprises: a light source (10) that emits emission light; a solid-state imaging element (20) having a plurality of pixels that are arranged two-dimensionally and that respectively include a photoelectric conversion element for receiving reflected light, produced by the emission light emitted by the light source (10) being reflected by an object, and converting the received reflected light into electrical charge, the solid-state imaging element (20) outputting, for each of the pixels, a signal based on the charge; a distance computation unit (50) for performing a prescribed computation on the basis of the signal outputted from the solid-state imaging element (20) for each of the pixels and thereby calculating the distance to the object for each of the pixels; a storage unit (80) for storing a corrective amount for the distance for each of the pixels, based on fixed pattern noise of the solid-state imaging element (20); and a distance correction unit (60) for correcting, for each of the pixels, the distance calculated by the distance computation unit (50), using the corrective amounts stored in the storage unit (80).
A power storage device (1) is characterized by comprising an electrode assembly (5) formed by laminating positive electrode plates (6a, 6b) that contain a positive electrode active material and a negative electrode plate (7) that contains a negative electrode active material, and is characterized in that: the positive electrode plates (6a, 6b) each have a positive electrode plate current drawing-out part (14a) for drawing out current to an end section; the negative electrode plate (7) has a negative electrode plate current drawing-out part (14b) for drawing out current to an end section; and the positive electrode plate current drawing-out part (14a) and the negative electrode plate current drawing-out part (14b) at least partially overlap with each other when the electrode assembly (5) is viewed in the lamination direction.
H01M 10/0585 - Structure ou fabrication d'accumulateurs ayant uniquement des éléments de structure plats, c.-à-d. des électrodes positives plates, des électrodes négatives plates et des séparateurs plats
H01M 50/55 - Bornes caractérisées par la position des terminaux sur les cellules sur le même côté de la cellule
H01M 50/586 - Moyens pour empêcher un usage ou une décharge indésirables pour empêcher les contacts incorrects à l’intérieur ou à l’extérieur des batteries à l’intérieur des batteries p. ex. les contacts incorrects des électrodes
H01M 50/588 - Moyens pour empêcher un usage ou une décharge indésirables pour empêcher les contacts incorrects à l’intérieur ou à l’extérieur des batteries à l’extérieur des batteries, p. ex. les contacts incorrects des bornes ou des barres omnibus
A hydrogen detection device (10) comprises a hydrogen sensor (100) as a first resistive element, a resistor (R1) as a second resistive element, a reference element (100a) as a third resistive element, and a resistor (R2) as a fourth resistive element, said resistive elements constituting a bridge circuit. At least the hydrogen sensor (100) and reference element (100a) are formed on a single semiconductor chip (12). The hydrogen sensor (100) includes: a first electrode (103) and a second electrode (106); a metal oxide layer (104); and an insulating film (107b). The insulating film (107b) has an opening (106a) that exposes the second electrode (106). The reference element (100a) includes: a first electrode (103) and a second electrode (106); a metal oxide layer (104); and an insulating film (107b). The insulating film (107b) does not have an opening that exposes the second electrode (106).
G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
G01N 27/04 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance
A cable (1) comprises a first retimer (10a), a second retimer (10b), and coaxial transmission lines (20). The first retimer (10a) and the second retimer (10b) each have a differential-to-single-ended conversion unit (11) that receives input of a differential signal to output a single-ended signal, and a single-ended-to-differential conversion unit (12) that receives input of a single-ended signal to output a differential signal. The first retimer (10a) and the second retimer (10b) are connected through the coaxial transmission lines (20).
A retimer (10) (signal processing device) comprises a reception unit (110) that receives a signal, a transmission unit (120) that transmits the signal received by the reception unit (110), and a control unit (100). The reception unit (110) comprises an equalizer circuit that compensates for attenuation in the received signal, and the transmission unit (120) has a noise cancellation circuit for suppressing noises included in the signal processed by the reception unit (110). The control unit (100) detects a threshold voltage of a transistor included in the retimer (10), and if the detected threshold voltage is equal to or smaller than a predetermined voltage value, reduces the current of the equalizer circuit such that the current is equal to or smaller than a predetermined current value and deactivates the noise cancellation circuit, or if the detected threshold voltage is larger than the predetermined voltage value, increases the current of the equalizer circuit such that the current is larger than the predetermined current value and activates the noise cancellation circuit.
brevets
