A semiconductor device includes: a Si substrate; a back electrode provided below the Si substrate; a SiC layer provided above the Si substrate; a nitride semiconductor layer provided above the SiC layer; a source electrode and a drain electrode provided above the nitride semiconductor layer; a gate electrode in contact with the nitride semiconductor layer; an intermediate layer provided in an opening that creates an opening in the SiC layer and the nitride semiconductor layer; a metal layer provided above the opening so as to cover the intermediate layer; and a conductor that is provided inside a through via that penetrates the intermediate layer and the Si substrate and is electrically connected with the back electrode and the metal layer. The intermediate layer is a metal nitride layer or a silicon oxide layer.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
A semiconductor device includes a semiconductor layer. The entire length of an outer peripheral side among outer peripheral sides of a first gate electrode region and the entire length of an outer peripheral side among outer peripheral sides of a first resistance element region match a portion of an outer peripheral side, among outer peripheral sides of the semiconductor layer, that is orthogonal to a border line and has the shortest distance to a first gate pad. Among four corner portions of an outer periphery of the first gate electrode region, only one corner portion is included in the outer peripheral sides of the first resistance element region, the only one corner portion having the shortest distance to the border line and the shortest distance to an outer peripheral side, among the outer peripheral sides of the semiconductor layer, that is orthogonal to the border line.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
H10D 64/60 - Électrodes caractérisées par leurs matériaux
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
A battery pack includes: an assembled battery in which power storage devices are connected; a current application line for applying current to the assembled battery; voltage detection lines for detecting voltages of the power storage devices; and a battery monitoring device that measures internal impedances of the power storage devices via the current application line and the voltage detection lines. Each of the power storage devices includes an electrode assembly in which a positive electrode plate and a negative electrode plate are alternately stacked, and an electrode plate on one principal surface of the electrode assembly and an electrode plate on the other principal surface of the electrode assembly have the same polarity, the direction of current that flows through the positive electrode plate is an opposite direction of the direction of current that flows through the negative electrode plate, and each of the power storage devices is stacked.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
H01M 50/129 - Boîtiers primairesFourreaux ou enveloppes caractérisés par le matériau ayant une structure en couches comprenant au moins trois couches dont au moins deux couches de matériaux organiques uniquement
H01M 50/548 - Bornes caractérisées par la position des terminaux sur les cellules sur des côtés opposés de la cellule
H01M 50/55 - Bornes caractérisées par la position des terminaux sur les cellules sur le même côté de la cellule
H05K 9/00 - Blindage d'appareils ou de composants contre les champs électriques ou magnétiques
A re-timer (a signal processing device) includes: a receiver that receives a signal; a transmitter that transmits the signal received by the receiver; and a controller. The receiver includes an equalizer circuit that compensates attenuation of the signal received. The transmitter includes a noise cancelling circuit that reduces noise included in a processed signal generated in the receiver. The controller: detects a threshold voltage of a transistor included in the re-timer; when the threshold voltage detected is lower than or equal to a predetermined voltage value, sets a current of the equalizer circuit to be lower than or equal to a predetermined current value and deactivates the noise cancelling circuit; and when the threshold voltage detected is higher than the predetermined voltage value, sets the current of the equalizer circuit to be higher than the predetermined current value and activates the noise cancelling circuit.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A cable includes a first retimer, a second retimer, and a coaxial line. Each of the first retimer and the second retimer includes: a differential-to-single-ended signal converter that receives an input of a differential signal and outputs a single-ended signal; and a single-ended-to-differential signal converter that receives an input of a single-ended signal and outputs a differential signal. The first retimer and the second retimer are connected via the coaxial line.
A hydrogen detection device includes a bridge circuit including: a hydrogen sensor that is a first resistive element; a resistor that is a second resistive element; a reference element that is a third resistive element; and a resistor that is a fourth resistive element, and at least the hydrogen sensor and the reference element are provided on a single semiconductor chip. The hydrogen sensor includes a first electrode, a second electrode, a metal oxide layer, an insulating film, or the like, and the insulating film includes an opening through which part of the second electrode is exposed. The reference element includes a first electrode, a second electrode, a metal oxide layer, an insulating film, or the like, and the insulating film includes no opening through which part of the second electrode is exposed.
G01N 27/04 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance
G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes
7.
FIXED OBJECT DETECTOR, FIXED OBJECT DETECTION METHOD, AND RECORDING MEDIUM
A fixed object detector includes: a capturing device; a fixed-object area information obtainer (a dirt area information obtainer) that searches for a fixed object candidate that is a candidate for a fixed object appearing in a video captured by the capturing device, and obtains a fixed-object area information item indicating coordinates of the fixed object candidate in the video, the fixed object having a fixed relative position with respect to the capturing device; a storage that stores therein the fixed-object area information item obtained; and an observer that determines that the coordinates indicated by the fixed-object area information item to be coordinates of the fixed object in the video and outputs a determination result, the coordinates indicated by the fixed-object area information item matching coordinates indicated by a past fixed-object area information item stored in the storage in past.
A semiconductor device includes a substrate, a back-barrier layer, a channel layer that has a band gap smaller than a band gap of the back-barrier layer, a first barrier layer that has a band gap larger than the band gap of the channel layer, a second barrier layer that is provided to fill a first recessed portion and has a band gap larger than the band gap of the channel layer, a source electrode, a drain electrode, and a gate electrode. An In composition ratio of the first barrier layer is greater than or equal to 0 and less than an In composition ratio of the second barrier layer. An Al composition ratio of the first barrier layer is greater than or equal to an Al composition ratio of the second barrier layer.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/60 - Électrodes caractérisées par leurs matériaux
A semiconductor device for high-frequency amplification includes a substrate; a first nitride semiconductor layer above the substrate; a two-dimensional electron gas layer; a second nitride semiconductor layer; and a source electrode, a drain electrode, and a gate electrode spaced apart from each other above the first nitride semiconductor layer. In a plan view, an active region with a two-dimensional electron gas layer includes a high-electron-mobility transistor and the resistor provided above the second nitride semiconductor layer. In the plan view, a non-active region includes a drain terminal and a gate terminal connected to the drain electrode or the gate electrode; and a first resistor terminal and a second resistor terminal connected to the resistor.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
A nitride semiconductor light-emitting element includes an N-type cladding layer, an N-side guide layer, an active layer, a P-type cladding layer, and a P-side guide layer (an upper P-side guide layer) and an electron blocking layer that are disposed between the active layer and the P-type cladding layer. The N-type cladding layer, the N-side guide layer, the P-side guide layer, the electron blocking layer, and the P-type cladding layer contains Al. The active layer includes an N-side barrier layer, a well layer disposed above the N-side barrier layer, and a P-side barrier layer disposed above the well layer. The average band gap energy of the P-side barrier layer is greater than the average band gap energy of the N-side barrier layer. A thickness of the P-side barrier layer is less than a thickness of the N-side barrier layer.
H10H 20/825 - Matériaux des régions électroluminescentes comprenant uniquement des matériaux du groupe III-V, p. ex. GaP contenant de l’azote, p. ex. GaN
H10H 20/816 - Corps ayant des structures contrôlant le transport des charges, p. ex. couches semi-conductrices fortement dopées ou structures bloquant le courant
H10H 20/832 - Électrodes caractérisées par leurs matériaux
An image sensor includes: a pixel array in which pixels are arranged in a matrix; impedance converter circuits for each column, each of which receives a pixel signal from at least one pixel; and an AD converter for each column that converts from analog to digital signals output from the impedance converter circuits. The pixel array includes, for each column, N pixel groups each including K or more pixels consecutively arranged in a column direction. Each of the N pixel groups includes a vertical signal line connected to L or more pixels among the K or more pixels. In each column, each of the N vertical signal lines of the N pixel groups is connected to the input of one of the impedance converter circuits, and the output of each of the impedance converter circuits is connected to the AD converter.
H04N 25/772 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F
H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N
A semiconductor device includes: a first semiconductor chip mounted onto a die pad; a second semiconductor chip mounted face down onto the first semiconductor chip and including a band gap element. The first semiconductor chip and the second semiconductor chip are electrically bonded to each other by a bonding material. A filler is disposed between the first semiconductor chip and the second semiconductor chip. When the distance from the band gap element to the bonding material is defined as r1 and the distance from the band gap element to an outline side of the first semiconductor chip is defined as r2, r1/r2≥(−0.148×r1+0.021)×r2+(0.550×r1+0.020).
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
A semiconductor device includes a semiconductor chip in a rectangular shape having longer sides extending in a first direction and shorter sides extending in a second direction. The semiconductor chip includes: a first vertical MOS transistor that includes a first gate pad and a plurality of first source pads, and a second vertical MOS transistor that includes a second gate pad and a plurality of second source pads. A plurality of first linear disposition regions in each of which source pads are linearly aligned in the first direction and a plurality of second linear disposition regions in each of which source pads are linearly aligned in the second direction are provided on an upper surface of the semiconductor chip. The semiconductor device further includes a plurality of ball-shaped bump electrodes connected to the first gate pad, the first source pads, the second gate pad, and the second source pads.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
A BMS for managing a battery assembly includes: a BMU that manages the battery assembly; and a plurality of CMUs that monitor the battery assembly. One CMU among the plurality of CMUs includes a wireless communication circuit and a timer circuit, and based on a timing at which the timer circuit times out, repeatedly transitions between a first state in which the wireless communication circuit is supplied with power and therefore capable of receiving a wake-up signal transmitted by the BMU, and a second state in which the wireless communication circuit is not supplied with power.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H02J 50/20 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant des micro-ondes ou des ondes radio fréquence
A BMS includes: a BMU that manages a battery assembly; and a plurality of CMUs that monitor the battery assembly. Among the plurality of CMUs, a first CMU includes a first wireless communication circuit and a first communication antenna for communicating with the BMU, and a second CMU includes a second wireless communication circuit and a second communication antenna for communicating with the BMU. The modulation scheme for wireless communication by the first wireless communication circuit is different from the modulation scheme for wireless communication by the second wireless communication circuit.
A BMS includes: a BMU that manages a battery assembly; a first CMU that monitors one or more battery cells included in the battery assembly; and a second CMU that monitors the one or more battery cells monitored by the first CMU. The first CMU includes a wireless communication circuit and a communication antenna for communicating with the BMU. The second cell monitoring circuit CMU includes a power line communication circuit, for communicating with the BMU, that uses a power line in the battery assembly.
A BMS for managing a battery assembly includes: a BMU that manages the battery assembly; a plurality of CMUs that monitor the battery assembly; and a setting circuit. The BMU wirelessly transmits, to the plurality of CMUs, a first signal including identification information of one CMU among the plurality of CMUs. Each of the plurality of CMUs includes identification information identifying itself, receives the first signal transmitted by the BMU, and outputs a second signal on condition that the first signal received matches the identification information. The setting circuit generates and outputs correspondence information that associates (i) position information of the one CMU, among the plurality of CMUs, that output the second signal with (ii) the identification information included in the first signal transmitted by the BMU.
G01R 31/382 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge
G01R 31/371 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge avec indication à distance, p. ex. sur des chargeurs séparés
G06T 7/70 - Détermination de la position ou de l'orientation des objets ou des caméras
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
A measurement system includes: n measurement paths that output measurement data of one or more measurement objects, where n is an integer of four or greater; m reference signal generation circuits that output reference signals to be referenced by the n measurement paths, each of the m reference signal generation circuits outputting the reference signal to two or more measurement paths among the n measurement paths, where m is an integer of two or greater; k path anomaly detection circuits that detect/confirm presence or absence of anomalies by comparing the measurement data output from two measurement paths among the n measurement paths, where k is an integer of two or greater; and a processing circuit that receives the measurement data output from the n measurement paths and outputs from the k path anomaly detection circuits as its inputs.
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
G01R 1/20 - Modifications des éléments électriques fondamentaux en vue de leur utilisation dans des appareils de mesures électriquesCombinaisons structurelles de ces éléments avec ces appareils
G01R 1/30 - Combinaison structurelle d'appareils de mesures électriques avec des circuits électroniques fondamentaux, p. ex. avec amplificateur
A semiconductor device includes: a semiconductor layer; first and second vertical MOS transistors provided in the semiconductor layer; a metal layer in contact with and connected to an entire back face of the semiconductor layer; and a support bonded to the back face side of the metal layer via a conductive adhesive. In a plan view, the support is larger in area than the semiconductor layer and encompasses the semiconductor layer. A thickness of the support is greater than a thickness of the semiconductor layer. In a cross-sectional view of the semiconductor device including a center of the semiconductor layer and an outer periphery of the semiconductor layer in the plan view, a semiconductor chip resulting from excluding the support and the conductive adhesive from the semiconductor device is in a curved shape projecting in a direction away from the support.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
A semiconductor device includes: a semiconductor layer; first and second vertical MOS transistors provided in the semiconductor layer; a metal layer connected to and in contact with an entire surface on a back face side of the semiconductor layer; and a support bonded to a back face side of the metal layer via an adhesive. In a plan view, the support is larger in area than the semiconductor layer and encompasses the semiconductor layer. A thickness of the support is greater than a thickness of the semiconductor layer. In a cross-sectional view, a height of the adhesive along a lateral face of the semiconductor layer does not reach a top face of the semiconductor layer. In the cross-sectional view, a semiconductor chip resulting from excluding the support and the adhesive from the semiconductor device is in a curved shape that projects in a direction toward the support.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A BMS for managing a battery assembly includes: a BMU that manages the battery assembly and includes a communication antenna; and one or more CMUs that monitor the battery assembly and each include a communication antenna that communicates with the communication antenna. A communication antenna group including the communication antenna and one or more communication antennas is arranged in a straight line. The BMS further includes a conductor that covers at least part of the communication antenna group. The conductor includes a recess that extends in the alignment direction of the communication antenna group and is recessed in a direction away from the communication antenna group in a cross-section orthogonal to the alignment direction.
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
B60L 58/10 - Procédés ou agencements de circuits pour surveiller ou commander des batteries ou des piles à combustible, spécialement adaptés pour des véhicules électriques pour la surveillance et la commande des batteries
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H01M 50/209 - Bâtis, modules ou blocs de multiples batteries ou de multiples cellules caractérisés par leur forme adaptés aux cellules prismatiques ou rectangulaires
H01M 50/249 - MonturesBoîtiers secondaires ou cadresBâtis, modules ou blocsDispositifs de suspensionAmortisseursDispositifs de transport ou de manutentionSupports spécialement adaptés aux aéronefs ou aux véhicules, p. ex. aux automobiles ou aux trains
H01M 50/271 - Couvercles des boîtiers secondaires, des bâtis ou des blocs
H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
A measuring device includes a voltage divider resistor component, an AD converter component, and a calculator. The voltage divider resistor component includes a plurality of voltage divider resistors that divide a voltage of a battery (object to be measured). The AD converter component includes a plurality of AD converters that convert voltages of at least two of the plurality of voltage divider resistors of the voltage divider resistor component into a plurality of first digital data items, the voltages each being a voltage across a voltage divider resistor among the at least two of the plurality of voltage divider resistors. The calculator calculates the voltage (electrical parameter) of the battery (object to be measured) from the plurality of first digital data items converted by the plurality of AD converters.
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
23.
IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD
An image processing device includes signal processors, a second-control-signal generator that generates second control signals in accordance with first control signals generated by the signal processors, and an image synthesizer. Each signal processor includes a first digital processor for performing image adjustment and a second digital processor. The second digital processor includes a defect detector that detects a defective pixel and a defective pixel adaptation processor that generates, in accordance with the result of defective pixel detection, the first control signal specifying a synthesis coefficient to the second-control-signal generator. In accordance with synthesis coefficients indicated by the second control signals, the image synthesizer synthesizes images that have undergone the image adjustment by the first digital processors of the signal processors. When the defective pixel is detected, the defective pixel adaptation processor generates the first control signal for enabling the images to include an image in which the defective pixel remains.
A semiconductor device includes: a gate electrode including a junction portion forming a Schottky junction with a barrier layer; a projecting portion including first and second gate field plates and projecting from the junction portion; and an insulating layer including first and second sidewalls. An angle formed between a highest position of a bottom surface of the first gate field plate and a main surface of a substrate, viewed from the first position, is a second elevation angle. An angle formed between an end on the drain electrode side of a lowest portion of a bottom surface of the second gate field plate and the main surface, viewed from the first position, is a third elevation angle. The second elevation angle is larger than the third elevation angle. The bottom surface of the second gate field plate includes an inclined surface where a distance from the barrier layer monotonically increases.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
A degradation estimation device includes: a first calculator that calculates a voltage change amount from a first voltage value and a second voltage value measured when the storage battery is charged and discharged; a second calculator that calculates an electric charge change amount from a first current value and a second current value when the storage battery is charged and discharged; a data storage that stores measured data that includes the voltage change amount and the electric charge change amount; a model storage that stores an estimation model that uses one or more electric charge change amounts as inputs and outputs the degradation state of the storage battery; and an estimator that estimates the degradation state of the storage battery by using the estimation model and using, as inputs, the one or more voltage change amounts and the one or more electric charge change amounts.
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge
G01R 31/367 - Logiciels à cet effet, p. ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
G01R 31/388 - Détermination de la capacité ampère-heure ou de l’état de charge faisant intervenir des mesures de tension
26.
BLOOD PRESSURE ESTIMATION DEVICE, BLOOD PRESSURE ESTIMATION METHOD, AND RECORDING MEDIUM
A blood pressure estimation device includes: a sensing module that obtains biological information of a target; a blood-pressure-estimation-model inference module that inputs the biological information of the target which has been obtained into a trained model generated through machine learning to infer a blood pressure value estimation model for the target; and a blood-pressure estimation module that estimates a blood pressure value of the target based on the biological information of the target which has been obtained and the blood pressure value estimation model for the target which has been inferred.
A semiconductor device for power amplification includes a lower electrode, a semiconductor layer, a source electrode, a drain electrode, and a gate electrode. The semiconductor layer is divided into an active region and an isolation region. A channel region includes unit channel regions that are separated by the isolation region. The source electrode includes unit source electrodes each of which faces a corresponding one of the unit channel regions. Unit source regions each include at least one source via that contains a conductor in contact with the lower electrode, the unit source regions each including a corresponding one of the unit source electrodes. In a plan view, a length of a side of a minimum rectangular region in an X-axis direction is greater than a length of a side of the minimum rectangular region in the Y-axis direction, the minimum rectangular region surrounding the at least one source via.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A semiconductor device for power amplification includes a substrate, a lower electrode, a semiconductor layer, a source electrode, a drain electrode, a gate electrode, and a field plate. The semiconductor layer is divided into an active region and an isolation region. In a plan view, a channel region includes unit channel regions that are separated by the isolation region and arranged in a Y-axis direction. The source electrode includes unit source electrodes each of which faces a corresponding one of the unit channel regions. The field plate includes unit plates each of which faces a corresponding one of the unit channel regions. At least one of plate drive lines is provided, for each of the unit plates, within the isolation region, the plate drive lines extending in an X-axis direction and electrically connecting the unit source electrodes and the unit plates.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A power amplifier semiconductor device includes: a substrate; a semiconductor layer provided on the surface of the substrate and including a plurality of unit HEMTs; a connection layer provided on the semiconductor layer and including a source electrode, a drain electrode, and a gate electrode of each of the plurality of unit HEMTs; a terminal layer provided on the connection layer; a back electrode which is provided on the bottom surface of the substrate and whose potential is set to a source potential; and substrate vias that pass through the substrate and have a shield wiring layer on inner walls of the substrate vias. In plan view, either one of the drain aggregation portion or the gate aggregation portion is or both of the drain aggregation portion and the gate aggregation portion are each surrounded by the substrate vias.
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
30.
SOLID-STATE IMAGE CAPTURING DEVICE AND CONTROL METHOD
A solid-state image capturing device includes a pixel which includes: a first photoelectric converter; a floating diffusion; a first charge accumulator including one electrode and an other electrode; a first transfer transistor including a source and a drain, one of which is connected to the first photoelectric converter and an other of which is connected to the floating diffusion; a second transfer transistor including a source and a drain, one of which is connected to the one electrode; a reset transistor including a source and a drain, one of which is connected to the other of the source and the drain of the second transfer transistor and an other of which is connected to a power supply line; and a switching transistor including a source and a drain, one of which is connected to the other electrode, and an other of which is connected to the power supply line.
H04N 25/77 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
H04N 25/59 - Commande de la gamme dynamique en commandant la quantité de charge stockable dans le pixel, p. ex. en modifiant le rapport de conversion de charge de la capacité du nœud flottant
H04N 25/709 - Circuits de commande de l'alimentation électrique
31.
DEPTH IMAGING DEVICE, PACKAGE, MODULE, AND DEPTH IMAGING SYSTEM
A depth imaging device includes: a plurality of delay adjustment circuits that adjust a delay time of each of a plurality of control signals that control a plurality of gate electrodes of a plurality of pixels and output a plurality of delayed control signals with adjusted delay times; and a plurality of drivers that receive input of the plurality of delayed control signals and output a plurality of drive signals that drive the plurality of gate electrodes of the plurality of pixels.
A solid-state imaging device includes a pixel circuit that outputs a plurality of pixel signals, a detection circuit, and a signal processor. The pixel circuit includes a photodiode, a transfer transistor that reads out a signal of the photodiode to a charge storage, and a storage capacitance that stores a charge overflowing from the photodiode. The detection circuit compares a signal of the storage capacitance with a reference signal and, when the signal of the storage capacitance has reached the reference signal, initializes the photodiode and the storage capacitance and counts an initialization count. The signal processor calculates a first signal that indicates intensity of incident light, in accordance with the initialization count and a mixed signal of the signal of the storage capacitance and the signal of the photodiode that has been read out to the charge storage by the transfer transistor.
H04N 25/59 - Commande de la gamme dynamique en commandant la quantité de charge stockable dans le pixel, p. ex. en modifiant le rapport de conversion de charge de la capacité du nœud flottant
H04N 25/42 - Extraction de données de pixels provenant d'un capteur d'images en agissant sur les circuits de balayage, p. ex. en modifiant le nombre de pixels ayant été échantillonnés ou à échantillonner en commutant entre différents modes de fonctionnement utilisant des résolutions ou des formats d'images différents, p. ex. entre un mode d'images fixes et un mode d'images vidéo ou entre un mode entrelacé et un mode non entrelacé
H04N 25/771 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des moyens de stockage autres que la diffusion flottante
H04N 25/772 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F
H04N 25/778 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des amplificateurs partagés entre une pluralité de pixels, c.-à-d. qu'au moins une partie de l'amplificateur doit se trouver sur la matrice de capteurs elle-même
33.
RADIATION DOSE DETECTION DEVICE AND RADIATION DOSE DETECTION METHOD
A radiation dose detection device includes: a power supply circuit that outputs a power supply voltage; a temperature sensor unit that functions as a first current source that outputs a first current dependent on the ambient temperature, using the power supply voltage; a radiation sensor unit that functions as a second current source that outputs a second current dependent on the dose of radiation to the radiation dose detection device, using the power supply voltage; and a detection circuit that outputs a first signal indicating the temperature corresponding to the magnitude of the first current, and a second signal indicating the dose of radiation corresponding to the magnitude of the second current. The temperature sensor unit includes one or more resistance change elements each including a variable resistance layer containing a transition metal oxide. The second current source includes a transistor.
A battery pack includes: a cell stack including secondary cells connected in series or parallel; a cell data calculator that calculates the SOC and the SOH of the secondary cells; and a first NFC unit that uses NFC to communicate with an external device regarding cell information related to the SOC and the SOH calculated by the cell data calculator.
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge
G01R 31/371 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge avec indication à distance, p. ex. sur des chargeurs séparés
G01R 31/387 - Détermination de la capacité ampère-heure ou de l’état de charge
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
35.
BATTERY PACK MANAGEMENT SYSTEM AND BATTERY PACK MANAGEMENT METHOD
A battery pack management system that manages a battery pack of storage batteries connected in series or parallel, includes: an acquisition unit (for example, a model parameter expander) that acquires respective impedances of the storage batteries corresponding to a first time point; and a generator (for example, an ID converter) that generates identification information of the battery pack based on the acquired impedances of the storage batteries.
In a neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation on input data and connection weight coefficients, a computation circuit unit that expresses one connection weight coefficient includes a plurality of selection transistors and a plurality of nonvolatile variable resistance elements. The nonvolatile variable resistance elements each express a weight coefficient with a different weight. Each of the nonvolatile variable resistance elements holds information of an upper digit of an absolute value of a positive weight coefficient, information of a lower digit of the absolute value of the positive weight coefficient, information of an upper digit of an absolute value of a negative weight coefficient, or information of a lower digit of the absolute value of the negative weight coefficient.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
37.
BATTERY MONITORING DEVICE AND BATTERY MONITORING SYSTEM
A battery monitoring device includes: a reference resistor connected to a cell stack in series; a measurement calculation unit (a voltage measurement unit, a current measurement unit, and an impedance calculation unit) configured to measure impedance of each of cells in the cell stack and impedance of the reference resistor; and a calibration unit configured to correct a gain and a phase of the impedance of each of the cells that has been measured, using the impedance of the reference resistor that has been measured.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/374 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge avec des moyens pour corriger la mesure en fonction de la température ou du vieillissement
A neural network computation circuit holds a plurality of connection weight coefficients in one-to-one correspondence with a plurality of input data items, and outputs output data according to a result of a multiply-accumulate operation on the plurality of input data items and the plurality of connection weight coefficients in one-to-one correspondence, and includes at least two bits of semiconductor storage elements provided for each of the plurality of connection weight coefficients, the at least two bits of semiconductor storage elements including a first semiconductor storage element and a second semiconductor storage element that are provided for storing the connection weight coefficient. Each of the plurality of connection weight coefficients corresponds to a total current value that is a sum of a current value of current flowing through the first semiconductor storage element and a current value of current flowing through the second semiconductor storage element.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A battery monitoring device includes a measurement unit and a calculation unit. The measurement unit includes a voltage measurement unit and a current measurement unit. The calculation unit includes: storage that holds first relationship data indicating a relationship between SOC and OCV and second relationship data indicating a relationship between impedance and SOH; an impedance calculation unit that identifies a low current interval, sets a voltage obtained during the low current interval as a provisional OCV, and calculates an impedance of secondary cells from a voltage value and a current value in a transient current response; an SOH estimate unit that estimates an SOH by referencing the second relationship data using the impedance; and an SOC estimate unit that estimates an SOC by referencing the first relationship data based on the provisional OCV.
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
G01R 31/374 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge avec des moyens pour corriger la mesure en fonction de la température ou du vieillissement
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
40.
NEURAL NETWORK COMPUTATION CIRCUIT, CONTROL CIRCUIT THEREFOR, AND CONTROL METHOD THEREFOR
A neural network computation circuit includes: a plurality of word lines; a plurality of memory cells; a word-line drive circuit; a column selection circuit; a computation circuit that performs neuron computation; a word-line selected-state signal generation circuit; a timing generation circuit; a computation-result processing circuit; and a selected word-line count management circuit that manages a selected word-line count that is information relevant to a total number of word lines that are placed in a selected state when a multiply-accumulate operation is performed, and transmits the selected word-line count to the timing generation circuit. The timing generation circuit sets, according to the selected word-line count, a delay time from when a word-line activation signal is output until when a computation-circuit control signal is output.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p. ex. neurone
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
A battery pack includes: an assembled battery in which a plurality of batteries are connected; a current applying wire for applying an electric current to the assembled battery; a plurality of voltage detecting wires for detecting voltages of the plurality of batteries; and a battery monitoring device that measures internal impedances of the plurality of batteries. The battery monitoring device is located between a positive electrode-side battery terminal and a negative electrode-side battery terminal of each of the plurality of batteries that constitute the assembled battery. The plurality of voltage detecting wires are routed radially from the battery monitoring device.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/364 - Connexions pour bornes de batteries, munies de dispositions de mesure intégrées
G01R 31/3835 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge ne faisant intervenir que des mesures de tension
H01M 50/298 - MonturesBoîtiers secondaires ou cadresBâtis, modules ou blocsDispositifs de suspensionAmortisseursDispositifs de transport ou de manutentionSupports caractérisés par le câblage des blocs de batterie
H01M 50/505 - Interconnecteurs pour connecter les bornes des batteries adjacentesInterconnecteurs pour connecter les cellules en dehors d'un boîtier de batterie comprenant une barre omnibus unique
An oscillator circuit includes an oscillator and an amplifier circuit that amplifies a voltage of the oscillator. The amplifier circuit includes a first inverter that outputs signals to a first node and a second node, a second inverter that outputs an output signal to a third node when the signals are inputted to the first node and the second node, and a variable resistor connected between the first node and the second node and controlled by a control signal.
H03B 5/24 - Élément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p. ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p. ex. alimentation, charge, température
A motor driver includes: a current detector that outputs a current signal corresponding to a motor current; a current comparison circuit that compares the current signal with a reference waveform signal; and a PWM circuit that outputs a first drive signal and a second drive signal. The first drive signal includes a first pulse that starts synchronously with a start of a reference pulse signal and ends after the pulse duration time has elapsed from a beginning of the reference pulse signal and when an absolute value of the current signal exceeds an absolute value of the reference waveform signal, and the second drive signal includes a second pulse that starts after the first pulse ends when the absolute value of the current signal exceeds the absolute value of the reference waveform signal within the pulse duration time.
An oscillator circuit includes an oscillator and an amplifier that amplifies a voltage of the oscillator. The amplifier includes an amplifier circuit that includes: an amplifier device (an inverter) that inverts and amplifies an input voltage and outputs a resulting voltage; a first element (a capacitor) connected to an input node of the amplifier device; and a second element (a capacitor) identical to the first element in type and connected between the input node and an output node of the amplifier device.
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p. ex. alimentation, charge, température
H03B 5/06 - Modifications du générateur pour assurer l'amorçage des oscillations
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A semiconductor device includes: a transistor provided in a first region of a semiconductor layer in a plan view; a transistor provided in a second region adjacent to the first region of the semiconductor layer in the plan view; and a drain pad provided in a third region not overlapping the first region and the second region in the plan view. In the plan view, the first region and the second region are one region and an other region that divide an area of the semiconductor layer excluding the third region in half. In the plan view, the transistors are arranged in a first direction. The center of the third region is located on a straight center line that divides the semiconductor layer in half in the first direction and is orthogonal to the first direction. In the plan view, the drain pad is contained in the third region.
A nitride semiconductor light-emitting element includes: a substrate comprising GaN; a first cladding layer comprising AlGaN and disposed above the substrate; an active layer disposed above the substrate; and a first semiconductor layer interposed between the first cladding layer and the active layer. The active layer includes a well layer comprising a nitride semiconductor, and a barrier layer comprising a nitride semiconductor including Al. The average band gap energy of the first semiconductor layer is smaller than the average band gap energy of the first cladding layer. The first semiconductor layer comprises AlGaInN.
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
47.
OBSTRUCTION DETECTION METHOD, RECORDING MEDIUM, AND OBSTRUCTION DETECTION DEVICE
An obstruction detection method includes: determining an exclusion depth pixel; and detecting an obstruction, based on depth pixel(s) other than the exclusion depth pixel. The determining includes performing the following: calculating an average value related to a depth pixel, based on the depth-pixel value of the depth pixel and the depth-pixel value of each of first surrounding depth pixels, and associating the average value with the depth pixel; calculating a normal line, based on the average value associated with the depth pixel and an average value associated with each of second surrounding depth pixels; determining whether an angle formed by the normal line calculated and the normal line of a predetermined reference plane is smaller than or equal to a predetermined angle; and determining the depth pixel as the exclusion depth pixel when the angle is determined to be smaller than or equal to the predetermined angle.
G06V 10/26 - Segmentation de formes dans le champ d’imageDécoupage ou fusion d’éléments d’image visant à établir la région de motif, p. ex. techniques de regroupementDétection d’occlusion
G06T 7/50 - Récupération de la profondeur ou de la forme
G06V 10/75 - Organisation de procédés de l’appariement, p. ex. comparaisons simultanées ou séquentielles des caractéristiques d’images ou de vidéosApproches-approximative-fine, p. ex. approches multi-échellesAppariement de motifs d’image ou de vidéoMesures de proximité dans les espaces de caractéristiques utilisant l’analyse de contexteSélection des dictionnaires
A nitride semiconductor light-emitting element includes: an N-type cladding layer; an N-side guide layer disposed above the N-type cladding layer; an active layer disposed above the N-side guide layer; a first P-side guide layer disposed above the active layer; an electron barrier layer disposed above the first P-side guide layer; a second P-side guide layer disposed above the electron barrier layer; and a P-type cladding layer disposed above the second P-side guide layer. An average band gap energy of the second P-side guide layer is greater than an average band gap energy of the first P-side guide layer. An average band gap energy of the P-type cladding layer is less than an average band gap energy of the electron barrier layer.
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
H01S 5/30 - Structure ou forme de la région activeMatériaux pour la région active
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
A semiconductor device includes: a lead frame; a first semiconductor chip mounted face-up above the lead frame; and a second semiconductor chip mounted face-down above the first semiconductor chip. The second semiconductor chip has a chip size smaller than a chip size of the first semiconductor chip. The second semiconductor chip includes a bandgap element (an NPN transistor, an N-parallel NPN transistor) including a positive-negative (PN) junction and included in a band gap reference circuit.
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
50.
SEMICONDUCTOR LASER ELEMENT AND METHOD FOR MANUFACTURING THE SAME
A semiconductor laser element includes a substrate and a semiconductor stacked structure that is provided on one face of the substrate. The semiconductor stacked structure includes an optical waveguide. A pair of first recesses are provided in an other face of the substrate, the pair of first recesses extending in the resonator length direction. Both end portions of each of the pair of first recesses are located in positions recessed from end faces of the semiconductor stacked structure. Second recesses are provided in the semiconductor stacked structure, the second recesses extending from the end faces of the semiconductor stacked structure in the resonator length direction. In a top view, the second recesses are provided on both sides of the optical waveguide, and are each provided between a corresponding one of the pair of first recesses and the optical waveguide.
A gas detection system is for detecting the remaining amount of gas in a gas tank that stores a predetermined gas. The gas detection system includes: a gas detector that detects the predetermined gas; and a shutter (e.g., a pressure detector) that is connected between the gas tank and the gas detector and opens and closes a path of the predetermined gas from the gas tank to the gas detector.
A hydrogen detection method is a method performed using a hydrogen sensor that includes: a metal oxide layer; a second electrode that is in surface contact with the metal oxide layer; a first terminal connected to the second electrode; and a second terminal connected to the second electrode. The hydrogen detection method includes: applying a first voltage pulse between the first terminal and the second terminal to cause a chemical reaction of the metal oxide layer to hydrogen; and applying a second voltage pulse between the first terminal and the second terminal after the applying of the first voltage pulse, to detect a change in resistance between the first terminal and the second terminal. The amplitude of the second voltage pulse is smaller than the amplitude of the first voltage pulse.
G01N 27/04 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance
G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes
53.
STORAGE BATTERY CAPACITY ESTIMATION DEVICE AND SYSTEM
An estimation device includes a measurement data storage storing measurement data items including: the first smoothed voltage value of a storage battery, a smoothed voltage change amount obtained by subtracting the first smoothed voltage value from the second smoothed voltage value of the storage battery, and a smoothed current value measured in synchronization with measurement of the first smoothed voltage value or the second smoothed voltage value, estimates an accumulated charge change amount using a trained estimation model that receives a first smoothed voltage value in a predetermined voltage range, a smoothed voltage change amount, and a smoothed current value, updates the trained estimation model using, as correct answer data, an accumulated charge change amount obtained by integrating current values measured during obtainment of the smoothed voltage change amount, and calculates the total sum of estimated accumulated charge change amounts in the predetermined voltage range to obtain the battery status.
G01R 31/388 - Détermination de la capacité ampère-heure ou de l’état de charge faisant intervenir des mesures de tension
G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge
G01R 31/367 - Logiciels à cet effet, p. ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
An impedance measurement device includes: a switching circuit that forms a loop circuit together with a battery; a current measurer connected to a path connecting the battery and the switching circuit; and a voltage measurement device connected to both ends of the battery, in which the switching circuit generates a current flowing intermittently through the loop circuit from the battery, and the impedance measurement device: changes a time during which the current flows intermittently and a time during which the current does not flow to sweep a frequency of an alternating current from the battery; and measures the alternating current using the current measurer and measures an alternating current voltage of the battery using the voltage measurement device to derive an alternating current impedance of the battery.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
A semiconductor device includes a vertical field-effect transistor including: a first gate trench and a second gate trench extending in a first direction, the second gate trench being deeper than the first trench; a first gate insulating film and a first gate conductor inside the first gate trench; and a second gate insulating film and a second gate conductor inside the second gate trench. The first gate conductor and the second gate conductor have the same potential. When a total number of first gate trenches is denoted by n, a total number of second gate trenches is at least 2 and at most n+1. In a second direction orthogonal to the first direction, the second gate trench is disposed at each of farthest ends of a region in which the first gate trenches and the second gate trenches are disposed.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
A semiconductor device that is a facedown mountable, chip-size-package type semiconductor device, the semiconductor device including: a semiconductor substrate; and a metal layer that is disposed on the semiconductor substrate and is exposed to outside. One or more marks are provided on an exposed surface of the metal layer. The one or more marks each include an outline portion defining an outline of the mark, and a central portion located inward of the outline portion. In a plan view of the exposed surface of the metal layer, the outline portion has a color different from at least one of a color of the central portion or a color of a base portion that is a portion of the exposed surface of the metal layer on which the one or more marks are not provided.
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
B23K 26/073 - Détermination de la configuration du spot laser
B23K 26/18 - Travail par rayon laser, p. ex. soudage, découpage ou perçage utilisant des couches absorbantes sur la pièce à travailler, p. ex. afin de marquer ou de protéger
B23K 26/40 - Enlèvement de matière en tenant compte des propriétés du matériau à enlever
B23K 101/00 - Objets fabriqués par brasage, soudage ou découpage
A power storage pack includes: a power storage cell; a power storage tab; a protection circuit substrate; a semiconductor element; and a metal plate for power storage tab joint that is connected to the semiconductor element on the first main surface of the metal plate for power storage tab joint and that includes a portion whose thickness is at most 0.2 mm. The metal plate for power storage tab joint is joined to the power storage tab on the second main surface of the metal plate for power storage tab joint to include an overlap portion in which the power storage tab, the metal plate for power storage tab joint, the semiconductor element, and the protection circuit substrate overlap each other; and there is a portion in which a region that may be the conduction path between the power storage tab and the protection circuit substrate overlaps the overlap portion.
A motor driving device includes: a rotor position detector that detects a rotor position of the motor; a first waveform generator that generates a first reference waveform based on the rotor position; a second waveform generator that generates a second reference waveform based on the rotor position, the second reference waveform being different from the first reference waveform; a waveform outputter that outputs, as an output waveform, the first reference waveform, the second reference waveform, or a composite waveform of the first reference waveform and the second reference waveform, based on the torque command value; and a current supplier that supplies, to the motor, a motor current generated based on the output waveform. In the motor driving device, the waveform outputter changes a composite ratio between the first reference waveform and the second reference waveform in the composite waveform, according to the torque command value.
A nitride-based semiconductor light-emitting element includes: a substrate that is an example of a n-type nitride-based semiconductor including a group IV n-type impurity; and an n-side electrode in contact with the substrate. The substrate includes: a surface layer region in contact with the n-side electrode and including a halogen element; and an internal region located across the surface layer region from the n-side electrode. A peak concentration of the group IV n-type impurity in the surface layer region is at least 1.0×1021 cm−3. A peak concentration of the halogen element in the surface layer region is at least 10% of the peak concentration of the group IV n-type impurity in the surface layer region. A concentration of the group IV n-type impurity in the internal region is lower than a concentration of the group IV n-type impurity in the surface layer region.
H01L 33/02 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
H01L 33/20 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une forme particulière, p.ex. substrat incurvé ou tronqué
H01L 33/32 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique contenant de l'azote
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
60.
ARTIFICIAL INTELLIGENCE PROCESSING DEVICE AND TRAINING INFERENCE METHOD FOR ARTIFICIAL INTELLIGENCE PROCESSING DEVICE
An artificial intelligence processing device includes: a first variable-resistance nonvolatile storage element and a second variable-resistance nonvolatile storage element having different properties and provided on a single substrate. When successive applications of a voltage pulse with a same polarity and a same voltage are made, a proportion of an amount of change in conductance caused by a second application of the voltage pulse relative to an amount of change in conductance caused by a first application of the voltage pulse in the first variable-resistance nonvolatile storage element is less than a proportion of an amount of change in conductance caused by a second application of the voltage pulse relative to an amount of change in conductance caused by a first application of the voltage pulse in the second variable-resistance nonvolatile storage element.
A semiconductor memory device includes memory cells, a first power supply line, a second power supply line, a first transistor and a second transistor that are connected in parallel between the first power supply line and the second power supply line, and a control circuit. In accordance with a first signal for switching between a first mode and a second mode, the control circuit (i) switches off the first transistor and the second transistor in the period of the second mode and (ii) switches on the first transistor when switching from the second mode to the first mode is performed and switches on the second transistor after the first transistor is switched on, the first mode being a mode for supplying the power supply voltage to the memory cells, the second mode being a mode for not supplying the power supply voltage to memory cells.
A motor driving device includes: a series circuit of a Zener diode and a detection resistor, connected between a gate terminal and a ground of a first high-side transistor; a comparator that compares a voltage of the detection resistor with a reference voltage; a first driving transistor that short-circuits between the gate and source terminals of the first high-side transistor, using a detection signal output by the comparator; a control circuit; and an OR circuit that puts the first driving transistor into an open state regardless of a drive signal from the control circuit. The motor driving device puts the first high-side transistor into a conducting state when a power supply voltage increases and the gate terminal of the first high-side transistor reaches or exceeds a predetermined voltage, to inhibit an increase in the power supply voltage.
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
H03K 17/30 - Modifications pour fournir un seuil prédéterminé avant commutation
A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon;
A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon;
forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A semiconductor light-emitting element includes: a semiconductor stack; a contact electrode disposed above the semiconductor stack; and a pad layer disposed above the contact electrode and containing Au. The pad layer includes a first layer disposed above a region in which the pad layer and the contact electrode are in contact with each other, and a second layer disposed above the first layer and in contact with the first layer. In a direction parallel to a principal surface of the contact electrode, a mean grain size of Au in the second layer is larger than a mean grain size of Au in the first layer.
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
65.
HYDROGEN DETECTION DEVICE AND CONTROL METHOD FOR HYDROGEN DETECTION DEVICE
A hydrogen detection device includes a hydrogen sensor and a detection circuit, wherein the hydrogen sensor includes: a first electrode; a second electrode; a metal oxide layer; a first insulating film (insulating film); a first terminal and a second terminal that are connected, through a via, to an other surface of the second electrode opposite a principal surface of the second electrode; and a third terminal connected, through a via, to an other surface of the first electrode opposite a principal surface of the first electrode, and the detection circuit includes: an ammeter that measures (1) a first resistance value between the first terminal and the second terminal and (2) a second resistance value between the third terminal and at least one of the first terminal or the second terminal; and a control circuit that selectively outputs one of the first resistance value or the second resistance value.
G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes
66.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: a substrate; a buffer layer; an intermediate layer; an electron transport layer; an electron supply layer; a source electrode and a drain electrode; and a gate electrode. The intermediate layer includes a stack resulting from stacking a first intermediate layer and a second intermediate layer. The second intermediate layer is provided above the first intermediate layer. A first position that is 100 nm above a lower surface of the intermediate layer is in the first intermediate layer. A second position that is 100 nm below an upper surface of the intermediate layer is in the second intermediate layer. A value obtained by dividing a density of edge screw mixed dislocations with a Burgers vector of <11-23>/3 at the second position by a density of edge screw mixed dislocations with the Burgers vector of <11-23>/3 at the first position is at most 0.66.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer; a source electrode and a drain electrode; and a gate electrode that is spaced apart from the source electrode and the drain electrode, and is in contact with the second nitride semiconductor layer. The gate electrode includes: a first barrier layer that includes TaN, has a layer thickness of Z1, and forms a Schottky junction with the second nitride semiconductor layer; a second barrier layer that is disposed above and in contact with the first barrier layer, includes TiN or WN, and has a layer thickness of Z2; and a wiring layer disposed above and in contact with the second barrier layer. In the semiconductor device, 200 nm≥Z1+Z2≥50 nm, Z1Z1>3 nm are satisfied.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
A variable capacitance element includes a substrate, a first semiconductor layer, a two-dimensional electron gas layer, a first electrode including a first terminal, and a second terminal. The two-dimensional electron gas layer below the first electrode functions as a second electrode. The interval between the bottom surface of the first electrode and the top surface of the first semiconductor layer monotonically increases in a first direction from the first electrode toward the second terminal or in a second direction orthogonal to the first direction. A capacitance value between the first electrode and the second electrode changes according to the voltage applied between the first electrode and the second terminal.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
A nitride semiconductor light-emitting element includes: an n-side semiconductor layer; one or more light-emitting layers disposed above the n-side semiconductor layer; a first barrier layer disposed above the one or more light-emitting layers and including Al; a second barrier layer disposed above the first barrier layer and including Al; a p-side guiding layer disposed above the second barrier layer and having an Al composition ratio smaller than an Al composition ratio of the second barrier layer; an electron blocking layer disposed above the p-side guiding layer, including Mg, and having an Al composition ratio larger than the Al composition ratio of the second barrier layer; and a p-side semiconductor layer disposed above the electron blocking layer.
H01L 33/14 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure contrôlant le transport des charges, p.ex. couche semi-conductrice fortement dopée ou structure bloquant le courant
H01L 33/32 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique contenant de l'azote
A nitride semiconductor light-emitting element includes: an N-type first cladding layer; an N-side guide layer; an active layer that includes a well layer and a barrier layer, and has a quantum well structure; a P-side guide layer; and a P-type cladding layer. A band gap energy of the N-side guide layer monotonically increases with increasing distance from the active layer, the N-side guide layer includes a portion in which the band gap energy continuously increases with increasing distance from the active layer, an average band gap energy of the P-side guide layer is larger than or equal to an average band gap energy of the N-side guide layer, and Tn
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
H01S 5/40 - Agencement de plusieurs lasers à semi-conducteurs, non prévu dans les groupes
A voltage measurement device individually detects, in a cell stack of n (n is an integer greater than or equal to two) battery cells connected in series, a voltage of each of the n battery cells, and includes: n+1 resistor elements, first terminals of which are connected to a positive electrode of an upper-end battery cell among the n battery cells, a negative electrode of a lower-end battery cell among the n battery cells, and connection points between the n battery cells; n+1 capacitors, first terminals of which are respectively connected to second terminals of the n+1 resistor elements; and a voltage measurer connected to the second terminals of the n+1 resistor elements. Second terminals of two or more capacitors among the n+1 capacitors are connected to a positive electrode of a k-th battery cell (k is an integer; 1≤k≤n−1) among the n battery cells.
H01M 50/569 - Détails de construction des connexions conductrices de courant pour détecter les conditions à l'intérieur des cellules ou des batteries, p. ex. détails des bornes de détection de tension
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
A semiconductor device includes a vertical field-effect transistor including: a low-concentration impurity layer; a body region; a gate trench; a gate insulating film; and a gate conductor. The body region includes: a first body portion containing an active region and has a constant depth; and a second body portion adjacent to the first body portion and includes a zone that has a limited length in a second direction orthogonal to the first direction along the top surface of the low-concentration impurity layer, and has a constant depth at a position shallower than the constant depth of the first body portion. The second body portion includes a portion in which a region having relatively high concentration of an impurity and a region having relatively low concentration of an impurity are alternately and periodically present in the first direction in a cross-sectional view of a plane orthogonal to the second direction.
A radio-frequency power amplifier device includes: a carrier amplifier semiconductor device and a peak amplifier semiconductor device on a multilayer submount substrate; a bias power supply semiconductor device; second radio-frequency signal wiring that transmits radio-frequency signal to the carrier amplifier semiconductor device and the peak amplifier semiconductor device; and carrier-amplifier bias power supply wiring that is wired in a third wiring layer and supplies a bias power supply voltage. The second radio-frequency signal wiring and the carrier-amplifier bias power supply wiring intersect in a plan view. The radio-frequency power amplifier device includes: a shield pattern that is located in a second wiring layer between a first wiring layer and the third wiring layer; and one or more connection vias disposed in an extension direction of the carrier-amplifier bias power supply wiring. The one or more connection vias are connected to the shield pattern.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/26 - Modifications des amplificateurs pour réduire l'influence du bruit provoqué par les éléments amplificateurs
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
A phase-locked loop (PLL) circuit generates an output clock signal and includes: a selection circuit that selects one of a plurality of clock signals as a reference clock signal of the PLL circuit; and a control circuit that when a switch is made for the selection of the reference clock signal, temporarily reduces a division ratio used by a frequency divider that generates a feedback clock signal to be compared with the reference clock signal.
A semiconductor laser device includes: a pedestal; a submount that is joined to the pedestal via solder; and a semiconductor laser that is mounted on the submount. When a view of the submount from a side on which the semiconductor laser is mounted is defined as a top view, in the top view: the solder includes a plurality of protruding portions; and the plurality of protruding portions are provided on the pedestal outside the submount, protrude in directions away from an inside of the submount, and are located at regular intervals on at least a portion of a periphery of the submount.
H01S 5/02212 - SupportsBoîtiers caractérisés par la forme des boîtiers du type CAN, p. ex. boîtiers TO-CAN avec émission le long ou parallèlement à l’axe de symétrie
A hydrogen sensor includes a first electrode that is a planar electrode; a second electrode that is a planar electrode facing the first electrode and includes an exposed portion to be exposed to a gas containing hydrogen; a metal oxide layer disposed between the two facing surfaces of the first electrode and the second electrode and having the resistance value that is changed by the exposed portion being exposed to the gas; a first terminal, a second terminal, and a heat dissipation portion spaced apart from each other; one or more first vias provided above the second electrode and electrically connected to the first terminal and the second electrode; one or more second vias provided above the second electrode and electrically connected to the second terminal and the second electrode; and one or more third vias above the second electrode and in contact with the heat dissipation portion.
G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
77.
DISTANCE MEASURING DEVICE AND DISTANCE MEASUREMENT METHOD
A distance measuring device includes: a light source that emits irradiation light; a solid-state imaging device that generates, for each of pixels, a plurality of packets that hold signal charges generated at different exposure timings for the irradiation light; and a signal processing circuit that calculates a distance value based on the plurality of packets. For each of the pixels, the signal processing circuit: determines presence or absence of stray light using the plurality of packets corresponding to the pixel; when it is determined that there is no stray light, calculates a distance value of the pixel using a first process; and when it is determined that there is stray light, calculates a distance value of the pixel using a second process different from the first process.
G01S 17/10 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes à modulation d'impulsion interrompues
G01S 17/32 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées
A solid-state imaging device includes: a plurality of pixel circuits arranged in rows and columns; a plurality of selector circuits that each receive, as inputs, two pixel signals corresponding to two columns different from each other; k column AD conversion circuits that perform AD conversion on pixel signals output from the plurality of selector circuits, k being an integer greater than or equal to two; and m column AD conversion circuits that are provided redundantly. In the solid-state imaging device, the plurality of selector circuits selectively exclude, from among the k column AD conversion circuits and the m column AD conversion circuits, m column AD conversion circuits corresponding to m columns adjacent to each other, and associate k pixel signals output from the plurality of pixel circuits with k column AD conversion circuits which have not been excluded.
H04N 25/68 - Traitement du bruit, p. ex. détection, correction, réduction ou élimination du bruit appliqué aux défauts
H04N 25/771 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des moyens de stockage autres que la diffusion flottante
H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N
79.
THREE-DIMENSIONAL RANGING MODULE AND THREE-DIMENSIONAL RANGING SYSTEM
A three-dimensional ranging module includes: a light source that emits a laser beam; a lens module including: a lens that collects light resulting from the laser beam emitted being reflected off an object; an imaging element that receives the light collected by the lens; and a lens tube surrounding a space between the lens and the imaging element and supporting the lens; and a lens cover positioned between the lens module and the object and transparent to a wavelength range of the laser beam. In a cross section obtained when the lens tube is cut along a plane including an optical axis of the lens, a first surface of the lens tube that faces the object includes a first slope portion sloping away from the lens cover with an increase in distance from the optical axis.
An object detection device includes: a light emitter that emits light; a sensor that generates a first pixel signal by exposure to reflected light according to a combination of emission by the light emitter and first exposure and a second pixel signal by exposure to reflected light according to a combination of the emission and second exposure; and a distance calculator that generates a distance image by ratio operation using the first pixel signal and the second pixel signal. Timing of the first exposure is set to timing during which the sensor is not exposed to reflected waves from an object included in a first section in which a distance from the object detection device is from 0 to a predetermined value. A time difference between the emission and the second exposure is greater than a time difference between the emission and the first exposure.
G01S 17/86 - Combinaisons de systèmes lidar avec des systèmes autres que lidar, radar ou sonar, p. ex. avec des goniomètres
H04N 13/207 - Générateurs de signaux d’images utilisant des caméras à images stéréoscopiques utilisant un seul capteur d’images 2D
H04N 13/254 - Générateurs de signaux d’images utilisant des caméras à images stéréoscopiques en combinaison avec des sources de rayonnement électromagnétique pour l’éclairage du sujet
H04N 23/45 - Caméras ou modules de caméras comprenant des capteurs d'images électroniquesLeur commande pour générer des signaux d'image à partir de plusieurs capteurs d'image de type différent ou fonctionnant dans des modes différents, p. ex. avec un capteur CMOS pour les images en mouvement en combinaison avec un dispositif à couplage de charge [CCD] pour les images fixes
H04N 23/56 - Caméras ou modules de caméras comprenant des capteurs d'images électroniquesLeur commande munis de moyens d'éclairage
H04N 23/73 - Circuits de compensation de la variation de luminosité dans la scène en influençant le temps d'exposition
81.
ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND CURRENT MEASUREMENT CIRCUIT
An analog-to-digital conversion circuit includes: a first variable gain amplifier connected to an input terminal; a first AD converter connected to the first variable gain amplifier; a second variable gain amplifier connected to the input terminal; a second AD converter connected to the second variable gain amplifier; a selection circuit to which an output of the first AD converter and an output of the second AD converter are input, and which selects one of the outputs; and a control circuit that controls a gain change period of the first variable gain amplifier and a gain change period of the second variable gain amplifier in a relative manner.
A distance measurement device determines, out of pixels, first pixels that are readout targets and second pixels that are not readout targets; performs, on each of the first pixels, exposure operations of n types at different timings where n is an integer of at least 4; and reading out signal charges of n types to n packets in each of vertical transfer portions, the signal charges of the n types being generated through the exposure operations of the n types. Within a region in which the vertical transfer portions are disposed, a first region in which the n packets are created is adjacent to a pixel region in which m pixels are consecutively disposed in a vertical direction where m is an integer of at least 3. The m pixels include at least one of the first pixels and at least one of the second pixels.
G01S 17/10 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes à modulation d'impulsion interrompues
G01S 7/4914 - Réseaux des détecteurs, p. ex. portes de transfert de charge
G01S 17/89 - Systèmes lidar, spécialement adaptés pour des applications spécifiques pour la cartographie ou l'imagerie
A nitride semiconductor light-emitting element includes: a nitride semiconductor that has two resonator faces opposed to each other; and a dielectric multilayer film that is layered on at least one resonator face of the two resonator faces. For example, the dielectric multilayer film layered on a resonator face includes a first dielectric film layered on the resonator face and a second dielectric film layered on the first dielectric film. The first dielectric film includes aluminum oxynitride. The second dielectric film includes aluminum oxide. The first dielectric film is a crystalline film. At least one of chemical elements of yttrium or lanthanum is added to the first dielectric film. At least one of chemical elements of yttrium or lanthanum is added to the second dielectric film.
H01L 33/32 - Matériaux de la région électroluminescente contenant uniquement des éléments du groupe III et du groupe V de la classification périodique contenant de l'azote
H01L 33/16 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les corps semi-conducteurs ayant une structure cristalline ou une orientation particulière, p.ex. polycristalline, amorphe ou poreuse
H01L 33/44 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les revêtements, p.ex. couche de passivation ou revêtement antireflet
A solid-state imaging device includes a plurality of pixel circuits arranged in rows and columns; and a relief unit which includes N signal lines and n pixel circuits among the plurality of pixel circuits, N being an integer greater than or equal to 3, n being an integer less than or equal to N. Each of the n pixel circuits is connected to a group of at least two signal lines out of the N signal lines, and selectively outputs a pixel signal to one of the at least two signal lines included in the group; and n groups corresponding to the n pixel circuits have mutually different combinations of signal lines, the n groups each being the group.
A solid-state imaging apparatus includes a pixel circuit, a detection and selection circuit, and an AD conversion circuit. The pixel circuit outputs a plurality of pixel signals corresponding to mutually different gains or sensitivities. The detection and selection circuit compares one or more of the plurality of pixel signals with a reference value to generate a signal selection signal that instructs selection of a pixel signal among the plurality of pixel signals. The detection and selection circuit includes a sample and hold circuit that holds the plurality of pixel signals, and selects at least one pixel signal among the plurality of pixel signals held in the sample and hold circuit based on the signal selection signal. The detection and selection circuit is arranged in a stage before the AD conversion circuit that AD converts the at least one pixel signal selected.
H04N 25/772 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F
A battery anomaly detection device includes: an alternating-current (AC) impedance measurer that measures AC impedance of a battery cell; and an anomaly determiner that determines whether the AC impedance is within a reference range, and when the AC impedance is not within the reference range, determines that the battery cell is an anomalous cell.
An object detecting device includes: a first luminance obtainer and a distance obtainer that obtain a first luminance image and a depth image, respectively; a first clustering unit that generates a group that is a set of pixels taken as the same object in the depth image, and determines that the group is a cluster when a total number of pixels included in the group is at least a first threshold; a second clustering unit that determines that the group is a cluster, when (i) the total number of pixels included in the group is less than the first threshold and (ii) luminance of a pixel group in the first luminance image which corresponds to the group is at least a second threshold; and a 3D object detector that generates 3D object information indicating an object in the depth image which is detected based on the cluster.
G01S 7/48 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe
G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p. ex. caméras à temps de vol ou lidar flash
G06V 10/60 - Extraction de caractéristiques d’images ou de vidéos relative aux propriétés luminescentes, p. ex. utilisant un modèle de réflectance ou d’éclairage
G06V 10/762 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant le regroupement, p. ex. de visages similaires sur les réseaux sociaux
G06V 10/80 - Fusion, c.-à-d. combinaison des données de diverses sources au niveau du capteur, du prétraitement, de l’extraction des caractéristiques ou de la classification
A solid-state imaging device includes a pixel array that is quadrilateral and includes pixels arranged in rows and columns, where each of the pixels accumulates an electric charge resulting from photoelectric conversion. The pixel array includes: a first area including first pixels for obtaining a captured image; and a second area including a second pixel for individually identifying the solid-state imaging device. The second area is provided in the vicinity of at least one corner among four corners of the pixel array, where the vicinity is a range of a predetermined number of pixels away from the at least one corner. The second pixel includes circuit elements or optical elements different from circuit elements or optical elements in each of the first pixels.
H04N 25/778 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des amplificateurs partagés entre une pluralité de pixels, c.-à-d. qu'au moins une partie de l'amplificateur doit se trouver sur la matrice de capteurs elle-même
H04N 25/79 - Agencements de circuits répartis entre des substrats, des puces ou des cartes de circuits différents ou multiples, p. ex. des capteurs d'images empilés
89.
BATTERY STATE ESTIMATION DEVICE, BATTERY STATE ESTIMATION SYSTEM, AND BATTERY STATE ESTIMATION METHOD
A battery state estimation device includes: a first state of charge (SOC) calculator that calculates a first SOC using a first method that uses the battery model parameter of a battery; a second SOC calculator that calculates a second SOC using a second method different from the first method; an alternating-current (AC) impedance measurement unit that measures the AC impedance of the battery when the error between the first SOC and the second SOC is greater than a predetermined threshold; and a battery model parameter calculator that calculates a battery model parameter using the measured AC impedance. The first SOC calculator recalculates the first SOC using the battery model parameter calculated.
A solid-state imaging apparatus includes a pixel circuit that outputs a pixel signal and a negative feedback circuit. The negative feedback circuit includes a sample and hold circuit (hereinafter “SH circuit”) that samples and holds the pixel signal, and a feedback amplifier that negatively feeds back, to the SH circuit, a feedback signal according to a difference between the pixel signal from the pixel circuit and an output signal from the SH circuit.
H04N 25/65 - Traitement du bruit, p. ex. détection, correction, réduction ou élimination du bruit appliqué au bruit de réinitialisation, p. ex. le bruit KTC lié aux structures CMOS par des techniques autres que le CDS
G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p. ex. caméras à temps de vol ou lidar flash
H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N
H04N 25/79 - Agencements de circuits répartis entre des substrats, des puces ou des cartes de circuits différents ou multiples, p. ex. des capteurs d'images empilés
91.
Semiconductor laser element, testing method, and testing device
A semiconductor laser element that includes a semiconductor layer including a waveguide formed in an intra-layer direction of the semiconductor layer and a window region formed in a front-side end face of the waveguide, has a current-laser optical output characteristic in which, at an operating temperature of 25° C.±3° C., a laser optical output has a maximum value at a first driving current value and the laser optical output is at most 20% of the maximum value at a second driving current value greater than the first driving current value, and is not damaged at the second driving current value.
H01S 5/02 - Détails ou composants structurels non essentiels au fonctionnement laser
H01S 5/026 - Composants intégrés monolithiques, p. ex. guides d'ondes, photodétecteurs de surveillance ou dispositifs d'attaque
H01S 5/16 - Lasers du type à fenêtre, c.-à-d. avec une région en un matériau non absorbant entre la région active et la surface réfléchissante
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
H01S 5/22 - Structure ou forme du corps semi-conducteur pour guider l'onde optique ayant une structure à nervures ou à bandes
H01S 5/32 - Structure ou forme de la région activeMatériaux pour la région active comprenant des jonctions PN, p. ex. hétérostructures ou doubles hétérostructures
A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon; forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A radio-frequency power amplifier device includes: a carrier amplifier semiconductor device and a peak amplifier semiconductor device on a multilayer submount substrate; a bias power supply semiconductor device; second radio-frequency signal wiring that transmits a radio-frequency signal to the carrier amplifier semiconductor device and the peak amplifier semiconductor device; and carrier-amplifier bias power supply wiring that is wired in a third wiring layer and supplies a bias power supply voltage. The second radio-frequency signal wiring and the carrier-amplifier bias power supply wiring intersect in a plan view. The radio-frequency power amplifier device includes: a shield pattern that is located in a second wiring layer between a first wiring layer and the third wiring layer; and one or more connection vias disposed in an extension direction of the carrier-amplifier bias power supply wiring. The one or more connection vias are connected to the shield pattern.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/26 - Modifications des amplificateurs pour réduire l'influence du bruit provoqué par les éléments amplificateurs
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
95.
CURRENT LEAKAGE DETECTION CIRCUIT, AND BATTERY STATE DETECTION CIRCUIT
A current leakage detection circuit that detects current leakage from a battery having a first electrode and a second electrode, which is either the positive electrode or the negative electrode opposite to the first electrode, to a chassis includes: a detection circuit including a reference voltage source terminal, a first detection terminal, and a ground terminal connected to the first electrode; a first resistor connected between the second electrode and the chassis; a second resistor connected between the chassis and the first detection terminal; and a third resistor connected between the first detection terminal and a predetermined terminal. When the first electrode is the positive electrode, the predetermined terminal is the reference voltage source terminal. When the first electrode is the negative electrode, the predetermined terminal is the first electrode. The detection circuit detects an occurrence of current leakage based on a voltage of the first detection terminal.
G01R 31/52 - Test pour déceler la présence de courts-circuits, de fuites de courant ou de défauts à la terre
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
96.
SEMICONDUCTOR LASER LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LASER LIGHT-EMITTING DEVICE
A semiconductor laser light-emitting device includes: a mounting base (mounting substrate); a submount disposed above the mounting base; a connecting member that connects the mounting base and the submount and is composed of a porous metal material; and a semiconductor laser disposed above the submount. The submount includes a front face that is a face on the light emission side of the semiconductor laser. The connecting member includes a peripheral portion that continuously covers at least part of the front face of the submount and the peripheral area of a first area of the top surface of the mounting base, where the first area corresponds to the submount. The top surface of the peripheral portion is straight or recessed at a cross section that intersects the front face of the submount and the top surface of the mounting base.
An analog-to-digital conversion circuit includes: a variable gain amplifier; a delta-sigma modulator that modulates an output of the variable gain amplifier to a pulse density modulation (PDM) signal; and a decimation filter that downsamples the PDM signal to output a first digital signal that is converted into a multi-bit digital signal. The decimation filter includes: a weight change unit that converts the PDM signal into a second digital signal that is weighted by multiplying a weight of the PDM signal by a reciprocal of an amplification factor of the variable gain amplifier; and a first digital filter that receives the second digital signal as an input, and outputs the first digital signal.
A voltage measurement device measures the voltage of at least one of series-connected battery cells, and includes one or more voltage detection circuits. Each voltage detection circuit includes: a first communication path; a mode control circuit that switches a mode of operation of the voltage detection circuit between normal and low-power modes; a first communication control circuit (communication control circuit) that transmits and receives a command signal to and from the first communication path; an activation signal detection circuit that detects an activation signal input from the first communication path; and an alarm generation circuit that, in the low-power mode, generates and outputs an alarm signal indicating an anomaly in the battery cells to the first communication path. In the low-power mode, when the activation signal detection circuit detects the activation signal, the mode control circuit switches the mode of operation to the normal mode.
G01R 31/371 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge avec indication à distance, p. ex. sur des chargeurs séparés
G01R 31/3835 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge ne faisant intervenir que des mesures de tension
G01R 31/396 - Acquisition ou traitement de données pour le test ou la surveillance d’éléments particuliers ou de groupes particuliers d’éléments dans une batterie
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
A nitride semiconductor light-emitting element includes: an N-type cladding layer; an N-side first guide layer; an N-side second guide layer; an active layer including a well layer and a barrier layer; and a P-type cladding layer. The band gap energy of the barrier layer is larger than the band gap energy of the N-side second guide layer. The band gap energy of the N-side second guide layer is smaller than the band gap energy of the N-side first guide layer. The band gap energy of the N-side first guide layer is smaller than the band gap energy of the N-type cladding layer. The cladding layers, the guide layers, and the barrier layer each comprise a nitride semiconductor including Al.
H01S 5/30 - Structure ou forme de la région activeMatériaux pour la région active
H01S 5/32 - Structure ou forme de la région activeMatériaux pour la région active comprenant des jonctions PN, p. ex. hétérostructures ou doubles hétérostructures
H01S 5/34 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH]
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
A cell stack management system includes a cell monitoring unit that measures an output voltage of a plurality of power storage cells, a battery management unit that manages a cell stack, and a first communication network that connects the cell monitoring unit and the battery management unit. The battery management unit includes: a first communication circuit connected to the first communication network; a second communication circuit connected to a second communication network for connecting to a higher-level system; a control circuit that controls the battery management unit; and a control circuit power supply. The cell stack management system includes a normal mode and a low-power mode as modes of operation. During transition from the low-power mode to the normal mode, the first communication circuit activates at least one of the control circuit power supply, the control circuit, or the second communication circuit.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
G01R 31/3835 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge ne faisant intervenir que des mesures de tension
G01R 31/396 - Acquisition ou traitement de données pour le test ou la surveillance d’éléments particuliers ou de groupes particuliers d’éléments dans une batterie
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
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