A semiconductor device capable of low-speed operation is provided. The semiconductor device includes first to eighth transistors and first and second capacitor elements. Gates of the first transistor and the second transistor are connected to each other. A first terminal of the first transistor is electrically connected to a first terminal of the fourth transistor and a first terminal of the fifth transistor. A first terminal of the third transistor is electrically connected to a first terminal of the second transistor, a gate of the fourth transistor, a first terminal of the first capacitor element, a gate of the seventh transistor, and a first terminal of the eighth transistor. A second terminal of the fifth transistor is electrically connected to a gate of the sixth transistor and a first terminal of the second capacitor element. A first terminal of the sixth transistor is electrically connected to a second terminal of the second capacitor element, a first terminal of the seventh transistor, and a gate of the eighth transistor.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED]
G09G 3/3225 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active
G09G 3/3266 - Détails des circuits de commande pour les électrodes de balayage
G09G 3/3275 - Détails des circuits de commande pour les électrodes de données
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
A positive electrode active material that can be used in a lithium-ion secondary battery and in which conductivity is improved and/or insertion and extraction of lithium ions are promoted is provided. A secondary battery includes a positive electrode active material; the positive electrode active material contains an additive element whose oxide can be a semiconductor, magnesium, and lithium cobalt oxide; the positive electrode active material includes a crack; the positive electrode active material includes a surface portion and a crack portion; the surface portion is a region within 10 nm from a surface other than the crack portion in a direction substantially perpendicular to the surface; the crack portion is a region within 10 nm from a surface of the crack portion in a direction substantially perpendicular to the surface and is a region other than the surface portion; magnesium is detected from the surface portion and the crack portion; the element whose oxide can be a semiconductor is detected from the surface portion; and the element whose oxide can be a semiconductor is one or two selected from nickel and titanium.
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
H01M 4/36 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs
H01M 4/38 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'éléments simples ou d'alliages
H01M 10/0525 - Batteries du type "rocking chair" ou "fauteuil à bascule", p. ex. batteries à insertion ou intercalation de lithium dans les deux électrodesBatteries à l'ion lithium
3.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE
A semiconductor device including a transistor having a minute size is provided. A semiconductor device includes a semiconductor layer, first to fourth conductive layers, and first and second insulating layers. The second conductive layer is provided over the first conductive layer and includes a first opening overlapping with the first conductive layer. The third conductive layer is provided over the second conductive layer and includes a second opening overlapping with the first opening. The first insulating layer is in contact with a sidewall of the first opening. The semiconductor layer is provided over the first conductive layer, the first insulating layer, and the third conductive layer. The semiconductor layer includes a first region in contact with the top surface of the first conductive layer, a second region in contact with the side surface of the first insulating layer, and a third region in contact with the top surface of the third conductive layer. The second insulating layer is provided over the semiconductor layer. The fourth conductive layer is provided over the second insulating layer. The fourth conductive layer faces the second conductive layer with the second insulating layer, the semiconductor layer, and the first insulating layer therebetween. Each of the first region and the third region has a lower resistance than the second region.
A battery module that includes a circuit for safe control and that is capable of space-saving is to be provided. The battery module includes a flexible printed circuit (FPC) board, an exterior body, a positive electrode, and a negative electrode; the FPC board includes a first resin layer, a second resin layer, a third resin layer, a first metal layer positioned between the first resin layer and the second resin layer, and a second metal layer positioned between the second resin layer and the third resin layer; the first resin layer and the exterior body are bonded to each other at a sealing portion; the positive electrode includes a positive electrode current collector; the negative electrode includes a negative electrode current collector; and in a sealed space surrounded by the first resin layer, the exterior body, and the sealing portion, the first resin layer includes a first opening reaching the first metal layer, the first resin layer, the first metal layer, and the second resin layer each include a second opening reaching the second metal layer, the positive electrode current collector is connected to the first metal layer in the first opening, and the negative electrode current collector is connected to the second metal layer in the second opening.
H01M 50/284 - MonturesBoîtiers secondaires ou cadresBâtis, modules ou blocsDispositifs de suspensionAmortisseursDispositifs de transport ou de manutentionSupports comprenant l’insertion de cartes de circuits, p. ex. de cartes de circuits imprimés
5.
DISPLAY APPARATUS, DISPLAY MODULE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING DISPLAY APPARATUS
A higher-definition or higher-resolution display apparatus is provided. The display apparatus includes a first light-emitting device, a second light-emitting device, a first insulating layer, a first coloring layer, and a second coloring layer. The first light-emitting device includes a first pixel electrode, a first light-emitting layer over the first pixel electrode, and a common electrode over the first light-emitting layer. The second light-emitting device includes a second pixel electrode, a second light-emitting layer over the second pixel electrode, and the common electrode over the second light-emitting layer. The first insulating layer covers side surfaces of the first pixel electrode, the second pixel electrode, the first light-emitting layer, and the second light-emitting layer. The first coloring layer is placed to overlap with the first light-emitting device. The second coloring layer is placed to overlap with the second light-emitting device. The first light-emitting device and the second light-emitting device have a function of emitting white light. The first coloring layer and the second coloring layer have a function of transmitting visible light of different colors.
H10K 59/38 - Dispositifs spécialement adaptés à l'émission de lumière multicolore comprenant des filtres de couleur ou des supports changeant de couleur [CCM]
H10K 50/10 - OLED ou diodes électroluminescentes polymères [PLED]
H10K 71/16 - Dépôt d'une matière active organique en utilisant un dépôt physique en phase vapeur [PVD], p. ex. un dépôt sous vide ou une pulvérisation cathodique
H10K 71/60 - Formation de régions ou de couches conductrices, p. ex. d’électrodes
6.
SEPARATOR, SECONDARY BATTERY, AND A METHOD FOR MANUFACTURING SEPARATOR
A secondary battery with little deterioration is provided. A secondary battery with high safety is provided. A separator having excellent characteristics is provided. A separator achieving the secondary battery with high safety is provided. A novel separator is provided. In the separator, a polymer porous film and a layer including a ceramic-based material containing a metal oxide microparticle are stacked, the thickness of the layer including a ceramic-based material is greater than or equal to 1 μm and less than or equal to 100 μm, and the film thickness of the polymer porous film is greater than or equal to 4 μm and less than or equal to 50 μm.
H01M 50/451 - Séparateurs, membranes ou diaphragmes caractérisés par le matériau ayant une structure en couches comprenant des couches de matériau organique uniquement et des couches comprenant un matériau inorganique
H01M 10/0525 - Batteries du type "rocking chair" ou "fauteuil à bascule", p. ex. batteries à insertion ou intercalation de lithium dans les deux électrodesBatteries à l'ion lithium
H01M 50/403 - Procédés de fabrication des séparateurs, des membranes ou des diaphragmes
A novel display module that is highly convenient, useful, or reliable is provided. The display module includes a first support, a second support, a first adhesive layer, a gap, a fluid layer, and a display apparatus. The first support overlaps with the second support. The first support has flexibility. The second support has higher elasticity than the first support. The first adhesive layer bonds the first support and the second support to each other. The first adhesive layer fomes the gap between the first support and the second support. The gap holds the fluid layer. The fluid layer has fluidity within the range of 0° C. to 80° C., and the difference in refractive index between the fluid layer and the first support is greater than 0 and less than or equal to 0.2. The display apparatus is sandwiched between the first support and the second support, has a function of performing display toward the first support, and includes a first display region, a second display region, and a third display region. The first display region is fixed between the first support and the first adhesive layer. The second display region is sandwiched between the first display region and the third display region, can be bent, and is positioned inside the gap. The third display region is positioned inside the gap and slides inside the gap in accordance with bending of the second display region.
A light-emitting element containing a light-emitting material and having high light emission efficiency is provided. The light-emitting element includes a host material and a guest material. The host material includes at least a first molecule and a second molecule having the same molecular structure. The guest material has a function of exhibiting fluorescence or converting triplet excitation energy into light emission. The first molecule and the second molecule each include a first skeleton, a second skeleton, and a third skeleton, and the first skeleton and the second skeleton are bonded to each other through the third skeleton. The first skeleton includes at least one of a π-electron rich heteroaromatic skeleton and an aromatic amine skeleton and the second skeleton includes a π-electron deficient heteroaromatic skeleton. The first molecule and the second molecule have a function of forming an excited complex.
H10K 85/60 - Composés organiques à faible poids moléculaire
C09K 11/02 - Emploi de substances particulières comme liants, revêtements de particules ou milieux de suspension
C09K 11/06 - Substances luminescentes, p. ex. électroluminescentes, chimiluminescentes contenant des substances organiques luminescentes
H10K 50/11 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL]
H10K 101/00 - Propriétés des matériaux organiques couverts par le groupe
H10K 101/30 - Valeurs d'énergie de la plus haute orbitale moléculaire occupée [HOMO], de la plus basse orbitale moléculaire inoccupée [LUMO] ou de Fermi
9.
INPUT/OUTPUT PANEL, INPUT/OUTPUT DEVICE, AND SEMICONDUCTOR DEVICE
An input/output device includes a first sensor electrode and a second sensor electrode. In addition, the input/output device includes a first electrode and a second electrode which are electrodes for a display element, and a substrate sandwiched between the first sensor electrode and the second sensor electrode. The second sensor electrode is formed concurrently with the first electrode using the same material. The input/output device sensors a change in capacitance of a capacitor formed between the first sensor electrode and the second sensor electrode. Furthermore, a third sensor electrode to which a floating potential is applied may be provided to overlap with the first electrode. In the input/output device, either a liquid crystal element or a light-emitting element may be used, or both the liquid crystal element and the light-emitting element may be used.
A method for forming a lithium-rich positive electrode active material particle which enables high charge and discharge capacities and has a stable crystal structure is provided. The method for forming the positive electrode active material particle includes the steps of: mixing a lithium source and an M source (M is one or more selected from Mn, Ni, Co, Cr, Mo, Nb, V, Fe, Ti, and Ru) to form a first mixture; heating the first mixture at higher than or equal to 850° C. and lower than 950° C. to synthesize a first composite oxide; mixing the first composite oxide and an additive element source to form a second mixture; and heating the second mixture at higher than or equal to 850° C. and lower than or equal to 950° C. The additive element source includes a fluorine source and a magnesium source.
C01G 53/502 - Oxydes complexes contenant du nickel et au moins un autre élément métallique contenant des métaux alcalins, p. ex. LiNiO2 contenant du manganèse du type (MnO2)n-, p. ex. Li(NixMn1-x)O2 ou Li(MyNixMn1-x-y)O2 contenant du lithium et du cobalt
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
H01M 4/36 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs
H01M 4/505 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de manganèse d'oxydes ou d'hydroxydes mixtes contenant du manganèse pour insérer ou intercaler des métaux légers, p. ex. LiMn2O4 ou LiMn2OxFy
H01M 4/58 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs de composés inorganiques autres que les oxydes ou les hydroxydes, p. ex. sulfures, séléniures, tellurures, halogénures ou LiCoFyEmploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs de structures polyanioniques, p. ex. phosphates, silicates ou borates
11.
LIGHT-EMITTING DEVICE, LIGHT-EMITTING APPARATUS, ELECTRONIC DEVICE, LIGHTING DEVICE, AND COMPOUND
A novel light-emitting device is provided. A light-emitting device with high emission efficiency is provided. A light-emitting device having a long lifetime is provided. A light-emitting device with low driving voltage is provided. The light-emitting device includes an anode, a cathode, and an EL layer between the anode and the cathode. The EL layer includes a light-emitting layer and an electron-transport layer. The electron-transport layer is positioned between the light-emitting layer and the cathode. The electron-transport layer contains an electron-transport material. The electron-transport material is an organic compound including a first skeleton, a second skeleton, and a third skeleton. The first skeleton has a function of transporting electrons. The second skeleton has a function of accepting holes. The third skeleton includes a monocyclic π-electron deficient heteroaromatic ring.
H10K 85/60 - Composés organiques à faible poids moléculaire
C07D 401/10 - Composés hétérocycliques contenant plusieurs hétérocycles comportant des atomes d'azote comme uniques hétéro-atomes du cycle, au moins un cycle étant un cycle à six chaînons avec un unique atome d'azote contenant deux hétérocycles liés par une chaîne carbonée contenant des cycles aromatiques
C07D 491/048 - Systèmes condensés en ortho avec un seul atome d'oxygène comme hétéro-atome du cycle contenant de l'oxygène le cycle contenant de l'oxygène étant à cinq chaînons
H10K 50/11 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL]
H10K 50/165 - Couches de transport d'électrons comprenant des dopants
H10K 101/30 - Valeurs d'énergie de la plus haute orbitale moléculaire occupée [HOMO], de la plus basse orbitale moléculaire inoccupée [LUMO] ou de Fermi
H10K 101/40 - Interrelation des paramètres entre plusieurs couches ou sous-couches actives constitutives, p. ex. valeurs HOMO dans des couches adjacentes
A semiconductor device of one embodiment of the present invention includes a semiconductor, an insulator, a first conductor, and a second conductor. In the semiconductor device, a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator; the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween; the first region has a region in contact with the top surface of the semiconductor and a region in contact with the side surface of the semiconductor; the second conductor has a second region in contact with the semiconductor; and the first region and the second region do not overlap with each other.
H10D 62/80 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
A high-resolution display device is provided. A display device with both high display quality and high resolution is provided. The display device includes a first light-emitting element and a second light-emitting element. The first light-emitting element includes a first pixel electrode, a first EL layer, and a common electrode. The second light-emitting element includes a second pixel electrode, a second EL layer, and the common electrode. An insulating layer is included between the first pixel electrode and the second pixel electrode. The insulating layer includes a first region overlapping with the first EL layer, a second region overlapping with the second EL layer, and a third region positioned between the first region and the second region. A side surface of the first EL layer and a side surface of the second EL layer are positioned over the insulating layer and are provided to face each other. The common electrode is provided along the side surface of the first EL layer, the side surface of the second EL layer, and a top surface of the insulating layer. A width of the insulating layer is greater than or equal to 2 times and less than or equal to 4 times that of a distance between the first pixel electrode and the second pixel electrode.
H10K 59/122 - Structures ou couches définissant le pixel, p. ex. bords
H10K 50/13 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] spécialement adaptées à l'émission de lumière multicolore, p. ex. à l'émission de lumière blanche comprenant des couches EL empilées dans une unité EL
A semiconductor device with favorable electrical characteristics is provided. Alternatively, a transistor in which the breakdown voltage of a gate insulating layer is high is provided. In the semiconductor device, a first conductive layer and a second conductive layer positioned at different levels with a first insulating layer therebetween are one and the other of a source electrode and a drain electrode of a first transistor. The first insulating layer has a first opening reaching the first conductive layer. The second conductive layer is provided over the first insulating layer. A semiconductor layer includes a first region covering the top surface of the first conductive layer, a second region covering a side surface of the first opening, and a third region covering the top surface of the second conductive layer and overlapping with a gate electrode. A gate insulating layer includes a fourth region provided to face a sidewall of the first opening, a fifth region covering the top surface of the third region, and a sixth region covering the top surface of the second conductive layer and being positioned outward from an end portion of the gate electrode in a top view. The thickness of the fifth region is larger than the thickness of the fourth region and the thickness of the sixth region.
A display device with both high display quality and high resolution is provided. The display device includes a light-emitting element and a connection portion. The connection portion is provided along an outer periphery of a display region where the light-emitting element is provided. The light-emitting element includes a pixel electrode, a first EL layer over the pixel electrode, a second EL layer over the first EL layer, and a common electrode over the second EL layer. The connection portion includes a connection electrode, a second EL layer over the connection electrode, and the common electrode over the second EL layer. The second EL layer includes a first region in contact with the connection electrode and a second region in contact with the common electrode. The area of a region where the first region and the second region overlap with each other in a top view is greater than or equal to 40000 square micrometers. The second EL layer includes a region where the film thickness is greater than or equal to 0.5 nm and less than or equal to 1.5 nm. The second EL layer contains a substance with a high electron-injection property.
H10K 50/13 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] spécialement adaptées à l'émission de lumière multicolore, p. ex. à l'émission de lumière blanche comprenant des couches EL empilées dans une unité EL
H10K 50/17 - Couches d'injection des porteurs de charge
H10K 59/131 - Interconnexions, p. ex. lignes de câblage ou bornes
H10K 59/35 - Dispositifs spécialement adaptés à l'émission de lumière multicolore comprenant des sous-pixels rouge-vert-bleu [RVB]
H10K 102/00 - Détails de structure relatifs aux dispositifs organiques couverts par la présente sous-classe
A semiconductor device that can be miniaturized or highly integrated is to be provided. The semiconductor device includes a first conductor and a second conductor that are over an oxide and separated from each other; a third conductor in contact with a part of a top surface of the first conductor; a fourth conductor in contact with a part of a top surface of the second conductor; a first insulator that is positioned over the third conductor and the fourth conductor and has an opening overlapping with a region between the third conductor and the fourth conductor; a second insulator that is positioned in the opening of the first insulator and in contact with another part of the top surface of the first conductor, another part of the top surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator that is in contact with a top surface of the oxide, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the second insulator; and a fifth conductor that is positioned over the third insulator. A distance between the first conductor and the second conductor is smaller than a distance between the third conductor and the fourth conductor. The second insulator includes a first layer and a second layer over the first layer. The first layer includes a nitride insulator, and the second layer includes an oxide insulator.
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
A novel data processing system comprising a first component, a second component, and a third component is provided. The first component receives a document, prior art literature, and a scope of claims and transmits them to the third component; the second component performs processing with a large language model; and the third component shares the received data and creates prompts. The third component has a function of creating and executing a prompt chain and a function of creating an annotated document. The system is configured to find a description related to the scope of claims in the prior art literature and a description related to the description in the prior art literature from the document. The system is configured to attach an annotation to a position of the description in the document.
An electronic device that enables smooth communication is provided. The electronic device includes a display portion including a first camera; a second camera; and an image processing portion. The second camera is positioned in a region not overlapping with the display portion. The first camera has a function of generating a first image of a subject, and the second camera has a function of generating a second image of the subject. The image processing portion includes a generator that performs learning using training data. The training data includes an image including a person's face. The image processing portion has a function of making the first image clear when the first image is input to the generator and a function of tracking the gaze of the subject on the basis of the second image.
G06V 40/18 - Caractéristiques de l’œil, p. ex. de l’iris
H04N 23/611 - Commande des caméras ou des modules de caméras en fonction des objets reconnus les objets reconnus comprenant des parties du corps humain
H04N 23/617 - Mise à niveau ou mise à jour des programmes ou des applications pour la commande des caméras
H04N 23/90 - Agencement de caméras ou de modules de caméras, p. ex. de plusieurs caméras dans des studios de télévision ou des stades de sport
19.
LIGHT-EMITTING DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME
An object is to provide a light-emitting display device in which a pixel including a thin film transistor using an oxide semiconductor has a high aperture ratio. The light-emitting display device includes a plurality of pixels each including a thin film transistor and a light-emitting element. The pixel is electrically connected to a first wiring functioning as a scan line. The thin film transistor includes an oxide semiconductor layer over the first wiring with a gate insulating film therebetween. The oxide semiconductor layer is extended beyond the edge of a region where the first wiring is provided. The light-emitting element and the oxide semiconductor layer overlap with each other.
H10H 20/817 - Corps caractérisés par des structures ou des orientations cristallines, p. ex. polycristallines, amorphes ou poreuses
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor, a capacitor, and a first insulating layer. The first insulating layer is provided over a first conductive layer and a second conductive layer and includes a first opening reaching the first conductive layer and a second opening reaching the second conductive layer. The transistor is a vertical transistor in which a channel formation region is provided along the side wall of the first opening. The capacitor is a vertical capacitor in which a pair of electrodes and a dielectric are provided along the side surface of the second opening.
A display device that has a function of emitting visible light and infrared light and a function of detecting light. The display device is a display device including a first light-emitting device, a second light-emitting device, and a light-receiving device, in a display portion. The first light-emitting device includes a first pixel electrode, a first optical adjustment layer, a first light-emitting layer, a second light-emitting layer, and a common electrode. The second light-emitting device includes a second pixel electrode, a second optical adjustment layer, the first light-emitting layer, the second light-emitting layer, and the common electrode. The light-receiving device includes a third pixel electrode, an active layer, and the common electrode. The active layer includes an organic compound. The first light-emitting device emits infrared light emitted by the first light-emitting layer. The second light-emitting device emits visible light emitted by the second light-emitting layer. The light-receiving device has a function of absorbing at least part of visible light and infrared light.
A semiconductor device with less variation in transistor characteristics is provided. The semiconductor device includes a semiconductor film, a pair of blocking films over the semiconductor film, and an insulating film provided over the semiconductor film and between the pair of blocking films. The semiconductor film includes a pair of n-type regions and an i-type region provided between the pair of n-type regions. The n-type regions overlap with the blocking films. The i-type region overlaps with the insulating film.
A semiconductor device with high storage capacity and low power consumption is provided. The semiconductor device includes first to third conductors, first and second transistors, and an MTJ element. The MTJ element includes a free layer and a fixed layer. In the semiconductor device, the first conductor, the second conductor, the free layer, the fixed layer, the first and second transistors, and the third conductor are provided in this order from the bottom. In particular, in a plan view, the third conductor is positioned in a region overlapping with the first conductor. The first conductor is electrically connected to the second conductor, and the second conductor is electrically connected to the free layer and a first terminal of the first transistor. The fixed layer is electrically connected to a first terminal of the second transistor, and a second terminal of the first transistor is electrically connected to a second terminal of the second transistor and the third conductor. The first transistor and the second transistor each include a metal oxide in a channel formation region.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
A semiconductor device that has lower power consumption and is capable of non-destructive reading is provided. The semiconductor device includes a first transistor, a first FTJ element, and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element and an input terminal of the second FTJ element. In data writing, polarization is caused in each of the first FTJ element and the second FTJ element in accordance with the data. In data reading, voltage with which the polarization does not change is applied between the output terminal of the first FTJ element and the input terminal of the second FTJ element. At this time, the first transistor is turned on, whereby a differential current between current flowing through the first FTJ element and current flowing through the second FTJ element flows through the first transistor. Obtaining the differential current using a read circuit or the like enables the data written to the first FTJ element and the second FTJ element to be read.
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 53/40 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
A driver circuit includes a circuit 200, a transistor 101_1, and a transistor 101_2. A signal is selectively input from the circuit 200 to a gate of the transistor 101_1 and the transistor 101_2, so that the transistor 101_1 and the transistor 101_2 are controlled to be on or off. The transistor 101_1 and the transistor 101_2 are turned on or off; thus, the wiring 112 and the wiring 111 become conducting or non-conducting.
G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides
G02F 1/1362 - Cellules à adressage par une matrice active
G02F 1/1368 - Cellules à adressage par une matrice active dans lesquelles l'élément de commutation est un dispositif à trois électrodes
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
H10D 62/80 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
A display device that has high display quality is provided. A highly reliable display device is provided. A display device with low power consumption is provided and a display device that can easily achieve a higher resolution is provided. A display device with both high display quality and a high resolution is provided. A display device with high contrast is provided. The display device includes a first layer, a second layer over the first layer, and a third layer over the second layer. The first layer includes a first transistor including silicon in a channel formation region. The second layer includes a second transistor including a metal oxide in a channel formation region. The third layer includes a first light-emitting element, a second light-emitting element, a third light-emitting element, an EL layer including a light-emitting layer exhibiting white light, a first coloring layer over the first light-emitting element, a second coloring layer over the second light-emitting element, and a third coloring layer over the third light-emitting element. Crosstalk is not observed between the second light-emitting element and the third light-emitting element.
H10K 59/38 - Dispositifs spécialement adaptés à l'émission de lumière multicolore comprenant des filtres de couleur ou des supports changeant de couleur [CCM]
G09G 3/3225 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active
H10K 50/00 - Dispositifs organiques émetteurs de lumière
H10K 59/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément organique émetteur de lumière couvert par le groupe
A light-emitting device with high emission efficiency and low driving voltage is provided. A light-emitting apparatus, an electronic device, and a lighting device with low power consumption are provided. The following organic compound is provided: the organic compound has an arylamine structure; and when the organic compound is deposited to be a film, the ordinary refractive index of the deposited film with respect to light with a wavelength of 458 nm is greater than or equal to 1.50 and less than or equal to 1.75, the birefringence Δn of the deposited film with respect to light with a wavelength of 458 nm is greater than or equal to 0 and less than or equal to 0.008, or the alignment order parameter of the deposited film with respect to light with a wavelength corresponding to the longest wavelength where an absorption peak appears in the absorption spectrum is greater than or equal to −0.07 and less than or equal to 0.00.
H10K 85/60 - Composés organiques à faible poids moléculaire
C07C 211/61 - Composés contenant des groupes amino liés à un squelette carboné ayant des groupes amino liés à des atomes de carbone de cycles aromatiques à six chaînons du squelette carboné ayant des groupes amino liés à des atomes de carbone de cycles aromatiques à six chaînons faisant partie de systèmes cycliques condensés du squelette carboné avec au moins un des systèmes cycliques condensés formé par trois cycles ou plus
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor and an insulator; the insulator is provided over one of a source and a drain of the transistor; the other of the source and the drain of the transistor is provided over the insulator; an opening portion reaching one of the source and the drain is provided in the insulator and the other of the source and the drain; an oxide semiconductor included in the transistor is in contact with a top surface of one of the source and the drain, a side surface of the insulator, and a side surface of the other of the source and the drain that are in the opening portion; a gate insulator of the transistor is provided over the oxide semiconductor; a gate of the transistor is provided over the gate insulator; the oxide semiconductor includes a first region in contact with one of the source and the drain, a second region in contact with the insulator, and a third region in contact with the other of the source and the drain; the first and third regions have lower resistance than the second region; and the second region has a lower potential than the first and third regions.
A conversation device having high security is provided. The conversation device includes a reception unit, a processing unit, and a presentation unit. The reception unit has a function of receiving input information showing a user's instruction in a conversation. The processing unit has a function of performing processing using the monitoring model and a function of performing processing using the conversational model. The processing unit has a function of determining whether or not to transmit the input information to the conversational model, on the basis of the input information with the use of the monitoring model. In the case where the monitoring model transmits the input information to the conversational model, the processing unit has a function of generating output information on the basis of the input information with the use of the conversational model. The output information can show a response in a conversation. The presentation unit has a function of presenting the output information and a function of presenting error information showing that the output information is not presented. The conversational model is a language model, which is a different type of model from the monitoring model.
A semiconductor device with high display quality is provided. The semiconductor device includes first to eighth transistors, first to third capacitors, and a light-emitting device. A first terminal of the first transistor is connected to a first terminal of the third transistor and a first terminal of the sixth transistor; a gate of the first transistor is connected to a first terminal of the first capacitor and a first terminal of the eighth transistor; a second terminal of the sixth transistor is connected to a first terminal of the seventh transistor and an anode of the light-emitting device; and a second terminal of the third transistor is connected to a second terminal of the eighth transistor and a first terminal of the fourth transistor. A second terminal of the first capacitor is connected to a first terminal of the second transistor, a first terminal of the fifth transistor, a first terminal of the second capacitor, and a first terminal of the third capacitor.
H10H 29/32 - Affichages LED à matrice active caractérisés par la géométrie ou l’agencement des éléments à l’intérieur d’un sous-pixel, p. ex. l’agencement du transistor à l’intérieur de son sous-pixel RGB
G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED]
G09G 3/3233 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active avec un circuit de pixel pour commander le courant à travers l'élément électroluminescent
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
An imaging device that has an image processing function and is capable of operating at high speed is provided. The imaging device has an additional function such as image processing, image data obtained by an imaging operation is binarized in a pixel unit, and a product-sum operation is performed using the binarized data. A memory circuit is provided in the pixel unit and retains a weight coefficient used for the product-sum operation. Thus, an arithmetic operation can be performed without the weight coefficient read from the outside every time, whereby power consumption can be reduced. Furthermore, a pixel circuit, a memory circuit, and the like and a product-sum operation circuit and the like are stacked, so that the lengths of wirings between the circuits can be reduced, and high-speed operation with low power consumption can be performed.
A novel display panel that is highly convenient or reliable is provided. The display panel includes a first pixel; the first pixel includes a first display element, a first color conversion layer, and a first absorption layer; the first display element emits first light; the first absorption layer overlaps with the first display element; and the first absorption layer absorbs the first light. Furthermore, the first color conversion layer is sandwiched between the first display element and the first absorption layer; the first color conversion layer converts the first light into second light; and the second light has a spectrum including a high proportion of light with a long wavelength compared with the first light.
G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
G06F 3/041 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction
G09G 3/3208 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED]
H10K 59/38 - Dispositifs spécialement adaptés à l'émission de lumière multicolore comprenant des filtres de couleur ou des supports changeant de couleur [CCM]
A semiconductor device having favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first semiconductor layer, a first gate insulating layer, and a first gate electrode. The first semiconductor layer includes a metal oxide. The second transistor includes a second semiconductor layer, a second gate insulating layer, and a second gate electrode. The second semiconductor layer includes crystalline silicon. The first insulating layer includes a region overlapping with the first transistor with the second insulating layer therebetween. The second insulating layer includes a region overlapping with the second transistor with the first insulating layer therebetween. The second insulating layer has higher film density than the first insulating layer.
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
A high-resolution display device with reduced display unevenness is provided. In the display device, a plurality of pixels are included over a substrate; each of the plurality of pixels includes a transistor and a light-emitting element; the light-emitting element includes a first electrode, an EL layer over the first electrode, and a second electrode over the EL layer; the first electrode is electrically connected to the transistor; in the plurality of pixels, the first electrodes in adjacent pixels are separated by an insulating layer; the second electrode includes a conductive material having light-transmitting property with respect to visible light; the second electrode of each of the plurality of pixels is shared; and light is emitted from the second electrode side. A wiring is included; in a plane view with respect to the substrate, the wiring is placed in a region where the EL layer is not placed; and the second electrode is placed over and in contact with the wiring.
A memory device with few transistor manufacturing steps is provided. Each of a first selection transistor, a cell transistor, and a second selection transistor included in a memory string includes a cylindrical structure body. The structure body includes an oxide semiconductor, an insulator, and a conductor concentrically in an inward direction from a side surface. In the memory string, the transistors can be arranged in the lateral direction, and the first selection transistor and the second selection transistor can be formed in the same step. Accordingly, the number of transistor manufacturing steps can be reduced.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
An electronic device with good visibility of display is provided. The electronic device includes a reflective liquid crystal display device for displaying information, and part of external light taken into the electronic device can be supplied to the reflective liquid crystal display device to be used as a light source of display light. Thus, the visibility of display can be increased even when external light is intense. Furthermore, since external light is utilized for display, power consumption can be reduced compared with a transmissive liquid crystal display device that constantly uses a light source, a self-luminous organic EL display device, and the like.
After first and second documents are received, a text generation language model generates a summary sentence of the second document. A difference presentation language model presents a difference in the first document from the summary sentence. When the difference is not appropriate, the difference presentation language model is made to present a difference again on the basis of a first instruction document created by a user. When the difference is appropriate, the difference presentation language model is made to confirm that the difference is absent in the second document. The difference presentation language model is fine-tuned using a plurality of data points each including an order sentence, two learning texts, and a learning response sentence. Among the plurality of data points, some of the learning response sentences show the absence of a difference between the two learning texts, and the rest show a difference between the two learning texts.
A light-emitting device with high resistance to heat in a fabrication process is provided. The light-emitting device includes an EL layer between an anode and a cathode. The EL layer includes at least a light-emitting layer and an electron-transport layer that includes a first electron-transport layer in contact with the light-emitting layer and a second electron-transport layer in contact with the first electron-transport layer. The first electron-transport layer includes a first heteroaromatic compound including at least one heteroaromatic ring. The second electron-transport layer includes a second heteroaromatic compound that includes at least one heteroaromatic ring and is different from the first heteroaromatic compound. The first heteroaromatic compound has a difference of 20° C. or less between the crystallization temperature (Tpc) of a powder state and the crystallization temperature (Ttc) of a thin film state. The second heteroaromatic compound has a difference of 100° C. or less between Tpc and Ttc.
C07D 401/14 - Composés hétérocycliques contenant plusieurs hétérocycles comportant des atomes d'azote comme uniques hétéro-atomes du cycle, au moins un cycle étant un cycle à six chaînons avec un unique atome d'azote contenant au moins trois hétérocycles
C07D 403/10 - Composés hétérocycliques contenant plusieurs hétérocycles, comportant des atomes d'azote comme uniques hétéro-atomes du cycle, non prévus par le groupe contenant deux hétérocycles liés par une chaîne carbonée contenant des cycles aromatiques
C07D 403/14 - Composés hétérocycliques contenant plusieurs hétérocycles, comportant des atomes d'azote comme uniques hétéro-atomes du cycle, non prévus par le groupe contenant au moins trois hétérocycles
C07D 409/10 - Composés hétérocycliques contenant plusieurs hétérocycles, au moins un cycle comportant des atomes de soufre comme uniques hétéro-atomes du cycle contenant deux hétérocycles liés par une chaîne carbonée contenant des cycles aromatiques
C07D 491/048 - Systèmes condensés en ortho avec un seul atome d'oxygène comme hétéro-atome du cycle contenant de l'oxygène le cycle contenant de l'oxygène étant à cinq chaînons
C07D 519/00 - Composés hétérocycliques contenant plusieurs systèmes de plusieurs hétérocycles déterminants condensés entre eux ou condensés avec un système carbocyclique commun non prévus dans les groupes ou
Provided is a power storage system, a secondary battery control system, a secondary battery measurement circuit, or the like that consumes low power. Provided is a power storage system, a secondary battery control system, a secondary battery measurement circuit, or the like that is highly integrated. The power storage system includes a secondary battery and a measurement circuit; the measurement circuit includes a resistor, a capacitor, and an inductor; one terminal of the resistor is electrically connected to one electrode of the capacitor; the other terminal of the resistor is electrically connected to one terminal of the inductor; one terminal of the inductor is electrically connected to a positive electrode of the secondary battery; and the measurement circuit has a function of measuring impedance of the secondary battery by measuring current of the resistor.
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
A multifunctional display apparatus or electronic device is provided. An electronic device that can switch between VR display and AR display is provided. The electronic device includes a first display apparatus, a second display apparatus, a lens, a screen, a wearing tool, and a housing. The wearing tool has a function of fixing the housing to a head. The housing has a function of being transformed into a first mode that closes to block view and a second mode that opens to allow a front side to be viewed. The electronic device has a function of providing a first image displayed on the first display apparatus through the lens and the screen in the first mode, and a function of providing a second image projected to the screen from the second display apparatus in the second mode.
A positive electrode active material with a small decrease in discharging capacity in charging and discharging cycles is provided. The positive electrode active material contains cobalt, nickel, and oxygen. The proportion of nickel in the sum of the cobalt and the nickel, Ni/(Co+Ni), is greater than 0.175 and less than or equal to 0.215. When the positive electrode active material in a state of being charged to 4.5 V (vs. Li/Li+) is analyzed by powder X-ray diffraction using CuKα1 radiation, diffraction peaks are observed at at least two or more of 2θ±18.526±0.1°, 2θ=37.391±0.1°, 2θ=37.628±0.1°, 2θ=39.015±0.1°, 2θ=44.947±0.1°, 2θ=49.029±0.1°, and 2θ=58.857±0.1°.
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
B60L 50/64 - Détails de construction des batteries spécialement adaptées aux véhicules électriques
C01G 53/42 - Oxydes complexes contenant du nickel et au moins un autre élément métallique contenant des métaux alcalins, p. ex. LiNiO2
A light-emitting device having favorable characteristics and a wide range of material choices. The light-emitting device includes an anode over an insulating surface, a cathode opposite to the anode, and a first electron-transport layer and a second electron-transport layer which are between the anode and the cathode. The first electron-transport layer and the second electron-transport layer are in contact with each other. The second electron-transport layer and the cathode are in contact with each other. The GSP_Slope (mV/nm) of an evaporated film of a material included in the second electron-transport layer is larger than the GSP_Slope (mV/nm) of an evaporated film of a material included in the first electron-transport layer. The thickness of the second electron-transport layer is greater than 0 nm and less than 10 nm. The GSP_Slope (mV/nm) is represented by ΔV/Δd, where ΔV (mV) is an amount of change in a surface potential with respect to an amount of change in a thickness Δd (nm).
To increase emission efficiency of a fluorescent light-emitting element by efficiently utilizing a triplet exciton generated in a light-emitting layer. The light-emitting layer of the light-emitting element includes at least a host material and a guest material. The triplet exciton generated from the host material in the light-emitting layer is changed to a singlet exciton by triplet-triplet annihilation (TTA). The guest material (fluorescent dopant) is made to emit light by energy transfer from the singlet exciton. Thus, the emission efficiency of the light-emitting element is improved.
H10K 101/30 - Valeurs d'énergie de la plus haute orbitale moléculaire occupée [HOMO], de la plus basse orbitale moléculaire inoccupée [LUMO] ou de Fermi
H10K 101/40 - Interrelation des paramètres entre plusieurs couches ou sous-couches actives constitutives, p. ex. valeurs HOMO dans des couches adjacentes
44.
SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE
A novel semiconductor device is provided. The semiconductor device includes a memory cell including a transistor and a capacitor that includes a ferroelectric; a word line; a bit line; and a plate line. A gate of the transistor is electrically connected to the word line. One of a source and a drain of the transistor is electrically connected to the bit line. The other of the source and the drain of the transistor is electrically connected to one electrode of the capacitor. The other electrode of the capacitor is electrically connected to the plate line. The semiconductor device has a function of supplying a potential that controls an on state or an off state of the transistor to the word line, a function of supplying a first potential or a second potential to the bit line, and a function of supplying a third potential, a fourth potential, or a fifth potential to the plate line.
G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
Provided is a light-emitting element with high external quantum efficiency and a low drive voltage. The light-emitting element includes a light-emitting layer which contains a phosphorescent compound and a material exhibiting thermally activated delayed fluorescence between a pair of electrodes, wherein a peak of a fluorescence spectrum and/or a peak of a phosphorescence spectrum of the material exhibiting thermally activated delayed fluorescence overlap(s) with a lowest-energy-side absorption band in an absorption spectrum of the phosphorescent compound, and wherein the phosphorescent compound exhibits phosphorescence in the light-emitting layer by voltage application between the pair of electrodes.
H10K 101/30 - Valeurs d'énergie de la plus haute orbitale moléculaire occupée [HOMO], de la plus basse orbitale moléculaire inoccupée [LUMO] ou de Fermi
H10K 101/40 - Interrelation des paramètres entre plusieurs couches ou sous-couches actives constitutives, p. ex. valeurs HOMO dans des couches adjacentes
H10K 102/00 - Détails de structure relatifs aux dispositifs organiques couverts par la présente sous-classe
46.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a transistor having high saturation. The semiconductor device is provided with a vertical transistor including a back gate electrode. In the semiconductor device, a lower electrode, a spacer, and an upper electrode are provided in this order. The spacer includes a first opening portion reaching the lower electrode, and the upper electrode includes a second opening portion including a region overlapping with the first opening portion. The back gate electrode is provided in the first opening portion and includes a region in contact with the lower electrode. A back gate insulating layer, a semiconductor layer, a gate insulating layer, and a gate electrode are provided in this order to cover the back gate electrode. After the formation of the first opening portion and the second opening portion, a conductive film is formed to cover the first opening portion and is subjected to anisotropic etching, whereby the back gate electrode can be formed. An insulating film is formed to cover the back gate electrode and is subjected to anisotropic etching, whereby the back gate insulating layer can be formed.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
H10K 59/122 - Structures ou couches définissant le pixel, p. ex. bords
H10K 59/123 - Connexion des électrodes de pixel aux transistors à couches minces [TFT]
H10K 65/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément organique émetteur de lumière et au moins un composant organique sensible aux rayonnements, p. ex. des optocoupleurs organiques
47.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE
A transistor with low parasitic capacitance is provided. A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a transistor whose source electrode and drain electrode are positioned at different levels and an insulating layer provided between the source electrode and the drain electrode; the insulating layer includes a first opening reaching one of the source electrode and the drain electrode; the other of the source electrode and the drain electrode is provided over the insulating layer and includes a second opening overlapping with the first opening; a semiconductor layer includes a region provided in the first opening; a gate insulating layer and a gate electrode are provided in this order over the semiconductor layer; the gate electrode has a two-layer structure; the end portion of the lower layer of the gate electrode overlaps with the other of the source electrode and the drain electrode; the upper layer of the gate electrode includes a first region extending outward from the end portion of the lower layer; and a gap is provided between the first region and the other of the source electrode and the drain electrode.
A transistor with small parasitic capacitance is provided. A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a first insulating layer, and a second insulating layer. The first insulating layer is positioned over the first conductive layer. The second conductive layer is positioned over the first insulating layer. The first insulating layer and the second conductive layer have an opening reaching the first conductive layer. In the opening, the oxide semiconductor layer is in contact with at least the top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer. The second insulating layer is positioned over the oxide semiconductor layer in the opening. The third conductive layer overlaps with the oxide semiconductor layer with the second insulating layer therebetween in the opening. In a cross-sectional view, the width of the third conductive layer is smaller than or equal to the width of the opening in the second conductive layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 53/10 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la configuration vue du dessus
H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 53/40 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
H10K 59/122 - Structures ou couches définissant le pixel, p. ex. bords
H10K 59/123 - Connexion des électrodes de pixel aux transistors à couches minces [TFT]
H10K 59/124 - Couches isolantes formées entre les éléments TFT et les éléments OLED
H10K 59/131 - Interconnexions, p. ex. lignes de câblage ou bornes
A novel semiconductor device is provided. A power management portion and a data retention portion are provided in a first layer; a setting information retention portion, a power switch portion, and a backup portion are provided in a second layer over the first layer; the data retention portion has a function of retaining data; the power management portion has a function of supplying an instruction for controlling power gating to the power switch portion and supplying, to the setting information retention portion, setting information indicating whether to block power supply to the data retention portion by the power gating; the setting information retention portion has a function of retaining the setting information supplied from the power management portion; the power switch portion has a function of switching whether to block power supply to the data retention portion on the basis of the instruction and the setting information retained in the setting information retention portion; and the backup portion has a function of storing and retaining the data on the basis of a signal supplied from the power management portion.
G11C 11/417 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation pour des cellules de mémoire du type à effet de champ
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/80 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples composants passifs, p. ex. des résistances, des condensateurs ou des inducteurs
A novel light-emitting device which is highly convenient, useful, or reliable can be provided. The light-emitting device includes a first electrode, a second electrode, a first unit, and a first layer. The second electrode overlaps with the first electrode, the second electrode contains a metal atom, and the second electrode contains a carbon atom at a predetermined concentration. The first unit is sandwiched between the first electrode and the second electrode, and the first unit contains a first light-emitting material. The first layer is sandwiched between the second electrode and the first unit, the first layer contains the first organic compound and the second organic compound, the first organic compound has an acid dissociation constant pKa larger than or equal to 8, and the second organic compound has a polarization term δp smaller than or equal to a predetermined value in the solubility parameter δ.
A novel semiconductor device is provided. The semiconductor device includes a first conductive layer, a first insulating layer over the first conductive layer, a second conductive layer over the first insulating layer, a first semiconductor layer, a second insulating layer over the first semiconductor layer, a third insulating layer over the second insulating layer, and a third conductive layer over the third insulating layer. An opening portion reaching the first conductive layer is provided in the first insulating layer and the second conductive layer. In the opening portion, the first semiconductor layer includes a region in contact with the top surface of the first conductive layer, a region in contact with a side surface of the first insulating layer, and a region in contact with a side surface of the second conductive layer. The second insulating layer has a barrier property against oxygen. The third insulating layer is a ferroelectric containing hafnium, zirconium, at least one of the Group 3 elements in the periodic table, and oxygen, and the content percentage of at least one of the Group 3 elements in the periodic table in the third insulating layer is higher than or equal to 0.1 atomic % and lower than or equal to 5 atomic %.
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
A semiconductor device with a novel structure is provided. First to third element layers are included. The second element layer is stacked over the first element layer. The third element layer is stacked over the second element layer. A first storage portion is provided in the second element layer. A second storage portion is provided in the third element layer. The first element layer includes a first sense amplifier circuit portion electrically connected to the first storage portion, and a second sense amplifier circuit portion electrically connected to the second storage portion. The first sense amplifier circuit portion and the second sense amplifier circuit portion each include a first transistor including a first semiconductor layer including silicon in a channel formation region. The first storage portion includes a second transistor including a second semiconductor layer including an oxide semiconductor in a channel formation region. The second storage portion includes a third transistor including a third semiconductor layer including an oxide semiconductor in a channel formation region. The third element layer provided with the second storage portion is provided by stacking a plurality of element layers.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/405 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe avec trois portes à transfert de charges, p. ex. transistors MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
53.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device that occupies a small area is provided. The semiconductor device includes a first insulating layer, a second insulating layer over the first insulating layer, and a transistor. The transistor includes a semiconductor layer, a third insulating layer, a fourth insulating layer, a gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode are provided over the first insulating layer. The second insulating layer has an opening reaching the first insulating layer and overlapping with a part of the source electrode and a part of the drain electrode. The semiconductor layer and the third insulating layer are provided along a perimeter of the opening. The semiconductor layer is provided in contact with a side surface of the second insulating layer in the opening, a top surface of the first insulating layer in the opening, a top surface of the source electrode, and a top surface of the drain electrode. The third insulating layer is positioned over the semiconductor layer. The fourth insulating layer covers the third insulating layer and the semiconductor layer and is in contact with the first insulating layer. The gate electrode overlaps with the opening and is positioned over the fourth insulating layer. At least a part of the semiconductor layer is opposite to the gate electrode with the third insulating layer and the fourth insulating layer therebetween.
A novel organometallic complex is provided. One embodiment of the present invention provides a novel organometallic complex having a high quantum yield. An Ir complex has a structure including a 1H-naphtho[1,2-d]imidazole skeleton as a ligand and being represented by General Formula (G-1) below. Of Ns included in the 1H-naphtho[1,2-d]imidazole skeleton, N that is not bonded to Ir is bonded to a substituted or unsubstituted aryl group.
A novel organometallic complex is provided. One embodiment of the present invention provides a novel organometallic complex having a high quantum yield. An Ir complex has a structure including a 1H-naphtho[1,2-d]imidazole skeleton as a ligand and being represented by General Formula (G-1) below. Of Ns included in the 1H-naphtho[1,2-d]imidazole skeleton, N that is not bonded to Ir is bonded to a substituted or unsubstituted aryl group.
A novel organometallic complex is provided. One embodiment of the present invention provides a novel organometallic complex having a high quantum yield. An Ir complex has a structure including a 1H-naphtho[1,2-d]imidazole skeleton as a ligand and being represented by General Formula (G-1) below. Of Ns included in the 1H-naphtho[1,2-d]imidazole skeleton, N that is not bonded to Ir is bonded to a substituted or unsubstituted aryl group.
In General Formula (G-1), each of R1 to R10 independently represents any of hydrogen, an alkyl group having 1 to 6 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 7 carbon atoms, a substituted or unsubstituted aryl group having 6 to 25 carbon atoms, and an electron-withdrawing group, and Ar represents a substituted or unsubstituted aryl group having 6 to 25 carbon atoms.
A novel organic compound and a light-emitting device using the organic compound are provided. The organic compound is represented by General Formula (G1). In General Formula (G1), Ar1 represents any one of General Formulae (g1-1) to (g1-3). Each of R1 to R8 independently represents hydrogen, an alkyl group having 1 to 6 carbon atoms, a cycloalkyl group having 3 to 10 carbon atoms, an alkoxy group having 1 to 6 carbon atoms, a substituted or unsubstituted aryl group having 6 to 15 carbon atoms, or a substituted or unsubstituted heteroaryl group having 1 to 30 carbon atoms. Any one of R1 to R4 represents General Formula (g2-1) or (g2-2). Each of Ar2 and Ar3 independently represents a substituted or unsubstituted aryl group having 6 to 60 carbon atoms or a substituted or unsubstituted heteroaryl group having 1 to 60 carbon atoms.
A novel organic compound and a light-emitting device using the organic compound are provided. The organic compound is represented by General Formula (G1). In General Formula (G1), Ar1 represents any one of General Formulae (g1-1) to (g1-3). Each of R1 to R8 independently represents hydrogen, an alkyl group having 1 to 6 carbon atoms, a cycloalkyl group having 3 to 10 carbon atoms, an alkoxy group having 1 to 6 carbon atoms, a substituted or unsubstituted aryl group having 6 to 15 carbon atoms, or a substituted or unsubstituted heteroaryl group having 1 to 30 carbon atoms. Any one of R1 to R4 represents General Formula (g2-1) or (g2-2). Each of Ar2 and Ar3 independently represents a substituted or unsubstituted aryl group having 6 to 60 carbon atoms or a substituted or unsubstituted heteroaryl group having 1 to 60 carbon atoms.
H10K 85/60 - Composés organiques à faible poids moléculaire
C07D 405/10 - Composés hétérocycliques contenant à la fois un ou plusieurs hétérocycles comportant des atomes d'oxygène comme uniques hétéro-atomes du cycle et un ou plusieurs hétérocycles comportant des atomes d'azote comme uniques hétéro-atomes du cycle contenant deux hétérocycles liés par une chaîne carbonée contenant des cycles aromatiques
A touch panel with higher sensing accuracy or higher detection sensitivity is provided. The touch panel includes a first conductive layer, a second conductive layer, a plurality of display elements, and a scan line. In a plan view, the first conductive layer has an outline including a first portion that is linear and parallel to a first direction. In the plan view, the second conductive layer has an outline including a second portion that is linear and parallel to the first direction. The first portion and the second portion face each other. The display element is in a position not overlapping with the first conductive layer nor the second conductive layer. The scan line has a portion extending in a second direction. An angle between the first direction and the second direction is greater than or equal to 30° and less than or equal to 60°.
A display device capable of displaying high-quality images can be provided. A display device includes a first light-emitting element, a second light-emitting element, a first protective layer, a second protective layer, and a gap. The first light-emitting element includes a first lower electrode, a first EL layer over the first lower electrode, a first upper electrode over the first EL layer, and the second light-emitting element includes a second lower electrode, a second EL layer over the second lower electrode, and a second upper electrode over the second EL layer. The first light-emitting element and the second light-emitting element are adjacent to each other. The first protective layer is provided over the first light-emitting element and the second light-emitting element and includes a region in contact with the side surface of the first EL layer and the side surface of the second EL layer. The second protective layer is provided over the first protective layer. The gap is provided between the first EL layer and the second EL layer and is provided between the first protective layer and the second protective layer.
A display device in which a puddle in the vicinity of a partition of a light-emitting element is reduced when a light-emitting layer is formed by a wet process is provided. The display device includes a first anode; a second anode adjacent to the first anode in an X direction; a third anode adjacent to the first anode in a Y direction; a hole-injection layer provided across the first anode to the third anode; a partition provided over the hole-injection layer; a first light-emitting layer; a second light-emitting layer; a third light-emitting layer; and a cathode. The partition includes, in a top view, a first region positioned between the first anode and the third anode and extending in the X direction, and a second region positioned between the first anode and the second anode and extending in the Y direction. The height of the first region is larger than the height of the second region in a cross-sectional view of the partition.
H10K 71/13 - Dépôt d'une matière active organique en utilisant un dépôt liquide, p. ex. revêtement par centrifugation en utilisant des techniques d'impression, p. ex. l’impression par jet d'encre ou la sérigraphie
H10K 71/60 - Formation de régions ou de couches conductrices, p. ex. d’électrodes
H10K 77/10 - Substrats, p. ex. substrats flexibles
H10K 102/00 - Détails de structure relatifs aux dispositifs organiques couverts par la présente sous-classe
59.
Positive Electrode Active Material, Method for Manufacturing Positive Electrode Active Material, and Secondary Battery
A positive electrode active material which can improve cycle characteristics of a secondary battery is provided. Two kinds of regions are provided in a superficial portion of a positive electrode active material such as lithium cobaltate which has a layered rock-salt crystal structure. The inner region is a non-stoichiometric compound containing a transition metal such as titanium, and the outer region is a compound of representative elements such as magnesium oxide. The two kinds of regions each have a rock-salt crystal structure. The inner layered rock-salt crystal structure and the two kinds of regions in the superficial portion are topotaxy; thus, a change of the crystal structure of the positive electrode active material generated by charging and discharging can be effectively suppressed. In addition, since the outer coating layer in contact with an electrolyte solution is the compound of representative elements which is chemically stable, the secondary battery having excellent cycle characteristics can be obtained.
H01M 4/131 - Électrodes à base d'oxydes ou d'hydroxydes mixtes, ou de mélanges d'oxydes ou d'hydroxydes, p. ex. LiCoOx
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
H01M 4/1315 - Électrodes à base d'oxydes ou d'hydroxydes mixtes, ou de mélanges d'oxydes ou d'hydroxydes, p. ex. LiCoOx contenant des atomes d'halogène, p. ex. LiCoOxFy
H01M 4/134 - Électrodes à base de métaux, de Si ou d'alliages
H01M 4/1391 - Procédés de fabrication d'électrodes à base d'oxydes ou d'hydroxydes mixtes, ou de mélanges d'oxydes ou d'hydroxydes, p. ex. LiCoOx
H01M 4/13915 - Procédés de fabrication d'électrodes à base d'oxydes ou d'hydroxydes mixtes, ou de mélanges d'oxydes ou d'hydroxydes, p. ex. LiCoOx contenant des atomes d'halogène, p. ex. LiCoOxFy
H01M 4/36 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
H01M 4/62 - Emploi de substances spécifiées inactives comme ingrédients pour les masses actives, p. ex. liants, charges
H01M 4/86 - Électrodes inertes ayant une activité catalytique, p. ex. pour piles à combustible
H01M 10/0525 - Batteries du type "rocking chair" ou "fauteuil à bascule", p. ex. batteries à insertion ou intercalation de lithium dans les deux électrodesBatteries à l'ion lithium
A lithium-ion secondary battery with excellent cycle performance and safety is provided. The lithium-ion secondary battery includes a positive electrode, a negative electrode, and an electrolyte solution. The positive electrode includes lithium cobalt oxide whose median diameter (D50) is greater than 12 μm. The lithium cobalt oxide includes magnesium in its surface portion. The negative electrode includes a graphite particle, a silicon particle, and a high molecular including a carboxy group.
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
H01M 4/36 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs
H01M 4/38 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'éléments simples ou d'alliages
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
H01M 4/583 - Matériau carboné, p. ex. composés au graphite d'intercalation ou CFx
H01M 4/62 - Emploi de substances spécifiées inactives comme ingrédients pour les masses actives, p. ex. liants, charges
H01M 10/0563 - Matériaux liquides, p. ex. pour éléments au Li-SOCl2
A semiconductor device that includes different kinds of memory devices in the same chip is provided. Data transfer speed between two memory devices is improved. The semiconductor device includes a first layer, a second layer, and a third layer. The first layer includes a first storage device where a plurality of nonvolatile first storage elements are stacked in a thickness direction of the first layer. The second layer includes a second storage device that includes a plurality of second storage elements each including a transistor including an oxide semiconductor. The third layer includes a first driver circuit controlling operation of the first storage device and a second driver circuit controlling operation of the second storage device. The first layer, the second layer, and the third layer include a portion where they overlap each other.
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 14/00 - Mémoires numériques caractérisées par des dispositions de cellules ayant des propriétés de mémoire volatile et non volatile pour sauvegarder l'information en cas de défaillance de l'alimentation
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 53/40 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
62.
Semiconductor Device And Method For Manufacturing The Semiconductor Device
A semiconductor device that can be miniaturized or highly integrated is provided, which includes a memory device, a sense amplifier, and a processing portion. The sense amplifier and the processing portion are placed on a first layer, and the memory device is placed on a second layer stacked over the first layer. The memory device includes first and second transistors and a capacitor, the second transistor and the capacitor are each provided over the first transistor to overlap therewith, and the second transistor is positioned diagonally above the first transistor. A source electrode and a drain electrode of each of the first and second transistors are provided at different levels with respect to a substrate surface to overlap with each other. A gate electrode of the first transistor has both a function of one of the source electrode and the drain electrode of the second transistor and a function of one electrode of the capacitor. A dielectric layer of the capacitor is provided over the gate electrode of the first transistor. Over the dielectric layer of the capacitor, the other electrode of the capacitor is provided apart from a gate electrode of the second transistor.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 53/10 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la configuration vue du dessus
H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
A novel photoelectric conversion device that is highly convenient, useful, or reliable is provided. The photoelectric conversion device includes a first electrode (551S), a second electrode (552S), and a first unit (103S). The first unit (103S) is interposed between the first electrode (551S) and the second electrode (552S). The first unit (103S) includes a first layer (112) and a second layer (114S). The first layer (112) is interposed between the second layer (114S) and the first electrode (551S). The first layer (112) includes a first organic compound HTM, and the first organic compound HTM has a hole-transport property. The second layer (114S) includes a second organic compound CTM, the second organic compound CTM emits delayed fluorescent light at room temperature, and the second organic compound has an aromatic amine skeleton.
An information processing system comprising three components is provided. The first component receives a document and a target, transmits the document and the target to the third component, and receives and provides an embodiment draft. The second component receives a prompt and generates a composition and the embodiment draft using a large language model. The third component receives and shares the document, the target, and the composition, and receives the embodiment draft, and transmits the embodiment draft to the first component. The third component also includes a subcomponent for creating and executing a prompt chain. The system proposes the composition not described in the document, proposes the composition relevant to the target, and generates the embodiment draft on the basis of the composition. A user can implement the composition in accordance with the proposal or the embodiment draft and confirm the effect of the composition.
A touch panel capable of performing display and sensing along a curved surface or a touch panel that maintains high detection sensitivity even when it is curved along a curved surface is provided. A flexible display panel is placed along a curved portion included in a surface of a support. A first film layer is attached along a surface of the display panel by a bonding layer. Second to n-th film layers (n is an integer of 2 or more) are sequentially attached along a surface of the first film layer by bonding layers. A flexible touch sensor is attached along a surface of the n-th film layer by a bonding layer.
A semiconductor device with a novel structure is provided. A first element layer is provided with an arithmetic unit. A second element layer is provided with a memory unit. The arithmetic unit includes a first transistor in which a first semiconductor layer including a channel formation region contains silicon. The memory unit includes the first transistor and a second transistor in which a second semiconductor layer including a channel formation region contains an oxide semiconductor. The arithmetic unit includes an instruction decoding portion. The memory unit includes an instruction cache. The second element layer includes a plurality of layers each including the second transistor, and layers including the second transistors are stacked. The instruction cache is provided in a region included in the second element layer above the instruction decoding portion provided in the first element layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/405 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe avec trois portes à transfert de charges, p. ex. transistors MOS, par cellule
67.
SEMICONDUCTOR DEVICE, MEMORY DEVICE, ELECTRONIC DEVICE, AND PROCESSING DEVICE
A semiconductor device comprising a first layer including a processing portion and a sense amplifier and a second layer including a memory cell is provided. The memory cell is included in a memory device that is used as a cache memory or a main memory in the processing portion. The sense amplifier has a function of reading data retained in the memory cell, and the memory cell includes a transistor and a capacitor. In particular, the transistor is a vertical transistor whose channel formation region is included in a first opening of a first insulating layer. The capacitor includes a first capacitor region in a second opening of a second insulating layer and a second capacitor region in a region overlapping with a top surface of the second insulating layer. The first opening includes a region overlapping with at least part of the second capacitor region.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 53/10 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la configuration vue du dessus
H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
A novel human interface with excellent operability is provided. A novel data processing device with excellent operability is provided. A novel data processing device, a novel display device, or the like is provided. An input and output device is supplied with image data and supplies sensing data, and an arithmetic device supplies the image data and is supplied with the sensing data. The input and output device includes a plurality of display portions that display display data and a sensing portion that senses an object obscuring one of the display portions, and includes one region provided with the one of the display portions and the sensing portion, another region provided with the other display portions, and a curved portion between the one region and the other region. The arithmetic device includes an arithmetic portion and a memory portion that stores a program to be executed by the arithmetic portion.
A novel compound is provided. The novel compound is represented by General Formula (G1).
A novel compound is provided. The novel compound is represented by General Formula (G1).
A novel compound is provided. The novel compound is represented by General Formula (G1).
In General Formula (G1), A represents a substituted or unsubstituted condensed aromatic ring having 10 to 30 carbon atoms or a substituted or unsubstituted condensed heteroaromatic ring having 10 to 30 carbon atoms, and R1 represents a substituted or unsubstituted aryl group having 6 to 25 carbon atoms. Each of Y1 and Y2 independently represents a cycloalkyl group having a bridge structure and having 7 to 10 carbon atoms.
C09K 11/06 - Substances luminescentes, p. ex. électroluminescentes, chimiluminescentes contenant des substances organiques luminescentes
C07C 211/61 - Composés contenant des groupes amino liés à un squelette carboné ayant des groupes amino liés à des atomes de carbone de cycles aromatiques à six chaînons du squelette carboné ayant des groupes amino liés à des atomes de carbone de cycles aromatiques à six chaînons faisant partie de systèmes cycliques condensés du squelette carboné avec au moins un des systèmes cycliques condensés formé par trois cycles ou plus
C09K 11/02 - Emploi de substances particulières comme liants, revêtements de particules ou milieux de suspension
H10K 50/11 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL]
H10K 50/12 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] comprenant des dopants
H10K 59/12 - Affichages à OLED à matrice active [AMOLED]
H10K 59/131 - Interconnexions, p. ex. lignes de câblage ou bornes
H10K 59/35 - Dispositifs spécialement adaptés à l'émission de lumière multicolore comprenant des sous-pixels rouge-vert-bleu [RVB]
H10K 59/38 - Dispositifs spécialement adaptés à l'émission de lumière multicolore comprenant des filtres de couleur ou des supports changeant de couleur [CCM]
A control system for a secondary battery which is less affected by the ambient temperature by performing temperature control of the secondary battery is provided. A control system for a secondary battery which is less affected by the ambient temperature and in which a plurality of kinds of secondary batteries are used for temperature control is achieved and mounted on a vehicle. Specifically, when the ambient temperature is low, some of second secondary batteries are heated by self-heating of a first secondary battery. After the second secondary batteries are sufficiently heated, the rest of the second secondary batteries are heated in stages by self-heating of the some of the second secondary batteries whose temperature has been increased. Whether the some or all of the second secondary batteries are sufficiently heated can be confirmed if the temperatures of a plurality of temperature sensors provided in the second secondary batteries are within the operating temperature range of the second secondary batteries. For example, with the use of a temperature sensing terminal (T terminal) for a temperature sensor, a switch is closed when the internal temperature of the secondary batteries is out of the operating temperature range.
H01M 10/0525 - Batteries du type "rocking chair" ou "fauteuil à bascule", p. ex. batteries à insertion ou intercalation de lithium dans les deux électrodesBatteries à l'ion lithium
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
A positive electrode active material particle with little deterioration is provided. A power storage device with little deterioration is provided. A highly safe power storage device is provided. The positive electrode active material particle includes a first crystal grain, a second crystal grain, and a crystal grain boundary positioned between the crystal grain and the second crystal grain; the first crystal grain and the second crystal grain include lithium, a transition metal, and oxygen; the crystal grain boundary includes magnesium and oxygen; and the positive electrode active material particle includes a region where the ratio of the atomic concentration of magnesium in the crystal grain boundary to the atomic concentration of the transition metal in first crystal grain and the second crystal grain is greater than or equal to 0.010 and less than or equal to 0.50.
H01M 4/36 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
H01M 4/505 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de manganèse d'oxydes ou d'hydroxydes mixtes contenant du manganèse pour insérer ou intercaler des métaux légers, p. ex. LiMn2O4 ou LiMn2OxFy
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
A semiconductor device with a novel structure is provided. The semiconductor device includes a first arithmetic device including a register, a second arithmetic device including memory circuits, layer selection circuits, and an arithmetic circuit. The first arithmetic device and the second arithmetic device are each provided in an element layer where a plurality of second element layers are stacked over a first element layer. The register includes flip-flop and data retention circuits. The flip-flop and the arithmetic circuit are provided in the first element layer. The data retention circuits are provided in the plurality of second element layers over the first element layer provided with the flip-flop. The memory circuits and the layer selection circuit are provided in the plurality of second element layers over the first element layer provided with the arithmetic circuit.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10D 62/83 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé
A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
H10K 59/126 - Blindage, p. ex. moyens de blocage de la lumière sur les TFT
A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes first to fifth circuits. Each of the first to fourth circuits includes first and second cells, a sixth circuit, first and second current generation circuits, a first input terminal, and a second output terminal. The first circuit to the fourth circuit are electrically connected to each other in a ring, and the first circuit is electrically connected to the fifth circuit. In each of the first to fourth circuits, the first cell is electrically connected to the second cell through the first wiring, the first current generation circuit, and the third wiring, and is electrically connected to the first input terminal and the sixth circuit through the second wiring. The second cell is electrically connected to the first output terminal through the second current generation circuit. Note that the first current generation circuit functions as a current mirror circuit, and the second current generation circuit functions as an arithmetic circuit of a function system. The first cell performs an arithmetic operation of a product, and the second cell retains the result of the arithmetic operation.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H10D 62/80 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux
H10D 80/20 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex des ensembles comprenant des condensateurs, des transistors FET de puissance ou des diodes Schottky
A display apparatus with a driver circuit having redundancy is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a first driver circuit and a second driver circuit. The second layer includes a first pixel region and a second pixel region. The first pixel region includes a first pixel circuit and the second pixel region includes a second pixel circuit. The first pixel region includes a region overlapping with the first circuit and the second pixel region includes a region overlapping with the second circuit. The first pixel circuit is electrically connected to the first driver circuit through a first wiring, the second pixel circuit is electrically connected to the second driver circuit through a second wiring, and the first wiring is electrically connected to the second wiring through a switch.
H10K 59/131 - Interconnexions, p. ex. lignes de câblage ou bornes
H10K 59/12 - Affichages à OLED à matrice active [AMOLED]
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
H10K 59/127 - Affichages à OLED à matrice active [AMOLED] comprenant deux substrats, p. ex. un affichage comprenant une matrice OLED et un circuit de commande de TFT sur des substrats différents
A novel semiconductor device is provided. The semiconductor device includes an oxide semiconductor as a first semiconductor, silicon as a second semiconductor, and a plurality of memory cells lined up in a first direction; and a memory cell includes a writing transistor and a reading transistor. The first semiconductor and the second semiconductor extend in the first direction, part of the first semiconductor functions as a channel formation region of the writing transistor, and part of the second semiconductor functions as a channel formation region of the reading transistor. The second semiconductor includes a region in contact with a first layer containing a first metal element.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
77.
DISPLAY APPARATUS, DISPLAY MODULE, AND ELECTRONIC DEVICE
A novel display apparatus that is highly convenient, useful, or reliable is provided. The display apparatus includes a first light-emitting device, a first layer, a first reflective film, a second light-emitting device, a second layer, and a second reflective film. The first light-emitting device includes a third layer, a first electrode, and a first unit. The first unit is interposed between the first electrode and the third layer. The first unit includes a first light-emitting material. The first light-emitting material has an emission spectrum having a peak at a first wavelength. The third layer has a light-transmitting property and includes a second electrode. The first layer is interposed between the third layer and the first reflective film. The first layer has a light-transmitting property and an ordinary refractive index lower than that of the third layer at the first wavelength. The second light-emitting device includes a fourth layer, a third electrode, and a second unit. The second unit is interposed between the third electrode and the fourth layer. A space is provided between the fourth layer and the third layer. The second layer is interposed between the fourth layer and the second reflective film.
A display device having both a touch detection function and a function of capturing an image of a shape of a fingerprint or a vein is provided. The display device includes a first substrate, a first light-emitting element, a second light-emitting element, a light-receiving element, a light-blocking layer, a first resin layer, and a second resin layer. The first light-emitting element and the light-receiving element are arranged over the first substrate, and the first resin layer is provided over the first light-emitting element and the light-receiving element. The light-blocking layer is provided over the first resin layer, and the second light-emitting element is provided over the light-blocking layer. The second resin layer is provided over the second light-emitting layer. The first light-emitting element emits visible light upward, and the second light-emitting element emits invisible light upward. The light-receiving element is a photoelectric conversion element having sensitivity to visible light and invisible light. In a plan view, the light-blocking layer includes a portion positioned between the first light-emitting element and the light-receiving element, and the second light-emitting element overlaps with the light-blocking layer and is positioned inside the outline of the light-blocking layer.
A method for modifying an insulating film is provided. The method includes a first step of preparing an insulating film containing hydrogen, and a second step of performing microwave treatment on the insulating film to release the hydrogen in the insulating film as water molecules, so that a hydrogen concentration in the insulating film is reduced. Note that the microwave treatment is preferably performed using an oxygen gas and an argon gas at a temperature range of higher than or equal to 200° C. and lower than or equal to 300° C., and the proportion of the flow rate of the oxygen gas to the total of the flow rate of the oxygen gas and the flow rate of the argon gas is preferably greater than 0% and less than or equal to 50%.
Highly accurate document search, especially intellectual property-related document search, is achieved with a simple input method. A processing portion has a function of generating text analysis data from text data input to an input portion; a function of extracting a search word from words included in the text analysis data; and a function of generating first search data from the search word on the basis of weight dictionary data and thesaurus data. A memory portion stores second search data generated when the first search data is modified by a user. The processing portion updates the thesaurus data in accordance with the second search data.
A highly safe secondary battery is provided. The secondary battery includes a positive electrode and a negative electrode. The positive electrode includes a positive electrode active material. The positive electrode active material includes lithium cobalt oxide including magnesium. Magnesium concentration in a surface portion of the positive electrode active material is higher than magnesium concentration in an inner portion of the positive electrode active material. The negative electrode includes a negative electrode active material. The negative electrode active material includes a carbon material. The secondary battery is subjected to AC impedance measurement in a state where charging is performed until a voltage reaches 4.5 V, an AC impedance value at a frequency of 1 kHz is less than 90 mΩ.
H01M 4/505 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de manganèse d'oxydes ou d'hydroxydes mixtes contenant du manganèse pour insérer ou intercaler des métaux légers, p. ex. LiMn2O4 ou LiMn2OxFy
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
H01M 4/1315 - Électrodes à base d'oxydes ou d'hydroxydes mixtes, ou de mélanges d'oxydes ou d'hydroxydes, p. ex. LiCoOx contenant des atomes d'halogène, p. ex. LiCoOxFy
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
H01M 4/583 - Matériau carboné, p. ex. composés au graphite d'intercalation ou CFx
H01M 10/0525 - Batteries du type "rocking chair" ou "fauteuil à bascule", p. ex. batteries à insertion ou intercalation de lithium dans les deux électrodesBatteries à l'ion lithium
H01M 10/0569 - Matériaux liquides caracterisés par les solvants
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
A semiconductor device that occupies a small area is provided. The semiconductor device includes a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a second conductive layer, and a first semiconductor layer. The second transistor includes a third conductive layer over the first insulating layer, a second insulating layer in contact with a top surface and a side surface of the third conductive layer and a top surface of the first insulating layer, a third insulating layer over the second insulating layer, and a second semiconductor layer over the third insulating layer. The first insulating layer is provided over the first conductive layer. The first insulating layer and the second insulating layer include a first opening reaching the first conductive layer. The second conductive layer is provided over the second insulating layer. The second conductive layer includes a second opening in a region overlapping with the first opening. In the first opening and the second opening, the first semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second insulating layer, and a side surface of the second conductive layer.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10H 29/32 - Affichages LED à matrice active caractérisés par la géométrie ou l’agencement des éléments à l’intérieur d’un sous-pixel, p. ex. l’agencement du transistor à l’intérieur de son sous-pixel RGB
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
A display device with excellent characteristics is provided. The display device includes a first tandem light-emitting device, a second tandem light-emitting device, and a third tandem light-emitting device emitting light with different hues. The first to third tandem light-emitting devices each include a first light-emitting layer, a second light-emitting layer, and an intermediate layer sandwiched between the first light-emitting layer and the second light-emitting layer. In each of at least two of the first to third tandem light-emitting devices, an orientation parameter a of a transition dipole moment of an emission center substance in each of the first light-emitting layer and the second light-emitting layer is less than or equal to 0.25.
H10K 59/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément organique émetteur de lumière couvert par le groupe
One embodiment of the present invention provides a secondary battery that can be used in a wide temperature range and is not susceptible to the ambient temperature. Another embodiment of the present invention provides a highly safe secondary battery. A barrier layer is provided for a positive electrode active material, and an electrolyte containing fluorinated cyclic carbonate or fluorinated linear carbonate is used. The structure of this embodiment leads to a state where almost no coating film, ideally no coating film, is formed on a surface of the positive electrode active material. In addition, aging treatment for forming a coating film on the positive electrode active material can be unnecessary.
H01M 10/0525 - Batteries du type "rocking chair" ou "fauteuil à bascule", p. ex. batteries à insertion ou intercalation de lithium dans les deux électrodesBatteries à l'ion lithium
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
H01M 4/505 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de manganèse d'oxydes ou d'hydroxydes mixtes contenant du manganèse pour insérer ou intercaler des métaux légers, p. ex. LiMn2O4 ou LiMn2OxFy
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
H01M 10/0569 - Matériaux liquides caracterisés par les solvants
A semiconductor device with a novel structure is provided. The semiconductor device includes a first element layer and a second element layer including n (n is an integer greater than or equal to 2) element layers. The memory circuit includes n memory cells each having a function of retaining n-bit data. The n memory cells each include a first transistor and a second transistor and has a function of retaining a potential corresponding to the data by turning off the first transistor and a function of allowing a current with an amount corresponding to the data to flow by applying the potential to a gate of the second transistor. Any one of the n memory cells is provided in any one of the n element layers. A parallel number of the second transistors electrically connected to the second wiring is different between the n memory cells, and the parallel number corresponds to a power of two.
A semiconductor device with high reliability is provided. A latch circuit including Si transistors is combined with a memory circuit including OS transistors. A soft error is less likely to occur in the memory circuit including OS transistors. The logic value of the latch circuit and the logic value of the memory circuit including OS transistors are compared and a comparison result is output. The logic value of the latch circuit is inverted in accordance with the comparison result. High-speed operation by the latch circuit including Si transistors and high reliability by the memory circuit including OS transistors are achieved.
A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.
G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides
G02F 1/1362 - Cellules à adressage par une matrice active
G02F 1/1368 - Cellules à adressage par une matrice active dans lesquelles l'élément de commutation est un dispositif à trois électrodes
G11C 19/28 - Mémoires numériques dans lesquelles l'information est déplacée par échelons, p. ex. registres à décalage utilisant des éléments semi-conducteurs
A high-resolution or high-definition display device is provided. The display device includes a first light-emitting device and a second light-emitting device. The first light-emitting device includes a first pixel electrode, a first hole-injection layer, a first hole-transport layer, a first light-emitting layer, a first electron-transport layer, a second electron-transport layer, and a common electrode that are stacked in this order. The second light-emitting device includes a second pixel electrode, a second hole-injection layer, a second hole-transport layer, a second light-emitting layer, a third electron-transport layer, a second electron-transport layer, and a common electrode that are stacked in this order. The first light-emitting device and the second light-emitting device have a function of emitting light of different colors from each other. The second electron-transport layer covers at least a side surface of the first pixel electrode, a side surface of the second pixel electrode, a side surface of the first light-emitting layer, and a side surface of the second light-emitting layer.
H10K 59/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément organique émetteur de lumière couvert par le groupe
H10K 59/35 - Dispositifs spécialement adaptés à l'émission de lumière multicolore comprenant des sous-pixels rouge-vert-bleu [RVB]
A semiconductor device that operates stably is provided. The semiconductor device retains the potential of a floating node stably with use of a transistor with a long channel length. The transistor includes first to third conductive layers, a semiconductor layer, and an insulating film. The first and second conductive layers each include a region in contact with a top surface of a first insulating layer. The semiconductor layer includes a region in contact with a side surface of an opening formed in the first insulating layer, a top surface of a second insulating layer in a bottom portion of the opening, a top surface of the first conductive layer, and a top surface of the second conductive layer. The insulating film includes a region in contact with a top surface of the semiconductor layer, the top surface of the first conductive layer, and the top surface of the second conductive layer. The third conductive layer includes a region overlapping with at least part of the semiconductor layer and in contact with a top surface of the insulating film. The transistor includes a channel formation region in the semiconductor layer. In a display apparatus, the semiconductor device can be provided in a driver circuit having a function of transmitting a signal for displaying an image.
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
G02F 1/1368 - Cellules à adressage par une matrice active dans lesquelles l'élément de commutation est un dispositif à trois électrodes
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10H 29/32 - Affichages LED à matrice active caractérisés par la géométrie ou l’agencement des éléments à l’intérieur d’un sous-pixel, p. ex. l’agencement du transistor à l’intérieur de son sous-pixel RGB
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
A metal oxide film having high carrier mobility is provided. In the metal oxide film, a sum of a content percentage of indium and a content percentage of zinc is greater than or equal to 95%. The metal oxide film includes a crystal. The crystal includes a layered crystal structure. In the crystal, the ratio of the number of zinc atoms to the number of indium atoms is greater than 0 and less than 1.5. The electron effective mass in the crystal is smaller than the electron effective mass in an indium oxide having a cubic crystal structure. The metal oxide film may include tin, and the content percentage of tin is higher than or equal to 0.1% and lower than or equal to 3%.
C30B 29/68 - Cristaux avec une structure multicouche, p. ex. superréseaux
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
A display apparatus suitable for an under-display camera system is provided. The display apparatus includes a first display portion and a second display portion having the same pixel density. A first pixel included in the first display portion includes a subpixel R, a subpixel G, a subpixel B, and a subpixel W, and a second pixel included in the second display portion has a structure in which the subpixel W is removed from the first pixel and a light-transmitting region with an area equivalent to one subpixel is provided. By providing the second display portion and a lens of a camera to overlap with each other, imaging through the light-transmitting region can be performed.
H10H 29/32 - Affichages LED à matrice active caractérisés par la géométrie ou l’agencement des éléments à l’intérieur d’un sous-pixel, p. ex. l’agencement du transistor à l’intérieur de son sous-pixel RGB
H10H 29/34 - Affichages LED à matrice active caractérisés par la géométrie ou l’agencement des sous-pixels à l’intérieur d’un pixel, p. ex. la disposition relative des sous-pixels RGB
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
H10K 59/65 - OLED intégrées avec des capteurs d'images inorganiques
A display device capable of image capturing with high sensitivity is provided. A light-emitting element emitting visible light, an infrared light-emitting element emitting infrared light, and a light-receiving element that has sensitivity to infrared light are provided in a display region. After the light-emitting element emits light to display an image on the display region, black display is performed. In the period in which black display is performed, the infrared light-emitting element emits light and light exposure is performed on the light-receiving element. The light-receiving element detects infrared light emitted from the infrared light-emitting element and reflected by an object that is in contact with or approaches the display region. The display device functions as a touch sensor or a noncontact sensor.
G09G 3/3208 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED]
G06F 3/042 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens opto-électroniques
An EL layer includes a low refractive index layer comprising an organic compound and a light-emitting layer comprising a light-emitting substance. The organic compound has an ordinary refractive index of 1.50 to 1.75 with respect to light at 455 nm to 465 nm, or an ordinary refractive index of 1.45 to 1.70 with respect to light at 633 nm. Given that a wavelength corresponding to an intensity 1/e times a maximum peak intensity in an emission spectrum of the light-emitting substance is λn, a shortest λn in a range of wavelengths longer than a maximum peak wavelength λmax of the light-emitting substance is λ1, and a longest λn in a range of wavelengths shorter than λmax is λ2, a difference between λ1 and λ2 is greater than or equal to 5 nm and less than or equal to 45 nm.
A display device with high luminance is provided. A pixel includes a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor. One electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor. A gate of the first transistor is electrically connected to one electrode of the first capacitor and one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is electrically connected to one electrode of the second capacitor. One electrode of the second capacitor is electrically connected to a first wiring having a function of supplying a first potential. The other electrode of the second capacitor is electrically connected to the other electrode of the first capacitor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor.
G09G 3/3233 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active avec un circuit de pixel pour commander le courant à travers l'élément électroluminescent
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
G09G 3/30 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents
G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED]
A semiconductor device in which variation in characteristics is small is provided. A first insulator is formed; a first insulator is formed; a conductor is formed over the first insulator; a second insulator is formed over the conductor; a third insulator is formed over the second insulator; an oxide is formed over the third insulator; first heat treatment is performed; and second heat treatment following the first heat treatment is performed. The temperature of the first heat treatment is lower than the temperature of the second heat treatment.
A novel semiconductor device is provided. The semiconductor device includes a first circuit, a second circuit, and a third circuit, and the first circuit has a function of outputting a second signal corresponding to an input first signal, in synchronization with a clock signal. The second circuit has a function of retaining a third signal corresponding to the second signal even when power supply is stopped. The third circuit has a function of supplying a signal corresponding to the third signal to the first circuit in accordance with a selection signal. The second circuit includes an OS transistor.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
To obtain a technical feature from a claim of a patent to support comprehension of the claim. A text processing method, and a text processing device that has a function of performing processing using a language model, a function of generating a claim feature list from claim text using the language model, a function of searching a technical feature database for a technical feature similar to a claim feature in the claim feature list, a function of selecting a technical feature corresponding to the claim feature from a technical feature candidate list using the language model, and a function of outputting a technical feature list.
A display device that can easily achieve higher resolution is provided. A display device having high display quality and high resolution is provided. A display device with high contrast is provided. A highly reliable display device is provided. The display device is manufactured in the following manner: a first pixel electrode and a second pixel electrode are formed over a substrate; an insulating layer is formed between the first pixel electrode and the second pixel electrode; a conductive film is formed over the first pixel electrode, the second pixel electrode, and the insulating layer; a first side surface of the conductive film is formed by removing a portion of the conductive film overlapping with the first pixel electrode; a first organic compound layer is formed over the first pixel electrode and the conductive film; a sacrificial layer is formed over the first organic compound layer; a second side surface of the conductive film is formed by removing a portion of the conductive film overlapping with the second pixel electrode; a second organic compound layer is formed over the sacrificial layer and the second pixel electrode; the sacrificial layer is removed; and an upper electrode is formed over the first organic compound layer and the second organic compound layer to be in contact with the first side surface and the second side surface.
An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
G11C 11/405 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe avec trois portes à transfert de charges, p. ex. transistors MOS, par cellule
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
H10B 69/00 - Dispositifs de mémoire morte reprogrammable [EPROM] non couverts par les groupes , p. ex. dispositifs de mémoire morte reprogrammable aux ultraviolets [UVEPROM]
H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
H10D 62/80 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux
H10D 62/83 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/90 - Circuits intégrés à tranches maîtresses
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10D 87/00 - Dispositifs intégrés comprenant à la fois des composants en vrac et des composants SOI ou SOS sur le même substrat
It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power consumption is kept small. A semiconductor device which includes a plurality of pixels each including a display element and at least one first transistor and a scan line driver circuit supplying a signal for selecting the plurality of pixels to a scan line. A light-transmitting conductive layer is used for a pixel electrode layer of the display element, a gate electrode layer of the first transistor, source and drain electrode layers of the first transistor, and the scan line. The scan line driver circuit includes a second transistor and a capacitor for holding a voltage between a gate electrode layer of the second transistor and a source electrode layer of the second transistor. The source electrode of the second transistor is connected to the scan line.
G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides
G09G 3/3266 - Détails des circuits de commande pour les électrodes de balayage
G09G 3/34 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante
G11C 19/18 - Mémoires numériques dans lesquelles l'information est déplacée par échelons, p. ex. registres à décalage utilisant des capacités comme éléments principaux des étages
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
brevets
