A novel data processing device that is highly convenient, useful, or reliable is provided. The data processing device includes a memory unit and a processing unit. A program is stored in the memory unit, and the processing unit calculates a vertex normal vector in accordance with the program. The program is composed of five steps. In the first step, a unit region is placed on an object. The unit region has the center of gravity. In the second step, a portion where the unit region and the object overlap is specified. In the third step, the center of gravity of the overlap portion is specified. In the fourth step, a vector from the center of gravity of the overlap portion to a point in the object is specified. In the fifth step, the vector is used as a vertex normal vector at the point in the object.
A semiconductor device with little characteristic variation is provided. A transistor includes an oxide semiconductor; a first conductor and a second conductor over the oxide semiconductor; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator that is positioned over the first insulator and the second insulator and provided with a first opening overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned over the oxide semiconductor and between the first conductor and the second conductor; and a third conductor over the fourth insulator. A capacitor includes the second conductor; the third insulator provided with a second opening reaching the second conductor; a fifth insulator positioned inside the second opening; and a fourth conductor over the fifth insulator. A plug is positioned to penetrate the first insulator, the third insulator, the first conductor, and the oxide semiconductor. The plug is electrically connected to the first conductor. The first insulator and the second insulator are each formed using a metal oxide including an amorphous structure.
An electronic device including a flexible display panel is provided. The electronic device includes a display panel, a first component, a movable module, and a housing. The housing includes a first movable portion, a second component, and a third component. The third component includes a first space where the first component is stored. The display panel includes a flexible display portion. The display portion includes a first region, a second region, and a third region. The first region is fixed to the second component. The second region is fixed to the first component stored in the third component. The movable module has a function of holding a first angle that is formed between the second component and the third component by the first movable portion. The third region positioned between the first region and the second region has a function of forming a curved surface according to the first angle. The first component slides in the first space according to the first angle.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
To provide an electronic device capable of a variety of display. To provide an electronic device capable of being operated in a variety of ways. An electronic device includes a display device and first to third surfaces. The first surface includes a region in contact with the second surface, the second surface includes a region in contact with the third surface, and the first surface includes a region opposite to the third surface. The display device includes first to third display regions. The first display region includes a region overlapping with the first surface, the second display region includes a region overlapping with the second surface, and the third display region includes a region overlapping with the third surface. The first display region has a larger area than the third display region.
Provided is a display device having high display quality and low power consumption. The display device comprises an organic EL element on a microlens array that is formed on an insulation layer. The organic EL element includes an EL layer that is separated for each sub-pixel using a lithography step. A negative electrode is connected to a negative electrode line via a conductive layer in a relief part that is capable of being formed using a shared step with the microlens array. For the conductive layer, a layer that is capable of being formed by a shared step with a positive electrode is used. Therefore, it is possible to simplify a step for connecting the negative electrode to the negative electrode line.
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
G09F 9/00 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels
H10K 50/824 - Cathodes combinées avec des électrodes auxiliaires
H10K 50/858 - Dispositifs pour extraire la lumière des dispositifs comprenant des moyens de réfraction, p. ex. des lentilles
H10K 59/123 - Connexion des électrodes de pixel aux transistors à couches minces [TFT]
H10K 59/124 - Couches isolantes formées entre les éléments TFT et les éléments OLED
H10K 71/20 - Modification de la forme de la couche active dans les dispositifs, p. ex. mise en forme
6.
POSITIVE ELECTRODE ACTIVE MATERIAL PARTICLES AND LITHIUM ION SECONDARY BATTERY
Provided are novel positive electrode active material particles and a lithium ion secondary battery using the same. These positive electrode active material particles have lithium, a transition metal M, and oxygen. The transition metal M is one or more selected from the group consisting of cobalt, nickel, and manganese. Each of the positive electrode active material particles has, in the stated order from the surface toward the interior, a rock salt-type crystal structure, a spinel'-type crystal structure, and a layered rock salt-type crystal structure. When analyzed by using each of the particles as a whole, the positive electrode active material particle has a Ti/transition metal M ratio (a weight ratio) of 0.0005 or smaller.
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
C01G 51/42 - Oxydes complexes contenant du cobalt et au moins un autre élément métallique contenant des métaux alcalins, p. ex. LiCoO2
H01M 4/36 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs
H01M 4/505 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de manganèse d'oxydes ou d'hydroxydes mixtes contenant du manganèse pour insérer ou intercaler des métaux légers, p. ex. LiMn2O4 ou LiMn2OxFy
The present invention provides an imaging device that allows easy drive control. The imaging device includes circuit blocks arranged in two rows and two columns, pixel blocks arranged in two rows and two columns on the circuit blocks, and a control circuit. Pixels are arranged in a matrix in each of the pixel blocks. Each of the circuit blocks arranged in two rows and two columns has a plurality of drive circuits. Each of the plurality of drive circuits has a function of controlling driving of mutually different pixels. The circuit blocks arranged in two rows and two columns are laid out line-symmetrically about boundaries between the blocks. The control circuit has a function of simultaneously driving drive circuits having the same address among the drive circuits included in the circuit blocks arranged in two rows and two columns. The control circuit has a function of causing a part of the pixels included in each of the first to fourth pixel blocks to acquire imaging data.
H04N 25/76 - Capteurs adressés, p. ex. capteurs MOS ou CMOS
H04N 25/77 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
H04N 25/79 - Agencements de circuits répartis entre des substrats, des puces ou des cartes de circuits différents ou multiples, p. ex. des capteurs d'images empilés
H10F 39/18 - Capteurs d’images à semi-conducteurs d’oxyde de métal complémentaire [CMOS]Capteurs d’images à matrice de photodiodes
8.
POSITIVE ELECTRODE ACTIVE MATERIAL, POSITIVE ELECTRODE, SECONDARY BATTERY, ELECTRONIC DEVICE, AND VEHICLE
A positive electrode active material with high charge and discharge capacity is provided. A positive electrode active material with high charge and discharge voltage is provided. A secondary battery which hardly deteriorates is provided. A highly safe power storage device is provided. A novel secondary battery is provided. The positive electrode active material contains cobalt, oxygen, and fluorine and includes a bond of the cobalt and the fluorine in a surface portion or the vicinity of a grain boundary. By having the bond with fluorine, at least part of cobalt is high-spin (paramagnetic) Co2+. Thus, in ESR analysis, the spin concentration at 113 K is higher than the spin concentration at 300 K by 1.1×10−5 spins/g or more.
H01M 4/485 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques d'oxydes ou d'hydroxydes mixtes pour insérer ou intercaler des métaux légers, p. ex. LiTi2O4 ou LiTi2OxFy
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
H01M 4/62 - Emploi de substances spécifiées inactives comme ingrédients pour les masses actives, p. ex. liants, charges
H01M 10/0525 - Batteries du type "rocking chair" ou "fauteuil à bascule", p. ex. batteries à insertion ou intercalation de lithium dans les deux électrodesBatteries à l'ion lithium
A storage device that can be miniaturized or highly integrated is provided. The storage device includes a capacitor formed directly under a vertical transistor, and one of a source electrode and a drain electrode of the vertical transistor also serves as one electrode of the capacitor. It is thus possible to obtain a storage device that has a large overlapping area between the vertical transistor and the capacitor and a high degree of integration. Since the area proportion of the capacitor in the cell area can be increased, the capacitor can be reduced in height and a thin memory cell array can be formed.
Provided is a novel semiconductor device. The present invention includes a shift register, a first buffer, a second buffer, first wiring, and second wiring. The first buffer has a function by which, on the basis of a signal output from a first terminal of the shift register, a signal applied to the first wiring is supplied to a gate line provided to a first pixel region. The second buffer has a function by which, on the basis of a signal output from a second terminal of the shift register, a signal applied to the second wiring is supplied to a gate line provided to a second pixel region. The first pixel region has a function for performing display at a first resolution. The second pixel region has a function for performing display at the first resolution and a function for performing display at a second resolution. The second resolution is lower than the first resolution. When the first pixel region displays at the first resolution and the second pixel region displays at the second resolution, a constant potential or a signal having a pulse width longer than a pulse width of a signal applied to the first wiring is applied to the second wiring.
G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides
G02F 1/133 - Dispositions relatives à la structureExcitation de cellules à cristaux liquidesDispositions relatives aux circuits
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
G09G 3/3233 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active avec un circuit de pixel pour commander le courant à travers l'élément électroluminescent
G09G 3/3266 - Détails des circuits de commande pour les électrodes de balayage
G11C 19/28 - Mémoires numériques dans lesquelles l'information est déplacée par échelons, p. ex. registres à décalage utilisant des éléments semi-conducteurs
11.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
Provided is a highly reliable semiconductor device. The present invention has a semiconductor layer, a first conductive layer and a second conductive layer that are on the semiconductor layer and that are isolated from each other, an insulation layer that is located between the first conductive layer and the second conductive layer, and a third conductive layer that is on the insulation layer, wherein: the semiconductor layer has indium and oxygen; the semiconductor layer has a first region in contact with the first conductive layer, a second region in contact with the second conductive layer, and a third region located between the first region and the second region; the third region has boron; and the boron content in the third region is higher than each of the boron content in the first region and the boron content in the second region.
A display device having a photosensing function is provided. A display device having a biometric authentication function typified by fingerprint authentication is provided. A display device having both a touch panel function and a biometric authentication function is provided. The display device includes a first substrate, a light guide plate, a first light-emitting element, a second light-emitting element, and a light-receiving element. The first substrate and the light guide plate are provided to face each other. The first light-emitting element and the light-receiving element are provided between the first substrate and the light guide plate. The first light-emitting element has a function of emitting first light through the light guide plate. The second light-emitting element has a function of emitting second light to a side surface of the light guide plate. The light-receiving element has a function of receiving the second light and converting the second light into an electric signal. The first light includes visible light, and the second light includes infrared light.
H05B 33/14 - Sources lumineuses avec des éléments radiants ayant essentiellement deux dimensions caractérisées par la composition chimique ou physique ou la disposition du matériau électroluminescent
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
G06F 3/042 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens opto-électroniques
G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
A light-emitting device with a high resolution and high efficiency is provided. The light-emitting device includes a first EL layer, an intermediate layer, and a second EL layer between first and second electrodes. The first EL layer is provided between the first electrode and the intermediate layer, and the second EL layer is provided between the second electrode and the intermediate layer. Side surfaces of the first EL layer, the intermediate layer, and the second EL layer are substantially aligned. The first EL layer includes a layer having an electron-transport property. The intermediate layer is provided in contact with the layer having an electron-transport property. The intermediate layer includes a first organic compound and an alkali metal or a compound of an alkali metal. The layer having an electron-transport property includes a second organic compound. The second organic compound has a higher glass transition temperature than the first organic compound.
H10K 50/13 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] spécialement adaptées à l'émission de lumière multicolore, p. ex. à l'émission de lumière blanche comprenant des couches EL empilées dans une unité EL
H10K 85/60 - Composés organiques à faible poids moléculaire
H10K 101/30 - Valeurs d'énergie de la plus haute orbitale moléculaire occupée [HOMO], de la plus basse orbitale moléculaire inoccupée [LUMO] ou de Fermi
14.
METHOD FOR MANUFACTURING TANDEM-TYPE LIGHT-EMITTING DEVICE AND DISPLAY APPARATUS
Provided is a method for manufacturing a tandem-type light-emitting device which can be applied to a high-definition display apparatus and has a low drive voltage and good current efficiency. Provided is a method for manufacturing a tandem-type light-emitting device that includes a first light-emitting layer, an intermediate layer, and a second light-emitting layer in an EL layer, wherein: the intermediate layer contains a metal, a first organic compound, and a second organic compound; the first organic compound is an organic compound containing an electron-donating group and a first π-electron deficient heteroaromatic ring; the second organic compound is an organic compound having a second π-electron deficient heteroaromatic ring; and when processing the EL layer into a predetermined shape, an etching solution containing hydrofluoric acid and phosphoric acid and not containing nitric acid is used.
G09F 9/00 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
H05B 33/10 - Appareils ou procédés spécialement adaptés à la fabrication des sources lumineuses électroluminescentes
H05B 33/12 - Sources lumineuses avec des éléments radiants ayant essentiellement deux dimensions
H05B 33/14 - Sources lumineuses avec des éléments radiants ayant essentiellement deux dimensions caractérisées par la composition chimique ou physique ou la disposition du matériau électroluminescent
H10K 50/115 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] comprenant des nanostructures inorganiques actives, p. ex. des points quantiques luminescents
A semiconductor device that can be reduced in size or highly integrated is provided. The semiconductor device includes first and second transistors and first to third conductors. The first transistor includes first and second gate electrodes between which a semiconductor layer of the first transistor is positioned. The second gate electrode is provided over the semiconductor layer of the first transistor to overlap the first gate electrode. The second transistor includes a third gate electrode over a semiconductor layer of the second transistor. The second transistor is stacked over the first transistor. The third gate electrode overlaps the second gate electrode. The first conductor electrically connects a source electrode of the first transistor and a source electrode of the second transistor. The second conductor electrically connects a drain electrode of the first transistor and a drain electrode of the second transistor. The third conductor electrically connects the first gate electrode, the second gate electrode, and the third gate electrode.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
A transistor in which a short-channel effect is not substantially caused and which has switching characteristics even in the case where the channel length is short is provided. Further, a highly integrated semiconductor device including the transistor is provided. A short-channel effect which is caused in a transistor including silicon is not substantially caused in the transistor including an oxide semiconductor film. The channel length of the transistor including the oxide semiconductor film is greater than or equal to 5 nm and less than 60 nm, and the channel width thereof is greater than or equal to 5 nm and less than 200 nm. At this time, the channel width is made 0.5 to 10 times as large as the channel length.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
Provided is a light-emitting device that has excellent characteristics. Also provided is a novel organic compound. The light-emitting device includes a first electrode, a second electrode, and a light-emitting layer, wherein: the light-emitting layer is located between the first electrode and the second electrode; the light-emitting layer includes a first organic compound and a light-emitting substance; and the first organic compound has deuterium in a partial structure that greatly contributes to a lowest triplet excited state.
H10K 50/12 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] comprenant des dopants
C07D 209/86 - CarbazolesCarbazoles hydrogénés avec uniquement des atomes d'hydrogène, des radicaux hydrocarbonés ou des radicaux hydrocarbonés substitués, liés directement aux atomes de carbone du système cyclique
C07D 403/04 - Composés hétérocycliques contenant plusieurs hétérocycles, comportant des atomes d'azote comme uniques hétéro-atomes du cycle, non prévus par le groupe contenant deux hétérocycles liés par une liaison directe de chaînon cyclique à chaînon cyclique
C09K 11/06 - Substances luminescentes, p. ex. électroluminescentes, chimiluminescentes contenant des substances organiques luminescentes
H10K 85/60 - Composés organiques à faible poids moléculaire
H10K 101/30 - Valeurs d'énergie de la plus haute orbitale moléculaire occupée [HOMO], de la plus basse orbitale moléculaire inoccupée [LUMO] ou de Fermi
H10K 101/40 - Interrelation des paramètres entre plusieurs couches ou sous-couches actives constitutives, p. ex. valeurs HOMO dans des couches adjacentes
18.
POSITIVE ELECTRODE AND METHOD FOR MANUFACTURING POSITIVE ELECTRODE
H01M 4/58 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs de composés inorganiques autres que les oxydes ou les hydroxydes, p. ex. sulfures, séléniures, tellurures, halogénures ou LiCoFyEmploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs de structures polyanioniques, p. ex. phosphates, silicates ou borates
H01M 4/136 - Électrodes à base de composés inorganiques autres que les oxydes ou les hydroxydes, p. ex. sulfures, séléniures, tellurures, halogénures ou LiCoFy
H01M 4/1397 - Procédés de fabrication d’électrodes à base de composés inorganiques autres que les oxydes ou les hydroxydes, p. ex. sulfures, séléniures, tellurures, halogénures ou LiCoFy
H01M 4/36 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs
The present invention provides a semiconductor device having reduced power consumption. The semiconductor device has a first transistor, a second transistor, a third transistor, a first capacitive element, and a second capacitive element. The first transistor has a first gate and a second gate. The first gate of the first transistor is electrically connected to one among a source and a drain of the second transistor and a first terminal of the first capacitive element. The second gate of the first transistor is electrically connected to one among a source and a drain of the third transistor and a first terminal of the second capacitive element. The first transistor has a function for writing a first potential corresponding to first data to the first terminal of the first capacitive element and writing a second potential corresponding to second data to the first terminal of the second capacitive element, thereby causing a current corresponding to a multiplication result of the first data and the second data to flow between a source and a drain of the first transistor.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G06G 7/16 - Dispositions pour l'exécution d'opérations de calcul, p. ex. amplificateurs spécialement adaptés à cet effet pour la multiplication ou la division
G06G 7/60 - Calculateurs analogiques pour des procédés, des systèmes ou des dispositifs spécifiques, p. ex. simulateurs d'êtres vivants, p. ex. leur système nerveux
G06G 7/184 - Dispositions pour l'exécution d'opérations de calcul, p. ex. amplificateurs spécialement adaptés à cet effet pour l'intégration ou la différentiation utilisant des éléments capacitifs
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p. ex. neurone
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
20.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
Provided is a semiconductor device that has a transistor with little variation in electrical characteristics. This semiconductor device includes a transistor, and first and second insulating layers. The transistor includes first to third conductive layers, a semiconductor layer, and a third insulating layer. The first insulating layer overlaps with the first conductive layer and is located on the first conductive layer, the second conductive layer is located on the first insulating layer, ends of the first insulating layer and the second conductive layer coincide or substantially coincide, the second insulating layer is in contact with each of an upper surface and a side surface of the first conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer, the second insulating layer has a first opening overlapping with each of the first conductive layer and the second conductive layer, the semiconductor layer overlaps with the first opening and is located on the second insulating layer, and is in contact with, in the first opening, each of the upper surface of the first conductive layer, the side surface of the first insulating layer, and the upper surface and the side surface of the second conductive layer, the third insulating layer is located on the semiconductor layer, and the third conductive layer overlaps with the semiconductor layer and is located on the third insulating layer.
A semiconductor device is provided over a base insulating layer including hydrogen. A first conductive layer, a spacer, and a second conductive layer are provided over the base insulating layer. The spacer and the second conductive layer comprise an opening reaching the first conductive layer in which a metal oxide layer is provided. The metal oxide layer includes a region in contact with the first conductive layer and the second conductive layer. The first conductive layer and the second conductive layer function as one and the other of a source electrode and a drain electrode of the transistor. A gate insulating layer is provided over the metal oxide layer to include a region positioned in the opening. A gate electrode is provided to include a region facing the metal oxide layer with the gate insulating layer between the region and the metal oxide layer in the opening.
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10K 59/12 - Affichages à OLED à matrice active [AMOLED]
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
H10K 59/123 - Connexion des électrodes de pixel aux transistors à couches minces [TFT]
H10K 65/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément organique émetteur de lumière et au moins un composant organique sensible aux rayonnements, p. ex. des optocoupleurs organiques
A novel data processing system that is highly convenient, useful, or reliable. The data processing system is composed of three components. A first component has a function of receiving an original document and a translated document and providing a difference. A second component has a function of generating a question and answers with use of a large language model and transmitting a difference. A third component has a function of receiving and sharing various kinds of data and transmitting a prompt. The third component includes two subcomponents: a first subcomponent has a function of sharing the points to be noted with use of the database and the management system, and a second subcomponent has a function of creating a prompt. Each of the prompts includes an original document, a translated document, a question, an answer, a difference, and the like. These prompts are shared in the system and processed.
G06F 40/58 - Utilisation de traduction automatisée, p. ex. pour recherches multilingues, pour fournir aux dispositifs clients une traduction effectuée par le serveur ou pour la traduction en temps réel
A semiconductor device includes a first layer and a second layer over the first layer. The first layer and the second layer each include a transistor. The transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor over the first oxide, a first insulator placed to cover the first conductor, the second conductor, and the first oxide, a second insulator over the first insulator, a second oxide placed between the first conductor and the second conductor over the first oxide, a third insulator over the second oxide, a third conductor over the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor.
H10D 62/80 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
To provide a display device including a flexible panel that can be handled without seriously damaging a driver circuit or a connecting portion between circuits. The display device includes a bent portion obtained by bending an element substrate. A circuit for driving the display device is provided in the bent portion and a wiring extends from the circuit, whereby the strength of a portion including the circuit for driving the display device is increased and failure of the circuit is reduced. Furthermore, the element substrate is bent in a connecting portion between an external terminal electrode and an external connecting wiring (FPC) so that the element substrate provided with the external terminal electrode fits the external connecting wiring, whereby the strength of the connecting portion is increased.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
G02B 26/02 - Dispositifs ou dispositions optiques pour la commande de la lumière utilisant des éléments optiques mobiles ou déformables pour commander l'intensité de la lumière
G02F 1/1333 - Dispositions relatives à la structure
G02F 1/1345 - Conducteurs connectant les électrodes aux bornes de la cellule
G02F 1/1368 - Cellules à adressage par une matrice active dans lesquelles l'élément de commutation est un dispositif à trois électrodes
G02F 1/167 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur le mouvement de translation des particules dans un fluide sous l’influence de l’application d’un champ caractérisés par l’effet électro-optique ou magnéto-optique par électrophorèse
G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
A semiconductor device capable of product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding portion and a first transistor, and the second circuit includes a second holding portion and a second transistor. The first and second circuits are each electrically connected to first and second input wirings and first and second wirings. The first holding portion has a function of holding a first current flowing through the first transistor, and the second holding portion has a function of holding a second current flowing through the second transistor. The first and second currents are determined in accordance with first data. When a potential corresponding to second data is input to the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The amount of current output from the first or second circuit to the first wiring or the second wiring is determined in accordance with the first data and the second data.
G11C 11/405 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe avec trois portes à transfert de charges, p. ex. transistors MOS, par cellule
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
Text is generated from an object. Text is generated from a first object. The first object includes a second object and a third object. A step of detecting coordinate data of the second object is included. A step of detecting coordinate data of the third object is included. A step of extracting positional relation between the second object and the third object from coordinate data is included. A step of converting the extracted positional relation into graph data is included. A step of generating text about the positional relation between the second object and the third object from graph data is included.
A novel material and a transistor including the novel material are provided. One embodiment of the present invention is a composite oxide including at least two regions. One of the regions includes In, Zn and an element M1 (the element M1 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu) and the other of the regions includes In, Zn, and an element M2 (the element M2 is one or more of Al, Ga, Si, B, Y, Ti, Fe, Ni, Ge, Zr, Mo, La, Ce, Nd, Hf, Ta, W, Mg, V, Be, and Cu). In an analysis of the composite oxide by energy dispersive X-ray spectroscopy, the detected concentration of the element M1 in a first region is less than the detected concentration of the element M2 in a second region, and a surrounding portion of the first region is unclear in an observed mapping image of the energy dispersive X-ray spectroscopy.
H10D 62/80 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux
H10D 62/86 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe II-VI, p. ex. ZnO
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10D 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first transistor, a connection portion, a first insulator, a second insulator, and a first wiring. The connection portion includes a first electrode and a second electrode. The first transistor includes the second electrode, a third electrode, a first semiconductor, a gate insulator, and a first gate electrode. The first insulator includes a first opening reaching the first wiring. The first electrode is in contact with a side surface of the first opening and the top surface of the first wiring. The second electrode is in contact with the first electrode in the first opening. The second insulator includes a second opening reaching the second electrode. The third electrode is provided over the second insulator. The first semiconductor is in contact with the third electrode, a side surface of the second insulator in the second opening, and the top surface of the second electrode. The gate insulator is in contact with the first semiconductor in the second opening. The first gate electrode faces the first semiconductor with the gate insulator therebetween.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
A light-emitting device with a long lifetime is provided. A light-emitting device with high reliability is provided. The light-emitting device includes a first electrode, a first light-emitting layer, a first layer, a second layer, a third layer, a second light-emitting layer, and a second electrode stacked in this order. The first layer contains a first organic compound and a first substance. The second layer contains a second organic compound. The third layer contains a second substance. The first organic compound is an electron-transport material. The first substance is a metallic salt, a metal oxide, or an organometallic salt. The second organic compound is an electron-transport material. The second substance is an electron-injection material. The second layer has a lower concentration of the first substance than the first layer.
H10K 50/17 - Couches d'injection des porteurs de charge
H10K 85/60 - Composés organiques à faible poids moléculaire
H10K 101/40 - Interrelation des paramètres entre plusieurs couches ou sous-couches actives constitutives, p. ex. valeurs HOMO dans des couches adjacentes
30.
INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD
An inventor's maintenance or abandonment sorting task of a patent is assisted and creation of a reason for maintenance or abandonment of the patent that could convince the inventor is assisted. An information processing system has a function of performing processing using a language model, a function of generating a summary of patent information from the patent information, a function of generating a question relating to the patent, a function of generating a maintenance or abandonment determination result of the patent from the summary of the patent information, the question, and a reply to the question, and a function of generating a reason for maintenance or abandonment of the patent from the summary of the patent information, the maintenance or abandonment determination result of the patent, similar patents that have been determined to be maintained or abandoned, and reasons for determining maintenance or abandonment of the similar patents.
Provided is a highly reliable semiconductor device. The present invention has a semiconductor layer, an oxide layer, an insulating layer, and a conductive layer. The oxide layer is located between the semiconductor layer and the insulating layer, the conductive layer has a region overlapping the semiconductor layer with the oxide layer and the insulating layer interposed therebetween, the semiconductor layer comprises indium and oxygen, the insulating layer comprises a metal element and oxygen, the oxide layer comprises indium, the metal element, and oxygen, the metal element is an element capable of becoming a trivalent cation, the oxide layer has a region having a film thickness of 0.1-1 nm, and the electron affinity of the oxide layer is less than the electron affinity of the semiconductor layer and greater than the electron affinity of the insulating layer.
G09F 9/00 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
The present invention provides a semiconductor device that has a novel configuration. The semiconductor device includes a memory cell, a first sense amplifier, a product-sum operation circuit, a data holding circuit, and a second sense amplifier. The memory cell is electrically connected to the first sense amplifier via a first bit line. The first bit line is electrically connected to the product-sum operation circuit via the data holding circuit. The second sense amplifier is electrically connected to the first sense amplifier and the product-sum operation circuit via a second bit line. The first sense amplifier has a function of amplifying first data held by the memory cell selected by a word line selection signal, and a function of outputting the amplified first data to the second sense amplifier according to a column selection signal. The data holding circuit has a function of holding the amplified first data. The product-sum operation circuit has a function of executing a product-sum operation of the first data and the second data supplied from the second sense amplifier via the second bit line according to the column selection signal.
G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G11C 7/06 - Amplificateurs de lectureCircuits associés
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A semiconductor device with a novel structure is provided. A first element layer provided with a reading circuit, a second element layer provided with an amplifier circuit, and a third element layer provided with a memory cell are included. The second element layer is stacked over the first element layer. The third element layer is stacked over the second element layer. The memory cell and the amplifier circuit are electrically connected to each other through a first bit line. The amplifier circuit and the reading circuit are electrically connected to each other through a second bit line. The amplifier circuit has a function of transmitting a signal corresponding to a potential of the first bit line to the second bit line. The amplifier circuit includes a first transistor in which a first semiconductor layer including a channel formation region includes an oxide semiconductor. The memory cell includes a second transistor in which a second semiconductor layer including a channel formation region includes an oxide semiconductor and a capacitor. The first semiconductor layer is provided in a direction parallel to a surface of a substrate provided with the first element layer. The second semiconductor layer is provided in a direction perpendicular to the surface of the substrate provided with the first element layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
A semiconductor device including a transistor with a high on-state current is provided. The semiconductor device includes a first transistor, a first insulating layer, and a second insulating layer. The second insulating layer is provided in contact with a top surface of part of the first insulating layer. The first transistor includes a metal oxide layer, a third insulating layer, and a first conductive layer. The metal oxide layer is in contact with a top surface of the first insulating layer and a top surface and a side surface of the second insulating layer. The third insulating layer is in contact with a top surface and a side surface of the metal oxide layer, the top surface of the first insulating layer, and the top surface and the side surface of the second insulating layer. The first conductive layer includes a region overlapping with the side surface of the second insulating layer with the third insulating layer and the metal oxide layer therebetween. The second insulating layer includes a fourth insulating layer and a fifth insulating layer over the fourth insulating layer. The first insulating layer and the fifth insulating layer each contain nitrogen. The fourth insulating layer contains oxygen.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
An object is to provide a semiconductor device with reduced standby power. A transistor including an oxide semiconductor as an active layer is used as a switching element, and supply of a power supply voltage to a circuit in an integrated circuit is controlled by the switching element. Specifically, when the circuit is in an operation state, supply of the power supply voltage to the circuit is performed by the switching element, and when the circuit is in a stop state, supply of the power supply voltage to the circuit is stopped by the switching element. In addition, the circuit supplied with the power supply voltage includes a semiconductor element which is a minimum unit included in an integrated circuit formed using a semiconductor. Further, the semiconductor included in the semiconductor element contains silicon having crystallinity (crystalline silicon).
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
Provided is a novel semiconductor device. A first terminal of a first transistor is connected to a first terminal of a fifth transistor and a first terminal of a second capacitive element; a second terminal of the fifth transistor is connected to a first terminal of a second transistor, a first terminal of a fourth transistor, a first terminal of a sixth transistor, and a first terminal of a seventh transistor; a second terminal of the fourth transistor is connected to a first terminal of a first capacitive element and a second terminal of the second capacitive element; a gate of the second transistor is connected to a first terminal of a third transistor and a second terminal of the first capacitive element; and a second terminal of the sixth transistor is connected to a first terminal of a light-emitting element.
G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED]
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
G09G 3/3225 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10K 59/123 - Connexion des électrodes de pixel aux transistors à couches minces [TFT]
This semiconductor device includes: an oxide semiconductor; a first conductor and a second conductor disposed on the oxide semiconductor; a first insulator disposed on the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor; a second insulator disposed in the opening; a third conductor disposed on the second insulator in the opening; a third insulator disposed on the third conductor and the first insulator; a fourth conductor disposed in an opening formed in the first insulator and the third insulator and reaching the first conductor; and a fifth conductor disposed in an opening formed in the first insulator and the third insulator and reaching the second conductor, wherein the fourth conductor and the fifth conductor each have a sixth conductor, and a seventh conductor in contact with the lower surface and a side surface of the sixth conductor, and the seventh conductor has a region with a hydrogen concentration of less than 1×1022atoms/cm3.
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10K 59/12 - Affichages à OLED à matrice active [AMOLED]
Provided is a novel semiconductor device. The semiconductor device comprises: a first circuit including first to third transistors and an input terminal; and a fourth transistor. A first terminal of the first transistor is electrically connected to the input terminal, a gate of the first transistor, and a gate of the second transistor. A first terminal of the second transistor is electrically connected to a first wire. A second terminal of the first transistor is electrically connected to a first terminal of the third transistor. A gate of the third transistor is electrically connected to a second terminal of the second transistor, a gate of the fourth transistor, and a first terminal of the fourth transistor. A second terminal of the third transistor is electrically connected to a second wire. A second terminal of the fourth transistor is electrically connected to an output terminal. The semiconductor device includes a plurality of the first circuits.
G06G 7/60 - Calculateurs analogiques pour des procédés, des systèmes ou des dispositifs spécifiques, p. ex. simulateurs d'êtres vivants, p. ex. leur système nerveux
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
Provided is a highly reliable semiconductor device. The semiconductor device comprises a vertical transistor. The semiconductor device comprises first to third insulating layers. A semiconductor layer of the vertical transistor includes a metal oxide. The first insulating layer includes a portion positioned between a lower electrode and an upper electrode of the vertical transistor. The second insulating layer includes a region along a side surface of the first insulating layer. The third insulating layer is provided on the second insulating layer such that the third insulating layer includes a portion in contact with a side surface in said region on the opposite side from the first insulating layer. The first insulating layer and the upper electrode of the vertical transistor include an opening overlapping the lower electrode. The semiconductor layer of the vertical transistor, a gate insulating layer, and a gate electrode are provided in the opening. The first insulating layer is in contact with the semiconductor layer on a side surface in the opening, and has a function of supplying oxygen to the semiconductor layer. The second insulating layer has a function of capturing or fixing hydrogen.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
A display device with low power consumption is provided. Furthermore, a display device in which an image is displayed in a region that can be used in a folded state is provided. The conceived display device includes a display portion that can be opened and folded, a sensing portion that senses a folded state of the display portion, and an image processing portion that generates, when the display portion is in the folded state, an image in which a black image is displayed in part of the display portion.
A display apparatus with high display quality is provided. The display apparatus includes a pixel, a scan line driver circuit, and a power supply circuit. The pixel includes first and second transistors, and in the second transistor, a semiconductor layer is provided in a first opening portion formed in an interlayer insulating layer over a substrate. A first conductive layer functioning as a gate electrode of the first transistor includes a region extending in a first direction and is electrically connected to the scan line driver circuit. A second conductive layer functioning as a source electrode or a drain electrode of the second transistor is provided over the interlayer insulating layer and includes a second opening portion overlapping with the first opening portion. The second conductive layer includes a region extending in a second direction perpendicular to the first direction and is electrically connected to the power supply circuit. The first conductive layer and the second conductive layer include a region where they overlap with each other with an insulating layer, which functions as a gate insulating layer of the first and second transistors and is provided in a layer between the first conductive layer, and the second conductive layer and the semiconductor layer, therebetween.
A semiconductor device that occupies a small area is provided. The semiconductor device includes a first insulating layer, a second insulating layer, and a transistor. The transistor includes a semiconductor layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode are provided over the first insulating layer. The second insulating layer includes an opening reaching the first insulating layer and overlapping with part of the source electrode and part of the drain electrode. The semiconductor layer is provided in contact with a side surface of the second insulating layer in the opening, a top surface of the first insulating layer in the opening, a top surface of the source electrode, and a top surface of the drain electrode. The gate insulating layer is positioned over the semiconductor layer, the source electrode, and the drain electrode. The gate electrode overlaps with the opening and is positioned over the gate insulating layer.
The present invention provides a semiconductor device having a reduced circuit area. This semiconductor device has a voltage current conversion circuit, a current mirror circuit, and first to third switches. An output terminal of the voltage current conversion circuit is connected to a first terminal of the first switch and a first terminal of the third switch. An input terminal of the current mirror circuit is connected to a second terminal of the first switch, and an output terminal of the current mirror circuit is connected to a first terminal of the second switch. A second terminal of the third switch is connected to a second terminal of the second switch. The voltage current conversion circuit has a function of outputting a first current in an amount corresponding to digital data input to an input terminal, to the output terminal of the voltage current conversion circuit as a sink current. The current mirror circuit has a function, when a current generated by the voltage current conversion circuit is input to the input terminal, of outputting the current as a source current from the output terminal.
G06F 3/05 - Entrée numérique utilisant l'échantillonnage d'une quantité analogique à intervalles réguliers de temps
G06G 7/16 - Dispositions pour l'exécution d'opérations de calcul, p. ex. amplificateurs spécialement adaptés à cet effet pour la multiplication ou la division
G06G 7/60 - Calculateurs analogiques pour des procédés, des systèmes ou des dispositifs spécifiques, p. ex. simulateurs d'êtres vivants, p. ex. leur système nerveux
G06G 7/184 - Dispositions pour l'exécution d'opérations de calcul, p. ex. amplificateurs spécialement adaptés à cet effet pour l'intégration ou la différentiation utilisant des éléments capacitifs
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
44.
DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE
Provided is a high-definition display device. This display device has a first light-emitting device, a second light-emitting device, and an insulating layer. The first light-emitting device has a first pixel electrode, a first conductive layer on the first pixel electrode, a first EL layer on the first conductive layer, and a common electrode on the first EL layer. The second light-emitting device has a second pixel electrode, a second conductive layer on the second pixel electrode, a second EL layer on the second conductive layer, and a common electrode on the second EL layer. The insulating layer is located between the first pixel electrode and the second pixel electrode. An end of the first conductive layer overlaps the insulating layer. An end of the second conductive layer overlaps the insulating layer. An end of the first EL layer overlaps the first conductive layer. An end of the second EL layer overlaps the second conductive layer.
G09F 9/00 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
Provided is a highly reliable semiconductor device. This semiconductor device includes first to third conductive layers, a semiconductor layer, and first to fifth insulating layers. The third conductive layer, the second insulating layer, the third insulating layer, and the fifth insulating layer each have an opening that reaches the second conductive layer. The semiconductor layer has a region in contact with the second conductive layer, a region in contact with the third conductive layer, a region in contact with the lateral surface of the second insulating layer in the opening, a region in contact with the lateral surface of the third insulating layer in the opening, and a region in contact with the lateral surface of the fifth insulating layer in the opening. At least a part of the first conductive layer faces the semiconductor layer with the first insulating layer therebetween inside the opening. The lower surface of the third insulating layer is in contact with the second insulating layer. The other lateral surface of the third insulating layer is in contact with the fourth insulating layer. The upper surface of the third insulating layer is in contact with the fifth insulating layer.
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 51/00 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire
H10B 53/00 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire
H10K 50/115 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] comprenant des nanostructures inorganiques actives, p. ex. des points quantiques luminescents
H10K 59/12 - Affichages à OLED à matrice active [AMOLED]
The present invention provides a display device having a narrow bezel region. Provided is a display device having a display panel, a support substrate, and a counter substrate. The display panel has a first surface and a second surface. The first surface has a first region and a second region. In the first region, the support substrate is bonded to the display panel. In the second region, a substrate having the same material as the support substrate is not bonded to the display panel. In the second region, the counter substrate is bonded to the display panel. In the second region of the display device, a substrate equivalent to the support substrate is not provided. Thus, when the region is folded, a smaller radius of curvature can be achieved. With this configuration, the bezel region of the display device can be made narrower.
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
H05B 33/14 - Sources lumineuses avec des éléments radiants ayant essentiellement deux dimensions caractérisées par la composition chimique ou physique ou la disposition du matériau électroluminescent
The purpose of the present invention is to provide an electronic apparatus capable of easily obtaining accurate line-of-sight information. The electronic apparatus according to the present invention has a display device (20), a catadioptric optical system (30), and a light source (80) that emits infrared light, the display device (20) having light-emitting elements and light-receiving elements in pixels (21). The catadioptric optical system (30) forms two different optical paths between the outer surface (42) of the eye (40) and light-receiving elements, and between the light-emitting elements and the retina (41). Visible light (VL) is used between the light-emitting elements and the retina (41) and infrared light (IR) is used between the outer surface (42) of the eye (40) and the light-receiving elements. Additionally, half mirrors (33, 34) through which the light of one wavelength not involved in the optical path passes are used in the respective optical paths. Consequently, the focal distance of each optical path can be adjusted.
A61B 3/113 - Appareils pour l'examen optique des yeuxAppareils pour l'examen clinique des yeux du type à mesure objective, c.-à-d. instruments pour l'examen des yeux indépendamment des perceptions ou des réactions du patient pour déterminer ou enregistrer le mouvement de l'œil
H04N 13/344 - Affichage pour le visionnement à l’aide de lunettes spéciales ou de visiocasques avec des visiocasques portant des affichages gauche et droit
H04N 13/383 - Suivi des spectateurs pour le suivi du regard, c.-à-d. avec détection de l’axe de vision des yeux du spectateur
48.
DISPLAY APPARATUS AND METHOD FOR PRODUCING DISPLAY APPARATUS
Provided is a highly reliable display device. Provided is a display device with high contrast. Provided is a display device with high visibility. Provided is a high-brightness display device. Provided is a high-definition display device. Provided is a display device with high resolution. The display device includes a light-emitting device including a first electrode on a first insulating layer, an EL layer on the first electrode, and a second electrode on the EL layer. The first electrode covers a part of an upper surface and a side surface of the first insulating layer. An end of the first electrode is located between the upper surface and a lower surface of the first insulating layer.
G09F 9/00 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
H10K 50/816 - Multicouches, p. ex. multicouches transparentes
H10K 50/818 - Anodes réfléchissantes, p. ex. ITO combiné à des couches métalliques épaisses
H10K 50/828 - Cathodes transparentes, p. ex. comprenant des couches métalliques minces
H10K 59/122 - Structures ou couches définissant le pixel, p. ex. bords
H10K 59/124 - Couches isolantes formées entre les éléments TFT et les éléments OLED
H10K 71/20 - Modification de la forme de la couche active dans les dispositifs, p. ex. mise en forme
H10K 71/60 - Formation de régions ou de couches conductrices, p. ex. d’électrodes
H10K 102/10 - Électrodes transparentes, p. ex. utilisant du graphène
H10K 102/20 - Électrodes métalliques, p. ex. en utilisant un empilement de couches
A secondary battery with high capacity and a high level of safety is provided. The battery includes a positive electrode including a positive electrode active material and a conductive material. The positive electrode active material contains cobalt, oxygen, magnesium, and nickel. A median diameter of the positive electrode active material is greater than or equal to 1 μm and less than or equal to 12 μm. In EDX line analysis in a depth direction on a region of the positive electrode active material having a plane other than a (001) plane, a distribution of the magnesium partly overlaps with a distribution of the nickel. The conductive material adheres to part of the plane other than the (001) plane of the positive electrode active material.
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
H01M 4/62 - Emploi de substances spécifiées inactives comme ingrédients pour les masses actives, p. ex. liants, charges
A semiconductor device with a small occupation area is provided. The semiconductor device includes a first insulating layer, a second insulating layer, and a transistor. The transistor is provided over the first insulating layer and includes a semiconductor layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode. The second insulating layer includes an opening reaching the first insulating layer. The source electrode and the drain electrode are provided over the second insulating layer. The semiconductor layer is provided in contact with a side surface of the second insulating layer in the opening, a top surface of the first insulating layer in the opening, and side surfaces of the source electrode and the drain electrode. The gate insulating layer is positioned over the semiconductor layer, the source electrode, and the drain electrode. The gate electrode overlaps with the opening and is positioned over the gate insulating layer.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
51.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device that can be miniaturized or highly integrated is provided.
A semiconductor device that can be miniaturized or highly integrated is provided.
The semiconductor device includes a first conductor, a second conductor over the first conductor, a first insulator covering the second conductor, a first oxide over the first insulator, and a second oxide over the first oxide, an opening overlapping with at least part of the first conductor is provided in the first oxide and the first insulator, and the second oxide is electrically connected to the first conductor through the opening.
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
A highly visible display device is provided. The display device includes a transistor, a first conductive layer, a second conductive layer, and a third conductive layer. The channel width of the transistor is greater than or equal to 30 μm and less than or equal to 1000 μm. The transistor includes 2 to 50 semiconductor layers, each of which includes a first region, a second region, and a channel formation region. The channel formation region has a region overlaps with the first conductive layer. The first region overlaps with the second conductive layer and does not overlap with the first conductive layer. The second region overlaps with the third conductive layer and does not overlap with the first conductive layer. The third conductive layer has a function of transmitting visible light, and the second region and the third conductive layer in a stacked state have a function of transmitting visible light.
G02F 1/1368 - Cellules à adressage par une matrice active dans lesquelles l'élément de commutation est un dispositif à trois électrodes
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
53.
DOCUMENT SEARCH SYSTEM, DOCUMENT SEARCH METHOD, PROGRAM, AND NON-TRANSITORY COMPUTER READABLE STORAGE MEDIUM
A highly accurate document search, particularly a search for a document relating to intellectual property, is achieved with an easy input method. A document search system includes a processing portion. The processing portion has a function of extracting a keyword included in text data, a function of extracting a related term of the keyword from words included in a plurality of pieces of first reference text analysis data, a function of giving a weight to each of the keyword and the related term, a function of giving a score to each of a plurality of pieces of second reference text analysis data on the basis of the weight, a function of ranking the plurality of pieces of second reference text analysis data on the basis of the score to generate ranking data, and a function of outputting the ranking data.
A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.
G11C 11/4097 - Organisation de lignes de bits, p. ex. configuration de lignes de bits, lignes de bits repliées
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
An imaging device capable of detecting differences with low power consumption is provided. The imaging device includes a pixel including a photoelectric conversion element and a transistor; an analog processing circuit; and a digital processing circuit. The imaging device is operated in a first mode and a second mode. In the first mode, the analog processing circuit detects a difference between first imaging data taken by the pixel and second imaging data taken by the pixel and generates a trigger signal on the basis of the value of the difference. In the second mode, the digital processing circuit converts third imaging data taken by the pixel into digital data. Switching from the first mode to the second mode is performed on the basis of the trigger signal.
G08B 13/196 - Déclenchement influencé par la chaleur, la lumière, ou les radiations de longueur d'onde plus courteDéclenchement par introduction de sources de chaleur, de lumière, ou de radiations de longueur d'onde plus courte utilisant des systèmes détecteurs de radiations passifs utilisant des systèmes de balayage et de comparaison d'image utilisant des caméras de télévision
H04N 23/667 - Changement de mode de fonctionnement de la caméra, p. ex. entre les modes photo et vidéo, sport et normal ou haute et basse résolutions
H04N 25/77 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
H04N 25/771 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des moyens de stockage autres que la diffusion flottante
H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N
Provided is a novel drive circuit. A level shift circuit has first to third transistors, first to third power supply lines, and first to fourth wiring lines. A back gate of the first transistor is electrically connected with the first wiring line. One of a source and a drain of the first transistor is electrically connected with the first power supply line. The potential of the first power supply line is higher than the potential of the second power supply line, the potential of the third power supply line is lower than the potential of the first power supply line and the potential of the second power supply line, the signal of the fourth wiring line switches from a low potential level to a high potential level when the signal supplied to the first wiring line is at a high potential level, and the signal of the fourth wiring line switches from the high potential level to the low potential level when the signal supplied to the first wiring line is at a low potential level.
H03K 19/094 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs à semi-conducteurs utilisant des transistors à effet de champ
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
G09G 3/3266 - Détails des circuits de commande pour les électrodes de balayage
H03K 17/06 - Modifications pour assurer un état complètement conducteur
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 19/00 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion
H03K 19/017 - Modifications pour accélérer la commutation dans les circuits à transistor à effet de champ
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
Provided is a semiconductor device that exhibits little variation in electrical characteristics between transistors. The semiconductor device includes a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, and a semiconductor layer. The first insulating layer is located on the first conductive layer and the second conductive layer is located on the first insulating layer. End parts of the first insulating layer and the second conductive layer coincide or substantially coincide in plan view, and the first insulating layer and the second conductive layer assume the shape of a concave polygon in a plan view. Two sides configuring an internal angle that exceeds 180 degrees in the concave polygon overlap the first conductive layer in plan view. The semiconductor layer is located on the first conductive layer and the second conductive layer so as to have a region overlapping the two sides in plan view, and the semiconductor layer is in contact with the upper surface of the first conductive layer, a side surface of the first insulating layer, a side surface of the second conductive layer, and the upper surface of the second conductive layer.
Provided is a light-emitting device that has favorable characteristics. A tandem-type light-emitting device according to the present invention has a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a first light-emitting substance and a second light-emitting substance. The first light-emitting substance is a fluorescent light-emitting substance, the second light-emitting substance is a phosphorescent light-emitting substance or a TADF material, and the maximum peak wavelength of the emission spectrum of the first light-emitting substance is longer than the maximum peak wavelength of the emission spectrum of the second light-emitting substance. The second light-emitting layer includes a third light-emitting substance. The third light-emitting substance is a fluorescent light-emitting substance, and the difference between the maximum peak wavelength of the emission spectrum of the first light-emitting substance and the maximum peak wavelength of the emission spectrum of the third light-emitting substance is no more than 30 nm. The first light-emitting layer and the second light-emitting layer include a light-emitting layer that emits light in a different color gamut from a light-emitting layer of at least one of a plurality of other light-emitting devices that are to be adjacent to the light-emitting device.
H10K 50/12 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] comprenant des dopants
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
H10K 101/40 - Interrelation des paramètres entre plusieurs couches ou sous-couches actives constitutives, p. ex. valeurs HOMO dans des couches adjacentes
59.
LIGHT-EMITTING ELEMENT, DISPLAY DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE
Provided is a light-emitting element including a fluorescence-emitting material with high emission efficiency. The light-emitting element includes a pair of electrodes and an EL layer between the pair of electrodes. The EL layer includes a first organic compound, a second organic compound, and a guest material. The first organic compound has a function of emitting a thermally activated delayed fluorescence at room temperature. The guest material has a function of emitting fluorescence. A HOMO level of the first organic compound higher than or equal to a HOMO level of the second organic compound. A LUMO level of the first organic compound is lower than or equal to a LUMO level of the second organic compound.
H10K 101/40 - Interrelation des paramètres entre plusieurs couches ou sous-couches actives constitutives, p. ex. valeurs HOMO dans des couches adjacentes
A novel electronic device is provided. Alternatively an electronic device of a novel embodiment is provided. An electronic device includes a support and a display portion. The support has a first curved surface. The display portion is provided over the support. The display portion has a top surface and a side surface in contact with at least one side of the top surface. The side surface has a second curved surface. The top surface includes a first display region. The side surface includes a second display region. The first display region and the second display region are continuously provided.
An object of the present invention is to provide a semiconductor device with a new structure. Disclosed is a semiconductor device including a first transistor which includes a channel formation region on a substrate containing a semiconductor material, impurity regions formed with the channel formation region interposed therebetween, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, and a first source electrode and a first drain electrode which are electrically connected to the impurity region; and a second transistor which includes a second gate electrode over the substrate containing a semiconductor material, a second gate insulating layer over the second gate electrode, an oxide semiconductor layer over the second gate insulating layer, and a second source electrode and a second drain electrode which are electrically connected to the oxide semiconductor layer.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10D 87/00 - Dispositifs intégrés comprenant à la fois des composants en vrac et des composants SOI ou SOS sur le même substrat
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first conductor, a first insulator, a second conductor over the first insulator, an oxide semiconductor, a second insulator, a third conductor, a third insulator, and a fourth insulator. In the semiconductor device, an opening portion reaching the first conductor is provided in the first insulator and the second conductor, part of the oxide semiconductor is placed in the opening portion and is in contact with a top surface of the first conductor, another part of the oxide semiconductor is placed over the opening portion and is in contact with at least part of a top surface of the second conductor, the second insulator is placed over the oxide semiconductor so as to be at least partly positioned in the opening, the third conductor is placed over the second insulator so as to be at least partly positioned in the opening, the third insulator is placed between a sidewall of the opening portion and the oxide semiconductor so as to be positioned in the opening, and the fourth insulator is placed between the sidewall of the opening portion and the third insulator, the third insulator comprises a metal oxide, and the fourth insulator comprises silicon nitride.
An electronic device with a novel structure is provided. In the electronic device including a semiconductor device, the semiconductor device includes a logic circuit portion provided in a plurality of element layers, a display control portion, and a display portion. The display portion includes a plurality of display regions. The display control portion includes a plurality of driver circuit portions. The plurality of display regions each include a pixel circuit that controls light emission of a light-emitting device. The plurality of driver circuit portions each include a driver circuit that controls the pixel circuit. The plurality of display regions are each provided at a position overlapping with a region where any one of the plurality of driver circuit portions is provided. The logic circuit portion includes an arithmetic device. The arithmetic device has a function of controlling, in accordance with whether or not image data is updated in each of the plurality of display regions, an operation state or a stop state of the driver circuit corresponding to the pixel circuit included in the display region.
G09G 3/3233 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active avec un circuit de pixel pour commander le courant à travers l'élément électroluminescent
64.
SEMICONDUCTOR DEVICE, METHOD FOR DRIVING SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
A semiconductor device capable of performing authentication in a short time can be provided. The semiconductor device includes a light-emitting unit and an imaging unit. The imaging unit includes a row driver circuit, and the row driver circuit includes first to m latch circuits (m is an integer greater than or equal to 2) and first to m register circuits. A first start pulse signal is input to a first latch circuit and second start pulse signals are input to first to m latch circuits. Scan signals output from the first to (m−1)-th register circuits are input to the second to m-th latch circuits, respectively. The first latch circuit has a function of outputting one of the first start pulse signal and the second start pulse signal to the first register circuit on the basis of data held, and the second to m-th latch circuits have a function of outputting one of the scan signal and the second start pulse signal to the second to m-th register circuits on the basis of data held.
H04N 25/44 - Extraction de données de pixels provenant d'un capteur d'images en agissant sur les circuits de balayage, p. ex. en modifiant le nombre de pixels ayant été échantillonnés ou à échantillonner en lisant partiellement une matrice de capteurs SSIS
A novel light-emitting device that is highly convenient, useful, or reliable is provided. A novel functional panel that is highly convenient, useful, or reliable is provided. The light-emitting device includes an insulating film, a group of structure bodies, a layer containing a light-emitting material, a first electrode, and a second electrode. The group of structure bodies includes a structure body and a different structure body, a first distance is provided between the different structure body and the structure body, the insulating film includes a first surface, the structure body includes a sidewall, the sidewall forms a first angle with the first surface, and the first angle is greater than 0°and less than or equal to 90°. The layer containing a light-emitting material includes a first region and a second region, the first region is interposed between the second electrode and the first electrode, light is emitted from the first region, the second region is interposed between the second electrode and the sidewall, and the sidewall reflects light. The first electrode includes a third region, and the third region is interposed between the first region and the first surface.
H10K 50/856 - Dispositifs pour extraire la lumière des dispositifs comprenant des moyens réfléchissants
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
H10K 59/60 - OLED intégrées avec des éléments inorganiques sensibles à la lumière, p. ex. avec des cellules solaires inorganiques ou des photodiodes inorganiques
A novel data processing system that is highly convenient, useful, or reliable is provided. The data processing system is composed of three components. A component 1 receives identification data, transmits the identification data to a component 3, and provides an annotated document. A component 2 extracts a special technical feature and generates the annotated document with the use of a large language model. The component 3 receives and shares the identification data and the special technical feature, and creates and shares a table. The component 3 includes two subcomponents. A subcomponent 1 manages a patent application document and an examination record with the use of a database and a management system. A subcomponent 2 creates a prompt to extract the special technical feature and generate the annotated document.
A novel organic compound that enables a highly reliable light-emitting device is provided. An organic compound represented by Structural Formula (G1) below is provided. In the organic compound represented by General Formula (G1) below, at least one of R1 to R14 represents a group including aliphatic cyclic amine, and the others each independently represent any one of hydrogen, deuterium, an alkyl group having 1 to 10 carbon atoms, a cycloalkyl group having 3 to 10 carbon atoms, a substituted or unsubstituted monovalent aromatic hydrocarbon group having 6 to 30 carbon atoms, a substituted or unsubstituted monovalent heteroaromatic group having 1 to 30 carbon atoms, and a group including aliphatic cyclic amine.
A novel organic compound that enables a highly reliable light-emitting device is provided. An organic compound represented by Structural Formula (G1) below is provided. In the organic compound represented by General Formula (G1) below, at least one of R1 to R14 represents a group including aliphatic cyclic amine, and the others each independently represent any one of hydrogen, deuterium, an alkyl group having 1 to 10 carbon atoms, a cycloalkyl group having 3 to 10 carbon atoms, a substituted or unsubstituted monovalent aromatic hydrocarbon group having 6 to 30 carbon atoms, a substituted or unsubstituted monovalent heteroaromatic group having 1 to 30 carbon atoms, and a group including aliphatic cyclic amine.
Provided are a novel organic compound and light-emitting device. Specifically provided is an organic compound represented by general formula (G1). In general formula (G1): X1, X2, and X3each independently represent one of carbon, nitrogen, oxygen, silicon, and sulfur; at least one of X1, X2, and X3is carbon or silicon; if representing nitrogen or silicon, X1, X2, and X3may have a substituent group; said substituent group is one of hydrogen (including deuterium), an alkyl group, an alkoxy group, a silyl group, an aryl group, a heteroaryl group, a cyano group, and an aliphatic amine; if X1, X2, or X3represents carbon or silicon, a spirocycle having said X1, X2, or X3as a spiro atom may be formed; and R1to R9 represent one of hydrogen (including deuterium), an alkyl group, an alkoxy group, a silyl group, an aryl group, a heteroaryl group, a cyano group, and an aliphatic amine.
H10K 50/13 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] spécialement adaptées à l'émission de lumière multicolore, p. ex. à l'émission de lumière blanche comprenant des couches EL empilées dans une unité EL
The present invention provides: a highly safe separator; and a secondary battery comprising said separator. The separator is provided with particles of an endothermic agent on one or both surfaces thereof. The particles of the endothermic agent are gypsum dihydrate. Accordingly, even when the secondary battery generates heat due to some reason, the endothermic agent can suppress the rise in temperature. A binder having a water absorbing effect is used. Accordingly, even when water is generated in the secondary battery, generation of hydrofluoric acid can be suppressed. Thus, it is possible to provide the highly safe secondary battery.
H01M 50/451 - Séparateurs, membranes ou diaphragmes caractérisés par le matériau ayant une structure en couches comprenant des couches de matériau organique uniquement et des couches comprenant un matériau inorganique
H01M 50/414 - Résines synthétiques, p. ex. thermoplastiques ou thermodurcissables
Provided is a lithium-ion battery having a positive electrode active material of an olivine-type crystal structure and exhibiting excellent battery characteristics. The lithium-ion battery has a positive electrode, wherein: the positive electrode has a positive electrode active material; the positive electrode active material has an olivine-type crystal structure; and in the positive electrode active material, the atomic number ratio of manganese to a total of atomic number ratios of manganese, iron, and an additive element is 0.7 or more, the atomic number ratio of the additive element to a total of atomic number ratios of manganese and the additive element is 0.02 to 0.1 (exclusive of 0,1), and the additive element is a divalent cation.
H01M 4/58 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs de composés inorganiques autres que les oxydes ou les hydroxydes, p. ex. sulfures, séléniures, tellurures, halogénures ou LiCoFyEmploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs de structures polyanioniques, p. ex. phosphates, silicates ou borates
C01B 25/45 - Phosphates contenant plusieurs métaux ou un métal et l'ammonium
A novel electronic device is provided. The electronic device includes a display apparatus, an arithmetic portion, and a gaze detection portion, and the display apparatus includes a functional circuit and a display portion divided into a plurality of sub-display portions. The gaze detection portion has a function of detecting a user's gaze. The arithmetic portion has a function of dividing the plurality of sub-display portions between a first section and a second section using a detection result of the gaze detection portion. The first section includes a region overlapping with a user's gaze point. The functional circuit has a function of making a driving frequency of the second section lower than a driving frequency of the first section.
G09G 3/3233 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active avec un circuit de pixel pour commander le courant à travers l'élément électroluminescent
G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur
G09G 3/00 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
Provided is an information processing system that assists in correcting a document by using a language model. A processing unit of the information processing system is configured to execute: processing for extracting at least one component from a first document; processing for creating a first prompt having a first instruction sentence including a command for extracting, from a second document, at least one description corresponding to the component; processing for causing the language model to generate a first response sentence from the first prompt; processing for determining whether or not the description conforms to a regulation; processing for creating a second prompt having a second instruction sentence including a command for presenting a correction plan for conforming the description to the regulation if the description does not conform to the regulation; processing for causing the language model to generate a second response sentence from the second prompt; and processing for generating result data on the basis of the component, the description, and the correction plan.
Provided is a semiconductor device comprising a transistor having a large on-current. The semiconductor device comprises a vertical transistor. A lower electrode of the vertical transistor has a laminated structure of: a first conductive layer having high electrical conductivity; a second conductive layer containing zirconium, titanium, or tin; and a third conductive layer containing an oxide that includes indium and a metallic element. An insulating layer is provided on the third conductive layer. The insulating layer and the third conductive layer are provided with an opening reaching the second conductive layer. A semiconductor layer contains indium oxide, and has a region that is in contact with the upper surface of the second conductive layer and a region that is in contact with the side surface of the opening in the third conductive layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
H10B 53/10 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la configuration vue du dessus
Provided is a secondary battery or an electrolyte solution that exhibits excellent battery characteristics below the ice point. According to the present invention, a secondary battery includes an electrolyte solution that includes at least a lithium salt and a mixed solvent that includes a cyclic carbonate and a chain carbonate, the molar ratio (CH/CY) of the chain carbonate (CH) to the cyclic carbonate (CY) being greater than 1.5, and the concentration of the lithium salt per liter of the mixed solvent being 0.25–1 mol.
H01M 10/0569 - Matériaux liquides caracterisés par les solvants
H01M 4/36 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
Provided is a storage device that has a new configuration. The storage device that has a memory cell array and a switch circuit is described. The memory cell array has a first memory cell and a second memory cell, and each of the memory cells is provided with a terminal. The switch circuit has a plurality of terminals and has a function of bringing the terminals into a conductive state or a non-conductive state. The storage device has a first state and a second state and achieves different operation modes in the respective states. In the first state, the first memory cell and the second memory cell operate independently by the switch circuit. Meanwhile, in the second state, the terminals of the memory cell array are connected by the switch circuit, and the first memory cell and the second memory cell operate as one memory cell.
G11C 11/405 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe avec trois portes à transfert de charges, p. ex. transistors MOS, par cellule
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
76.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a highly-reliable semiconductor device. The semiconductor device comprises: a semiconductor layer; first to third conductive layers; and first to third insulating layers. The first insulating layer has a portion that is located on the first conductive layer and has a first opening that reaches the first conductive layer. The second insulating layer has a portion in contact with a lateral surface of the first opening in the first insulating layer. The second conductive layer is located on the first insulating layer and the second insulating layer. The second conductive layer and the second insulating layer have a second opening that reaches the first conductive layer. The semiconductor layer has, in the second opening, a portion in contact with a lateral surface of the second conductive layer, a portion in contact with a lateral surface of the second insulating layer, and a portion in contact with the upper surface of the first conductive layer. The third insulating layer covers the semiconductor layer. The third conductive layer is located on the third insulating layer. The upper surface of the second insulating layer has a portion in contact with the lower surface of the second conductive layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
77.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
Provided is a semiconductor device in which a high-quality semiconductor film is used. The semiconductor device comprises a sapphire substrate, a first insulating layer, and a transistor. The first insulating layer is provided on the substrate and has an opening that reaches the substrate. The transistor has a semiconductor layer. The semiconductor layer has a portion in contact with the upper surface of the first insulating layer, and a portion in contact with the upper surface of the substrate in the opening. The substrate has a single crystal structure. The first insulating layer has an amorphous structure. The semiconductor layer contains a metal oxide and has a single crystal structure.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
78.
LIGHT-EMITTING ELEMENT, DISPLAY DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE
A light-emitting element having high luminous efficiency is provided. The light-emitting element includes a first organic compound, a second organic compound, and a third organic compound. The first organic compound and the second organic compound, in combination, are capable of forming an exciplex. The first organic compound is a phosphorescent compound and the third organic compound is a fluorescent compound. Light emitted from the light-emitting element includes light emitted from the third organic compound to which excitation energy is supplied from the exciplex formed by the first organic compound and the second organic compound.
C09K 11/06 - Substances luminescentes, p. ex. électroluminescentes, chimiluminescentes contenant des substances organiques luminescentes
C09K 11/02 - Emploi de substances particulières comme liants, revêtements de particules ou milieux de suspension
H10K 50/11 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL]
H10K 50/12 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] comprenant des dopants
H10K 59/12 - Affichages à OLED à matrice active [AMOLED]
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
H10K 59/38 - Dispositifs spécialement adaptés à l'émission de lumière multicolore comprenant des filtres de couleur ou des supports changeant de couleur [CCM]
H10K 101/30 - Valeurs d'énergie de la plus haute orbitale moléculaire occupée [HOMO], de la plus basse orbitale moléculaire inoccupée [LUMO] ou de Fermi
H10K 101/40 - Interrelation des paramètres entre plusieurs couches ou sous-couches actives constitutives, p. ex. valeurs HOMO dans des couches adjacentes
A memory device that can be miniaturized or highly integrated can be provided. The memory device includes a memory cell, a first insulator, and a second insulator. The memory cell includes a capacitor and a transistor over the capacitor. The capacitor includes a second conductor, a third insulator over the second conductor, and a third conductor over the third insulator. Part of the second conductor, part of the third insulator, and part of the third conductor are placed in an opening portion formed in the first insulator. The transistor includes the third conductor, a fourth conductor over the second insulator, an oxide semiconductor, a fourth insulator over the oxide semiconductor, and a fifth conductor over the fourth insulator. Part of the oxide semiconductor is placed in an opening portion formed in the second insulator and the fourth conductor. The oxide semiconductor includes a region in contact with a top surface of the third conductor, a region in contact with a side surface of the fourth conductor, and a region in contact with part of a top surface of the fourth conductor. The oxide semiconductor has a stacked-layer structure.
An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
G02F 1/1362 - Cellules à adressage par une matrice active
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10H 29/14 - Dispositifs intégrés comprenant au moins un composant émetteur de lumière à semi-conducteurs couvert par le groupe comprenant plusieurs composants émetteurs de lumière à semi-conducteurs
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
H10K 59/124 - Couches isolantes formées entre les éléments TFT et les éléments OLED
H10K 59/131 - Interconnexions, p. ex. lignes de câblage ou bornes
To provide a novel organic compound and a light-emitting device including the organic compound. In General Formula (G1-1), Z1 represents carbon or nitrogen; when Z1 represents carbon, the carbon has hydrogen (including deuterium); each of R1 to R9 independently represents any one of hydrogen (including deuterium), an alkyl group having 1 to 10 carbon atoms, an alkoxy group having 1 to 10 carbon atoms, a silyl group having 1 to 20 carbon atoms, a substituted or unsubstituted aryl group having 6 to 30 carbon atoms, a substituted or unsubstituted heteroaryl group having 1 to 30 carbon atoms, a cyano group, and an aliphatic amine group represented by General Formula (g1); and at least one of R1 to R3 and at least one of R4 to R6 each represent a group represented by General Formula (g2).
To provide a novel organic compound and a light-emitting device including the organic compound. In General Formula (G1-1), Z1 represents carbon or nitrogen; when Z1 represents carbon, the carbon has hydrogen (including deuterium); each of R1 to R9 independently represents any one of hydrogen (including deuterium), an alkyl group having 1 to 10 carbon atoms, an alkoxy group having 1 to 10 carbon atoms, a silyl group having 1 to 20 carbon atoms, a substituted or unsubstituted aryl group having 6 to 30 carbon atoms, a substituted or unsubstituted heteroaryl group having 1 to 30 carbon atoms, a cyano group, and an aliphatic amine group represented by General Formula (g1); and at least one of R1 to R3 and at least one of R4 to R6 each represent a group represented by General Formula (g2).
C07D 401/14 - Composés hétérocycliques contenant plusieurs hétérocycles comportant des atomes d'azote comme uniques hétéro-atomes du cycle, au moins un cycle étant un cycle à six chaînons avec un unique atome d'azote contenant au moins trois hétérocycles
C07D 405/14 - Composés hétérocycliques contenant à la fois un ou plusieurs hétérocycles comportant des atomes d'oxygène comme uniques hétéro-atomes du cycle et un ou plusieurs hétérocycles comportant des atomes d'azote comme uniques hétéro-atomes du cycle contenant au moins trois hétérocycles
C07D 519/00 - Composés hétérocycliques contenant plusieurs systèmes de plusieurs hétérocycles déterminants condensés entre eux ou condensés avec un système carbocyclique commun non prévus dans les groupes ou
C07F 7/08 - Composés comportant une ou plusieurs liaisons C—Si
H10K 50/11 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL]
H10K 85/40 - Composés organosiliciés, p. ex. pentacène TIPS
H10K 85/60 - Composés organiques à faible poids moléculaire
Provided is a semiconductor device having a novel configuration. This semiconductor device includes: a state control unit; a register unit having a first storage circuit; and a cache unit having a second storage circuit. The first storage circuit includes a flip-flop circuit and a first data holding circuit. The second storage circuit includes an inverter loop circuit and a second data holding circuit. The first storage circuit has a function of holding, in the first data holding circuit, first data output by the flip-flop circuit, in response to a first signal supplied from the state control unit, and a function of outputting the first data held in the first data holding circuit to the flip-flop circuit in response to a second signal supplied from the state control unit. The second storage circuit has a function of holding, in the second data holding circuit, second data output by the inverter loop circuit, in response to the first signal, and a function of outputting the second data held in the second data holding circuit to the inverter loop circuit in response to the second signal.
G11C 14/00 - Mémoires numériques caractérisées par des dispositions de cellules ayant des propriétés de mémoire volatile et non volatile pour sauvegarder l'information en cas de défaillance de l'alimentation
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 41/70 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes la grille flottante étant une électrode partagée par plusieurs éléments
H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
Provided are a secondary battery excellent in charge/discharge characteristics and impact resistance and a method for manufacturing the same. The secondary battery includes a positive electrode, a negative electrode, and an exterior body that houses the positive electrode and the negative electrode, wherein: on one side of the exterior body, the positive electrode and the exterior body are connected at at least two locations and the negative electrode and the exterior body are connected at at least two locations; the positive electrode includes a positive electrode active material layer; the positive electrode active material layer contains lithium cobalt oxide; the lithium cobalt oxide has, in a surface layer part, magnesium, titanium, aluminum, and nickel; the surface layer part is a region within 50 nm from the surface of the lithium cobalt oxide; and when STEM-EDX line analysis is performed in the depth direction of the surface layer part, the aluminum has a peak closer to the inside of the lithium cobalt oxide than the magnesium.
H01M 10/0585 - Structure ou fabrication d'accumulateurs ayant uniquement des éléments de structure plats, c.-à-d. des électrodes positives plates, des électrodes négatives plates et des séparateurs plats
C01G 53/82 - Composés contenant du nickel, avec ou sans oxygène ou hydrogène, et contenant plusieurs autres éléments
H01M 4/36 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
H01M 50/178 - Dispositions pour introduire des connecteurs électriques dans ou à travers des boîtiers adaptées à la forme des cellules pour des cellules en forme de poches ou de sacs souples
84.
SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SEMICONDUCTOR DEVICE
A semiconductor device that is highly integrated and reliable is provided. A back gate electrode of a second transistor is electrically connected to a control signal line supplying a control signal controlling the threshold voltage of the second transistor. One of a source and a drain of the second transistor is electrically connected to a read word line supplying a read word signal. The other of the source and the drain of the second transistor is electrically connected to a read bit line reading a potential corresponding to data. In a memory cell selected in a data reading period, a low level is supplied as the read word signal and a high level is supplied as the control signal. In the memory cell not selected in the data reading period, a high level is supplied as the read word signal and a low level is supplied as the control signal.
G11C 11/405 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe avec trois portes à transfert de charges, p. ex. transistors MOS, par cellule
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
A novel power storage system is provided. The power storage system includes a secondary battery, a current measuring circuit, a voltage measuring circuit, and a control circuit. The secondary battery includes a negative electrode. The negative electrode contains graphite and silicon. The current measuring circuit and the voltage measuring circuit are electrically connected to the control circuit. The control circuit has a function of starting charge of the secondary battery. The control circuit has a function of performing a first arithmetic operation of calculating a voltage differential value of the amount of electricity of charge current of the secondary battery with the use of a current value detected by the current measuring circuit and a voltage value detected by the voltage measuring circuit, and has a function of performing a second arithmetic operation of detecting an extremum of the voltage differential value. The control circuit has a function of stopping the charge after a predetermined time elapses since the extremum is detected through the second arithmetic operation.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
H01M 4/131 - Électrodes à base d'oxydes ou d'hydroxydes mixtes, ou de mélanges d'oxydes ou d'hydroxydes, p. ex. LiCoOx
H01M 4/133 - Électrodes à base de matériau carboné, p. ex. composés d'intercalation du graphite ou CFx
H01M 4/134 - Électrodes à base de métaux, de Si ou d'alliages
H01M 4/136 - Électrodes à base de composés inorganiques autres que les oxydes ou les hydroxydes, p. ex. sulfures, séléniures, tellurures, halogénures ou LiCoFy
H01M 4/38 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'éléments simples ou d'alliages
H01M 4/505 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de manganèse d'oxydes ou d'hydroxydes mixtes contenant du manganèse pour insérer ou intercaler des métaux légers, p. ex. LiMn2O4 ou LiMn2OxFy
H01M 4/525 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs d'oxydes ou d'hydroxydes inorganiques de nickel, de cobalt ou de fer d'oxydes ou d'hydroxydes mixtes contenant du fer, du cobalt ou du nickel pour insérer ou intercaler des métaux légers, p. ex. LiNiO2, LiCoO2 ou LiCoOxFy
H01M 4/58 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs de composés inorganiques autres que les oxydes ou les hydroxydes, p. ex. sulfures, séléniures, tellurures, halogénures ou LiCoFyEmploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs de structures polyanioniques, p. ex. phosphates, silicates ou borates
H01M 4/587 - Matériau carboné, p. ex. composés au graphite d'intercalation ou CFx pour insérer ou intercaler des métaux légers
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor, a second conductor, and a third insulator over the oxide semiconductor, a second insulator over the first insulator, the first conductor, and the second conductor, and a third conductor over the third insulator. The oxide semiconductor includes a first region overlapping with the first conductor, a second region overlapping with the second conductor, and a third region positioned between the first region and the second region. The second insulator includes an opening portion in a region overlapping with the third region, and the third insulator and the third conductor are provided in the opening portion. The first region and the second region are in contact with the first insulator and the second insulator, and the third region is in contact with the first insulator and the third insulator. The first insulator and the second insulator contain silicon and nitrogen.
A novel data processing system that is highly convenient, useful, or reliable is provided. The data processing system includes three components. A first component receives a job script, transmits the job script to a third component, and provides a determination result. A second component receives a first prompt, performs processing using a large language model, and extracts first setting information. The third component receives the job script and the first setting information, shares the job script and the first setting information in the third component, and transmits a determination result to the first component. The third component includes a first subcomponent and a second subcomponent. The first subcomponent creates the first prompt and transmits the first prompt to the second component. The second subcomponent performs processing using a classifier and determines whether the first setting information includes an inappropriate setting.
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
G06F 18/2415 - Techniques de classification relatives au modèle de classification, p. ex. approches paramétriques ou non paramétriques basées sur des modèles paramétriques ou probabilistes, p. ex. basées sur un rapport de vraisemblance ou un taux de faux positifs par rapport à un taux de faux négatifs
An object is to provide a material suitably used for a semiconductor included in a transistor, a diode, or the like. Another object is to provide a semiconductor device including a transistor in which the condition of an electron state at an interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is favorable. Further, another object is to manufacture a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. A semiconductor device is formed using an oxide material which includes crystal with c-axis alignment, which has a triangular or hexagonal atomic arrangement when seen from the direction of a surface or an interface and rotates around the c-axis.
H10D 62/80 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux
89.
MATERIAL FOR HOLE-TRANSPORT LAYER, MATERIAL FOR HOLE-INJECTION LAYER, ORGANIC COMPOUND, LIGHT-EMITTING DEVICE, LIGHT-EMITTING APPARATUS, ELECTRONIC DEVICE, AND LIGHTING DEVICE
A material for a hole-transport layer includes a monoamine compound. The first aromatic group, the second aromatic group, and the third aromatic group are bonded to the nitrogen atom of the monoamine compound. The first and second aromatic groups each independently include 1 to 3 benzene rings. One or both of the first and second aromatic groups have one or more hydrocarbon groups each having 1 to 12 carbon atoms each forming a bond only by the sp3 hybrid orbitals. The total number of the carbon atoms in the hydrocarbon group in the first or second aromatic group is 6 or more. The total number of the carbon atoms in all of the hydrocarbon groups in the first and second aromatic groups is 8 or more. The third aromatic group is a substituted or unsubstituted monocyclic condensed ring or a substituted or unsubstituted bicyclic or tricyclic condensed ring.
C09K 11/06 - Substances luminescentes, p. ex. électroluminescentes, chimiluminescentes contenant des substances organiques luminescentes
C07C 211/61 - Composés contenant des groupes amino liés à un squelette carboné ayant des groupes amino liés à des atomes de carbone de cycles aromatiques à six chaînons du squelette carboné ayant des groupes amino liés à des atomes de carbone de cycles aromatiques à six chaînons faisant partie de systèmes cycliques condensés du squelette carboné avec au moins un des systèmes cycliques condensés formé par trois cycles ou plus
A novel classification device is provided. The classification device includes a memory unit, a processing unit, and a classifier. A plurality of pieces of image data and a discriminative model are stored in the memory unit. Each of the plurality of pieces of image data is image data determined to contain a defect. The discriminative model includes an input layer, an intermediate layer, and an output layer. First to n-th (n is an integer greater than or equal to 2) image data of the plurality of pieces of image data are supplied to the processing unit. The processing unit has a function of outputting feature values of the first to the n-th image data (a first to an n-th feature value) on the basis of the discriminative model. A feature value output from the processing unit is a numerical value of a neuron included in the intermediate layer. The first to the n-th feature value output from the processing unit are supplied to the classifier. The classifier has a function of performing clustering of the first to the n-th image data on the basis of the first to the n-th feature value.
G06V 10/774 - Génération d'ensembles de motifs de formationTraitement des caractéristiques d’images ou de vidéos dans les espaces de caractéristiquesDispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p. ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]Séparation aveugle de source méthodes de Bootstrap, p. ex. "bagging” ou “boosting”
G06V 10/762 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant le regroupement, p. ex. de visages similaires sur les réseaux sociaux
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
G06V 10/77 - Traitement des caractéristiques d’images ou de vidéos dans les espaces de caractéristiquesDispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p. ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]Séparation aveugle de source
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
91.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10D 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
An image processing system that can reduce display unevenness in an image displayed on a display device is provided. The image processing system includes a display device, an image capturing device, and a learning device. The learning device stores a table representing information on the correspondence between first image data and second image data that is generated by display of an image corresponding to the first image data on the display device and image capturing of the image by the image capturing device. The learning device generates teacher data in accordance with the table and generates a machine learning model with the use of the teacher data generated. Image processing using the machine learning model is performed on image data input to the display device, so that display unevenness in the image displayed on the display device can be reduced.
Provided is a novel display device. The present invention includes: a pixel having first to third transistors and a light-emitting device; a gate line drive-circuit that is electrically connected to a gate line; a data line drive-circuit that is electrically connected to a data line; and a selection control drive-circuit that is electrically connected to a selection control line. The gate of the first transistor is electrically connected to the gate line. One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the third transistor. The other of the source and the drain of the first transistor is electrically connected to the gate of the second transistor. One of the source and the drain of the second transistor is electrically connected to the light-emitting device. The other of the source and the drain of the third transistor is electrically connected to the data line. The gate of the third transistor is electrically connected to the selection control line.
G09G 3/3225 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active
G09F 9/30 - Dispositifs d'affichage d'information variable, dans lesquels l'information est formée sur un support, par sélection ou combinaison d'éléments individuels dans lesquels le ou les caractères désirés sont formés par une combinaison d'éléments individuels
G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice
94.
SEMICONDUCTOR DEVICE, DISPLAY APPARATUS, AND ELECTRONIC DEVICE
A semiconductor device includes first to tenth transistors and first to fourth capacitors. Gates of the first and the fourth transistors are electrically connected to each other. First terminals of the first, second, fifth, and eighth transistors are electrically connected to a first terminal of the fourth capacitor. A second terminal of the fifth transistor is electrically connected to a gate of the sixth transistor and a first terminal of the second capacitor. A second terminal of the eighth transistor is electrically connected to a gate of the ninth transistor and a first terminal of the third capacitor. Gates of the second, seventh, and tenth transistors are electrically connected to first terminals of the third and fourth transistors and a first terminal of the first capacitor. First terminals of the sixth and seventh transistors are electrically connected to a second terminal of the second capacitor.
G09G 3/3225 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active
A semiconductor device that has both high performance and high productivity is provided. The semiconductor device includes a first transistor and a second transistor over a substrate. The first transistor includes a first conductive layer, a first insulating layer, and a second conductive layer in this order, and includes a first semiconductor layer, a second insulating layer, and a third conductive layer in this order over the first conductive layer in an opening provided in the first insulating layer and the second conductive layer. The second transistor includes the first insulating layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, the second insulating layer, and a sixth conductive layer in this order, and the second semiconductor layer includes a region in contact with the second insulating layer and a region overlapping with the second insulating layer with the fourth conductive layer or the fifth conductive layer therebetween. The second conductive layer, the fourth conductive layer, and the fifth conductive layer can be formed from the same film.
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
A display device including a touch sensor and a driver for driving the touch sensor is provided. The display device has a touch panel function, an electrode of the touch sensor is electrically connected to a first driver circuit formed monolithically on a substrate where a pixel circuit is formed. A transistor including a metal oxide in a semiconductor layer can be used in the first driver circuit. The transistor included in the first driver circuit is easily downsized and can operate at high speed. Thus, the area occupied by the circuit can be reduced, which contributes to a narrower bezel.
G06F 3/041 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction
G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
H10K 59/123 - Connexion des électrodes de pixel aux transistors à couches minces [TFT]
H10K 59/124 - Couches isolantes formées entre les éléments TFT et les éléments OLED
H10K 59/131 - Interconnexions, p. ex. lignes de câblage ou bornes
H10K 59/65 - OLED intégrées avec des capteurs d'images inorganiques
97.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including agate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and/or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
A novel organic compound is provided. A novel organic compound having a carrier-transport property is provided. A novel organic compound having a hole-transport property is provided. An organic compound having a low refractive index is provided. An organic compound having a low refractive index and a carrier-transport property is provided. An organic compound having a low refractive index and a hole-transport property is provided. An organic compound represented by the following general formula (G1) is provided.
A novel organic compound is provided. A novel organic compound having a carrier-transport property is provided. A novel organic compound having a hole-transport property is provided. An organic compound having a low refractive index is provided. An organic compound having a low refractive index and a carrier-transport property is provided. An organic compound having a low refractive index and a hole-transport property is provided. An organic compound represented by the following general formula (G1) is provided.
C09K 11/06 - Substances luminescentes, p. ex. électroluminescentes, chimiluminescentes contenant des substances organiques luminescentes
C07C 211/54 - Composés contenant des groupes amino liés à un squelette carboné ayant des groupes amino liés à des atomes de carbone de cycles aromatiques à six chaînons du squelette carboné ayant des groupes amino liés à deux ou trois cycles aromatiques à six chaînons
H10K 50/17 - Couches d'injection des porteurs de charge
H10K 59/12 - Affichages à OLED à matrice active [AMOLED]
A memory device comprising a memory cell over a first transistor including silicon in a semiconductor layer is provided. The memory cell includes a capacitor and a second transistor over the capacitor. The capacitor includes a first conductor, a first insulator, and a second conductor that are stacked in this order. The second conductor serves as one of a source and a drain of the second transistor. A third conductor functioning as the other of the source and the drain of the second transistor is located over the second insulator. An opening reaching the second conductor is provided in the second insulator and the third conductor. An oxide semiconductor, a third insulator, and a fourth conductor are stacked in this order to overlap with the opening. The fourth conductor is electrically connected to a source or a drain of the first transistor.
