Provided in the embodiments of the present disclosure are a calibration circuit, a signal processing device, and a signal processing system. The calibration circuit comprises a signal generation circuit, the signal generation circuit comprising: a clock module, which generates a first clock signal, wherein the first clock signal is at least used for generating an operating clock signal for a control module and an input clock signal for a frequency-division module; the control module, which sends a first frequency-division reset signal to the frequency-division module and triggers the startup of a timer in the control module, wherein the timer performs timing on the basis of the operating clock signal, and the first frequency-division reset signal controls an interval between an initial moment at which the frequency-division module outputs a frequency-division signal and a startup moment of the timer to be a first predetermined duration; and a low-pass filter, which filters the frequency-division signal to obtain a first calibration signal, wherein an interval between an initial moment of the first calibration signal and the startup moment of the timer is a second predetermined duration, and the first calibration signal is used for analog-to-digital conversion to obtain a first digital signal, so as to determine a first measurement duration between an initial moment of the first digital signal and the startup moment of the timer.
Provided in the embodiments of the present disclosure are a signal generation circuit, a signal generation method, an electronic device and a storage medium. The signal generation circuit comprises a clock module, a control module and a frequency division module; the clock module is configured to generate a first clock signal on the basis of an input reference clock signal, wherein the first clock signal is at least used for generating a working clock signal of the control module; the control module is configured to send to the frequency division module a first frequency division reset signal, and trigger start of a timer in the control module associated with the first frequency division reset signal, the timer performing timing on the basis of the working clock signal; the frequency division module is configured to perform frequency division on an input clock signal on the basis of the first frequency division reset signal, so as to output a frequency-divided signal, the input clock signal being generated on the basis of the first clock signal, and the first frequency division reset signal being configured to control the starting time of outputting the frequency-divided signal by the frequency division module to be separated from the start time of the timer by a first predetermined duration.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
3.
SIGNAL PROCESSING APPARATUS, SIGNAL PROCESSING METHOD, ELECTRONIC DEVICE, AND STORAGE MEDIUM
Embodiments of the present disclosure provide a signal processing apparatus, a signal processing method, an electronic device, and a storage medium. The signal processing apparatus comprises: a signal processing circuit, configured to receive, by means of an input interface, a first transmission parameter of a transmission path associated with an input signal; to perform frequency resampling on the first transmission parameter on the basis of a predetermined frequency parameter to obtain a second transmission parameter, and to determine a first frequency response of the transmission path on the basis of the second transmission parameter, the first frequency response being associated with embedding processing or de-embedding processing of the input signal; to perform conjugate symmetry processing on the first frequency response to obtain a second frequency response that is a complex conjugate symmetric counterpart of the first frequency response; to perform frequency domain to time domain conversion on the second frequency response to obtain a unit impulse response of the transmission path; and to determine filter parameters of a digital filter on the basis of the unit impulse response. The digital filter is configured to process the input signal on the basis of the filter parameters to obtain an output signal.
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
H03M 1/08 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques du bruit
A clock synchronization (SYNC) system. The clock SYNC system comprises a trigger group (110) and a frequency divider group (120); the trigger group (110) comprises N triggers; the frequency divider group (120) comprises N frequency dividers; and the trigger group (110) receives N clock signals and one SYNC pulse signal, respectively transmits the N clock signals to the N frequency dividers, and respectively transmits to the N frequency dividers the N pulse signals outputted by the trigger group (110), wherein N is a positive integer greater than 1.
An oscilloscope. The oscilloscope comprises: a first data processing unit (10), which sends a first synchronization signal to a first multi-output unit (20); the first multi-output unit (20), which outputs a second synchronization signal to each of N sampling channels on the basis of the first synchronization signal; analog-to-digital conversion units (30), which perform signal sampling to determine first sampling data, and synchronously transmit, on the basis of the second synchronization signals, the first sampling data to second data processing units (40) of the sampling channels to which the analog-to-digital conversion units (30) belong; and the second data processing units (40), which process the received first sampling data, and send to the first data processing unit (10) second sampling data obtained by processing the first sampling data.
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
6.
OUTPUT CIRCUIT FOR MULTI-PHASE CLOCK SIGNAL AND CONTROL METHOD THEREFOR
The present application provides an output circuit for a multi-phase clock signal and a control method therefor. The output circuit for a multi-phase clock signal comprises at least two clock signal output links; and each clock signal output link comprises a phase selection module, a phase conversion module and a delay module. A plurality of input ends of the phase selection module are electrically connected to a plurality of clock signal input ends in one-to-one correspondence, the input ends of the phase selection module serve as input ends of the clock signal output links, and an output end of the phase selection module is electrically connected to an input end of the phase conversion module; and the phase selection module is configured to select input clock signals. An output end of the phase conversion module is electrically connected to an input end of the delay module, the phase conversion module is configured to invert the phases of clock signals, and the delay module is configured to adjust the phases of the clock signals.
H03K 5/14 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de lignes à retard
H03L 7/085 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie
An amplifier, comprising a transconductance amplification module (100), a feedforward transconductance module (200) and a gain control module (300), wherein an input control end pair (101P, 101N) of the transconductance amplification module (100) is connected to an input signal pair (VIP, VIN), and the transconductance amplification module (100) is configured to convert the input signal pair (VIP, VIN) into an output current pair (IOP, ION) and output same; a first feedforward control end pair (201P, 201N) comprised in the feedforward transconductance module (200) is connected to the input signal pair (VIP, VIN) and outputs a feedforward current pair; the gain control module (300) comprises a first differential pair (301) and a second differential pair (302), and a first output end (302P) and second output end (303P) of the first differential pair (301) are respectively configured to compensate for a non-inverting output current and inverting output current in the output current pair; and a first output end (302N) and second output end (303N) of the second differential pair (302) are respectively configured to compensate for the non-inverting output current and inverting output current in the output current pair.
The present application relates to a bandwidth limiting circuit and a front-end circuit. The bandwidth limiting circuit comprises at least two signal transmission paths connected in parallel between a signal input end and a signal output end. The at least two signal transmission paths are configured to have different bandwidth ranges. The bandwidth ranges include a first bandwidth range, so that the bandwidth of a signal transmitted via the signal transmission path having the first bandwidth range and outputted from the signal output end is limited. Any one of the at least two signal transmission paths is connected when other paths are disconnected.
A waveform selection method and apparatus, a device, and a storage medium. The method comprises: in response to a click operation of a user, determining a click position on a display (S110); on the basis of the click position, determining a waveform selection region (S120); respectively determining waveform energy of multiple channel waveforms in the waveform selection region (S130); and on the basis of the waveform energy of the multiple channel waveforms, selecting a target waveform from among the multiple channel waveforms (S140).
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
10.
OSCILLOSCOPE SIGNAL WAVEFORM DISPLAY PROCESSING METHOD AND APPARATUS, AND OSCILLOSCOPE
An oscilloscope signal waveform display processing method and apparatus, and an oscilloscope. The method comprises: opening AUTO functions of some oscilloscope channels (S110); detecting whether said oscilloscope channels have signal access (S120); and when it is detected that at least one oscilloscope channel among said oscilloscope channels has signal access, using the AUTO function of the oscilloscope channel, which has signal access, to automatically adjust the time base, the vertical gear and the offset parameter of the oscilloscope channel having signal access, so as to generate input signal display suitable for observation (S130).
Embodiments of the present application relate to a signal analysis interaction method and a signal analysis apparatus. The method comprises: on the basis of an acquired signal, displaying an image of at least one waveform of the signal in an image display area of a screen; in response to a first control operation, displaying a selected area in the image display area, wherein the selected area is used for indicating an area selected on the basis of the first control operation in the image display area; on the basis of the image in the selected area, determining a channel list of a signal selected on the basis of the first control operation; and on the basis of the channel list, displaying a function option to be executed.
The present application discloses a signal source and a radio frequency signal output control method of the signal source. The signal source comprises a frequency source, a radio frequency switch, a frequency lock detection module and a processor. The frequency source is connected to the radio frequency switch. An input end of the frequency lock detection module is connected to the frequency source, and an output end of the frequency lock detection module is connected to an input end of the processor; the frequency lock detection module is configured to detect whether the frequency generated by the frequency source is in a locked state to obtain a first detection result, and send the first detection result to the processor. An output end of the processor is connected to the radio frequency switch. When the frequency source is about to perform frequency switching, the processor controls the radio frequency switch to be turned off. When the frequency source performs frequency switching and the first detection result indicates that the frequency generated by the frequency source is in the locked state, the processor controls the radio frequency switch to be turned on.
Disclosed are a signal sampling system, a signal sampling method, and an electronic device. The signal sampling system comprises K signal sampling circuits (11), N switch circuits (12), N analog-to-digital converters (13), and one digital filtering module (14), wherein the K signal sampling circuits (11) are used for collecting target signals, the K signal sampling circuits (11) are divided into N groups of signal sampling modules, and the number of signal sampling circuits (11) that are comprised in each group of signal sampling modules is greater than or equal to 2; the N switch circuits (12) respectively correspond to the N groups of signal sampling modules on a one-to-one basis, and each switch circuit (12) is respectively in communication with one signal sampling circuit (11) at the same moment; the N analog-to-digital converters (13) are respectively connected to the N switch circuits (12) in a one-to-one correspondence, and each analog-to-digital converter (13) is used for converting the target signals into digital signals; and the digital filtering module (14) is connected to the N analog-to-digital converters (13), and is used for respectively processing N digital signals on the basis of a digital filtering algorithm for which a target filtering frequency is set.
A signal processing apparatus and method, and a digital oscilloscope. The signal processing apparatus is configured to output one of two target signals according to a trigger signal and a trigger level. The signal processing apparatus comprises a trigger comparison unit (100), a trigger display unit (500) and a controller (200), wherein the trigger comparison unit (100) is configured to extract a low-frequency component signal of the trigger signal; the controller (200) is electrically connected to the trigger comparison unit (100), and is configured to generate a trigger comparison signal according to the relationship between the low-frequency component signal and the trigger signal, and output, according to a preset rule, a target signal obtained on the basis of the trigger comparison signal; and the trigger display unit (500) is electrically connected to the controller (200), and is configured to receive the target signal and display the target signal on a target interaction interface.
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
15.
MULTI-DESKTOP SYSTEM AND CONTROL METHOD FOR MULTI-DESKTOP SYSTEM, AND MULTI-DESKTOP DEVICE AND COMPUTER MEDIUM
A multi-desktop system and a control method for a multi-desktop system, and a multi-desktop device and a computer medium, wherein the control method for a multi-desktop system is used for switching between different desktops in a test and measurement instrument. The method comprises: when a desktop switching instruction is received, recording configuration information and a thumbnail of the current desktop and generating a desktop control instruction; and in response to the desktop control instruction, storing the configuration information and the thumbnail of the current desktop in a preview region of a multi-desktop control module, and selecting a thumbnail of a target desktop from the preview region and loading configuration information of the target desktop, wherein the configuration information of the target desktop is the configuration information of when the target desktop is stored in the preview region last time.
A relay and an electrical device. The relay comprises a main body unit (110) and a circuit board unit (100). The circuit board unit (100) comprises an insulating layer portion (101) and a conductive layer portion stacked on the insulating layer portion (101). The conductive layer portion comprises a first patterned area (102), and the first patterned area (102) forms at least a part of a static contact. The main body unit (110) comprises a driving structure (112) and a moving conductor (111). The driving structure (112) is used for driving the moving conductor (111) to move, and the moving conductor (111) is electrically connected to or disconnected from the first patterned area (102) under the drive of the driving structure (112).
A touch-control method, apparatus, system and device, and a medium. The touch-control method is used for performing touch control on a waveform region in a touch display screen of an oscilloscope, and comprises: acquiring a user's touch operation feedback signal on a touch display screen, determining whether the duration of the touch operation feedback signal is greater than or equal to a preset period of time, and determining whether a touch position within the duration is fixed and remains unchanged; and when the duration of the touch operation feedback signal is greater than or equal to the preset period of time and the touch position within the duration is fixed and remains unchanged, resetting a selected waveform region in the touch operation feedback signal.
G06F 3/0488 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] utilisant des caractéristiques spécifiques fournies par le périphérique d’entrée, p. ex. des fonctions commandées par la rotation d’une souris à deux capteurs, ou par la nature du périphérique d’entrée, p. ex. des gestes en fonction de la pression exercée enregistrée par une tablette numérique utilisant un écran tactile ou une tablette numérique, p. ex. entrée de commandes par des tracés gestuels
18.
ROTARY INPUT CONTROL DEVICE AND USER INPUT APPARATUS
The present disclosure relates to a rotary input control device and a user input apparatus. The rotary input control device comprises: a rotary input mechanism provided with a magnet; an electro-permanent magnet assembly, comprising an electro-permanent magnet and a coil, wherein the coil is arranged on the electro-permanent magnet to magnetize or demagnetize the electro-permanent magnet when energized; and a control module, configured to control the current of the coil such that the electro-permanent magnet is in a magnetized state or a demagnetized state.
An oscilloscope and a data processing method. The oscilloscope comprises: a plurality of data acquisition channels (101) and a plurality of processing modules (102). One processing module (102) is connected to one data acquisition channel (101); the processing modules (102) are electrically connected to each other; and one processing module (102) is used for processing data in at least one data acquisition channel (101). The data processing method comprises: acquiring first data of a first data acquisition channel of an oscilloscope (S201); determining a first resource utilization rate of a first processing module corresponding to the first data acquisition channel of the oscilloscope (S203); determining a second resource utilization rate of a second processing module corresponding to a second data acquisition channel of the oscilloscope (S205); and according to the first resource utilization rate and the second resource utilization rate, processing at least part of the first data by using the first processing module and/or the second processing module (S207).
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
20.
OSCILLOSCOPE PROBE, PROBE DETECTION METHOD AND APPARATUS, OSCILLOSCOPE, SYSTEM, AND MEDIUM
Disclosed in the present invention are an oscilloscope probe, a probe detection method and apparatus, an oscilloscope, a system, and a storage medium. The oscilloscope probe comprises a signal testing path and a detection circuit, wherein the signal testing path is used for connecting to an oscilloscope channel of an oscilloscope and transmitting a signal under test to the oscilloscope channel; and the detection circuit comprises a capacitor and a detection connector, a first end of the capacitor being grounded, a second end of the capacitor being electrically connected to a first end of the detection connector, and a second end of the detection connector being used for connecting to an identification circuit in the oscilloscope, wherein the capacitance value of the capacitor is related to the type of the oscilloscope probe. By means of the technical solution, the measurement accuracy and reliability can be effectively ensured while the power consumption is reduced.
An adjustable time delay circuit. The circuit comprises: a first adjustment module, comprising a first input end and a control output end; a second adjustment module, comprising a second input end and a first output end; a third adjustment module, comprising a third input end and a second output end; and a time delay module, comprising: a signal input end configured to receive a target differential signal pair; a strobe signal input end connected to the control output end and configured to receive a control strobe signal; a first control end configured to receive a first pair of differential signals; a second control end configured to receive a second pair of differential signals, wherein the time delay module is configured to delay the target differential signal pair according to the inputted control strobe signal, the first pair of differential signals, and the second pair of differential signals; and a signal output end configured to output the target differential signal pair delayed by the time delay module.
Provided in the embodiments of the present application is a counter, comprising: a counting module, which comprises a plurality of cascaded sub-counters and a delay unit connected between at least two adjacent sub-counters among the plurality of sub-counters, wherein the sub-counters are used for counting the number of clock pulses to output count output signals and carry output signals, and the delay unit is used for receiving a carry output signal from the sub-counter at the former stage among the at least two sub-counters, delaying the received carry output signal and outputting same to the sub-counter at the latter stage; and a data alignment module, which is used for receiving the count output signals from the plurality of sub-counters and performing, according to a correspondence with a delay time caused by the delay unit, data alignment on a plurality of received count output signals that belong to the same counting period, so as to output a counting result. In this way, the operating speed of the counter is increased while the counting accuracy is ensured, thereby facilitating the implementation of a counter having more bits.
The present application provides a high-low level conversion circuit. The circuit comprises a high voltage to low voltage module, a low voltage to high voltage module, a first target chip, and a second target chip; the low voltage to high voltage module comprises a switch unit and a level translation unit; an input end of the level translation unit is configured to be input with a level signal of the second target chip, and an output end of the level translation unit is electrically connected to a control end of the switch unit; two input ends of the switch unit are configured to be input with different voltages; the level translation unit is configured to control connection states of the two input ends and an output end of the switch unit; the first target chip is electrically connected to an input end of the high voltage to low voltage module and is electrically connected to the output end of the switch unit; and the second target chip is communicationally connected to the first target chip and is electrically connected to an output end of the high voltage to low voltage module; wherein the voltage tolerable by the first target chip is greater than the voltage tolerable by the second target chip.
An analog front-end chip (1) and an oscilloscope. An input buffer module (11), a variable gain amplification module (12), and at least two output branches (13) are integrated in the analog front-end chip (1). An input end of the input buffer module (11) serves as an input end of the analog front-end chip (1), and an output end of the input buffer module (11) is electrically connected to an input end of the variable gain amplification module (12). An input end of each output branch (13) is electrically connected to an output end of the variable gain amplification module (12), and an output end of each output branch (13) serves as an output end of the analog front-end chip (1). Each output branch (13) comprises an output buffer module (131).
G01R 13/00 - Dispositions pour la présentation de variables électriques ou de formes d'ondes
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
A chip test circuit, a chip and a test device. The chip test circuit comprises: a signal input end (10); a plurality of signal output ends (30); and a switch assembly (20), comprising at least one switch module (210) which comprises a plurality of switch branches (211, 212, 213, 214), the number of the switch branches (211, 212, 213, 214) being matched with the number of the signal output ends (30). The switch branches (211, 212, 213, 214) comprise: first ends of the switch branches electrically connected to the signal input end (10); second ends of the switch branches (211, 212, 213, 214) connected to the signal output ends (30) in an one-to-one correspondence manner; and switch units (211a, 212a, 213a, 214a) connected between the first ends of the switch branches (211, 212, 213, 214) and the second ends of the switch branches (211, 212, 213, 214), the switch units (211a, 212a, 213a, 214a) being configured to be selectively switched on according to the type of a signal to be tested so as to transmit said signal to the signal output ends (30).
Provided in the present application are an offset voltage calibration circuit and method. The circuit comprises: a multi-stage amplifier; a gating switch, which comprises a plurality of switches each correspondingly connected to an output end of each stage of amplifier in the multi-stage amplifier, wherein an offset voltage of the output end is transmitted to the gating switch; a comparator, which is electrically connected to the gating switch, wherein the comparator is configured in such a way that the offset voltages of the multi-stage amplifier are input into the comparator via the gating switch, and the comparator outputs a high level or a low level according to the offset voltages; and a controller, which is electrically connected to the gating switch, and is configured to receive a control instruction and control the on/off of each switch in the gating switch according to the control instruction, so as to calibrate the offset voltages by means of the comparator.
Provided in the embodiments of the present application is a signal transmission circuit. The signal transmission circuit comprises a positive input end; a negative input end; and an amplification unit which is connected to the positive input end and the negative input end and is configured to receive a differential voltage signal, convert same into a differential current signal and output the differential current signal. The amplification unit comprises a current source, which is configured to independently generate and supply current; a first branch, which is connected to the current source, acquires a positive terminal voltage signal, converts the positive terminal voltage signal into a positive current signal and transmits same to a first transmission line; and a second branch, which is connected to the current source, acquires a negative terminal voltage signal, converts the negative terminal voltage signal into a negative current signal and transmits same to a second transmission line.
The present application relates to the technical field of signal processing, and discloses a sample and hold circuit and a sample and hold method. The circuit comprises an input unit, track/hold switch units, and output units. The input unit is configured to receive differential input signals, and amplify the differential input signals and then input the amplified differential input signals into the track/hold switch units. The track/hold switch units are configured to track or hold the amplified differential input signals. The track/hold switch units each comprise a first emitter follower, a hold capacitor, a shunt circuit subunit and a first current supply, wherein an emitter of the first emitter follower is connected to the hold capacitor, a power supply voltage is inputted into a collector of the first emitter follower, a base of the first emitter follower is connected to a first output end of the input unit; and the first output end is configured to output one of the two amplified differential input signals.
The present application relates to a combined operational amplifier circuit, a chip and a signal processing apparatus. The combined operational amplifier circuit comprises: a first operational amplifier, configured, when an in-phase input terminal and a reverse-phase input terminal of the first operational amplifier have the same electrical properties, to generate a signal to be calibrated; a second operational amplifier, connected to an output terminal of the first operational amplifier; and a calibration circuit, comprising: a judgment branch configured for judging an amplitude and a reference value of the signal to be calibrated generated by the first operational amplifier, and generating a judgment result; and a calibration branch, configured for generating a calibration signal according to the judgment result outputted by the judgment branch, and providing the calibration signal as feedback to the first operational amplifier. Utilizing the technical scheme of the present application allows for improving the precision and bandwidth of the combined operational amplifier circuit.
H03F 1/30 - Modifications des amplificateurs pour réduire l'influence des variations de la température ou de la tension d'alimentation
H03F 1/42 - Modifications des amplificateurs pour augmenter la bande passante
H03F 3/08 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs commandés par la lumière
H03F 3/68 - Combinaisons d'amplificateurs, p. ex. amplificateurs à plusieurs voies pour stéréophonie
30.
ANALOG FRONT-END CHIP, ANALOG FRONT-END CIRCUIT, AND SIGNAL PROCESSING DEVICE
Embodiments of the present application provide an analog front-end chip, an analog front-end circuit, and a signal processing device. The analog front-end chip comprises: a first operational amplifier module, configured to perform amplitude adjustment on an electric signal on a path connected to a first input impedance network; and a second operational amplifier module, configured to perform amplitude adjustment on an electric signal on a path connected to a second input impedance network, wherein the impedance of the second input impedance network is different from that of the first input impedance network, and the first operational amplifier module and the second operational amplifier module are integrated in a same chip.
Disclosed in the present application are a multi-phase clock generation circuit and method. The circuit comprises: a frequency division module, wherein a signal input end of the frequency division module receives and connects to a clock source signal, and the frequency division module is configured to perform two divided-frequency on the clock source signal, so as to generate a first reference clock signal and a second reference clock signal, which intersect with each other; and a multi-phase clock generation module, which is connected to an output end of the frequency division module, wherein the multi-phase clock generation module is configured to receive the first reference clock signal and the second reference clock signal, and output a four-phase clock signal with a predetermined phase difference relationship.
A time delay calibration apparatus (100), comprising: a source signal supply module (110), a source signal processing module (120) and a fan-out module (130), wherein the source signal supply module (110) is connected to the source signal processing module (120) and is used for providing a source signal for the source signal processing module (120); the source signal processing module (120) is used for generating a time delay calibration signal on the basis of the source signal and outputting the time delay calibration signal to the fan-out module (130); and the fan-out module (130) is used for performing fan-out processing on the time delay calibration signal, so as to obtain a plurality of paths of output signals, which are output to the outside of the time delay calibration apparatus (100). In this way, time delay calibration can be performed on a plurality of probes simultaneously, thereby facilitating a user operation and saving on the time delay calibration time; and compared with time delay calibration using an ordinary signal source, time delay calibration in the present application can better meet time delay calibration requirements, such that the accuracy of time delay calibration is improved. An oscilloscope comprising a time delay calibration apparatus, a time delay calibration system, and a time delay calibration method, which is applied to a time delay calibration apparatus, are provided.
Provided in the embodiments of the present application are a probe, an oscilloscope and a digital signal test system. The probe comprises an input end, a sending signal conversion module and an output end, wherein the input end is used for receiving a digital signal to be tested; the sending signal conversion module is connected between the input end and the output end, and is used for converting, according to a first clock signal, said digital signal, which is received, into a sending signal, which can be received by an analog channel of the oscilloscope; the first clock signal and a second clock signal are same-source clock signals, the second clock signal is a clock signal used when a receiving signal conversion module in the oscilloscope works, and the receiving signal conversion module is a module which is connected to the analog channel so as to receive a sending signal; and the output end is used for outputting the sending signal to the analog channel of the oscilloscope.
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
34.
ABNORMAL WAVEFORM CAPTURING METHOD AND APPARATUS, ELECTRONIC DEVICE AND STORAGE MEDIUM
The present application relates to the technical field of signal processing, and provides an abnormal waveform capturing method and apparatus, an electronic device and a storage medium for accurately capturing an abnormal waveform in a signal in real time. The method comprises: determining an eye pattern formed by a waveform to be detected at the first time; determining a first measurement item corresponding to the eye pattern; determining, on the basis of the eye pattern, a first measurement value corresponding to the first measurement item; and under the condition that the first measurement value does not meet a first preset condition, outputting an abnormal waveform corresponding to the first time in the eye pattern.
G06K 9/00 - Méthodes ou dispositions pour la lecture ou la reconnaissance de caractères imprimés ou écrits ou pour la reconnaissance de formes, p.ex. d'empreintes digitales
35.
TIME DOMAIN INTERLEAVING ANALOG-TO-DIGITAL CONVERTER SYNCHRONIZATION METHOD AND APPARATUS
The present application belongs to the field of control systems. Disclosed are a time domain interleaving analog-to-digital converter synchronization method and apparatus. The apparatus comprises: a time domain interleaving analog-to-digital conversion module, wherein in a first state, an input end thereof is connected to a signal input end, and the time domain interleaving analog-to-digital conversion module performs interleaved sampling on a target analog signal by means of a plurality of analog-to-digital conversion sub-modules, and outputs a multi-channel target digital signal; a calibration module, wherein an input end thereof is connected to the time domain interleaving analog-to-digital conversion module, and in the first state, the calibration module calibrates the multi-channel target digital signal according to a delay error value, so as to obtain a calibrated multi-channel digital signal, and the delay error value is determined in a second state and according to a reference analog signal and a synchronization control signal, the reference analog signal being in clock synchronization with the time domain interleaving analog-to-digital conversion module, and the synchronization control signal being in phase synchronization with the reference analog signal; and a waveform generator module, which is connected to the time domain interleaving analog-to-digital conversion module in the second state, is also connected to the calibration module, and is used for outputting the reference analog signal and the synchronous control signal.
Disclosed are a snubber circuit and a delay circuit. The snubber circuit comprises: an input terminal configured to access an input differential signal; an output terminal configured to be connected to a functional circuit; a power supply terminal configured to access power supply; a drive unit configured to respond to the input differential signal at the input terminal and generate an output differential signal to the output terminal; a load unit coupled between the output terminal and the power supply terminal; and a negative capacitance unit coupled between the power supply terminal and the output terminal, and configured to reduce the capacitance of the functional circuit.
The present invention provides a duty ratio adjustment circuit and an output circuit. The duty ratio adjustment circuit comprises an input module, a current mode logic module, and an output module. The current mode logic module comprises at least two current mode logic circuits. The at least two current mode logic circuits have different adjustment degrees for the duty ratio of a differential signal when working. The current mode logic circuits are connected to the input module so as to receive an initial differential signal inputted by the input module. The output module is connected to at least one current mode logic circuit so as to output a target differential signal. According to the duty ratio adjustment circuit, the current mode logic circuits have different adjustment degrees for the duty ratio of the differential signal, such that the adjustment range of the duty ratio adjustment circuit for the duty ratio of the initial differential signal can be accurately and flexibly adjusted, and the duty ratio adjustment circuit is simple to design, has high replicability, and is more convenient in layout design.
Provided in the present application are an adjustable capacitor circuit and a delay adjustment circuit, the adjustable capacitor circuit comprising at least one capacitance adjustment unit. The capacitance adjustment unit comprises two adjustment sub-units, and each adjustment sub-unit comprises a capacitor, a unidirectional power conduction tube, and a loop module, wherein a first electrode of the capacitor serves as a first end of the adjustment sub-unit, and a second electrode of the capacitor is connected to a first electrode of the unidirectional power conduction tube and a second end of the loop module; a second electrode of the unidirectional power conduction tube is connected to a control signal end and serves as a second end of the adjustment sub-unit; and a first end of the loop module is connected to a first voltage end, and the two adjustment sub-units are arranged in a mirrored manner with respect to the control signal end.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H03K 17/284 - Modifications pour introduire un retard avant commutation dans les commutateurs à transistors à effet de champ
39.
MULTI-PATH SIGNAL COHERENT CIRCUIT AND RADIO FREQUENCY SIGNAL SOURCE
Disclosed in embodiments of the present application are a multi-path signal coherent circuit and a radio frequency signal source. The multi-path signal coherent circuit comprises: at least two signal generation modules, each signal generation module receiving a phase adjustment signal and outputting a single signal under the control of the phase adjustment signal; and a phase difference measurement module electrically connected to the at least two signal generation modules and configured to measure a phase difference between two signals and generate the phase adjustment signal.
Provided in the embodiments of the present application are a waveform sequence processing method and processing apparatus, and an electronic device and a storage medium. The apparatus comprises: a waveform fragment display module, which is used for displaying at least one waveform fragment in a sequence track that is displayed on a display interface; and a waveform sequence creation module, which is used for creating, on the basis of an editing operation on a target waveform fragment that is performed in the sequence track by a user, a waveform sequence which corresponds to the sequence track, wherein the target waveform fragment is a waveform fragment selected by the user from among the at least one waveform fragment. By means of the present embodiment, an editing operation between waveform fragments is made to be more convenient and intuitive.
A delay measurement apparatus (S00) and measurement method, which relate to the technical field of high-accuracy measurement of hardware circuits. The apparatus comprises: a data source module (100), which is used for outputting calibration data; a digital-to-analog conversion module (200), which is connected to the data source module (100) and is used for converting the calibration data into an analog calibration signal, wherein the analog calibration signal comprises periodic signals of at least two different features; an analog-to-digital conversion module (300), which is directly connected to the digital-to-analog conversion module (200) so as to form a first loop, and is connected to the digital-to-analog conversion module (200) by means of a sample to be subjected to measurement (10) so as to form a second loop; and a calculation module (400), which is used for acquiring a first time parameter according to the analog calibration signal and a first collection signal, acquiring a second time parameter according to the analog calibration signal and a second collection signal, and calculating the delay of said sample (10) according to the first time parameter and the second time parameter. Delay measurement is performed on said sample (10) by using the calibration signal comprising the periodic signals of at least two different features, such that the problem of it being difficult to determine the starting moment of high-frequency multi-period signals is solved.
A power-on and power-off control circuit and a signal output apparatus. The circuit comprises an output power supply module (10), an energy storage module (20) and a constant-current control module (30), wherein the output power supply module (10) comprises a power supply positive electrode and a power supply negative electrode; two ends of the energy storage module (20) are electrically connected to the power supply positive electrode and the power supply negative electrode, respectively, and are configured to store an electrical signal, which is output by the output power supply module (10) when the output power supply module (10) is powered on, and release the stored electrical signal when the output power supply module (10) is powered off; and the constant-current control module (30) is electrically connected to the two ends of the energy storage module (20), and is configured to control a discharge current of the energy storage module (20) when the output power supply module (10) is powered off.
G05B 19/042 - Commande à programme autre que la commande numérique, c.-à-d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
43.
MULTI-CHANNEL SIGNAL SYNCHRONIZATION METHOD, POWER SUPPLY MODULES, ELECTRONIC DEVICE AND POWER SUPPLY DEVICE
A multi-channel signal synchronization method, power supply modules, an electronic device, and a power supply device. In the multi-channel signal synchronization method, a first power supply module (700) is connected to a plurality of mutually isolated second power supply modules (800); according to total data information inputted by a user, target data information and a target duration are allocated to each second power supply module (800); and then the first power supply module (700) synchronously sends a clock signal to each second power supply module (800) so as to trigger each second power supply module (800) to synchronously output a data signal corresponding to the target data information, and the output duration of the data signal is controlled to be equal to the target duration.
Embodiments of the present application disclose a switch circuit, a chip, and a signal processing device. The switch circuit comprises: a switch module which comprises a switch input end and a switch output end, and is configured to connect the switch input end and the switch output end so as to transmit a signal of the switch input end to the switch output end; and an electric leakage compensation module which is configured to provide a compensation signal to the switch output end according to the electric leakage characteristic of the switch module.
Disclosed in the embodiments of the present application are a frequency response calibration circuit, a chip and a signal processing apparatus. The frequency response calibration circuit comprises an operational amplification module and a frequency response adjustment module, wherein the operational amplification module comprises an inverting input end and an operational amplification output end, and the operational amplification module is configured to adjust the amplitude of a received signal and then output same; the frequency response adjustment module is connected between the inverting input end and the operational amplification output end of the operational amplification module, and the frequency response adjustment module is configured to perform a flatness adjustment on the received signal; and the operational amplification module and the frequency response adjustment module are integrated into the same chip.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
46.
ANALOGUE FRONT-END CIRCUIT, CHIP AND SIGNAL PROCESSING APPARATUS
Provided are an analogue front-end circuit, a chip and a signal processing apparatus. The analogue front-end circuit comprises a receiving circuit (10), a first operational amplification module (20), a second operational amplification module (30) and a control module (40), wherein the receiving circuit (10) is configured to receive an input signal of the analogue front-end circuit; the first operational amplification module (20) is configured to perform in-phase amplitude regulation on a signal output from the receiving circuit (10), so as to output a first analogue signal; the second operational amplification module (30) is configured to perform inverting amplitude regulation on the signal output from the receiving circuit (10), so as to output a second analogue signal; and the control module (40) is configured to choose, according to an attribute of the input signal, the first analogue signal or the second analogue signal, to output the first analogue signal or the second analogue signal.
Disclosed are a signal transmission network, a chip, and a signal processing device. The signal transmission network comprises: an impedance unit comprising a signal input end and a plurality of signal output ends, the impedance unit being configured to perform different degrees of gain adjustment on an input signal received by the signal input end and then convert the input signal into a plurality of different current signals, and the plurality of different current signals being respectively supplied to the plurality of signal output ends; and a gating switch unit comprising a plurality of switch input ends and a switch output end, the plurality of switch input ends being connected to the plurality of signal output ends in a one-to-one correspondence manner, and the gating switch unit being configured to selectively turn on one switch input end and the switch output end so as to output a current signal.
H04B 1/401 - Circuits pour le choix ou l’indication du mode de fonctionnement
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
An electrical signal sampling apparatus (100), comprising a pulse signal source (110), a first sampling module (130) and a signal delay module (140), wherein the pulse signal source (110) is configured to generate a pulse signal; the first sampling module (130) is connected to the pulse signal source (110) by means of a coupler (120); the coupler (120) is configured to perform one-to-two fan-out on the pulse signal, so as to generate a test input signal and a sampling incident signal, and the test input signal is input into a tested device (150) from the coupler (120) and is then coupled to form a test output signal; the first sampling module (130) is configured to collect the sampling incident signal and the test output signal from the coupler (120); and the signal delay module (140) generates N excitation signals by means of preset delay, and the N excitation signals are used for controlling the pulse signal source (110) to generate N groups of pulse signals within the period of the pulse signal, or the N excitation signals are used for controlling the first sampling module (130) to generate N groups of sampling incident signals within the period of the sampling incident signal.
G01R 13/02 - Dispositions pour la présentation de variables électriques ou de formes d'ondes pour la présentation sous forme numérique des variables électriques mesurées
49.
ELECTRONIC TEST DEVICE AND OPTIONAL FUNCTION CONFIGURING METHOD
The present application relates to an electronic test device and an optional function configuring method. A ciphertext decryption authentication unit performs a decryption authentication operation according to a function selection key and a function selection ciphertext, executes a corresponding operation on a functional apparatus corresponding to the function selection ciphertext according to an authentication result signal, and outputs the authentication result signal to an operation control unit, such that the operation control unit operates, according to the authentication result signal, a target function corresponding to the function selection ciphertext.
The present application discloses a synchronization machine and a synchronization system, the synchronization machine comprising: a power distribution module and a shaping module which are connected to each other, the power distribution module being configured to perform power distribution on an original calibration signal inputted into the synchronization machine, so as to form M intermediate calibration signals, the shaping module being configured to shape the M intermediate calibration signals to form M target calibration signals, and the edge rate of each target calibration signal being greater than that of the original calibration signal.
H03K 5/15 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions
H03K 5/12 - Mise en forme d'impulsions par redressement des fronts avant ou arrière
A test instrument (100) and method. The test instrument (100) comprises: a first processing unit (110); a second processing unit (120), which is connected to the first processing unit (110); and at least one receiving RX link (130) and at least one transmitting TX link (140), which are connected to the second processing unit (120), wherein the first processing unit (110) is used for acquiring configuration information, which is used for reflecting a target test function that needs to be completed by the test instrument (100), and the first processing unit is also used for determining a target configuration program according to the configuration information, and for running an application program of the target test function according to the configuration information; and the second processing unit (120) is used for running the target configuration program, configuring some or all RX links of the at least one RX link (130), and/or configuring some or all TX links in the at least one TX link (140), so as to realize the transmission of test data generated during the running process of a target application program. The test instrument (100) and the method facilitate the realization of a plurality of measurement functions at the same time, thereby reducing the cost and saving on instrument space; and test function customization can be realized according to user requirements.
A differential probe and a control method therefor. The differential probe comprises a probe body, a first contact element (200), a second contact element (300) and a driving mechanism (400). The probe body comprises a shell (100), and the shell (100) has a receiving cavity; the first contact element (200) comprises a first contact (221) and a first rotating shaft, the first contact element (200) is rotatably arranged on the probe body around the first rotating shaft, and the first contact (221) is eccentrically distributed with respect to the first rotating shaft and rotates around the first rotating shaft in a first direction; the second contact element (300) comprises a second contact (321) and a second rotating shaft, the second contact element (300) is rotatably arranged on the probe body around the second rotating shaft, and the second contact (321) is eccentrically distributed with respect to the second rotating shaft and rotates around the second rotating shaft in a second direction; and the first direction is opposite to the second direction, and a detection area is formed between the first contact (221) and the second contact (321). The problem that the existing differential probes cannot accurately adjust the probe spacing can be solved.
Disclosed in the present application are a display control method and apparatus, an electronic device, and a readable storage medium. The method comprises: displaying, on a first function display interface of the electronic device, a function item display setting item and at least one function item of the electronic device; in response to a first operation instruction of the function item display setting item, displaying a second function display interface associated with the function item display setting item, the second function display interface being used for obtaining all the function items of the electronic device, each function item carrying a corresponding state statistic identifier, and the state statistic identifier being used for indicating a usage state parameter of a device function associated with each function item; in response to a second operation instruction of the second function display interface, determining at least one target function item in the function items obtained by the second function display interface; and according to the at least one target function item, updating the at least one function item currently displayed on the first function display interface.
G06F 3/0481 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] fondées sur des propriétés spécifiques de l’objet d’interaction affiché ou sur un environnement basé sur les métaphores, p. ex. interaction avec des éléments du bureau telles les fenêtres ou les icônes, ou avec l’aide d’un curseur changeant de comportement ou d’aspect
54.
INFORMATION PROCESSING METHOD AND APPARATUS, AND MULTI-FUNCTIONAL DEVICE
An information processing method, an information processing apparatus (400), and a multi-functional device (500). The information processing method comprises: when a multi-functional device (500) is provided with a first display area, a second display area and a physical response component, and a plurality of functions are integrated into the multi-functional device (500), responding to a function switching operation of the multi-functional device (500) (S110); displaying, in the first display area, a target function corresponding to the function switching operation, and displaying, in the second display area, first function information corresponding to the target function (S120), wherein the first function information comprises a virtual key and/or a first physical response component identifier; and if the first function information comprises the first physical response component identifier, updating the current operation function of the physical response component according to an operation function corresponding to the first physical response component identifier (S130).
A test function module, and a multi-functional testing system and method. The test function module comprises a first field-programmable gate array (FPGA) unit (110) and multiple functional circuit units (120). The first FPGA unit (110) is connected to the multiple functional circuit units (120). Functions of the multiple functional circuit units (120) are completely the same, partially the same, or completely different. The first FPGA unit (110) is used to receive a configuration program, configure a common resource according to the configuration program so as to define functions of the testing function module, and control, according to the configuration program, at least one functional circuit to operate, such that the testing function module operates in an operating mode corresponding to the configuration program. The above arrangement enables multiple measurement functions to be realized simultaneously, saves on costs and space required for an instrument, and enables a user to customize functions according to needs.
A multifunctional measurement device, a resource configuration method, a measurement method and apparatus, and a medium. The multifunctional measurement device comprises: a memory (110), a processor (120), a common circuit (130), and a plurality of functional circuits (140); the memory (110) is configured to store a software program capable of realizing a measurement function; the common circuit (130) is separately connected to the plurality of functional circuits (140); the functions of the plurality of functional circuits (140) are the same, or partially the same, or completely different; the processor (120) is configured to execute the software program, and perform resource configuration on the common circuit (130) based at least in part on a common resource required by the software program; and the processor (120) is further configured to control at least one functional circuit (140) to work, so as to realize the measurement function corresponding to the executed software program.
Embodiments of the present application provide a multi-channel signal synchronization system, circuit, and method. The multi-channel signal synchronization system comprises a clock signal generation module, a synchronization signal generation module, and signal receiving modules; the clock signal generation module is configured to generate a first clock signal; the synchronization signal generation module is configured to generate a synchronization signal on the basis of the first clock signal and transmit the synchronization signal to the clock signal generation module; the clock signal generation module generates second clock signals on the basis of the synchronization signal and transmits the second clock signals to the signal receiving modules; the synchronization signal generation module transmits the synchronization signal to the signal receiving modules.
The present invention relates to a metastable state detection device and method, and an ADC circuit. The metastable state detection device comprises: a delay unit used for receiving a synchronization signal and delaying the synchronization signal according to a preset stepping delay value; a first flip-flop unit which comprises a first clock input end, a first data input end, and a first data output end, the first clock input end being used for receiving a clock signal, and the first data input end being connected to the delay unit; a second flip-flop unit which comprises a second clock input end, a second data input end, and a second data output end, the second clock input end being separately connected to the delay unit and the first data input end, and the second data input end being connected to the first clock input end; and a processing module which is connected to the second data output end and used for receiving a target clock signal and detecting the metastable state of the first flip-flop unit according to the target clock signal. The structure of the detection device is simplified, and the cost is low.
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
59.
ADC-SAMPLED DATA IDENTIFICATION METHOD AND SYSTEM, INTEGRATED CIRCUIT, AND DECODING DEVICE
The invention provides an ADC-sampled data identification method and system, an integrated circuit, and a decoding device. The ADC-sampled data identification method comprises: an ADC integrated circuit converting sampled data from n time interleaved ADC chips into serial data, generating a preamble sequence, combining the serial data and the preamble sequence to acquire new serial data, sending the new serial data to a decoding device, generating a clock signal matching the new serial data, and sending the clock signal to the decoding device; and the decoding device receiving the new serial data and the clock signal sent by the ADC integrated circuit, acquiring, according to an agreement with the ADC integrated circuit, a combining preamble sequence, and identifying a start position of ADC-sampled data according to the new serial data, the clock signal, and the combining preamble sequence. Without changing working modes of time interleaved ADC chips, the invention determines a start position of sampled data and a synchronization state thereof.
SYNCHRONOUS-MACHINE-BASED SYNCHRONIZATION SYSTEM, SYNCHRONIZATION METHOD AND CALIBRATION METHOD FOR REALIZING SYNCHRONOUS OUTPUT OF MULTIPLE SIGNAL SOURCES
Provided are a synchronous-machine-based synchronization system, a synchronization method and a calibration method for realizing the synchronous output of multiple signal sources from multiple channels. The synchronization system comprises a synchronous machine and multiple signal source devices; the synchronous machine is correspondingly connected to the multiple signal source devices via multiple communication interfaces; and the synchronous machine respectively performs power division on input calibration signals and sampling clock signals to provide each signal source device with the same-source calibration signal and the same-source sampling clock signal, such that the multiple signal source devices can output signals synchronously. The synchronization system can support the synchronous output from up to eight signal source devices by means of one synchronous machine, that is, the synchronous output from 64 channels. If the interface design of one synchronous machine is expanded, one synchronous machine can also support the synchronous output from more signal source devices. Moreover, after the construction of the synchronization system is completed, there is no need to repeatedly disconnect a wiring, and a user can repeatedly perform power-on configuration. The synchronization system can also start a synchronous machine calibration mode according to changes in the configuration parameters of the user.
The present application discloses a synchronous machine cascade-based multi-channel synchronous output apparatus and method. The synchronous machine cascade-based multi-channel synchronous output apparatus comprises: a control module configured to generate waveform signals; a synchronization module connected to the control module, comprising at least two cascaded synchronous machines, and configured to synchronously transmit the waveform signals; and an output module connected to the synchronization module, comprising at least two signal source devices, and configured to synchronously output the waveform signals.
brevets
