Disclosed are embodiments of structure including: a chip with an embedded magnetic random access memory (eMRAM) or other on-chip component susceptible to magnetic field-induced performance degradation; and magnetic shield(s) for protecting the chip. In some embodiments, a magnetic shield includes abutting magnetic layers having different magnetic properties. In other embodiments, a magnetic shield includes abutting magnetic layers (of the same or different magnetic materials) having offset patterns of openings (e.g., through-holes or mesh). In any case, the chip can be mounted on a board and contained in a package. Such magnetic shields can be located on the package (opposite the board) and/or on the board (opposite the chip) depending upon the expected location of a potentially adverse magnetic field.
Structures including an access transistor and a resistive memory element, and methods of forming such structures. The structure comprises an access transistor including a semiconductor layer, a first source/drain region, a second source/drain region, a gate dielectric layer on the semiconductor layer, and a gate electrode overlapped with the gate dielectric layer. The gate dielectric layer has a first portion with a first thickness adjacent to the first source/drain region and a second portion with a second thickness adjacent to the second source/drain region, and the first thickness is greater than the second thickness. The structure further comprises a resistive memory element that is coupled to the first source/drain region of the access transistor.
Structures for an electro-absorption modulator and methods of forming a structure for an electro-absorption modulator. The structure comprises a first metal layer and a second metal layer adjacent to the multiple-layer structure, a waveguide core, and a multiple-layer structure on a portion of the waveguide core. The multiple-layer structure comprises a first plurality of layers and a second plurality of layers that alternate with the first plurality of layers. The first plurality of layers comprise a first material, and the second plurality of layers comprise a second material. The multiple-layer structure is positioned in a lateral direction between the first metal layer and the second metal layer.
G02F 1/015 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments à semi-conducteurs ayant des barrières de potentiel, p. ex. une jonction PN ou PIN
4.
IN-MEMORY COMPUTING CIRCUIT FOR ACCUMLATION FUNCTIONS AND CONTENT ADDRESSABLE MEMORY (CAM) INCLUDING THE IN-MEMORY COMPUTING CIRCUIT
An in-memory computing circuit structure can include an array of bit cells. Each bit cell includes: a first transistor and a first variable resistor series-connected between end nodes; and a second transistor and a second variable resistor series-connected between the end nodes. Within the columns, bit cells are series-connected in bit cell stacks, sense nodes are on the bit cell stacks, and analog-to-digital converters (ADCs) are connected to the sense nodes. Concurrent read operations are performed to sum resistances of selected variable resistors in the bit cells of the columns, respectively. The resulting currents on the sense nodes are provided as analog input signals to the ADCs. Each ADC for a column outputs a digital output signal indicating how close bit values stored in bit cells of the column are to matching input data signals applied to the rows. A content addressable memory (CAM) can include such a structure.
G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristiques, c.-à-d. mémoires associatives ou mémoires adressables par leur contenu utilisant des éléments semi-conducteurs
G11C 7/16 - Emmagasinage de signaux analogiques dans des mémoires numériques utilisant une disposition comprenant des convertisseurs analogiques/numériques [A/N], des mémoires numériques et des convertisseurs numériques/analogiques [N/A]
The present disclosure relates to semiconductor structures and, more particularly, to low leakage decoupling capacitor structures and methods of manufacture. The structure includes: a first gate structure comprising a gate dielectric region with a first thickness; and a second gate structure adjacent to the first gate structure, the second gate structure comprising a gate dielectric region with a second thickness different from the gate dielectric region with the first thickness.
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
6.
THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH TOP CHIP INCLUDING SCHOTTKY DIODE BODY CONTACT
Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions, a body region on a channel region between the source and drain regions, and a gate structure adjacent to and between the channel region and the dielectric material layers. An insulator layer is on the transistor opposite the dielectric material layers and includes an opening extending to the body region. Optionally, a semiconductor layer is at the bottom of the opening. A contact extends into the opening to the body region (or to the semiconductor layer thereon, if applicable).
Structures for a photonic component and methods of forming a structure for a photonic component. The photonic structure comprises a semiconductor substrate, a first waveguide core including a first plurality of segments, and a second waveguide core including a second plurality of segments. The second plurality of segments are positioned between the first plurality of segments and the substrate.
A structure includes at least one single-photon avalanche diode (SPAD), at least one dome-shaped lens over each SPAD, and a metal guard ring surrounding each SPAD. A front-side illuminated SPAD photodetector and a method of forming the structure is also provided. The dome-shaped lens(es) with the metal guard ring improve SPAD efficiency in terms of photo detection probability (PDP) and light absorption with minimal increase in area.
H10F 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément couvert par le groupe , p. ex. détecteurs de rayonnement comportant une matrice de photodiodes
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
9.
HIGH-ELECTRON-MOBILITY TRANSISTORS WITH FIELD PLATE
The present disclosure relates to semiconductor structures and, more particularly, to high-electron-mobility transistors with field plates and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a passivation layer adjacent to the gate structure and above the semiconductor substrate; an insulator material over the passivation layer; and a field plate comprising a first portion contacting the passivation layer and a second portion being separated from the passivation layer by the insulator material.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/824 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe III-V, p. ex. des hétérojonctions GaN/AlGaN
10.
STRUCTURE WITH EMITTER CONTACT WIDER THAN EMITTER TERMINAL AND RELATED METHOD
The disclosure provides a structure with an emitter contact wider than an emitter terminal, and related methods. A structure of the disclosure includes an emitter contact within an inter-level dielectric (ILD) layer and on an emitter terminal of a bipolar transistor, wherein a horizontal width of the emitter contact is greater than a horizontal width of the emitter terminal thereunder.
Structures for a phase shifter and methods of forming such structures. The structure comprises a first layer comprising a first electro-optic material, a second layer comprising a second electro-optic material, and a third layer between the first layer and the second layer. The third layer comprises a dielectric material that is an electrical insulator. A waveguide core is positioned on a portion of the first layer.
G02F 1/21 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence
G02F 1/225 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence dans une structure de guide d'ondes optique
12.
BIT CELL, IN-MEMORY COMPUTING CIRCUIT FOR MAJORITY FUNCTIONS, AND IN-MEMORY COMPUTING METHOD
A bit cell (BC) includes: a variable resistor and a first transistor connected in series between two end nodes; and a second transistor also connected between the two end nodes. Gates of the first and second transistors are connected to first and second word lines (WLs), respectively, for a row. A circuit includes an array of BCs. In each column, BCs are connected in a stack between a sense amplifier (SA) and footer device (FD). During a read operation, FDs connect the stacks to ground. Additionally, first and second WL voltages on first and second WLs for each row are such that, for any selected row, first transistors of BCs are on and second transistors are off and, for any unselected row, first transistors of BCs are off and second transistors are on. SAs compare sense currents from the stacks to a mid-level reference current to concurrently compute majority functions.
A structure includes: a first latch, which is powered on during a normal operating mode and powered off during a data retention mode; a second latch, which is continuously powered on regardless of the mode; and a switch (e.g., a transmission gate) connected between the two latches. The first latch includes a data retention structure (including a combination of feedforward and feedback paths) configured to avoid data loss when a clock signal that controls flip-flop operation is static for some extended period of time. The second latch includes a keeper loop configured to avoid data loss when the first voltage domain is powered off during the data retention mode. The first latch is controlled, in part, by a single-phase clock signal. The second latch is controlled, in part, by either a dual-phase clock signal or combination of a single-phase clock signal and an intermediate signal from the first latch.
Structures for a photonic chip that include a waveguide core and methods of forming such structures. The structure comprises a waveguide core including a slot and a dielectric layer inside the slot. The waveguide core comprises a material having a first refractive index, and the dielectric layer comprises a dielectric material having a second refractive index that is less than the first refractive index.
G02B 6/122 - Éléments optiques de base, p. ex. voies de guidage de la lumière
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/125 - Courbures, branchements ou intersections
G02B 6/13 - Circuits optiques intégrés caractérisés par le procédé de fabrication
15.
ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE INCLUDING A TRIGGER CIRCUIT DISCONNECT SWITCH AND METHODS
Disclosed is an electrostatic discharge (ESD) protection structure for a circuit component connected to a first pad by an interconnect. The structure includes: a trigger circuit; a trigger circuit disconnect switch connected between the interconnect and trigger circuit; and a discharge circuit connected to a trigger voltage output node of the trigger circuit and to the interconnect. The switch enables the interconnect to be disconnected from the trigger circuit during testing of the circuit component (e.g., during wafer level testing to assess gate integrity) and to otherwise be continuously connected to the trigger circuit to facilitate ESD protection. The switch can be a depletion mode high electron mobility transistor (HEMT) with a gate connected to a second pad, which is connected to receive a negative voltage during testing and which is otherwise left floating. Also disclosed are a package chip including the ESD protection structure and associated methods.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
16.
SINGLE PHOTON AVALANCHE DIODE WITH SHARED CONDUCTIVE LINE
A single-photon avalanche diode (SPAD) device includes a first deep trench isolation (DTI) structure on a first side of the SPAD device, a first vertical doped region over a side of the first DTI structure, a second DTI structure on a second side of the SPAD device, a second vertical doped region over a side of the second DTI structure, a deep well coupled between the first vertical doped region and the second vertical doped region, and a shallow trench structure over the second DTI structure, the shallow trench structure comprising insulating sidewalls and a first conductive line between the insulating sidewalls, wherein the first conductive line is coupled to the second vertical doped region.
H10F 77/00 - Détails de structure des dispositifs couverts par la présente sous-classe
H10F 30/221 - Dispositifs individuels à semi-conducteurs sensibles au rayonnement dans lesquels le rayonnement commande le flux de courant à travers les dispositifs, p. ex. photodétecteurs les dispositifs ayant des barrières de potentiel, p. ex. phototransistors les dispositifs étant sensibles au rayonnement infrarouge, visible ou ultraviolet les dispositifs ayant une seule barrière de potentiel, p. ex. photodiodes la barrière de potentiel étant une homojunction PN
H10F 30/225 - Dispositifs individuels à semi-conducteurs sensibles au rayonnement dans lesquels le rayonnement commande le flux de courant à travers les dispositifs, p. ex. photodétecteurs les dispositifs ayant des barrières de potentiel, p. ex. phototransistors les dispositifs étant sensibles au rayonnement infrarouge, visible ou ultraviolet les dispositifs ayant une seule barrière de potentiel, p. ex. photodiodes la barrière de potentiel fonctionnant en régime d'avalanche, p. ex. photodiodes à avalanche
H10F 71/10 - Fabrication ou traitement des dispositifs couverts par la présente sous-classe les dispositifs comprenant des matériaux semi-conducteurs amorphes
17.
EXTERNAL PAD ISOLATION POWER SWITCH FOR RRAM SECURITY
A pad isolation switch for a resistive random-access memory (RRAM) device. The switch includes: a first pair of transistors arranged in series between an external pad node and an internal node, the first pair of transistors coupled together with a connector node; a second pair of transistors arranged in series between a supply voltage and the connector node; a first high voltage selection circuit having a pair of inputs coupled to the external pad node and VDDW; and a first level shifter having an output coupled to a gate of the first transistor and an input coupled to an output of the first high voltage selection circuit.
A charge pump structure and integrated circuit device. The charge pump structure includes a first stage charge pump unit implemented with low voltage devices that raises an input voltage using a system clock signal; and a plurality of second stage charge pump units, each implemented with low voltage devices that raise an output voltage of a prior charge pump unit using one of a series of boosted clock signals.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
The present disclosure relates to a structure which includes at least one gate structure over semiconductor material, the at least one gate structure comprising an active layer, a gate metal extending from the active layer and a sidewall spacer on sidewalls of the gate metal; and a field plate aligned with the at least one gate structure and isolated from the gate metal by the sidewall spacer.
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
20.
CIRCUIT STRUCTURE AND METHOD WITH A RESISTOR FOR REDUCING VOLTAGE AT CONTROL NODE FOR DEVICE
Embodiments of the disclosure provide a circuit structure and method with a resistor for reducing a discharged pad voltage. A structure of the disclosure includes a resistor having a first end connected to a pad and a second end opposite the first end. A trigger circuit is connected between the pad and ground. A discharge circuit is connected between the second end of the resistor and ground. The discharge circuit is connected to an output node of the trigger circuit.
G05F 1/63 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée est indifféremment du type alternatif ou continu utilisant des impédances variables en série avec la charge comme dispositifs de réglage final
G05F 1/652 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée est indifféremment du type alternatif ou continu utilisant des impédances variables en parallèle avec la charge comme dispositifs de réglage final
21.
OPTO-ELECTRONIC CIRCUITS FOR OPTICAL POWER LIMITING
A structure includes: a photonic integrated circuit (PIC) with power detection and reduction photonic elements coupled to a waveguide near input and output ports, respectively; and an electronic integrated circuit (EIC) between the power detection and reduction photonic elements to reduce the power level of the optical signal near the output port when an over-power condition is detected. In some embodiments, the PIC includes first and second PIN photodiodes coupled to a waveguide near input and output ports, respectively. The first PIN photodiode is reverse biased, generating a sense current (Isen). The EIC receives Isen, detects when Isen is greater than a reference current (Iref) indicating detection of the over-power condition and, in response to the over-power condition, applies a bias voltage to forward bias the second PIN photodiode. Such forward biasing injects current into the waveguide near the output port and reduces the power level of the optical signal.
G02B 6/122 - Éléments optiques de base, p. ex. voies de guidage de la lumière
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a first transistor having an intrinsic base, an extrinsic base and an emitter; and a second transistor having an intrinsic base, an extrinsic base and an emitter. The extrinsic base of the first transistor and the extrinsic base of the second transistor have a common extrinsic base layer with a first dopant type for the first transistor and a second dopant type for the second transistor.
A gain cell memory device includes a semiconductor device layer of a silicon on insulator (SOI) substrate comprising an active region, a storage transistor over the active region of the semiconductor device layer, an isolation structure between a gate electrode of the storage transistor and a source/drain region adjacent to the storage transistor, the isolation structure extending through the active region such that a first portion of the active region is isolated from a second portion of the active region, and a capacitor coupled to the storage transistor. A bottom plate of the capacitor comprises the first portion of the active region, a gate dielectric layer of the storage transistor is an insulator of the capacitor, and a top plate of the capacitor comprises the gate electrode of the storage transistor and a metal structure over the gate electrode.
The embodiments herein relate to semiconductor devices including voids having different depths and methods of forming the same. The semiconductor device includes a device layer, a first metal layer over the device layer, a second metal layer over the first metal layer, a first void, and a second void. The device layer may include an active component. The first void is vertically over the active component and arranged through the first metal layer and the second metal layer. The second void is adjacent to the first void and has an upper portion at a same level as an upper portion of the first void.
A radio frequency (RF) circuit and associated operating method include a mixer configured for independent second order intercept point (IP2) calibration. The mixer includes three ports and multiple dual-gate transistors interconnected therebetween for down-converting an RF input signal to a lower frequency baseband output signal. To optimize performance, front gates of the transistors are biased with a front gate bias voltage (Vfg). To adjust second order non-linearity, back gates of the transistors are biased using a first back gate bias voltage (Vbgp) for half of the transistors of the mixer and a second back gate bias voltage (Vbgm) for a different half of the transistors. The circuit can also include a front gate bias voltage generator for generating Vfg and a back gate bias voltage generator (including a digital-to-analog converter (DAC) with multiple DAC units) for generating Vbgp and Vbgm independent of Vfg.
H03D 7/12 - Transfert de modulation d'une porteuse à une autre, p. ex. changement de fréquence au moyen de dispositifs à semi-conducteurs ayant plus de deux électrodes
The present disclosure generally relates to trench isolation structures for semiconductor devices. More particularly, the present disclosure relates to trench isolation structures with varying depths for electrically isolating integrated circuit (IC) components in semiconductor devices. The present disclosure provides a structure including a substrate, a first trench, a second trench, and a third trench in the substrate. The first, second, and third trenches have respective bottoms located at different depths. The structure may also include first, second, and third dielectric layers and a semiconductor layer in the trenches. The third dielectric layer is of a different material from the second dielectric layer. The second dielectric layer is of a different material from the first dielectric layer.
Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a layer stack including an active region, and a dielectric layer on the active region of the layer stack. The active region has a perimeter. The dielectric layer includes an opening and portions between the opening and the perimeter of the active region. The structure further comprises a source/drain region inside the opening in the dielectric layer.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H01L 21/76 - Réalisation de régions isolantes entre les composants
H10D 62/852 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs étant des matériaux du groupe III-V comprenant trois éléments ou plus, p. ex. AlGaN ou InAsSbP
H10D 64/62 - Électrodes couplées de manière ohmique à un semi-conducteur
28.
SILICON CONTROLLED RECTIFIER (SCR), INTEGRATED CIRCUIT (IC) CHIP INCLUDING SCR, AND METHODS OF FORMING SCR
A silicon controlled rectifier (SCR) includes a first well, a second well, a first well contact formed in the first well, a second well contact formed in the second well, a first junction contact raised compared to the first well contact, and a second junction contact raised compared to the second well contact.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
Structures for a phase shifter and methods of forming such structures. The structure comprises a waveguide core and a metamaterial structure laterally adjacent to the waveguide core. The metamaterial structure includes a first plurality of portions and a second plurality of portions that alternate with the first plurality of portions. The waveguide core comprises an electro-optic material, the first plurality of portions comprise a first material having a first refractive index, and the second plurality of portions comprise a second material having a second refractive index that is less than the first refractive index.
G02F 1/035 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des céramiques ou des cristaux électro-optiques, p. ex. produisant un effet Pockels ou un effet Kerr dans une structure de guide d'ondes optique
30.
BODY CONTACT IN SOI DEVICE AND METHOD FOR FORMING THE SAME
A semiconductor device includes a semiconductor substrate including a buried oxide layer and a semiconductor layer over the buried oxide layer, a gate dielectric over the semiconductor layer, a gate electrode over the gate dielectric, a source region on a first side of the gate electrode, the source region including a first doped layer doped with a first type of impurities and a second doped layer above the first doped layer and doped with a second type of impurities, and a PN junction between the first doped layer and the second doped layer, a drain region on a second side of the gate electrode, a body of the semiconductor layer between the source region and the drain region, and a source silicide layer in the source region, the source silicide layer including an edge portion that contacts the first doped layer.
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/00 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel
H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
31.
VERTICAL HALL DEVICE, SENSING APPARATUS, AND METHODS OF FORMING VERTICAL HALL DEVICE
A vertical Hall device includes a substrate, an epitaxial layer disposed over the substrate, a first terminal including a dopant region and a Deep Trench Isolation (DTI) structure, and a second terminal including a first contact. The dopant region is disposed in the substrate, the DTI structure passes through the epitaxial layer and is coupled to the dopant region, and the first contact is disposed in the epitaxial layer.
G01R 33/07 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques en utilisant des dispositifs galvano-magnétiques des dispositifs à effet Hall
H10N 59/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comportant au moins un élément galvanomagnétique ou à effet Hall couvert par les groupes
32.
SEMICONDUCTOR DEVICE WITH IMPROVED THERMAL CONDUCTIVITY AND METHOD OF FORMING THE SAME
A bonded semiconductor device includes a lower semiconductor device, an upper semiconductor device face bonded to the lower semiconductor device, and a nanopillar structure in an insulation layer of at least one of the lower semiconductor device and the upper semiconductor device, the nanopillar structure comprising a base layer and a plurality of nanopillars that contact the base layer. The nanopillar structure is electrically isolated from conductive structures of the lower semiconductor device and the upper semiconductor device.
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
33.
METHOD AND CIRCUIT FOR BIT READ DURING NON-VOLATILE MEMORY POWER-ON-RESET
Embodiments of the present disclosure provide a memory circuit, including: a non-volatile memory; a one-time-programmable memory; a sense amplifier coupled to the non-volatile memory and the one-time-programmable memory; a digital register coupled to an output of the sense amplifier for storing reference resistance bits; control logic coupled to an output of the digital register; a decoder coupled to an output of the control logic; and a controller for outputting a control signal to the control logic to select a first reference resistance for the sense amplifier from the decoder for a reading of bits from the one-time-programmable memory, and to select a second reference resistance for the sense amplifier from the decoder for a reading of bits from the non-volatile memory.
G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
34.
SEMICONDUCTOR DISLOCATION-BASED PHYSICALLY UNCLONABLE FUNCTION AND METHOD
A cell structure for a physically unclonable function (PUF) includes a field effect transistor (FET) with an active semiconductor region having opposing sides. One side is linear and the other is stepped or curved so the active semiconductor region has a first portion with a first width and a second portion with a greater second width. The FET also includes a gate with first and second gate fingers electrically connected and traversing the first and second portions, respectively. Optionally, the cell structure includes semiconductor fill material region(s) adjacent to at least one end and/or at least one side. Optionally, the cell structure includes a pair of mirror-image FETs. Various dimensions within the cell structure are predetermined to achieve an approximately random likelihood that the off-state drain current (Idoff) will be at any particular Idoff level within a relatively large range of possible Idoff levels, due to random occurrence of dislocation(s).
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
35.
SEMICONDUCTOR STRUCTURES INCLUDING A CONDUCTOR LAYER AND MULTIPLE ISOLATION LAYERS
Semiconductor structures that include a conductor layer and multiple dielectric layers, as well as methods of forming such semiconductor structures. The structure comprises a first dielectric layer, a second dielectric layer, and a conductor layer including a first section and a second section between the first dielectric layer and the second dielectric layer. The structure further comprises a semiconductor layer including a first section that overlaps with the first section of the conductor layer and a second section that overlaps with the second section of the conductor layer, and a trench isolation region including a first portion laterally between the first section of the conductor layer and the second section of the conductor layer.
H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
Photonic structures including ring resonators and methods of forming such structures. The photonic structure comprises first, second, and third waveguide cores, and a first ring resonator arranged between a first portion of the first waveguide core and a portion of the second waveguide core. The photonic structure further comprises a second ring resonator arranged between a second portion of the first waveguide core and a portion of the third waveguide core.
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
37.
ELECTRICAL FUSE HAVING FUSE LINK ALONG SIDEWALL(S) OF INACTIVE GATE STRUCTURE
An electronic fuse includes an inactive gate structure over a substrate, and a fuse link along at least one sidewall of the inactive gate structure. A first terminal is at a first end of the fuse link, and a second terminal is at a second of the fuse link. The fuse link takes the form of a conductive metal spacer along at least one sidewall of the inactive gate structure and can be formed without a silicide process. Although the e-fuse can be used with any semiconductor device, it is advantageous for use with, for example, III-IV semiconductor devices. The method of making the e-fuse does not require any additional masks and provides a fuse link having a sub-photolithographic width dimension.
An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).
The present disclosure relates to layout recommendations and, more particularly, to dynamic layout optimization systems, processes and methods of use. The method includes: determining mismatches between design notes and layout data of an integrated circuit; generating suggestions to correct the mismatches between the design notes and the layout data of the integrated circuit; providing an output of the mismatches between the design notes and the layout data of the integrated circuit including the suggestions; and saving the mismatches and suggestions to a log file.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G06F 119/02 - Analyse de fiabilité ou optimisation de fiabilitéAnalyse de défaillance, p. ex. performance dans le pire scénario, analyse du mode de défaillance et de ses effets [FMEA]
40.
SEMICONDUCTOR RING SURROUNDING VERTICAL DIODE AND RELATED METHODS
The disclosure provides a semiconductor ring surrounding a vertical diode, and related methods. Structures according to the disclosure include a vertical diode over a substrate. A semiconductor ring is over the substrate and horizontally surrounds the vertical diode. A spacer material is horizontally adjacent the semiconductor ring and separates the semiconductor ring from the vertical diode.
Disclosed are a word line (WL) driver and a memory structure including a WL driver system with multiple WL drivers. The WL driver includes a write WL voltage (VWL) control node, a read VWL control node, and an output node. First and second transistors are connected in series between the write VWL control node and the output node. Third and fourth transistors are connected in parallel between the read VWL control node and the output node. The first, second, and third transistors are P-type field effect transistors (PFETs) and the fourth transistor is an N-type field effect transistor (NFET). Additional NFETs are connected between the output node and ground and, optionally, between the gate and source of the second transistor. All transistors are the same gate dielectric type.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
42.
BIPOLAR TRANSISTOR STRUCTURES WITH SEMICONDUCTOR BASE FILM WITHIN ISOLATION LAYER, AND RELATED METHODS
The disclosure provides bipolar transistor structures with a semiconductor base film within an opening of an isolation layer, and related methods. A structure according to the disclosure includes a semiconductor base film on a collector terminal. The semiconductor base film includes a first portion within an opening of an isolation layer. The first portion includes an intrinsic semiconductor. A second portion of the semiconductor base film is on the first portion. The second portion includes a sidewall adjacent the isolation layer and a lower surface on the isolation layer. A semiconductor film is on an upper surface of the first portion of the isolation layer and adjacent a sidewall of the second portion of the isolation layer. An emitter is on the semiconductor film.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
43.
LATERALLY DIFFUSED FIELD EFFECT TRANSISTOR WITH CHANNEL IN FIN REGION AND DRAIN EXTENSION REGION IN PLANAR REGION
A laterally diffused field effect transistor (LDFET) and a related method are disclosed. The LDFET includes a substrate having a fin region and a planar region adjacent to the fin region. The LDFET also includes a source region in the fin region, a drain region in the planar region, a channel gate over the fin region and the planar region, and a drain extension region in the planar region between the source region and the drain region. The use of a substrate with a fin region for the source region and the channel of the channel gate and a planar region for the drain region and the drain extension region provides many of the benefits of both types of substrates for the LDFET.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/51 - Matériaux isolants associés à ces électrodes
The present disclosure relates to semiconductor structures and, more particularly, to a defect free bipolar transistor and methods of manufacture. The structure includes: a collector region; an emitter region over the base region; and an extrinsic base region adjacent to the emitter region, the extrinsic base region comprising a raised wing extension at a perimeter thereof.
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/83 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé
Structures for a photonic chip that include a waveguide and methods of forming such structures. The structure comprises a first waveguide core, a second waveguide core adjacent to the first waveguide core, and a first layer between the first waveguide core and the second waveguide core. The structure further comprises a second layer adjacent to the first waveguide core, and a third layer adjacent to the second waveguide core. The first layer comprises an electro-optic material, and the second and third layers comprise a metal.
G02F 1/035 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des céramiques ou des cristaux électro-optiques, p. ex. produisant un effet Pockels ou un effet Kerr dans une structure de guide d'ondes optique
The present disclosure relates to semiconductor structure and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region over the sub-collector region, the collector region having a first semiconductor material comprising polysilicon material and single crystalline semiconductor material which is over the sub-collector region, and a second semiconductor material on the single crystalline semiconductor material; diffusion regions in the first semiconductor material; an emitter region over the collector region; and a base region adjacent to the emitter region.
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
Structures including a phase shifter and methods of forming such structures. The structure comprises a dielectric layer, a heater on the dielectric layer, a back-end-of-line stack on the dielectric layer and the heater, a substrate, and a second back-end-of-line stack on the substrate. The second back-end-of-line stack adjoins the first back-end-of-line stack along a bonding interface. The structure further comprises a waveguide core on the dielectric layer. The waveguide core includes a section that overlaps with the heater.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
The present disclosure relates to semiconductor structures and, more particularly, to capacitor structures and methods of manufacture. The structure includes: a gate structure over an active region of a semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; a first contact structure shorting the drain region to the source region by; and a second contact structure connecting to the gate structure over the active region.
The present disclosure relates to semiconductor structures and, more particularly, to body contacted transistors and methods of manufacture. The structure includes: an active gate structure on a semiconductor substrate; at least one body contact extending through the active gate structure and connecting to a body region that contains a channel of the active gate which is under the active gate structure; and insulator material isolating the at least one body contact from the active gate structure.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/51 - Matériaux isolants associés à ces électrodes
50.
ELECTRO-OPTIC PHASE SHIFTERS INCLUDING A SLOTTED WAVEGUIDE STRUCTURE
Structures for a phase shifter and methods of forming such structures. The structure comprises a first waveguide core, a second waveguide core laterally adjacent to the first waveguide core, and a third waveguide core laterally adjacent to the second waveguide core. The second waveguide core and the first waveguide core are separated by a first slot, and the third waveguide core and the second waveguide core are separated by a second slot. The structure further comprises a layer that overlaps with respective portions of the first waveguide core, the second waveguide core, and the third waveguide core. The layer comprises a first electro-optic material.
G02F 1/035 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des céramiques ou des cristaux électro-optiques, p. ex. produisant un effet Pockels ou un effet Kerr dans une structure de guide d'ondes optique
G02F 1/025 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments à semi-conducteurs ayant des barrières de potentiel, p. ex. une jonction PN ou PIN dans une structure de guide d'ondes optique
51.
RESISTIVE RANDOM-ACCESS MEMORY STRUCTURE AND METHOD
Disclosed are a memory structure and an operating method. The structure includes: bit cells in columns and rows with all bit cells; source lines (SLs) and bit lines (BLs) for the columns; word lines (WL) for the rows; and peripheral circuitry to facilitate memory operations in a bit cell located in a selected column and a selected row. The peripheral circuitry includes a BL biasing circuit that applies an appropriate BL voltage to the BL for a selected column to achieve a desired memory operation and applies a positive unselected BL voltage to BLs for all unselected columns at least during write operations. The peripheral circuitry also includes a SL biasing circuit that applies an appropriate SL voltage to the SL for the selected column to achieve the desired memory operation and applies a positive unselected SL voltage to the SLs for all unselected columns at least during write operations.
Structures for a photonics chip that include a photonic component and methods of forming such structures. The structure may comprise a photodetector on a substrate and a waveguide core. The photodetector includes a light-absorbing layer having a longitudinal axis, a first sidewall, and a second sidewall adjoined to the first sidewall at an interior angle. The first sidewall is slanted relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis. The waveguide core includes a tapered section adjacent to the first sidewall and the second sidewall of the light-absorbing layer.
Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide core, a heater, a first plurality of segments positioned between a portion of the waveguide core and the heater, and a second plurality of segments positioned between the portion of the waveguide core and the heater. The first plurality of segments comprise a first material, the second plurality of segments comprise a second material, and the second plurality of segments alternate with the first plurality of segments.
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
G02B 6/122 - Éléments optiques de base, p. ex. voies de guidage de la lumière
G02F 1/21 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence
G02F 1/225 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence dans une structure de guide d'ondes optique
H05B 3/14 - Éléments chauffants caractérisés par la composition ou la nature des matériaux ou par la disposition du conducteur caractérisés par la composition ou la nature du matériau conducteur le matériau étant non métallique
Disclosed is a charge/discharge circuit structure for an output node (e.g., of a device, such as a charge pump in a memory structure, such as in a resistive random access memory (RRAM) structure). The circuit structure includes, among other components: a positive supply voltage node at a positive supply voltage level; a first input node connected to an output node of a device (e.g., a charge pump) to receive a variable output voltage (Vout); and an N-type field effect transistor (NFET) and a first P-type field effect transistor (PFET) connected in series between the positive supply voltage node and the first input node. The gate of the NFET can be connected to the drain region of the first PFET (and thereby also the first input node). Thus, the NFET functions as a source follower NFET switch controlled by feedback from the drain region of the first PFET.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
55.
RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND MULT-STEP MEMORY OPRERATION WITH ALL WORD LINES ACTIVATED
Disclosed is a memory structure including: an array of resistive random access memory cells (bit cells) in columns and rows; word lines (WLs) connected to the rows; and source line (SL)-bit line (BL) pairs connected to the columns. The structure is configured to perform a multi-step operation (e.g., a multi-step forming operation) during which: all WLs receive a low WL voltage; all BLs and SLs (except for the SL connected to a selected column) are discharged to ground; and the SL connected to the selected column receives a SL voltage (VSL) that starts high and decreases with each step. The operation concurrently and progressively changes the resistance states of resistors in bit cells of the selected column from an initial resistance state to a lower operational resistance state. Throughout the operation, BL current (IBL) on the BL of the selected column is monitored and, when a threshold IBL is reached, the next step is initiated.
Structures for a micro-ring resonator filter and methods of forming a structure for a micro-ring resonator filter. The structure comprises a bus-ring coupling section including a first Mach-Zehnder interferometer, and a micro-ring resonator section including a ring resonator coupled to the first Mach-Zehnder interferometer. The ring resonator includes a second Mach-Zehnder interferometer.
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/13 - Circuits optiques intégrés caractérisés par le procédé de fabrication
57.
POWER AMPLIFIER WITH VARIABLE POWER SUPPLY VOLTAGE
Disclosed is a circuit structure including a power amplifier and a temperature-dependent power supply system for the power amplifier. The power supply system includes a first voltage generator, which generates a reference voltage that is variable and depends on the operating temperature. In some embodiments, this first voltage generator employs a combination of proportional-to-absolute-temperature and constant-to-absolute temperature current sources to achieve the desired relationship between the operating temperature and the reference voltage. In other embodiments, a look-up table is employed to achieve the desired relationship between the operating temperature and the reference voltage. In any case, the power supply system also includes a second voltage generator, which is connected to receive the reference voltage and which generates (and outputs to the power amplifier) a power supply voltage that is dependent on the reference voltage.
H03F 3/213 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
An avalanche photodiode device includes a first doped layer having a first doping type, a second doped layer having a second doping type, a third doped layer having the first doping type, a first PN junction between the first doped layer and the second doped layer, a second PN junction between the second doped layer and the third doped layer, a first vertical conductive structure coupled to the first doped layer and the third doped layer, and a second vertical conductive structure coupled to the second doped layer.
H01L 31/107 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel fonctionnant en régime d'avalanche, p.ex. photodiode à avalanche
H01L 31/072 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails adaptés comme dispositifs de conversion photovoltaïque [PV] caractérisés par au moins une barrière de potentiel ou une barrière de surface les barrières de potentiel étant uniquement du type PN à hétérojonction
59.
LDMOS TRANSISTOR WITH SPLIT GATE FIELD PLATE TAPERED TOWARD DRAIN REGION AND RELATED METHOD
An LDMOS transistor includes a semiconductor substrate, a channel gate over the semiconductor substrate, a source region to a first side of the channel gate, and a drain region to a second, opposite side of the channel gate. The LDMOS transistor also includes a split gate field plate over the semiconductor substrate where the split gate field plate has a tapered surface that is thinner toward the drain region. In certain embodiments, the split gate field plate has no lateral overlap with the channel gate and an L-shaped gate dielectric separates the split gate field plate from the channel gate and the semiconductor substrate. The split gate field plate can be shorted to the source region to reduce gate-to-drain region (Miller) parasitic capacitance. The LDMOS transistor split gate field plate can be formed with no additional masks.
The present disclosure relates to semiconductor structures and, more particularly, to multi-finger semiconductor devices with dummy gate structures and methods of manufacture. The structure includes: a plurality of active gate structures over a semiconductor substrate; a shared diffusion region in the semiconductor substrate between adjacent active gate structures of the plurality of gate structures; and a gate structure shorted to the shared diffusion region.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A single photon avalanche diode (SPAD) device includes a semiconductor substrate, a central source/drain, an outer source/drain, and a shallow trench isolation (STI) structure between the central source/drain and the outer source/drain at an incident surface of the substrate, wherein a width of the STI structure is at least one third of a width of the central source/drain. The SPAD device may have superior dark current rate compared to conventional devices.
H01L 31/107 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel fonctionnant en régime d'avalanche, p.ex. photodiode à avalanche
H01L 31/0352 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails caractérisés par leurs corps semi-conducteurs caractérisés par leur forme ou par les formes, les dimensions relatives ou la disposition des régions semi-conductrices
62.
WORD LINE CHARGE PUMP CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
A word line charge pump circuit of a memory device includes a clock driver configured to drive a clock signal using a first voltage and output a buffered clock signal with a swing level corresponding to a level of the first voltage, and a charge pump configured to receive a bit line voltage and generate a word line voltage by boosting the bit line voltage using the buffered clock signal.
The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a field plate and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a field plate extending over the gate structure from the source region to the drain region, the field plate including at least one via structure extending toward the drain region.
Structures for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a device structure that includes a gate and an ohmic contact, and one or more active blocks that are laterally positioned between the gate and the ohmic contact. The one or more active blocks are configured to receive a supply voltage that is different from ground.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
Structures for a photonic chip that include a grating and a light source, as well as methods of forming such structures. The structure comprises a grating that includes segments. The grating comprises a material having a refractive index that is variable in response to a stimulus, such as an applied bias voltage. The structure further comprises a waveguide core that includes a section adjacent to the segments of the grating. The structure may further include a light source adjacent to the grating.
G02F 1/03 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des céramiques ou des cristaux électro-optiques, p. ex. produisant un effet Pockels ou un effet Kerr
G02B 6/132 - Circuits optiques intégrés caractérisés par le procédé de fabrication par le dépôt de couches minces
66.
STRUCTURE FOR POLARIZATION-INDEPENDENT COARSE WAVELENGTH DIVISION DEMULTIPLEXING
Disclosed are embodiments of a structure for polarization-independent coarse wavelength division demultiplexing. The structure includes a polarization splitter-rotator (PSR), which receives a dual polarization mode multi-wavelength optical signal and outputs a single polarization mode multi-wavelength optical signal. The structure includes a wavelength division demultiplexer (WDD) and a thermo-optic phase-shifter (TOPS), which is coupled to the PSR and either coupled to the input section of the WDD or integrated into the input section of the WDD. The structure includes at least one photodetector and a thermal control system (TCS). The photodetector is coupled to an unused end of a waveguide in either the TOPS or WDD (depending on the embodiment). The TCS monitors output current from the photodetector, and based thereon, sets heating voltage(s) applied to heating element(s) in the TOPS, ensuring that single wavelength optical signals output from output sections of the WDD are at desired wavelengths and power levels.
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
H04J 14/02 - Systèmes multiplex à division de longueur d'onde
67.
STRUCTURE WITH PORTIONS HAVING DIFFERENT GERMANIUM CONCENTRATIONS AND RELATED METHODS
The disclosure provides a structure base portions having different germanium concentrations, and related methods. A structure of the disclosure includes a base region including a first portion on a first emitter/collector (E/C) terminal and including germanium (Ge). A Ge concentration in the first portion varies with respect to distance from the first E/C terminal. A second portion is on the first portion and includes Ge. A third portion is between the second portion and a second E/C terminal and includes Ge. A Ge concentration in the third portion varies with respect to distance between the second portion and the second E/C terminal.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/15 - Structures avec une variation de potentiel périodique ou quasi périodique, p.ex. puits quantiques multiples, superréseaux
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
GlobalFoundries Dresden Module One Limited Liability Company & Co. KG (Allemagne)
Inventeur(s)
John, Peter
Herrmann, Grit
Lederer, Ulf
Maschke, Stefan
Wagenbreth, Frank
Werner, Martin
Vargason, Troy
Anne, Gopala Krishna
Balakrishnan, Ramaguru
Alagarsamy Muthukrishnan, Sabha Krishnan
Leucke, Uwe
Abrégé
The present disclosure relates to energy consumption of tools and, more particularly, to modeling energy consumption in semiconductor tools. The method includes: obtain, by a computing device, a state history of a tool over a predetermined period of time; model, by the computing device, the state history of the tool using machine learning to provide a predicted energy usage of the tool; compare, by the computing device, predicted energy usage obtained from the machine learning model to an actual energy usage of the tool; and determine, by the computing device, a deviation between the actual energy usage and the predicted energy usage of the tool to maintain energy consumption efficiency of the tool.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
69.
THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH TOP CHIP INCLUDING LOCAL INTERCONNECT FOR BODY-SOURCE COUPLING
Disclosed structures and methods include a chip including a transistor between an insulator layer and dielectric material layers. The transistor includes: within an active device region, source and drain regions and stacked body and channel regions laterally between the source and drain regions; and a gate structure on a surface of the active device region adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: within an active device region, a source region laterally between drain and stacked body and channel regions laterally between the source region and each drain region; and gate structures on a surface of the active device region adjacent to and between the channel regions, respectively, and the dielectric material layers. In any case, a local interconnect adjacent to another surface of the active device region opposite the gate structure(s) electrically couples the body region to the source region(s).
The present disclosure relates to a memory sense amplifier and, more particularly, to a non-volatile memory sense amplifier and methods of use. The structure includes: a first stage amplifier comprising a plurality of non-volatile memory cells connecting to a bit line; a second stage amplifier connecting to the first stage amplifier and a common reference node; and a reference unity gain amplifier connecting to the second stage amplifier through the common reference node and receiving a voltage bias from the first stage amplifier, wherein the reference unity gain amplifier is connected to provide a reference voltage to the second stage amplifier.
G11C 7/12 - Circuits de commande de lignes de bits, p. ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
G11C 7/14 - Gestion de cellules facticesGénérateurs de tension de référence de lecture
The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a plurality of active devices in a layout, the plurality of active devices comprising semiconductor material with a first dopant type; a protective film; and a fill shape covering the protective film and comprising the semiconductor material with the first dopant type.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/161 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en
Structures for a photonic receiver and methods of forming a photonic receiver. The structure comprises a photodetector including a pad with a side edge and a semiconductor layer configured to absorb light. The structure further comprises a plurality of waveguide core segments. Each waveguide core segment extends outwardly from a respective portion of the side edge of the pad.
The disclosure provides structures and related methods to provide a source/drain (S/D) terminal within a subcollector. A structure according to the disclosure includes a field effect transistor (FET) structure having a source/drain (S/D) terminal within a semiconductor layer, and a gate structure on the semiconductor layer. A bipolar transistor (BT) structure is on the FET structure and includes a subcollector within the semiconductor layer, and a collector-base-emitter stack on the subcollector and above the semiconductor layer.
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 84/40 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou avec au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET avec des transistors BJT
A contactless current sensing circuit for sensing current in a conductive wire on a dielectric substrate of a printed circuit board (PCB) includes a plurality of magnetic tunneling junction (MTJ) structures including first and second MTJ structures on a first side of the conductive wire, and third and fourth MTJ structures on a second side of the conductive wire opposite to the first side. The MTJ structures are located within the H-field induced by a current flowing through the conductive wire.
G01R 33/09 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques en utilisant des dispositifs galvano-magnétiques des dispositifs magnéto-résistifs
75.
TRANSISTORS HAVING VARYING THICKNESSES OF GATE DIELECTRIC LAYERS
The embodiments herein relate to transistors having varying thicknesses of gate dielectric layers. The transistor includes a gate dielectric layer between a gate electrode and a substrate. The gate dielectric layer includes a first dielectric portion on the substrate, a second dielectric portion at least partially in the substrate, and a third dielectric portion partially in the substrate between the first and second dielectric portions. The second dielectric portion is thicker than the first dielectric portion. The third dielectric portion is thicker than the first dielectric portion and thinner than the second dielectric portion.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
The disclosed subject matter relates generally to structures in semiconductor devices and integrated circuit (IC) chips. More particularly, the present disclosure relates to a metal-dielectric-metal capacitor having electrically inactive metal layers arranged in an interconnect level that is below another interconnect level containing two sets of metal lines interdigitated with each other.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
The present disclosure relates to semiconductor structures and, more particularly, to resistor trimming structures and methods of use. The structure includes: a set of resistors each of which include an increasing resistance value; and a set of switches each of which are connected to a respective resistor of the set of resistors and each of which comprise a decreasing width dimension for each resistor of increasing resistance value.
H01C 17/22 - Appareils ou procédés spécialement adaptés à la fabrication de résistances adaptés pour ajuster la valeur de la résistance
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
78.
BIPOLAR TRANSISTOR STRUCTURES WITH SEMICONDUCTOR FILM AND RELATED METHODS
The disclosure provides bipolar transistor structures with a semiconductor film, and related methods. A structure of the disclosure includes an intrinsic base on a collector. The collector has a first doping type. A semiconductor film is on the intrinsic base and horizontally surrounds the intrinsic base. The semiconductor film horizontally encapsulates the intrinsic base. An emitter having the first doping type is on a first portion of the semiconductor film. An extrinsic base having a second doping type is on a second portion of the semiconductor film.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
A multi-phase circuit includes a plurality of phases respectively corresponding to a plurality of clock phases. To balance respective output currents from the phases, for each phase: in response to an occurrence of a sampling time of that phase, a measurement signal corresponding to a value at the sampling time of the current for that phase is produced using a sampling circuit and provided to the other phases, other measurement signals from the other phases are received, an indicator signal according to whether the measurement signal is greater than an average of the other measurement signals is produced using a comparator circuit, and the output current of the phase is adjusted according to the indicator signal. The plurality of phases may include three or more phases.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
80.
CHIP INCLUDING SILICON DEVICE AND III-V SEMICONDUCTOR DEVICE ON III-V SEMICONDUCTOR LAYER
Disclosed semiconductor structures include a stack of III-V semiconductor layers and a III-V semiconductor device and a silicon device on the stack. The III-V semiconductor device includes, among other components, a barrier layer above and immediately adjacent to a III-V semiconductor surface at the top of the stack in a first area. The silicon device includes, among other components, a silicon-based layer above and immediately adjacent to the same III-V semiconductor surface at the top of the stack in a second area. Thus, the barrier layer and the silicon-based layer are at the same level above the substrate. Optionally, an isolation well can be within the stack adjacent to the III-V semiconductor surface in the second area (e.g., to electrically isolate the III-V semiconductor device from the silicon device). Also disclosed are methods of forming the semiconductor structures.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/8252 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie III-V
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
H01L 29/205 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV comprenant plusieurs composés dans différentes régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
81.
DUAL-ANTIFUSE DEVICES AND MEMORY STRUCTURES INCLUDING DUAL-ANTIFUSE DEVICES
Disclosed is a dual-antifuse (DAF) device with two electrically isolated antifuses. The DAF device includes a gate structure including a dielectric layer lining a recess in a semiconductor layer between first and second conductive regions and a conductor layer on the dielectric layer. A gate cut isolation structure extends through the conductor layer, dividing the conductor layer into first and second conductor sections. As a result, the device includes a first antifuse (i.e., the first conductor section, the first conductive region, and the dielectric layer therebetween) and a second antifuse (i.e., a second conductor section, the second conductive region, and the dielectric layer therebetween), which is isolated from the first antifuse. Thus, the two antifuses are independently programable. Also disclosed herein are memory structure embodiments, which include DAF devices (either with or without electrically isolated antifuses) integrated into the cells of an array and which are configured for improved reliability.
H10B 20/25 - Dispositifs ROM programmable une seule fois, p. ex. utilisant des jonctions électriquement fusibles
G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
A disclosed D flip-flop includes first and second stages. The first stage includes a first intermediate node. The second stage includes second and third intermediate nodes and a pair of transistors connected in series to the second intermediate node. The first and third intermediate nodes are connected to the gates of different ones of the transistors in the pair in order to provide feedforward and feedback paths for maintaining the voltage level of a signal on the second intermediate node when a clock signal is static and the second intermediate node is floating. Optionally, the second stage can also include a feedback loop (including an inverter and a multiphase clock-controlled tri-state logic device connected in series from and back to the third intermediate node) for maintaining the voltage level of a signal on the third intermediate node when the clock signal is static and the third intermediate node is floating.
Disclosed is a circuit including a transistor with integrated circuitry for protection against damage due to an electrostatic discharge (ESD) event or other drain voltage (Vd) overstress condition. The transistor is an N-type field effect transistor (NFET) and includes a drain region, a source region connected to ground, and a gate connected to a first node. The first node is connected to receive an externally-generated gate bias voltage. A resistor-capacitor (RC)-triggered voltage clamp is connected in parallel with the transistor. Specifically, a resistor is connected between the source region and a second node and a capacitor is connected between the second node and the drain region. A first diode or series-connected first diodes is/are connected between the second node and the first node. Optionally, a resistor-diode (RD)-triggered voltage clamp is also connected in parallel with the transistor and shares the resistor and second node with the RC-triggered voltage clamp.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
84.
SEMICONDUCTOR DEVICES AND METHODS OF FORMING THEREOF
A semiconductor structure including an active region and an isolation region adjacent to the active region and a gate arranged over the active region and the isolation region is provided. A first gate contact and a second gate contact is arranged over the gate. The first gate contact overlaps the active region and the second gate contact overlaps the isolation region. A metal line extends over the first gate contact and the second gate contact.
Disclosed are predecoders and structures including the predecoders. Each predecoder includes, among other components, first and second latches controlled by write and read clock signals, respectively, and a multiplexer-enabled write logic bypass path. During a write, an address signal is latched by the first latch and propagated through logic downstream of the first latch (including through a write logic block) to the second latch (which is transparent). During a read, the write logic bypass path is activated so the address signal bypasses the first latch and the write logic block and is instead propagated only through logic downstream of the write logic block to the second latch (which periodically latches the received signal). In both operations, a predecoded address signal is output but, due to activation of the write logic bypass path during the read, the time between receiving the address signal and outputting the predecoded address signal is reduced.
A multi-domain RC clamp circuit. A circuit is provided that includes a first power domain having a first RC clamp with a first transistor arranged to bypass a first resistor of the first RC clamp; and a second power domain having a second RC clamp with a second transistor arranged to bypass a second resistor of the second RC clamp, wherein the second transistor is controlled by a first input from the first power domain and the first transistor is controlled by a second input from the second power domain.
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a semiconductor substrate; a collector region over the semiconductor substrate; an intrinsic base over the collector region; an electrically insulating heat dissipative material at a junction of the collector region and the intrinsic base; an extrinsic base over the intrinsic base; and an emitter region adjacent to the extrinsic base.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 29/66 - Types de dispositifs semi-conducteurs
Structures for a photonic chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad, a semiconductor layer on the pad, and a metal layer that extends into the pad. The semiconductor layer may be configured to absorb light of a given wavelength.
H01L 31/105 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel étant du type PIN
G02B 6/122 - Éléments optiques de base, p. ex. voies de guidage de la lumière
H01L 31/18 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives
Structures for a photonic phase shifter and methods of forming such structures. The structure comprises a device structure including a source, a drain, a body, a gate over the body, and a well laterally between the source and the drain. The structure further comprises a waveguide core including a portion that overlaps with the well. A dielectric layer is positioned between the well and the portion of the waveguide core.
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
90.
NANOSHEET FIELD-EFFECT TRANSISTORS DEPOPULATED OF NANOSHEET CHANNEL LAYERS
Structures for a nanosheet field-effect transistor and methods of forming a structure for a nanosheet field-effect transistor. The structure comprises a field-effect transistor including a first source/drain region, a second source/drain region, a nanosheet channel layer, a gate conductor layer, a first inner spacer, and a second inner spacer. The nanosheet channel layer extends laterally from the first source/drain region to the second source/drain region. The gate conductor layer includes a section positioned in a space above the nanosheet channel layer. The first inner spacer adjoins the second inner spacer, and the first and second inner spacers are positioned laterally between the section of the gate conductor layer and the first source/drain region.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
The present disclosure relates to a structure including a first curvature compensation circuit which includes a first set of transistors, and a second curvature compensation circuit which includes a second set of transistors. A voltage reference (VREF) signal output from a bandgap voltage reference core with the second curvature compensation circuit is received as an input to the first curvature compensation circuit.
G05F 3/30 - Régulateurs utilisant la différence entre les tensions base-émetteur de deux transistors bipolaires fonctionnant à des densités de courant différentes
92.
STRUCTURE WITH SWITCHABLE VOLTAGE DIVIDER AND RELATED METHOD
Structures and methods with a switchable voltage divider and a related method are disclosed. A structure of the disclosure includes a plurality of voltage nodes each receiving one of a plurality of voltages from the charge pump. A switchable voltage divider couples the plurality of voltage nodes to an output amplifier. The switchable voltage divider includes a common node and a plurality of first stages each coupled to one of the plurality of voltage node. Each first stage includes at least one first resistor, a first PFET, and a second PFET connected in series between a corresponding one of the plurality of voltage nodes and the common node, and a third PFET connected to a junction between the first PFET and the second PFET. A second stage includes multiple second resistors and an NFET connected in series between the common node and ground.
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
The present disclosure relates to semiconductor structures and, more particularly, to diode triggered silicon controlled rectifiers and methods of manufacture. The structure includes: a vertical silicon controlled rectifier (SCR) having a doped semiconductor material region over a semiconductor substrate; and at least one vertical triggering diode electrically connected to the SCR in series, and having a doped semiconductor material region over a doped region in the semiconductor substrate.
H01L 29/74 - Dispositifs du type thyristor, p.ex. avec un fonctionnement par régénération à quatre zones
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
A disclosed structure includes a FET with a gate structure (e.g., a RMG structure) having a scaled effective gate length proximal to a channel region and a large conductor surface distal to the channel region. The gate structure includes a first portion within a lower region of a gate opening proximal to the channel region and a second portion within a wider upper region. In this case, the gate structure can include a conformal gate dielectric layer that lines the gate opening and a gate conductor layer thereon. Alternatively, the gate structure includes a first portion including a short gate dielectric layer proximal to the channel region and a second portion (including a conformal gate dielectric layer and gate conductor layer) on the lower portion in a gate opening. Optionally, the structure also includes an additional FET without the scaled effective gate length. Also disclosed are associated methods.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
95.
ILLUSTRATION GENERATOR FOR INTEGRATED CIRCUIT DESIGN AND METHOD
Disclosed are a method, system, and software application (referred to herein as an illustration generator) for generating two or three dimensional (2D or 3D) digital illustrations of user-selected areas of integrated circuit (IC) layouts. The illustration generator can include a program of instructions executable by processor to cause the processor to perform a method. This method includes: generating a database of IC component regions (e.g., using a technology file, and a design manual); comparing a user-selected area of an IC layout to the database in order to identify specific IC component regions included within the user-selected area; and generating a 2D or 3D digital illustration of the area. The digital illustration can include representations of different structural features within the area including at least some of the previously identified specific integrated circuit component regions.
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G06F 111/20 - CAO de configuration, p. ex. conception par assemblage ou positionnement de modules sélectionnés à partir de bibliothèques de modules préconçus
Structures for a polarization splitter and methods of forming such structures. The structure comprises a multimode interference structure including a first multimode interference region, a second multimode interference region, a first waveguide core adjoined to a first portion of the first multimode interference region at a first acute angle, a second waveguide core adjoined to a second portion of the first multimode interference region at a second acute angle, and a third waveguide core adjoined to a third portion of the first multimode interference region. The second multimode interference region has an overlapping relationship with the first multimode interference region.
G02B 6/126 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré utilisant des effets de polarisation
The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor device and methods of manufacture. The structure includes: a gate structure including a gate dielectric material and a gate electrode with a stepped feature; sidewall spacers on sidewalls of the gate electrode, the sidewall spacers including a notched feature adjacent to the gate electrode; and a silicide contact on a surface of the gate electrode, the silicide contact being free of breaks on the surface of the gate electrode.
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
A deadtime generator configured to output a pair of non-overlapping clock signals. A circuit is provide that includes an input node for receiving a clock signal; a first signal path coupled to the input node and having a first output node for outputting a first modified clock signal, wherein the first signal path includes a feedback node coupled to an input of a feedback inverter; a second signal path coupled to the input node and having a second output node for outputting a second modified clock signal, wherein second signal path includes a Low-to-High skewed inverter; and a feedback signal path coupled to second signal path and having a High-to-Low skewed inverter with an output coupled to a gate of at least one transistor, wherein an output of the at least one transistor is coupled to the feedback node.
H03K 5/151 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions avec deux sorties complémentaires
G06F 1/06 - Générateurs d'horloge produisant plusieurs signaux d'horloge
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03K 5/05 - Mise en forme d'impulsions par augmentation de duréeMise en forme d'impulsions par diminution de durée par l'utilisation de signaux d'horloge ou d'autres signaux de référence de temps
The disclosed subject matter relates generally to structures for use in memory devices. More particularly, the present disclosure relates to three terminal resistive random-access (ReRAM) memory structures having source, drain, and control electrodes. The present disclosure provides a memory structure including a source electrode having an upper surface, a drain electrode having an upper surface, a dielectric channel layer laterally between the first electrode and the second electrode, a hole generating layer on the dielectric channel layer, and a control electrode on the hole generating layer, the control electrode has an upper surface. The upper surface of the control electrode is substantially coplanar with the upper surface of the source electrode and the upper surface of the drain electrode.
H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
Personal test units and methods of using a personal health unit for performing a health-monitoring test. The structure comprises a housing including a first interior chamber and a second interior chamber. The first interior chamber is configured to removably receive a sensor chip, and the second interior chamber is configured to removably receive a module that includes a plurality of reservoirs each containing a fluid. A microfluidic circuit is configured to couple the plurality of reservoirs to a plurality of sensing devices on the sensor chip. The structure may optionally include a light source that is disposed inside the housing. The light source may include a laser and a plurality of optical fibers configured to transfer light from the laser to the sensing devices on the sensor chip.
