The present disclosure relates to semiconductor structures and, more particularly, to metal-oxide semiconductor transistors and methods of manufacture. The structure includes: a substrate comprising a drift region and a body region; a gate structure between the drift region and the body region; an insulator material over the gate structure, the drift region and the body region; and an air gap within the insulator material and extending into the drift region.
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked diode-trigger silicon controlled rectifiers and methods of manufacture. The structure includes: a silicon controlled rectifier in a trap rich region of a semiconductor substrate; and at least one diode built in polysilicon (gate material) and isolated by a gate-dielectric.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/74 - Dispositifs du type thyristor, p.ex. avec un fonctionnement par régénération à quatre zones
4.
Laterally-diffused metal-oxide-semiconductor devices with an air gap
Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming same. The structure comprises a semiconductor substrate including a trench, a source and a drain in the semiconductor substrate, a dielectric layer inside the trench, and a gate in the dielectric layer. The trench has a first sidewall and a second sidewall, the source is adjacent to the first sidewall of the trench, the drain is adjacent to the second sidewall of the trench, and the gate is laterally between the first sidewall of the trench and the second sidewall of the trench. The structure further comprises an air gap in the dielectric layer. The air gap is below the gate, and the air gap is laterally between the first sidewall of the trench and the second sidewall of the trench.
The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
6.
PLASMONIC PHOTONIC STRUCTURES INCLUDING A LAYER THAT EXHIBITS AN ELECTRIC-FIELD-INDUCED POCKELS EFFECT
Plasmonic photonic structures that include a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a waveguide core on a substrate, a first layer that has an overlapping relationship with the first waveguide core, and a second layer that has an overlapping relationship with the first waveguide core and the first layer. The first layer comprises a metal, and the second layer comprising a material that exhibits an electric-field-induced Pockels effect.
G02F 1/015 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments à semi-conducteurs ayant au moins une barrière de potentiel, p.ex. jonction PN, PIN
G02F 1/025 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments à semi-conducteurs ayant au moins une barrière de potentiel, p.ex. jonction PN, PIN dans une structure de guide d'ondes optique
G02F 1/035 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des céramiques ou des cristaux électro-optiques, p.ex. produisant un effet Pockels ou un effet Kerr dans une structure de guide d'ondes optique
7.
STRUCTURES FOR AN ELECTROSTATIC DISCHARGE PROTECTION DEVICE
Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises adjacent first and second gates over a semiconductor substrate, a source adjacent to the first gate, and a drain adjacent to the second gate. The source includes a first well in the semiconductor substrate, a second well in the semiconductor substrate, and a doped region. The first well and the doped region have a first conductivity type, and the second well has a second conductivity type opposite from the first conductivity type. The doped region has a first portion that overlaps with the first well, and the doped region has a second portion that overlaps with the second well.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
8.
MULTI-SUBSTRATE COUPLING FOR PHOTONIC INTEGRATED CIRCUITS
Embodiments of the disclosure provide a multi-substrate coupling for photonic integrated circuits (PICs). Structures of the disclosure may include a first substrate having a first surface. The first surface includes a groove therein. A second substrate has a second surface coupled to the first surface. The second substrate includes a cavity substantially aligned with the groove of the first surface, and a photonic integrated circuit (PIC) structure horizontally distal to the cavity.
A structure includes a through semiconductor via (TSV) in a semiconductor substrate. The structure also includes a cavity including a first cavity portion in the semiconductor substrate and surrounding a middle section of the TSV and in direct contact with the TSV. The cavity also includes a plurality of second cavity portions in the semiconductor substrate and surrounding an upper section of the TSV. The semiconductor substrate is between adjacent second cavity portions, creating a bridge portion that provides structural support. The cavity reduces parasitic capacitance.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
10.
THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH TOP CHIP INCLUDING LOCAL INTERCONNECT FOR BODY-SOURCE COUPLING
Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions; a body region on a channel region between the source and drain regions; and a gate structure adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: a source region between drain regions; a body region on a channel region between the source region and each drain region; and gate structures adjacent to and between the channel regions and the dielectric material layers. The first chip also includes an insulator layer on the transistor opposite the dielectric material layers, a trench in the insulator layer extending to the source and body regions, and a local interconnect at the bottom of the trench.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
11.
THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH TOP CHIP INCLUDING SCHOTTKY DIODE BODY CONTACT
Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions, a body region on a channel region between the source and drain regions, and a gate structure adjacent to and between the channel region and the dielectric material layers. An insulator layer is on the transistor opposite the dielectric material layers and includes an opening extending to the body region. Optionally, a semiconductor layer is at the bottom of the opening. A contact extends into the opening to the body region (or to the semiconductor layer thereon, if applicable).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
12.
SEMICONDUCTOR DEVICE INCLUDING DIFFUSION BREAK STRUCTURE AND METHOD OF FORMING SEMICONDUCTOR DEVICE
A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.
Structures including a calibration marker adjacent to a photonic structure and methods of forming such structures. The structure comprises a semiconductor substrate, a photonic structure, and a back-end-of-line stack over the semiconductor substrate. The back-end-of-line stack includes a plurality of fill features, an exclusion area surrounded by the plurality of fill features, and a calibration marker in the exclusion area. The calibration marker is disposed adjacent to the photonic structure, and the calibration marker includes a feature having a predetermined dimension.
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor layer, a first raised source/drain region on the semiconductor layer, a second raised source/drain region on the semiconductor layer, a gate electrode laterally between the first raised source/drain region and the second raised source/drain region, a first airgap laterally between the first raised source/drain region and the gate electrode, and a second airgap laterally between the second raised source/drain region and the gate electrode. The gate electrode includes a first section and a second section between the first section and the semiconductor layer, the first section of the gate electrode has a first width, the second section of the gate electrode has a second width, and the first width is greater than the second width.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
15.
Structures for a laterally-diffused metal-oxide-semiconductor transistor
Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure comprises a drain and a source in a semiconductor substrate. The source includes a source region having a first terminating end, a second terminating end, and a length between the first terminating end and the second terminating end. The structure further comprises a shallow trench isolation region in the semiconductor substrate. The shallow trench isolation region surrounds the drain. The structure further comprises a gate that surrounds the shallow trench isolation region and the drain. The gate has a side section between the drain and the source region, the side section of the gate has a width, and the gate has a length in a direction transverse to the width. The length of the source region is substantially equal to the length of the gate.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
Photonics chip structures including an edge coupler and a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a substrate, an edge coupler on the substrate, and a layer including a portion that has an overlapping relationship with the edge coupler. The layer comprises a material that exhibits an electric-field-induced Pockels effect.
G02F 1/035 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des céramiques ou des cristaux électro-optiques, p.ex. produisant un effet Pockels ou un effet Kerr dans une structure de guide d'ondes optique
17.
STRUCTURES INCLUDING A GRATING COUPLER AND A LAYER EXHIBITING AN ELECTRIC-FIELD-INDUCED POCKELS EFFECT
Structures including a grating coupler and a layer that exhibits an electric-field-induced Pockels effect and methods of forming such structures. The structure comprises a first grating coupler on a substrate, a second grating coupler having an overlapping relationship with the first grating coupler, and a layer including a portion having an overlapping relationship with the second grating coupler. The layer comprises a material that exhibits an electric-field-induced Pockels effect.
G02F 1/03 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des céramiques ou des cristaux électro-optiques, p.ex. produisant un effet Pockels ou un effet Kerr
G02F 1/035 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des céramiques ou des cristaux électro-optiques, p.ex. produisant un effet Pockels ou un effet Kerr dans une structure de guide d'ondes optique
18.
BROADBAND OPTICAL SWITCHES BASED ON A RING-ASSISTED MACH-ZHENDER INTERFEROMETER
Structures for a broadband optical switch and methods of forming such structures. The structure comprises a Mach-Zehnder interferometer including first and second arms. The first arm comprises a first waveguide core, and the second arm comprises a second waveguide core. The structure further comprises a ring resonator comprising a third waveguide core that has a first thickness. A portion of the third waveguide core is adjacent to a portion of the first waveguide core over a light coupling region. A slab layer connects the portion of the first waveguide core to the portion of the third waveguide core. The slab layer has a second thickness that is less than the first thickness of the first waveguide core.
G02F 1/225 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence dans une structure de guide d'ondes optique
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
G02F 1/21 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence
The present disclosure relates to semiconductor structures and, more particularly, to gated body transistors and methods of manufacture. The structure includes: at least one fin structure composed of semiconductor material and including a channel region between a source region and a drain region; and a gated body under the channel region of the at least one fin structure.
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
20.
THIN FILM RESISTOR, THERMISTOR AND METHOD OF PRODUCING THE SAME
An apparatus includes a resistor structure within a back end of line (BEOL) via level. The resistor structure includes a lower resistor film, a first insulating layer over the lower resistor film, an upper resistor film over the first insulating layer, and a second insulating layer over the upper resistor film. First and second upper metal lines are above the second insulating layer, a first end of the upper resistor film is coupled to the first upper metal line by a first upper via or contact, and a second end of the upper resistor film is coupled to the second upper metal line by a second upper via or contact. The apparatus may be a resistor or a thermistor of a semiconductor device.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
21.
CAVITY WITH BOTTOM HAVING DIELECTRIC LAYER PORTION OVER GATE BODY WITHOUT ETCH STOP LAYER AND RELATED METHOD
A semiconductor device includes a transistor including source/drain regions and a gate, the gate having a gate body. An etch stop layer is over the source/drain regions but not over the gate body. An interconnect layer is over the transistor and includes a dielectric layer. A cavity extends partially through the interconnect layer above the gate, and a portion of the dielectric layer is over the gate body and defines a bottom of the cavity. The cavity provides a mechanism to reduce both on-resistance and off-capacitance for applications such as radio frequency switches.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
22.
METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
An integrated circuit product including a first layer of insulating material that includes a first insulating material, a metallization blocking structure positioned in an opening in the first layer of insulating material, a second layer of insulating material including a second insulating material positioned below the metallization blocking structure, a metallization trench defined in the first layer of insulating material on opposite sides of the metallization blocking structure, and a conductive metallization line positioned in the metallization trench on opposite sides of the metallization blocking structure.
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
Structures including a photonics chip and a cavity-mounted laser chip, and methods of forming and using such structures. The structure comprises a photonics chip including a substrate and a cavity in the substrate. The structure further comprises a laser chip inside the cavity, and a lead frame comprising a first section attached to a portion of the laser chip and a second section attached to a portion of the photonics chip.
A structure includes a first gate structure spaced from a second gate structure in a field effect transistor (FET) area of a substrate. A polysilicon resistor is in a space between the first gate structure and the second gate structure. The polysilicon resistor has a lower surface that is farther from the substrate than lower surfaces of the polysilicon bodies of the first and second gate structures. The polysilicon resistor may have a different polarity dopant compared to at least one of the polysilicon bodies of the first and second gate structures.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
Systems and methods for designing photonic integrated circuits (PICs) include a simulation program with virtual optical probing functions and, optionally, bidirectional optical signal propagation simulation. For probing, a processor receives an output expression specifying a virtual optical probing function (e.g., for power in dBm, etc.) and a net within a PIC design. If different simulation types are enabled, the expression specifies simulation type. If bidirectionality is enabled, the expression specifies the forward or reverse direction. In response, the processor accesses the PIC design and results of simulation(s) thereof and calculates and outputs an optical signal parameter value for the specified net. For bidirectionality, component descriptions of photonic device cells define, at each input/output terminal, pins associated with each of multiple optical signal components in both directions and, when such cells are incorporated into a PIC design, analytical functions employ the pins to model the optical signal components in both directions.
G02B 27/00 - Systèmes ou appareils optiques non prévus dans aucun des groupes ,
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G06F 30/31 - Saisie informatique, p.ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/323 - Traduction ou migration, p.ex. logique à logique, traduction de langage descriptif de matériel ou traduction de liste d’interconnections [Netlist]
26.
PIC DIE AND PACKAGE WITH MULTIPLE LEVEL AND MULTIPLE DEPTH CONNECTIONS OF FIBERS TO ON-CHIP OPTICAL COMPONENTS
A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/30 - Moyens de couplage optique pour usage entre fibre et dispositif à couche mince
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
G02B 6/43 - Dispositions comprenant une série d'éléments opto-électroniques et d'interconnexions optiques associées
Structures for a photonics chip that include a reflector and methods of forming such structures. The structure comprises a reflector including a dielectric layer on a semiconductor substrate, a plurality of trenches in the dielectric layer, and a reflector layer. Each trench includes a plurality of sidewalls, and the reflector layer includes a portion on the sidewalls of each trench. The structure further comprises a photonic component over the reflector.
Structures for a thermo-optic phase shifter and methods of forming a thermo-optic phase shifter. The structure comprises an interconnect structure including a dielectric layer, a waveguide core on the dielectric layer, and a heater on the dielectric layer. The heater includes a resistive heating element positioned adjacent to the waveguide core.
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
Structures for a thermo-optic phase shifter and methods of forming a thermo-optic phase shifter. The structure comprises a semiconductor substrate, and a heater including a first resistive heating element, a second resistive heating element, and a slab layer connecting the first resistive heating element to the second resistive heating element. The first resistive heating element and the second resistive heating element have a first thickness, and the slab layer has a second thickness that is less than the first thickness. The structure further comprises a waveguide core including a portion that is laterally positioned between the first resistive heating element and the second resistive heating element. The slab layer of the heater is disposed between the portion of the waveguide core and the semiconductor substrate.
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p.ex. commutation, ouverture de porte ou modulation; Optique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
The present disclosure relates to semiconductor structures and, more particularly, to a wraparound gate structure and methods of manufacture. The structure includes: a channel region comprising semiconductor material; an isolation structure surrounding the channel region; a divot within the isolation structure; and a gate structure comprising gate material within the divot and surrounding the channel region.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 29/66 - Types de dispositifs semi-conducteurs
The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an intrinsic base region; an emitter region above the intrinsic base region; a collector region under the intrinsic base region; and an extrinsic base region comprising metal material, and which surrounds the intrinsic base region and the emitter region.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
A magnetic memory device is provided. The magnetic memory device includes a first magnetic tunnel junction (MTJ) stack, a second MTJ stack, and a spin-orbit torque (SOT) electrode. The second MTJ stack is adjacent to the first MTJ stack. The SOT electrode is connected to the first MTJ stack and the second MTJ stack, wherein the SOT electrode has a first electrode section along a first axis and a second electrode section along a second axis, and the second axis is spaced apart from and parallel to the first axis.
Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a photodetector including a pad and a semiconductor layer positioned on the pad. The semiconductor layer has a sidewall, the pad comprises a semiconductor material, and the pad includes a top surface and a side edge. The structure further comprises a waveguide core including a tapered section adjacent to the side edge of the pad, and a confining feature in the pad adjacent to the sidewall of the semiconductor layer. The confining feature extends below the top surface of the pad, and the confining feature comprises a dielectric material.
H01L 33/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails
H01L 33/48 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs
H01L 33/50 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails caractérisés par les éléments du boîtier des corps semi-conducteurs Éléments de conversion de la longueur d'onde
Structures for a photonics chip that include a cavity or groove and methods of forming same. The structure comprises a semiconductor substrate including a first opening, a back-end-of-line stack on the semiconductor substrate, and a dielectric layer on the back-end-of-line stack. The back-end-of-line stack includes a pad, and the dielectric layer includes a second opening that extends to the pad. The structure further comprises an electrical interconnect inside the second opening in the dielectric layer. The electrical interconnect includes a sidewall that is separated in a lateral direction from the dielectric layer by a gap.
Disclosed are a structure with a multi-level field plate and a method of forming the structure. The field plate includes multiple first conductors on a dielectric layer and separated from each other by spaces with different widths (e.g., by with progressively decreasing widths). A conformal additional dielectric layer extends over the first conductors and onto the dielectric layer within the spaces. The field plate also includes, on the additional dielectric layer, second conductor(s) with portions thereof extending into the spaces. Within the spaces, the second conductor portions are at different heights (e.g., at progressively increasing heights) above the dielectric layer. Such a field plate can be incorporated into a transistor (e.g., a high electron mobility transistor (HEMT)) to, not only reduce the peak of an electric field exhibited proximal to a gate terminal, but to ensure the electric field is essentially uniform level between the gate and drain terminals.
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
36.
Ohmic contacts for a high-electron-mobility transistor
Structures including an ohmic contact for a high-electron-mobility transistor and methods of forming such structures. The structure comprises a layer stack on a substrate and a device structure including an ohmic contact. The layer stack includes a plurality of semiconductor layers each comprising a compound semiconductor material. The ohmic contact includes a metal layer in a contacting relationship with a portion of at least one of the semiconductor layers of the layer stack and a region comprising oxygen atoms, and the metal layer is positioned between the region and the portion of the at least one of the semiconductor layers of the layer stack.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
The present disclosure relates to a circuit and, more particularly, to comparator circuits used with a depletion mode device and methods of operation. The circuit includes: a comparator, a transistor connected to an output of the comparator; and a depletion mode device connected to ground and comprising a control gate connected to the transistor.
H03K 5/22 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p.ex. la pente, l'intégrale
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
38.
MAGNETIC-TUNNEL-JUNCTION DEVICES FOR A MAGNETIC-FIELD SENSOR
Structures including a magnetic-tunnel-junction device and methods of forming such structures. The structure comprises a magnetic-tunnel-junction device that includes a first electrode having a first sidewall, a second electrode having a second sidewall facing the first sidewall of the first electrode, a pinned layer adjacent to the first sidewall of the first electrode, a free layer adjacent to the second sidewall of the second electrode, and a tunnel barrier layer between the free layer and the pinned layer.
A photonic integrated circuit (PIC) includes a waveguide in or over a semiconductor substrate. The waveguide has a terminal end. The PIC also includes an optical absorber having a curved shape adjacent to opposing sides and an endwall of the terminal end of the waveguide, i.e., it surrounds the terminal end of the waveguide. The optical absorber is multi-layered and includes a light absorbing layer. The light absorbing layer may include germanium or a vanadate. The optical absorber terminates or attenuates any stray optical signals from the waveguide while maintaining low back reflection.
The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure of the disclosure includes a first pair of complementary transistors connected in series between a first voltage node and a second voltage node. Each transistor of the first pair includes a gate coupled to a first input node. A second pair of complementary transistors is connected in series between the first voltage node and the second voltage node in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node. An output line is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.
Structures for a non-volatile programmable device and methods of forming a structure for a non-volatile programmable device. The structure comprises a first electrode including a corner and a sidewall that extends to the corner, a first dielectric layer adjacent to the first sidewall, a second dielectric layer adjacent to the first dielectric layer, and a second electrode including a portion inside a recess between the first dielectric layer and the second dielectric layer. The portion of the second electrode is disposed adjacent to the corner of the first electrode.
An apparatus and method for providing high throughput memory responses are provided. The apparatus includes a memory device including a plurality of memory arrays, a memory controller configured to control the memory device, the memory controller having a read queue, a write queue, and an address match circuit, and a data output circuit. The memory controller receives a read request, searches the write queue for a write address that matches a read address of the read request, and sends data associated with the write address from the write queue to the data output circuit without accessing the memory device when the write address matches the read address, the write address that matches the read address being a target address. The data output circuit outputs the data associated with the target address to an external device.
Structures including an edge coupler and methods of forming such structures. The structure comprises an edge coupler including a first portion and a second portion between the first portion and a semiconductor substrate, a first coupling-assistance feature adjacent to the first portion of the edge coupler, and a second coupling-assistance feature adjacent to the first portion of the edge coupler. The first portion of the edge coupler is positioned in a lateral direction between the first coupling-assistance feature and the second coupling-assistance feature.
Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a photodetector including a pad and a semiconductor layer on the pad, a first waveguide core including a tapered section adjacent to a sidewall of the semiconductor layer, and a second waveguide core including a curved section adjacent to the sidewall of the semiconductor layer. The curved section includes a plurality of segments, and the tapered section of the first waveguide core is overlapped by at least one of the plurality of segments in the curved section of the second waveguide core.
Embodiments of the disclosure provide a structure including a passive component traversing multiple semiconductor chips, with related systems and methods. A structure of the disclosure includes a plurality of stacked semiconductor chips including a first chip coupled to a second chip through an interface. A passive component traverses the interface between the first chip and the second chip of the plurality of stacked semiconductor chips. The passive component includes a first portion within the first chip and a second portion within the second chip.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
G06F 30/39 - Conception de circuits au niveau physique
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p.ex. marques de repérage, schémas de test
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
47.
IC STRUCTURE FOR CONNECTED CAPACITANCES AND METHOD OF FORMING SAME
An integrated circuit (IC) structure, including a semiconductor-on-insulator (SOI) substrate, the SOI substrate including a buried insulator layer over a base semiconductor layer, and a semiconductor-on-insulator (SOI) layer over the buried insulator layer. The IC structure further includes a gate over a gate dielectric layer over the SOI layer. The IC structure includes an n-type metal-oxide semiconductor (n-MOS) capacitor. The n-MOS capacitor includes an n-well under the buried insulator layer, and an n-type semiconductor adjacent a first side of the gate. The IC structure also includes a p-type metal-oxide semiconductor (p-MOS) capacitor adjacent the n-MOS capacitor and includes a p-well adjacent the n-well and a p-type semiconductor adjacent a second side of the gate. The gate is electrically connected only to the n-MOS capacitor and the p-MOS capacitor.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
A process for performing a design rule check (DRC) by a computer may comprise receiving a DRC result comprising a plurality of DRC errors, the DRC result corresponding to a DRC deck comprising a plurality of rules and a design layout database comprising a plurality of components; classifying, using a neural network, each of the plurality of DRC errors according to whether that DRC should be ignored; and producing a final report including a plurality of respective indications of whether the plurality of DRC errors should be ignored. Performing the process may further include the receiving mistake feedback regarding the final report; updating, using the mistake feedback, a DRC result dataset comprising a plurality of dataset entries; and re-training the neural network using the updated DRC result dataset.
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
49.
PHOTONICS CHIP STRUCTURES INCLUDING A LIGHT SOURCE AND AN EDGE COUPLER
Structures including a light source and an edge coupler, and methods of forming and using such structures. The structure comprises a semiconductor substrate and a back-end-of-line stack on the semiconductor substrate. The back-end-of-line stack includes a first dielectric layer, a first plurality of metal features in the first dielectric layer, a second dielectric layer on the first dielectric layer, and a second plurality of metal features in the second dielectric layer. The second plurality of metal features have a non-overlapping relationship with the first plurality of metal features. The structure further comprises an edge coupler adjacent to the first plurality of metal features and the second plurality of metal features.
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/136 - Circuits optiques intégrés caractérisés par le procédé de fabrication par gravure
H04N 5/33 - Transformation des rayonnements infrarouges
50.
REFERENCE MARKERS ADJACENT TO A CAVITY IN A PHOTONICS CHIP
Structures including a cavity adjacent to an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate including a cavity with a sidewall, a dielectric layer on the semiconductor substrate, and an edge coupler on the dielectric layer. The structure further comprises a fill region including a plurality of fill features adjacent to the edge coupler. The fill region includes a reference marker at least partially surrounded by the plurality of fill features, and the reference marker has a perimeter that surrounds a surface area of the dielectric layer, and the surface area overlaps with a portion of the sidewall of the cavity.
Disclosed are embodiments of an amplifier circuit (e.g., a differential amplifier circuit with symmetric parallel branches between input and output stages or a single-ended amplifier circuit with one leg between input and output stages). The circuit includes a power stage. Within the power stage of a differential amplifier circuit, the parallel branches include one or more pairs of power transistors, and varactors are connected to gates of at least one pair of power transistors. Within the power stage of a single-ended amplifier circuit there are one or more power transistors, and a varactor is connected to a gate of at least one power transistor. In operation, capacitance of each varactor is adjustable to fine-tune power transistor gate capacitance and thereby achieve stability and/or improve performance of the amplifier circuit.
An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate having an upper substrate surface, an active well region, a first terminal well region, and a second terminal well region. The active well region is in the substrate, and the first terminal well region and the second terminal well region are in the active well region. The second terminal well region is spaced apart from the first terminal well region. The first terminal well region and the second terminal well region each includes a first doped region, a first contact region having at least a portion in the first doped region, and a second contact region spaced apart from the first doped region.
Disclosed are a multi-photodetector circuit and an optical receiver incorporating the circuit. The circuit includes parallel-connected photodiodes. In some embodiments, photodiodes are connected, in a same direction, between a positive power supply line and an output line. They receive equal power optical signals or a series of 1:2 optical dividers is employed so each photodiode receives a progressively lower power signal until the last two photodiodes, which receive equal power optical signals. In other embodiments, first photodiodes are connected, in one direction, between a positive power supply line and an output line and second photodiodes are connected, in an opposite direction, between a negative power supply line and the output line. First photodiodes receive equal power optical signals from an optical divider in response to an optical input signal and second photodiodes receive equal power optical signals from another optical divider in response to an inverted optical input signal.
H04B 10/69 - Dispositions électriques dans le récepteur
H04B 10/40 - Systèmes de transmission utilisant des ondes électromagnétiques autres que les ondes hertziennes, p.ex. les infrarouges, la lumière visible ou ultraviolette, ou utilisant des radiations corpusculaires, p.ex. les communications quantiques Émetteurs-récepteurs
54.
RESISTIVE RANDOM-ACCESS MEMORY ELEMENTS WITH LATERAL SIDEWALL SWITCHING
Structures for a resistive random-access memory element and methods of forming a structure for a resistive random-access memory element. The structure comprises an interlayer dielectric layer including a first trench having a sidewall and a second trench having a sidewall adjacent to the sidewall of the first trench. The structure further comprises a first layer on the sidewall of the first trench, a second layer inside the second trench, and a third layer on the sidewall of the second trench. The first layer comprises a first metal, the second layer comprises a second metal, and the third layer comprises a dielectric material. The third layer includes a portion positioned between the first layer and the second layer.
A structure includes an integrated circuit (IC) chip including a substrate. An input/output (I/O) opening extends inwardly from an exterior surface of the IC chip. A metal finger structure protrudes partly into the I/O opening, and outer surfaces of the metal finger structure are covered by a moisture barrier. The metal finger structure may provide stress-relief by removing attacking surfaces for stress in the I/O opening and/or otherwise reduces stress, such as film stresses, to reduce damage to the moisture barrier and improve reliability compared to conventional devices.
The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an emitter in a semiconductor substrate; a collector in the semiconductor substrate; a base contact region in the semiconductor substrate and adjacent to the collector and the emitter; and a shallow trench isolation structure overlapping the base contact region and separating the base contact region from the emitter and the collector.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
57.
STRUCTURE WITH DIFFERENTIAL AMPLIFIERS HAVING INPUT OFFSET AND RELATED METHODS
GlobalFoundries Dresden Module One Limited Liability Company & Co. KG (Allemagne)
Inventeur(s)
Stefanov, Stefan Manolov
Abrégé
Embodiments of the disclosure provide a structure with differential amplifiers each having an input offset, and related methods. A structure of the disclosure includes a first differential amplifier coupled to an input line, a reference line, and a first output line. The first differential amplifier has a first input offset. A second differential amplifier couples the input line and the reference line to a second output line. The second differential amplifier has a second input offset in a different direction from the first input offset.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p.ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
The present disclosure relates to semiconductor structures and, more particularly, to high-voltage electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a semiconductor material of a first dopant type; a first well having a second dopant type in the semiconductor material; a floating well in the first well, the second well having the first dopant type; and a diffusion region of the second dopant type adjacent to the floating well and in electrical contact to the first well.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
59.
LASER CHIPS ATTACHED TO A PHOTONICS CHIP BY MULTIPLE ANCHORS
Structures including a photonics chip and a cavity-mounted laser chip, and methods of forming such structures. The structure comprises a photonics chip including a substrate and a cavity in the substrate, a laser chip including a body inside the cavity, a first anchor disposed inside the cavity adjacent to a first corner of the body of the laser chip, and a second anchor disposed inside the cavity adjacent to a second corner of the body of the laser chip. The first and second anchors are configured to attach the laser chip to the photonics chip.
H01S 5/0237 - Fixation des puces laser sur des supports par soudage
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
60.
SYSTEM FOR IMAGING SUBSTRATE SURFACE AND RELATED METHOD
A system for imaging a substrate, including a single electromagnetic radiation (EMR) emitter at a first side of the substrate. The system further includes a diffuser between the single EMR emitter and the substrate, the electromagnetic radiation from the single EMR emitter passing through the diffuser to a surface of the substrate. The system includes a photodetector at a second side of the substrate, the photodetector configured to capture reflected electromagnetic radiation from the surface of the substrate. The system further includes a computing device configured to render a single image of substantially an entirety of the surface of the substrate from the captured reflected electromagnetic radiation. The single EMR emitter and the photodetector are at an angle relative to the surface of the substrate that is not one of parallel and perpendicular.
B24B 49/12 - Appareillage de mesure ou de calibrage pour la commande du mouvement d'avance de l'outil de meulage ou de la pièce à meuler; Agencements de l'appareillage d'indication ou de mesure, p.ex. pour indiquer le début de l'opération de meulage impliquant des dispositifs optiques
B24B 7/22 - Machines ou dispositifs pour meuler les surfaces planes des pièces, y compris ceux pour le polissage des surfaces planes en verre; Accessoires à cet effet caractérisés par le fait qu'ils sont spécialement étudiés en fonction des propriétés de la matière des objets non métalliques à meuler pour meuler de la matière inorganique, p.ex. de la pierre, des céramiques, de la porcelaine
61.
ACTIVE REGION ELECTRICALLY PROGRAMMABLE FUSE WITH GATE STRUCTURE AS SILICIDE BLOCK
An electrically programmable fuse includes a first contact, a second contact spaced from the first contact, and a link between and electrically connecting the first contact and the second contact. The first contact, the second contact and the link include semiconductor material. A gate structure is partially over the link, leaving an uncovered link region uncovered by the gate structure. A silicide region is within the uncovered link region and provides an effective fuse link. The gate structure blocks silicide formation over an entirety of the fuse link, reducing the width of the effective fuse link, reducing the necessary programming current and the overall size of the electrically programmable fuse.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
62.
TRANSISTORS WITH FIELD-SHIELD CONTACTS AND BASE CONTACTS
Structures for a transistor and methods of forming a structure for a transistor. The structure comprises a semiconductor substrate including a top surface and a trench, a gate electrode disposed in the trench, a first doped region disposed beneath the trench, a first contact coupled to the first doped region, a second doped region disposed in a vertical direction between the first doped region and the top surface, and a plurality of second contacts coupled to the second doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The first contact extends in the semiconductor substrate from the top surface to a first depth that adjoins the first doped region. The plurality of second contacts extend in the semiconductor substrate from the top surface to a second depth that adjoins the second doped region, and the second depth is less than the first depth.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
63.
Catalytic abatement system for semiconductor manufacturing process
x) from the emission stream. The abatement system provides carbon-free abatement of nitrogen oxide and hydride(s). The abatement system has significantly lower cost to manufacture and operate.
B01D 53/04 - SÉPARATION Épuration chimique ou biologique des gaz résiduaires, p.ex. gaz d'échappement des moteurs à combustion, fumées, vapeurs, gaz de combustion ou aérosols par adsorption, p.ex. chromatographie préparatoire en phase gazeuse avec adsorbants fixes
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c. à d. procédés de dépôt chimique en phase vapeur (CVD) caractérisé par le procédé de revêtement
64.
LASER CHIPS ATTACHED TO A PHOTONICS CHIP BY MULTIPLE ADHESIVES
Structures including a photonics chip and a surface-mounted laser chip, and methods of forming same. The structure comprises a photonics chip including a surface, a laser chip including a light output and a body that are spaced from the surface of the photonics chip, a first adhesive between the body of the laser chip and the surface of the photonics chip, and a second adhesive between the body of the laser chip and the surface of the photonics chip. The light output is oriented toward the surface of the photonics chip, the first adhesive has a first thermal conductivity, the second adhesive has a second thermal conductivity that is less than the first thermal conductivity of the first adhesive, and the second adhesive is disposed in a light path between the light output of the laser chip and the surface of the photonics chip.
H01S 5/0236 - Fixation des puces laser sur des supports en utilisant un adhésif
H01S 5/0237 - Fixation des puces laser sur des supports par soudage
H01S 5/183 - Lasers à émission de surface [lasers SE], p.ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités verticales, p.ex. lasers à émission de surface à cavité verticale [VCSEL]
The present disclosure relates to semiconductor structures and, more particularly, to silicon control rectifiers and methods of manufacture. A structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and at least one gate structure in the first well which abuts one shallow trench isolation structure of the plurality of shallow trench isolation structures.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
66.
MULTI-FIN FIN-TYPE FIELD EFFECT TRANSISTOR WITH FINE-TUNED EFFECTIVE CHANNEL WIDTH
Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/66 - Types de dispositifs semi-conducteurs
The present disclosure relates to semiconductor structures and, more particularly, to single-photon avalanche diodes and methods of manufacture. The structure includes: a first deep trench structure in a semiconductor substrate having a conductive material and a material of a first polarity; a second deep trench structure in the semiconductor substrate surrounding the first deep trench structure, the second deep trench structure having a conductive material and a material of a second polarity; and contacts to both the first deep trench structure and the second deep trench structure.
H01L 31/107 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel fonctionnant en régime d'avalanche, p.ex. photodiode à avalanche
H01L 27/144 - Dispositifs commandés par rayonnement
H01L 31/02 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails - Détails
H01L 31/0352 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails caractérisés par leurs corps semi-conducteurs caractérisés par leur forme ou par les formes, les dimensions relatives ou la disposition des régions semi-conductrices
68.
SEMICONDUCTOR DEVICES INCLUDING AN AIR GAP ADJACENT TO AN INTERCONNECT STRUCTURE AND METHODS OF FORMING THE SAME
A semiconductor device may include a first interlayer dielectric (ILD) over a substrate and a second ILD over the first ILD. An interconnect structure may be in the first ILD and the second ILD. The interconnect structure includes a conductive line on a via portion. An air gap may be arranged below the conductive line and between the via portion and the second ILD. The air gap may be defined by a sidewall of the via portion and a sidewall of the second ILD.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
69.
PHOTODETECTORS WITH A LIGHT-ABSORBING LAYER AT LEAST PARTIALLY WRAPPED ABOUT A WAVEGUIDE CORE
Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a semiconductor layer comprising a crystalline semiconductor material, a waveguide core including a first sidewall and a second sidewall, and a photodetector including a light-absorbing layer, an anode, and a cathode. The light-absorbing layer includes a first portion and a second portion that are disposed on the semiconductor layer. The first portion of the light-absorbing layer is adjacent to the first sidewall of the waveguide core, and the second portion of the light-absorbing layer is adjacent to the second sidewall of the waveguide core.
H01L 31/0232 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails - Détails Éléments ou dispositions optiques associés au dispositif
The present disclosure relates to semiconductor structures and, more particularly, to low capacitance, low resistance devices and methods of manufacture. The structure includes: a semiconductor substrate; a device having an active region; and a porous semiconductor material within the semiconductor substrate and surrounding the active region of the device.
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p.ex. pour produire des défectuosités internes
71.
GATE-ALL-AROUND FIELD EFFECT TRANSISTORS WITH INNER SPACERS AND METHODS
Disclosed are a gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes stacked nanosheets having end portions adjacent to source/drain regions and a center portion between the end portions. The thickness of each nanosheet is tapered from a maximum thickness near the source/drain regions to a minimum thickness near and across the center portion. A gate wraps around each center portion. Inner spacers are aligned below the end portions between the gate and source/drain regions. The thickness of each inner spacer is tapered from a maximum thickness at the gate to a minimum thickness near the adjacent source/drain region. Each inner spacer includes a first spacer layer immediately adjacent to the gate, a second spacer layer immediately adjacent to the gate at least above the first spacer layer and further extending laterally beyond the first spacer layer toward or to the adjacent source/drain region, and, optionally, an air-gap.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
72.
DUAL-LAYER EDGE COUPLERS WITH CURVED COUPLING-ASSISTANCE FEATURES
Structures for an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate, a first waveguide core including a curved section and an end that terminates the curved section, and a second waveguide core including a section disposed adjacent to the curved section of the first waveguide core. The first waveguide core is positioned between the second waveguide core and the semiconductor substrate.
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/122 - Elements optiques de base, p.ex. voies de guidage de la lumière
G02B 6/125 - Courbures, branchements ou intersections
73.
SEMICONDUCTOR DEVICE INCLUDING GATE WITH DIFFERENT LATERALLY ADJACENT SECTIONS AND METHOD
Disclosed are embodiments of a semiconductor device and method of forming the device. The device includes a gate with first and second sections on a semiconductor layer. The first section includes first gate dielectric and gate conductor layers and an optional additional gate conductor layer on the first gate conductor layer. The second section includes second gate dielectric and gate conductor layers on the semiconductor layer and further extending onto the top of the first gate conductor layer. The second gate dielectric layer is thinner than the first gate dielectric layer. A gate sidewall spacer is on the first gate conductor layer positioned laterally to a sidewall of the second section (e.g., between the sidewall and the optional additional gate conductor layer). The first and second sections are either electrically connected for biasing with the gate bias voltage or electrically isolated for biasing with different gate bias voltages.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
74.
OPTICAL INPUT/OUTPUT INTERFACES BETWEEN PHOTONICS CHIPS
Structures including multiple photonics chips and methods of fabricating a structure including multiple photonics chips. The structure comprises a first chip including a first edge and a first plurality of optical couplers disposed at the first edge, and a second chip including a second edge adjacent to the first edge of the first chip and a second plurality of optical couplers. The second plurality of optical couplers are disposed at the second edge adjacent to the first plurality of optical couplers.
The present disclosure relates to semiconductor structures and, more particularly, to silicon control rectifiers and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate; a third well in the semiconductor substrate which isolates the first well from the second well; and a first diffusion region at a surface of the semiconductor substrate and which extends into the first well and the second well, the first diffusion region includes a same polarity as the third well.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
76.
SEMICONDUCTOR DEVICE WITH DIFFERENT SIZED EPITAXIAL STRUCTURES
An apparatus has a first gate structure of a core device on a substrate, a first L-shaped spacer covering a sidewall of the first gate and part of the substrate adjacent to the first gate, a first raised source/drain (S/D) structure on the substrate and spaced apart from the first gate by the first L-shaped spacer, a second gate of an I/O device on the substrate, a second L-shaped spacer covering a sidewall of the second gate and part of the substrate adjacent to the second gate, and a second raised S/D structure spaced apart from the second gate by the second L-shaped spacer. The first and second L-shaped spacers have the same spacer width, and a distance between the first gate structure and a sidewall of the first S/D structure is less than a distance between the second gate structure and a sidewall of the second S/D structure.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
77.
SEMICONDUCTOR STRUCTURE WITH ISOLATION REGION INCLUDING COMBINATION OF DEEP AND SHALLOW TRENCH ISOLATION STRUCTURES AND METHOD
Disclosed is a semiconductor structure and method of forming the semiconductor structure. Specifically, the semiconductor structure can include a first semiconductor fin extending from a semiconductor substrate. The semiconductor structure can further include an isolation region on the semiconductor substrate adjacent to a lower portion of the first semiconductor fin. The first semiconductor fin can, for example, be incorporated into a single-fin fin-type semiconductor device, such as a single-fin fin-type field effect transistor (FINFET). The isolation region can include at least one shallow trench isolation (STI) structure positioned laterally between and immediately adjacent to sections of a deep trench isolation (DTI) structure. With this alternating DTI-STI-DTI configuration, overall shrinkage of isolation material of the isolation region during anneals is reduced and, thus, so are stress-induced crystalline defects in the first semiconductor fin. Also disclosed are methods for forming such a semiconductor structure.
The present disclosure relates to semiconductor structures and, more particularly, to high performance silicon controlled rectifier (SCR) devices and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; a plurality of shallow trench isolation structures extending into the first well and the second well; and a deep trench isolation structure between the plurality of shallow trench isolation structures and extending into the semiconductor material deeper than the plurality of shallow trench isolation structures.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
The present disclosure relates to semiconductor structures and, more particularly, to antenna structures and methods of manufacture. The structure includes an antenna cell comprising a single P-well isolated by a deep trench isolation structure and including at least one diffusion region.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01Q 1/38 - Forme structurale pour éléments rayonnants, p.ex. cône, spirale, parapluie formés par une couche conductrice sur un support isolant
H01Q 1/48 - ANTENNES, c. à d. ANTENNES RADIO - Détails de dispositifs associés aux antennes Écrans de terre; Contrepoids
80.
MEMORY ASSEMBLY WITH BODY BIASING AND RELATED METHODS
Embodiments of the disclosure provide a memory assembly with body biasing and related methods to operate such a structure. A structure according to the disclosure includes a memory cell having a pair of memory transistors each having a gate coupled to a word line. A pair of diode-connected transistors each have a source/drain (S/D) terminal coupled to a respective S/D terminal of one of the pair of memory transistors through a multiplexer. A bias voltage source is coupled to each body of the pair of diode-connected transistors or each body of the pair of memory transistors. The bias voltage source applies a different bias voltage to each body of the pair of diode-connected transistors or each body of the pair of memory transistors.
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
81.
OPENING IN WALL BETWEEN INPUT/OUTPUT OPENINGS OF IC CHIP
A structure includes an integrated circuit (IC) chip including a substrate. At least two input/output (I/O) openings extend inwardly from an exterior surface of the IC chip. The I/O openings can be used to connect any sort of I/O device, such as an external optical device like a laser. Each I/O opening is separated from an adjacent I/O opening by a wall. An opening extends through the wall to each of the at least two I/O openings, and a moisture barrier is on inner surfaces of each I/O opening and the opening. The opening may reduce stress and may reduce sharp corners in the I/O openings to reduce damage to the moisture barrier.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
The present disclosure relates to semiconductor structures and, more particularly, to silicon controlled rectifiers with field plate structures and methods of manufacture. The structure includes: a plurality of wells of a first type in a semiconductor substrate; a well of a second type in the semiconductor substrate, the well of the second type surrounding the plurality of wells of the first type; an isolation structure surrounding the plurality of wells of the first type, the isolation structure isolating the well of the second type from the plurality of wells of the first type; and a plurality of field plates on the isolation structure, the plurality of field plates surround the plurality of wells of the first type.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
A capacitor structure is provided. The capacitor structure includes a substrate, a first electrode, a second electrode, and a third electrode. The first electrode is in the substrate. The second electrode is over the substrate. The third electrode is over the second electrode and includes a middle portion over the second electrode and end portions laterally adjacent to the second electrode.
A structure includes a first metal structure including a first upper metal feature having a first sidewall spacer thereabout, and a first lower metal feature under the first upper metal feature. The first lower metal feature includes a sidewall devoid of the first sidewall spacer. The structure also includes a second metal structure spaced from the first metal structure. The second metal structure includes a second upper metal feature having a second sidewall spacer thereabout, and a second lower metal feature under the first upper metal feature. The second lower metal feature includes a sidewall devoid of the second sidewall spacer. A dielectric is between the first metal structure and the second metal structure. The dielectric is devoid of any voids therein, and the opening it fills has a high aspect ratio. A related method is also provided.
The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor on insulator substrate with cavity structures and methods of manufacture. The structure includes: a bulk substrate with at least one rectilinear cavity structure; an insulator material sealing the at least one rectilinear cavity structure; and a buried insulator layer on the bulk substrate and over the at least one rectilinear cavity structure.
The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
A system to abate an emission from a first semiconductor process is disclosed. The system includes an abatement apparatus, such as a gas scrubber, to remove hazardous and toxic gas species from the emission. The abatement apparatus may combust the emission to remove these gas species using a fuel and oxidant. The system includes a fuel assembly fluidly coupled to the abatement apparatus which transmits the fuel from at least one source through the abatement apparatus. The fuel assembly may include a supply tank which contains a volume of fuel, a recovery apparatus which recovers and contains a recovery volume of fuel from a second semiconductor process, and a mass flow controller which may transmit fuel from at least one of the supply tank and the recovery apparatus through the abatement apparatus.
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate comprising a wide bandgap semiconductor material, a gate electrode, a first gate dielectric layer disposed on the semiconductor substrate, and a second gate dielectric layer disposed between the first gate dielectric layer and the gate electrode.
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The method comprises cleaning a surface of a semiconductor substrate with atomic layer etching. The semiconductor substrate comprises a wide bandgap semiconductor material. The method further comprises forming a gate dielectric layer on the surface of the semiconductor substrate.
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs présentant au moins une barrière de potentiel ou une barrière de surface, p.ex. une jonction PN, une région d'appauvrissement, ou une région de concentration de porteurs de charges
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A shield structure for a semiconductor chip comprises a chip mounting region on a base plate and a shell connected to the base plate. The shell is arranged over the base plate to provide a chamber having a volume, and the chip mounting region is arranged within the volume.
Structures for a waveguide escalator and methods of forming such structures. A structure comprises a first waveguide core, and a back-end-of-line stack including a first dielectric layer, a second dielectric layer on the first dielectric layer, an opening in the second dielectric layer, a second waveguide core including a section that overlaps with a section of the first waveguide core, and a plurality of third waveguide cores disposed between the section of the first waveguide core and the section of the second waveguide core. The plurality of third waveguide cores are positioned inside the opening in the second dielectric layer, the first dielectric layer comprises a first material with a first refractive index, and the second dielectric layer comprises a second material with a second refractive index different from the first refractive index.
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
92.
INTEGRATED CIRCUIT STRUCTURE IN POROUS SEMICONDUCTOR REGION AND METHOD TO FORM SAME
Embodiments of the disclosure provide a structure including a semiconductor substrate. The semiconductor substrate includes a porous semiconductor region, the porous semiconductor region including a cavity. The cavity includes a semiconductor layer therein. The porous semiconductor further includes a device. The device includes a first well at least partially in the semiconductor layer and a second well at least partially in the semiconductor layer and positioned laterally immediately adjacent the first well. The device further includes a first doped region abutting the first well; and a second doped region abutting the second well, wherein the first well and the second doped region have a first type conductivity and the second well and the first doped region having a second type conductivity that is different from the first type conductivity.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
The present disclosure relates to semiconductor structures and, more particularly, to high performance silicon controlled rectifier (SCR) devices and methods of manufacture. The structure includes: a first well in a semiconductor substrate; a second well in the semiconductor substrate, adjacent to the first well; and a porous semiconductor region extending in the first well and the second well.
A reticle includes a body having a single-use illumination field. The single-use illumination field defines a layer including: a plurality of integrated circuit (IC) die clusters, each of the plurality of IC die clusters including a plurality of IC dies separated by a first scribe line having a first width. The plurality of IC die clusters are arranged in juxtaposition on the body and are separated by a second scribe line having a second width larger than the first width. The IC die clusters each have a same number of IC dies and a same area. There may be a different number of IC dies in an X direction than in a Y direction. The wider scribe lines are configured to include all optical or electrical test structures, and minimize effective die area. A wafer formed using the reticle and a method of forming the reticle are also provided.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
G03F 1/44 - Aspects liés au test ou à la mesure, p.ex. motifs de grille, contrôleurs de focus, échelles en dents de scie ou échelles à encoches
G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p.ex. correction par deuxième itération d'un motif de masque pour l'imagerie
95.
SEMICONDUCTOR STRUCTURE WITH DEVICE INCLUDING AT LEAST ONE IN-WELL POROUS REGION
Disclosed are embodiments of a structure including a semiconductor layer and a device, which has a well region within the semiconductor layer and at least one porous region within and shallower in depth than the well region. In some embodiments, the device can be a field effect transistor (FET) (e.g., a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFETs)) with a drain drift region that extends through the well region around the porous region(s) to a drain region. The porous region(s) can modify the electric field in this drain drift region, thereby improving device performance. Embodiments can vary with regard to the number, size, shape, configuration, etc. of the porous region(s) within the well region. Also disclosed herein are method embodiments for forming the semiconductor structure.
A structure provides a defect sensor for a cavity in an integrated circuit (IC). The structure includes a cavity defined in a substrate. A boundary is located where the cavity meets with a cavity-free area of the substrate. A metal line is arranged in a serpentine path in both a vertical and a horizontal direction and crosses the boundary. A controller may be provided that is configured to, in response to a change in an electrical characteristic of a signal through the metal line, generate an indication of the presence of a defect and/or change operation of at least one component of the IC. The structure may find application relative to a photonics integrated circuit (PIC) structure including an optical waveguide with a cavity under the optical waveguide.
G01R 31/28 - Test de circuits électroniques, p.ex. à l'aide d'un traceur de signaux
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
97.
SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
Disclosed is a semiconductor structure including a substrate with a first type conductivity (e.g., a P-silicon substrate); a deep well region within the substrate and having a second type conductivity (e.g., a deep Nwell); alternating stripes of first and second well regions (e.g., of Pwells and Nwells with each Pwell positioned laterally between and abutting two Nwells) within the substrate above and traversing the deep well region; and an isolation region (e.g., an Nwell-type isolation region) dividing a first well region (e.g., a Pwell) into sections. Since the sectioned first well region has the first type conductivity and since the isolation region, the deep well region below, and the adjacent well regions on either side have the second type conductivity, the different sections of the sectioned well region are electrically isolated and devices formed on an insulator layer above the different sections can be subjected to different back-biasing conditions.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
The present disclosure relates to semiconductor structures and, more particularly, to a device with workfunction metal in a drift region and methods of manufacture. The structure includes: a gate structure having at least a first workfunction metal in a channel region and a second workfunction metal, which is different from the first workfunction metal, in a trench in a drift region; and a sidewall spacer adjacent to the gate structure within the trench in the drift region.
Disclosed are a sense circuit and memory structure incorporating the sense circuit. The sense circuit is connected to voltage rails at VDD1 and VDD2, respectively, where VDD2˜½*VDD1. During a sensing operation, VDD1 provides power to develop a voltage differential between Vdata and Vref on sense nodes. A voltage comparator samples Vdata and Vref and, based on a detectable voltage differential (minVdiff), outputs a data output value. To increase the speed at which minVdiff is reached, an equalization process is performed at the initiation of the sensing operation and includes using pre-charge transistors to quickly equalize the sense nodes to VDD2. Following equalization, Vdata and Vref only need to be pulled up or down from VDD2. Thus, minVdiff is reached faster and sampling by the voltage comparator can be performed earlier in time, reducing the overall time required for performing the sensing operation and for powering the sense circuit.
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
100.
FERROELECTRIC MEMORY DEVICE WITH MULTI-LEVEL BIT CELL
A ferroelectric memory device includes a substrate including a source region and a drain region, and a gate structure disposed over the substrate. The gate structure includes a gate electrode including a plurality of electrode portions arranged in a first direction parallel to a top surface of the substrate, an oxide layer including a plurality of oxide portions corresponding respectively to the plurality of electrode portions, and a ferroelectric layer disposed between the gate electrode and the oxide layer along a second direction perpendicular to the first direction and including a plurality of ferroelectric portions corresponding respectively to the plurality of oxide portions. A least one of the plurality of oxide portions and at least one of the plurality of ferroelectric portions have different thicknesses along the second direction.
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
brevets
