A memory sub-system, having: a host interface; memory cells having a storage capacity; and a controller configured to provide data storage services over the host interface using the storage capacity. The controller is configured to provide, in a log file, information related to garbage collection, such as a current usage level of the memory cells, a target usage level of the memory cells which when reached can trigger garbage collection in the memory sub-system, planned targets of garbage collection when the target usage level is reached. A host system can extract information from the log file to schedule and perform operations to reduce garbage collection in the memory sub-system.
Semiconductor devices including thermally conductive structures are disclosed herein. A heat transfer structure may be thermally coupled to a semiconductor device and directly attached to a signaling layer of a substrate. The heat transfer structure may be configured to remove thermal energy from the semiconductor device and transfer at least a portion of the removed thermal energy directly into the signaling layer for dissipation within the substrate, for transfer through the substrate and out of a corresponding apparatus, or a combination thereof.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
Various aspects of the present disclosure relate to adaptive memory device partition closure. In some aspects, a memory device may open a partition comprising a plurality of sets of memory cells. The memory device may program one or more sets of memory cells of the plurality of sets of memory cells. The memory device may update, based on an aggregated drive temperature, an accumulated value that is reflective of one or more physical parameters of the one or more sets of memory cells. The memory device may determine whether the accumulated value satisfies a threshold criterion. The memory device, responsive to determining that the accumulated value satisfies the threshold criterion, may close the partition.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
4.
PHASE-TO-PHASE MISMATCH REDUCTION IN A CLOCK CIRCUIT OF A MEMORY DEVICE
A memory device may include memory cell array a clock circuit configured to generate a plurality of clock signals for access operations associated with the memory cell array. The clock circuit may include a ring oscillator circuit that is configured to equalize phase distortions of the plurality of clock signals.
Schedule Operations of a Host System to Reduce Garbage Collection in a Data Storage Device with Minimal Communications Outside of Protocol for Flexible Direct Placement
A host system having at least one processing device to execute instructions configured to implement a garbage collection manager, which can: compute, based on write commands sent from the host system to the memory sub-system according to a protocol of flexible direct placement (FDP) to store data of storage space tenants, an indicator of usage level of reclaim units in the memory sub-system; identify, in response to a determination that the indicator meets a condition, at least one reclaim unit in the memory sub-system having valid data; and communicate with the storage space tenants having the valid data in the at least one reclaim unit to cause the storage space tenants to perform operations that reduce garbage collection in the memory sub-system in reclaiming storage resources of the at least one reclaim unit.
A memory device includes an array of memory cells, a plurality of access lines, and a controller. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line is connected to a respective memory cell of each string of series-connected memory cells. The controller is configured to access the array of memory cells to program a selected memory cell of the array of memory cells connected to a first access line of the plurality of access lines. The selected memory cell is within a selected string of the plurality of strings of series-connected memory cells. The controller is further configured to, during a program operation, bias the first access line to a first voltage level and bias remaining access lines of the plurality of access lines to reduce the flow of residue electrons within the selected string to the selected memory cell.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
Aspects of the present disclosure are directed to a memory sub-system with isothermal cooling of components. A PCB assembly may be secured between a heat spreader and a heat sink that are thermally coupled. The heat sink radiates heat absorbed from both sides of the PCB assembly. By connecting the heat spreader to the heat sink, heat is more effectively transferred from the side of the PCB assembly not directly connected to the heat sink. The PCB assembly may be secured between a top enclosure and a bottom enclosure. The top enclosure and the bottom enclosure may be thermally coupled using a vapor chamber. The vapor chamber pumps heat from a higher-temperature side of the PCB assembly to a lower-temperature side of the PCB assembly. By using the vapor chamber to thermally couple the top and bottom enclosures, creation of hot spots is avoided.
A memory array comprising strings of memory cells comprises laterally-spaced memory-blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above conductor material of a conductor tier. Channel-material-string constructions extend through the insulative and conductive tiers to a lowest of the conductive tiers. The channel-material-string constructions comprise a charge-blocking-material string, a storage-material string laterally-inward of the charge-blocking-material string, a charge-passage-material string laterally-inward of the storage-material string, and a channel-material string laterally-inward of the charge-passage-material string. A lowest surface of the charge-blocking-material string that is above a lowest surface of the lowest conductive tier is below a lowest surface of a lowest of the insulative tiers that is immediately-above the lowest conductive tier. Conductive material in the lowest conductive tier directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Structure independent of method is disclosed.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
9.
APPARATUSES, SYSTEMS, AND METHODS FOR STORING ERROR INFORMATION AND PROVIDING RECOMMENDATIONS BASED ON SAME
Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.
Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; determining a read level adjustment as a function of a sequential number of a margin valley corresponding to the read level voltage; and adjusting the read level voltage by applying, to the read level voltage, the read level adjustment.
A variety of applications can include memory devices having strings of memory cells, where a string of memory cells is coupled to a stack of drain-side select gate (SGD) transistors. The threshold voltages of the SGD transistors can be tuned to a sequence of threshold voltages by a high-k dielectric liner adjacent to and contacting selected one or more SGD transistors of the stack. Additional devices, systems, and methods are discussed.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
Apparatuses, systems, and methods for algorithm qualifier commands are described according to embodiments of the present disclosure. One example method can include executing an algorithm qualifier command on a memory device and performing an operation on the memory device for a command sequence that follows the algorithm qualifier command using a number of settings indicated by the algorithm qualifier command. The algorithm qualifier command can indicate a number of settings to use while performing the operation on the memory device.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
A memory device includes a memory array and control logic, operatively coupled with the memory array, configured to identify an operation associated with at least one high current breakpoint, reconfigure the at least one high current breakpoint as at least one low current breakpoint, and in response to reconfiguring the at least one high current breakpoint as the at least one low current breakpoint, cause the operation to be executed. The at least one high current breakpoint corresponds to a point in time during execution of the operation at which more current is to be reserved to continue execution of the operation. The at least one low current breakpoint corresponds to a point in time during execution of the operation at which no more current is to be reserved to continue execution of the operation.
A memory device includes memory dies, a first memory die of the memory dies including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations including receiving a token from another memory die, in response to receiving the token, determining whether to reserve a data window during a token circulation time period having a first size determined based on a common clock signal shared among the memory dies and, in response to determining to reserve the data window, causing the data window to be reserved. The data window has a second size different from the first size determined based on the common clock signal. The operations further include causing a data frame to be generated within the data window. The data frame has a third size determined from the second size and includes current consumption information for the memory device.
Methods, systems, and devices for methods for data prioritization in memory are described. A memory device may be configured to prioritize data such that high-priority data may remain in a cache to await operations while low-priority data may be transferred to higher‑latency memory. For example, the memory device may receive a command to write data associated with one or more user operations to the memory system. The memory device may also receive an indication associated with the data that indicates to the memory device that the data is high priority. The memory device may store the data in a cache of the memory device to await operations. In response to a trigger, the memory device may transfer data not associated with the indication from the cache to multi-level memory cells (MLCs) of the memory device, such that the high-priority files may remain in the cache.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
16.
WEAR LEVELING IN A ZONED NAMESPACE MEMORY SUB-SYSTEM
A memory device comprises multiple quad-level cell (QLC) block sets and multiple single-level cell (SLC) block sets. A processing device allocates an SLC block set from the multiple SLC block sets for storing data. The allocating of the SLC block set comprises selecting the SLC block set from the multiple SLC block sets based on a program/erase cycle count of the SLC block sets. Based on detecting a migration trigger condition, the processing device allocates a QLC block set from the multiple QLC block sets to store the data and migrates the data from the SLC block set to the QLC block set. Based on migrating the data from the SLC block set to the QLC block set, the processing device releases the SLC block set.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
A memory device comprises multiple planes and each plane comprises multiple blocks. A processing device coupled to the memory device identifies good blocks in each plane of the memory device. The processing device generates multiple block sets by grouping the good blocks. Each block set comprises two blocks. The processing device generates a block set by grouping a first block from a first plane with a second block from a second plane.
Systems and methods related to testing of designs for system-in-packages (SiP) comprising high-bandwidth memory (HBM) and system on a chip (SOC) devices are discussed herein. Live HBM devices may be used in combination with a silicon bridge to form a proxy SiP device. The silicon bridge has the same size and shape as the SOC that it replaces. The differences in electrical properties between the proxy and the actual SiP are reduced by using the silicon bridge instead of connecting the HBMs through the substrate. By comparison with using a live SOC, using the silicon bridge reduces the cost of producing the proxy. An external testing device may be coupled to access pins of the proxy SiP device and execute one or more tests.
A variety of applications can include one or more memory devices comprising an array of pillars of memory cells, where the memory cells are stacked in a vertical direction within the pillars and the array of pillars are organized in blocks. Separation regions between blocks can be defined by spacing of a single row of pillars, except for a number of dedicated separation regions providing spacing defined by three rows of pillars.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
20.
VENDOR SPECIFIC SUB BLOCK ACCESS ACCORDING TO SUB BLOCK DESCRIPTOR
A memory sub-system, having: a host interface configured to operate on a computer bus; non-volatile memory cells; and a controller to store, in a vendor specific log page, data indicating that the memory sub-system supports sub block access and providing a sub block granularity level for the sub block access. After receiving, from the host system, an access command with a sub block descriptor configured to identify a portion of a logical block identified by the access command, the controller is to transfer, over the computer bus according to an opcode provided in the access command, data for the portion of the logical block without transferring over the computer bus data of the logical block outside of the portion of the logical block identified by the sub block descriptor.
A computing device including a memory sub-system having storage resources organized in reclaim units, and a host system coupled to the memory sub-system to write data into the reclaim units. The host system is configured to: monitor a usage level of the reclaim units; start, responsive to the usage level reaching a first level, operations configured to reduce valid data stored in a reclaim unit allocated as storage media of a set of logical addresses; and complete, before the usage level reaching a second level, the operations. The memory sub-system is configured to refrain, before the usage level reaching the second level, from copying valid data from the reclaim unit to outside of the reclaim unit for erasure of the unit of storage resources.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
22.
SCHEDULE OPERATIONS OF A HOST SYSTEM TO REDUCE GARBAGE COLLECTION IN A DATA STORAGE DEVICE WITH MINIMAL COMMUNICATIONS OUTSIDE OF PROTOCOL FOR FLEXIBLE DIRECT PLACEMENT
A host system having at least one processing device to execute instructions configured to implement a garbage collection manager, which can: compute, based on write commands sent from the host system to the memory sub-system according to a protocol of flexible direct placement (FDP) to store data of storage space tenants, an indicator of usage level of reclaim units in the memory sub-system; identify, in response to a determination that the indicator meets a condition, at least one reclaim unit in the memory sub-system having valid data; and communicate with the storage space tenants having the valid data in the at least one reclaim unit to cause the storage space tenants to perform operations that reduce garbage collection in the memory sub-system in reclaiming storage resources of the at least one reclaim unit.
A memory sub-system, having: a host interface operatable on a computer bus; a non-volatile memory; and a controller. In response to a request to create a first namespace, the controller create the first namespace and a second namespace having a same storage capacity as the first namespace. The first namespace has a first granularity level; and the second namespace has a second granularity level different from the first granularity level. The first namespace and the second namespace represent a storage capacity provided by a same set of storage resources in the memory sub-system. The controller maintains a mapping between logical addresses defined in the first namespace and physical addresses of the set of storage resources, and process access to addresses in the second namespace via the mapping between logical addresses defined in the first namespace and physical addresses of the set of storage resources.
Various aspects of the present disclosure relate to adaptive memory device partition closure. In some aspects, a memory device may open a partition comprising a plurality of sets of memory cells. The memory device may program one or more sets of memory cells of the plurality of sets of memory cells. The memory device may update, based on an aggregated drive temperature, an accumulated value that is reflective of one or more physical parameters of the one or more sets of memory cells. The memory device may determine whether the accumulated value satisfies a threshold criterion. The memory device, responsive to determining that the accumulated value satisfies the threshold criterion, may close the partition.
An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can include row hammer detection circuitry configured to receive signaling indicative of a row activation command having a row address, increment a row counter corresponding to the row address stored in a stored in a data structure in a register or storage device, determine whether the incremented row counter is greater than a row hammer threshold, and issue a row hammer mitigation command to mitigate row hammer.
G11C 11/4078 - Circuits de sécurité ou de protection, p. ex. afin d'empêcher la lecture ou l'écriture intempestives ou non autoriséesCellules d'étatCellules de test
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
26.
Asynchronous Event Reporting for Coordination of Operations of a Host System to Reduce Garbage Collection in a Data Storage Device
A memory sub-system having: a host interface; memory cells erasable for programming to store data; and a controller configured to provide data storage services over the host interface using a storage capacity of the memory cells. The controller is configured to: monitor an indicator of usage level of memory cells ready for programming in the memory sub-system; determine that the indicator being monitored by the memory sub-system satisfies a first condition; and send, via the host interface and responsive to the indicator satisfying the first condition, an asynchronous event notice representative of a request for a host system to perform operations to reduce garbage collection in the memory sub-system.
Systems and methods related to testing of designs for system-in-packages (SiP) comprising high-bandwidth memory (HBM) and system on a chip (SOC) devices are discussed herein. Live HBM devices may be used in combination with a silicon bridge to form a proxy SiP device. The silicon bridge has the same size and shape as the SOC that it replaces. The differences in electrical properties between the proxy and the actual SiP are reduced by using the silicon bridge instead of connecting the HBMs through the substrate. By comparison with using a live SOC, using the silicon bridge reduces the cost of producing the proxy. An external testing device may be coupled to access pins of the proxy SiP device and execute one or more tests.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
28.
APPARATUS INCLUDING GATE STRUCTURE ON SEMICONDUCTOR SUBSTRATE
Some embodiments of the disclosure provide an apparatus comprising a gate structure on a semiconductor substrate and a liner on a side wall of the gate structure. The side wall of the gate structure include a first spacer and a second spacer on the first spacer. The second spacer has a top portion lower than a top portion of the first spacer. The liner covers at least the second spacer including the top portion thereof.
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
29.
MULTIPLE PROCESSING UNIT COMMUNICATIONS USING ZERO-COPY PINNED COMPUTE EXPRESS LINK MEMORY
In some implementations, a compute express link (CXL) compliant memory system may configure a portion of a memory as a shared memory region directly accessible by multiple fabric-attached processing units. The CXL compliant memory system may establish, with a first and second fabric-attached processing unit, a first and second device direct access link, respectively, to the shared memory region. The CXL compliant memory system may receive, via the first device direct access link and from the first fabric-attached processing unit, communication information associated with communications between the multiple fabric-attached processing units. The CXL compliant memory system may store the communication information in the shared memory region. The CXL compliant memory system may permit, via the second device direct access link and by using a zero-copy operation, access to the communication information by the second fabric-attached processing unit.
An example apparatus includes a substrate; a first region on the substrate; a second region on the substrate different from the first region; at least one first transistor provided in the first region; at least one second transistor provided in the second region different from the first transistor; a first stress film covering over the first transistor; and a second stress film covering over the second transistor; wherein stress of the first stress film is different from stress of the second stress film.
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
31.
REDUCING READ OPERATIONS DURING READ ERROR HANDLING IN A MEMORY DEVICE
A plurality of read operations is performed on encoded host data stored in a memory device using the plurality of read voltage level adjustments to obtain current sensed data responsive to initiating an auto-read calibration operation comprising a plurality of read voltage level adjustments. A previous sensed data is obtained from a previous one of the plurality of read operations performed on the encoded host data using a previous read voltage level adjustment. One or more flipped bits of the current sensed data is identified based on the previous sensed data and the current sensed data. A likelihood value is assigned to the one or more flipped bits. Soft-decision decoding is performed on the encoded host data responsive to completion of the auto-read calibration, performing, using the assigned likelihood value.
An enclosure to at least partially enclose a memory sub-system within an interior of the enclosure. The enclosure includes a first enclosure portion including a first recessed portion. The enclosure further includes a first set of one or more heat pipes arranged within the first recessed portion. The enclosure further includes a second enclosure portion including a second recessed portion. The enclosure further includes a second set of one or more heat pipes arranged within the second recessed portion, where the first enclosure portion and the second enclosure portion form a cavity to house a memory sub-system, and where heat generated by the memory sub-system is conducted via the first set of one or more heat pipes and the second set of one or more heat pipes to a first end of the enclosure.
An apparatus, comprising a plurality of memories and a single integrated circuit (IC) that is configured to be coupled to a host device by a host bus and that is coupled to the plurality of memories by a memory bus, wherein the IC comprises a logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the plurality of memories, and a power management integrated circuit (PMIC) module that is configured to regulate voltage and monitor current provided to the plurality of memories.
A method includes identifying a logical address of a logical address space, translating the logical address to a set of physical addresses of a physical address space by using a set of translation functions, the set of translation functions including a position address translation function that translates the logical address to a position address of the set of physical addresses based on a cardinality of a set of datacache sections, and a section address translation function that translates the logical address to a section address of the set of physical addresses based on the cardinality of the set of datacache sections, and causing, using the position address and the section address, the set of datacache sections to process a set of media access operations in parallel, each media access operation of the set of media access operations corresponding to a respective datacache section of the set of datacache sections.
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
G06F 12/0844 - Accès à une mémoire cache à accès multiples simultanés ou quasi-simultanés
A system includes memory having a bank area and a channel area. The system further includes control circuitry to receive a command to access the memory. Responsive to receiving the command to access the memory, the control circuitry can provide a bank strobe signal for accessing memory in the bank area and at least two channel strobe signals for accessing memory in the channel area. The channel strobe signal may process a smaller amount of data than that processed by the bank strobe signal.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
Methods, systems, and devices for mitigating memory die misalignment are described. A memory system may receive a command to write data to a memory device including a memory die. The memory system may determine whether the data indicated by the command (e.g., a first set of data) satisfies a threshold size. If the first set of data satisfies the threshold size, the memory system may determine whether data currently in a write buffer aligns with a boundary of the memory die. For example, depending on the data currently in the buffer, adding the first set of data to the buffer may result in die misalignment for the first set of data. To mitigate die misalignment, the memory system may pad data (e.g., add dummy data) to the write buffer, such that the padding aligns the data with the die boundary.
A bonded semiconductor structure including a product wafer having a first metal layer disposed on a first frontside surface of the product wafer, and a carrier wafer having a second metal layer disposed on a second frontside surface of the carrier wafer and a third metal layer disposed under the second metal layer, wherein the first metal layer is bonded to the second metal layer by metal-metal bonds disposed at a bonding interface between the first frontside surface and the second frontside surface, and wherein the third metal layer includes a corrosion portion extending from an edge of the carrier wafer to a center of the carrier wafer.
B32B 43/00 - Opérations spécialement adaptées aux produits stratifiés et non prévues ailleurs, p. ex. réparationAppareils pour ces opérations
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
38.
FACILITATING WAFER DEBONDING BY INTRODUCING MOISTURE TO BONDING INTERFACE
A semiconductor wafer including a first dielectric layer disposed on top of the semiconductor wafer, the first dielectric layer having a first frontside surface, a second dielectric layer embedded in the first dielectric layer, the second dielectric layer containing moisture and having a second frontside surface horizontally aligned with the first frontside surface, and oxygen covalent dangling bonds and hydroxide dangling bonds disposed on the first frontside surface and the second frontside surface. Another semiconductor wafer including a first dielectric layer disposed on top of the semiconductor wafer, the first dielectric layer having a frontside surface, a second dielectric layer disposed underneath the first dielectric layer, the second dielectric layer containing moisture, and oxygen covalent dangling bonds and hydroxide dangling bonds disposed on the frontside surface.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
39.
METHODS AND APPARATUS FOR USING SPACER-ON-SPACER DESIGN FOR SOLDER JOINT RELIABILITY IMPROVEMENT IN SEMICONDUCTOR DEVICES
A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
40.
Heterogeneous Accelerators Connected via a Time Sensitive Networking Bus
An apparatus having: a time sensitive networking bus; a plurality of accelerators connected to the time sensitive networking bus to accelerate multiplication and accumulation operations; and a plurality of components connected to the time sensitive networking bus. The components are configured to: run a plurality of applications; generate, in the applications, tasks of multiplication and accumulation operations; assign the tasks to the accelerators; and allocate virtual channels over the time sensitive networking bus from the applications to the accelerators based on timing data of the applications.
A memory device can include a memory array and control logic, operatively coupled with the memory array, to perform operations including identifying a first base state information bin associated with a first index value and a second base state information bin associated with a second index value, determining a third index value based on the first index value and the second index value, assigning a target cell of the memory array to a target cell state information bin associated with the third index value, and causing the target cell, assigned to the target cell state information bin, to be read.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A microelectronic device includes a boron-doped semiconductor material, a stack structure, slot structures, and cell pillar structures. The boron-doped semiconductor material is vertically above a lateral contact material. The stack structure is vertically above the boron-doped semiconductor material and includes blocks horizontally extending in parallel in a first direction and individually having tiers respectively including conductive material and insulative material vertically neighboring the conductive material. The slot structures vertically extend through the stack structure, the boron-doped semiconductor material, and the lateral contact material. The slot structures horizontally alternate with the blocks of the stack structure in a second direction orthogonal to the first direction. The cell pillar structures respectively include semiconductor material in contact with the lateral contact material and vertically extending through each of the lateral contact material, the boron-doped semiconductor material, and the stack structure. Related methods and memory devices are also described.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10N 79/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comportant au moins un élément couvert par le groupe
In some implementations, a device may obtain a command table associated with a memory device, wherein the command table includes one or more entries associated with one or more respective commands, and wherein each entry, from the one or more entries, includes one or more units of data. The device may receive an indication of a modification associated with a first command, wherein the first command indicates a sequence of a first one or more units of data. The device may modify the command table based on the modification associated with the first command, wherein modifying the command table includes at least one of: adding an entry, that indicates the sequence, to the one or more entries to indicate the first command, or removing the entry from the one or more entries. The device may provide, to a controller of the memory device, an indication of the command table.
A system includes a plurality of memory components; and a processing device, operatively coupled with the plurality of memory components, to perform operations including: receiving, from a host system, a request to read data stored on the plurality of memory components; determining that the data contains a plurality of errors; identifying a plurality of locations of the plurality of errors, wherein each location of plurality of locations corresponds to a respective error of the plurality of errors; responsive to determining that the plurality of locations falls in a single memory component of the plurality of memory components, excluding the single memory component from future decoding and correcting the data to generate corrected data; sending, to the host system, the corrected data; and including the single memory component for future decoding.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
45.
SUB BLOCK DESCRIPTOR FOR STORAGE ACCESS AT SUB BLOCK LEVEL
A memory sub-system, having: a host interface configured to operate on a computer bus; non-volatile memory cells; and a controller. In response to a command to identify information about the memory sub-system, the controller is to provide structured data indicating that the memory sub-system supports sub block access and specifying a sub block granularity level for the sub block access. In response to an access command with a sub block descriptor embedded within the access command, the controller is to determine, based on the sub block descriptor provided within the access command, a portion of a logical block identified by the access command and implemented using a subset of the non-volatile memory cells. An operation is performed on the portion of the logical block according to an opcode specified by the access command.
Methods, systems, and devices for memory architectures with partially filled piers are described. A stack of materials including alternating layers of nitride and oxide may be formed, and piers and pillars may be formed through the stack of materials. Layers of nitride may be etched for metallization and one or more piers may be removed, which may result in corresponding cavities being formed in the stack of materials. Memory cells may be formed between one or more pillars and corresponding electrodes, and the cavities (e.g., the cavities resulting from removing one or more piers) may be partially filled with a dielectric material such that an air gap is formed within the cavity, or with a low-k dielectric material, or both.
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Methods, systems, and devices for charge loss weak die identification are described. The described techniques provide for a memory system to avoid sampling, during block family (BF) scans, blocks of memory cells associated with memory dies that are classified as read disturb charge loss (RDCL) weak dies. The memory system may identify a memory die as being an RDCL weak die based on a threshold quantity of blocks associated with the memory die experiencing relatively high charge loss. If the quantity satisfies a threshold value, the memory system may classify the memory die as an RDCL weak die and the memory system may refrain from selecting blocks from a BF that are associated with a memory die classified as an RDCL weak die.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
The present disclosure configures a memory sub-system controller to read virtual blocks using partial good block (PGBs) across different planes using different read voltages. The controller identifies a region of a set of memory components, the region comprising a plurality of planes across a plurality of decks of the set of memory components. The controller generates an individual virtual block (VB) using a first PGB on a first deck of the plurality of decks of the region associated with a first plane of the plurality of planes and a second RGB on a second deck of the plurality of decks associated with the first plane. The controller, in response to receiving the request to read the data, applies a first read voltage offset to read the individual VB from the first plane in parallel with applying a second read voltage offset to read an additional VB from a second plane.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
49.
FACILITATING WAFER DEBONDING BY INTRODUCING MOISTURE TO BONDING INTERFACE
A semiconductor wafer including a first dielectric layer disposed on top of the semiconductor wafer, the first dielectric layer having a first frontside surface, a second dielectric layer embedded in the first dielectric layer, the second dielectric layer containing moisture and having a second frontside surface horizontally aligned with the first frontside surface, and oxygen covalent dangling bonds and hydroxide dangling bonds disposed on the first frontside surface and the second frontside surface. Another semiconductor wafer including a first dielectric layer disposed on top of the semiconductor wafer, the first dielectric layer having a frontside surface, a second dielectric layer disposed underneath the first dielectric layer, the second dielectric layer containing moisture, and oxygen covalent dangling bonds and hydroxide dangling bonds disposed on the frontside surface.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
50.
CORROSION-SUSCEPTIBLE BONDING LAYER IN ASSISTING SEMICONDUCTOR WAFER DEBONDING
A bonded semiconductor structure including a product wafer having a first metal layer disposed on a first frontside surface of the product wafer, and a carrier wafer having a second metal layer disposed on a second frontside surface of the carrier wafer and a third metal layer disposed under the second metal layer, wherein the first metal layer is bonded to the second metal layer by metal-metal bonds disposed at a bonding interface between the first frontside surface and the second frontside surface, and wherein the third metal layer includes a corrosion portion extending from an edge of the carrier wafer to a center of the carrier wafer.
The present disclosure includes apparatuses and methods related to temperature compensation of voltage-controlled oscillators (VCOs). An example method includes performing a sweep of biasing voltage steps applied to an auxiliary varactor of a voltage-controlled oscillator (VCO) of a phase locked loop (PLL). For each of a plurality of the biasing voltage steps corresponding to the sweep: determining a frequency difference between a reference clock signal of the PLL and a VCO clock; and determining a difference between the determined frequency differences for the corresponding biasing voltage step and a different one of the plurality of biasing voltage steps. The method can include selecting a particular one of the plurality of biasing voltage steps as a target biasing voltage for the auxiliary varactor based on the calculated differences.
A microelectronic device comprises a source material adjacent to tiers of alternating conductive materials and dielectric materials. Interconnect structures extend through the tiers and into the source material. The interconnect structures comprises a dielectric liner adjacent to the tiers and the source material, a first interconnect liner adjacent to the dielectric liner, and a conductive fill material extending between opposing surfaces of the first interconnect liner. Contact structures within the source material are electrically coupled to the interconnect structures and the contact structures comprise a conductive barrier material adjacent to the interconnect structures, a metal nitride material adjacent to the conductive barrier material, and a conductive contact material adjacent to the metal nitride material. The conductive fill material of the interconnect structures is in electrical contact with the conductive barrier material of the contact structures. Additional microelectronic devices and methods of forming the microelectronic devices are disclosed.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
53.
ADAPTIVE BLOCK FAMILY ERROR AVOIDANCE IN A MEMORY SUB-SYSTEM
A system includes a memory device and a processing device operatively coupled with the memory device to perform operations including receiving a read command specifying a logical address; translating the logical address into a physical address referencing a physical block stored on the memory device; identifying a wordline group associated with the physical address; identifying, based on block family metadata associated with the memory device, a block family associated with the physical block and the wordline group; determining a first threshold voltage offset associated with the block family; and reading, using the first threshold voltage offset, data from the physical block.
G11C 29/52 - Protection du contenu des mémoiresDétection d'erreurs dans le contenu des mémoires
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
54.
APPARATUSES AND METHODS TO REFRESH MEMORY INCLUDING MEMORY BANKS
Apparatuses and methods for a refresh operation performed on a memory bank from a subset of memory of memory bank groups in a high bank-count memory device. The memory banks may be divided into memory bank groups. The memory device may receive an external refresh command. The refresh command may indicate that a memory bank from each of the memory bank groups is to be refreshed (e.g., a same bank refresh operation) rather than refreshing all of the memory banks of all the memory groups (e.g., an all bank refresh operation). Responsive to the refresh command and a mode register setting further indicating that a smaller subset is to be refreshed (e.g., a same bank subset refresh operation), the refresh control circuit will refresh a memory bank from a subset of memory bank groups. As a result, the number of available memory banks during a refresh operation increases.
A variety of applications can include one or more memory devices comprising an array of pillars of memory cells, where the memory cells are stacked in a vertical direction within the pillars and the array of pillars are organized in blocks. Separation regions between blocks can be defined by spacing of a single row of pillars, except for a number of dedicated separation regions providing spacing defined by three rows of pillars.
The present disclosure configures a memory sub-system controller to read virtual blocks using partial good block (PGBs) across different planes using different read voltages. The controller identifies a region of a set of memory components, the region comprising a plurality of planes across a plurality of decks of the set of memory components. The controller generates an individual virtual block (VB) using a first PGB on a first deck of the plurality of decks of the region associated with a first plane of the plurality of planes and a second PGB on a second deck of the plurality of decks associated with the first plane. The controller, in response to receiving the request to read the data, applies a first read voltage offset to read the individual VB from the first plane in parallel with applying a second read voltage offset to read an additional VB from a second plane.
Methods, systems, and devices for read disturb management for memory are described. In some instances, data may be read from a first page of a virtual block of a memory system. If the data includes one or more errors, the memory system may read data from a second page of the virtual block and determine whether one or more errors exist in the data. The memory system may continue reading pages of the virtual block until a page includes no (or relatively few errors). The memory system may then refresh the pages.
Methods, systems, and devices for techniques for memory zone size adjustment are described. A memory system may dynamically update the size of a stale zone configured to store data written during a write burst or write booster mode. The stale zone may be part of a first block of memory cells, and may retain data during a transfer operation, such as flush operation. The size of the stale zone may be updated in response to the memory system receiving a command, such as an unmap command. The size of the stale zone may be determined based on an available zone size, an amount of data indicated in the command, an amount of data indicated in the command that has been transferred to a second block of memory cells, or a combination thereof.
A training operation may be performed by a memory controller to provide a system clock signal and a data clock signal having a desired temporal (e.g., phase) relationship to one another. The system clock and data clock signals may be provided to a memory. In some examples, the memory controller may provide a command to the memory to put the memory in a training mode. Once in the training mode, the memory controller may provide a write command and toggle the data clock signal a number of times. If the memory provides one output, the memory controller may adjust the relationship between the data clock and system clock signals. If the memory provides another output, the memory controller may maintain the relationship between the data clock and system clock signals and exit the training mode.
An improved memory module and methods for constructing the same are disclosed herein. The memory module includes a substrate having a first surface and a second surface opposite the first surface, each having a central portion, a first array area and a second array area. The first array area is cooler than the second array area during operation. The memory module also includes a power management integrated circuit attached to the central portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array area. The first semiconductor die has a first performance rating of an operating parameter at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array area. The second semiconductor die has a second performance rating of an operating parameter better than the first performance rating at high temperatures.
H01L 23/467 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de gaz, p. ex. d'air
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
61.
PAGE REQUEST INTERFACE SUPPORT IN CACHING HOST MEMORY ADDRESS TRANSLATION DATA IN A MEMORY SUB-SYSTEM
A system includes a controller memory, coupled to host interface circuits, to store a host request queue to buffer a page request group of page miss requests associated with page miss messages received from a host interface circuit and an outbound queue to buffer memory commands directed to a host system. An outbound buffer buffers page request groups received from the host request queue and the memory commands received from the outbound queue. An outbound queue handling logic determines the outbound buffer contains a first page request group and causes the page miss requests of the first page request group to be sent to a translation agent of the host system, causing the translation agent to re-pin a physical page of memory to each respective virtual address of respective page miss requests.
G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page
G06F 12/123 - Commande de remplacement utilisant des algorithmes de remplacement avec listes d’âge, p. ex. file d’attente, liste du type le plus récemment utilisé [MRU] ou liste du type le moins récemment utilisé [LRU]
62.
ON-PITCH VIAS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED DEVICES AND SYSTEMS
Semiconductor devices with on-pitch vias, and associated systems and methods, are disclosed herein. In one embodiment, the semiconductor device may include a 3-dimensional (3D) cross-point memory array. The semiconductor device also includes access lines for the memory array, which couple with on-pitch vias connected to CMOS circuitry disposed underneath the memory array. In some embodiments, a first access line may be coupled with a first via outside a boundary of the memory array, where the first via is separated from the boundary by a first distance and has a first length longitudinal to the first access line. Further, a second access line may be coupled with a second via outside the boundary, where the second via is separated from the boundary by a second distance greater than the first distance and has a second length longitudinal to the second access line, the second length different from the first length.
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
63.
MEMORY DEVICE HAVING SHARED READ/WRITE DATA LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line, a second data line, a conductive line, and a memory cell coupled to the first and second data lines. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the first and second data lines, and charge storage structure electrically separated from the first region. The second transistor includes a second region electrically separated from the first region, the second region electrically coupled to the charge storage structure and the second data line. The conductive line is electrically separated from the first and second channel regions. Part of the conductive line is spanning across part of the first region of the first transistor and part of the second region of the second transistor.
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
Systems, methods, and apparatuses are provided for unipolar programming of memory cells in a semiconductor device. A memory has a plurality of self-selecting memory cells and circuitry configured to program a self-selecting memory cell of the plurality of self-selecting memory cells to a first data state or a second data state by applying a current pulse to the self-selecting memory cell. The current is a set pulse or a reset pulse. The set pulse and the reset pulse have a same polarity.
A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
66.
SEMICONDUCTOR DIE ASSEMBLIES WITH SIDEWALL PROTECTION AND ASSOCIATED METHODS AND SYSTEMS
Semiconductor die assemblies with sidewall protection, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes an interface die with a low-k dielectric layer and a stack of semiconductor dies attached to the interface die. The semiconductor die assembly also includes a molding structure that protects sidewalls of the interface die and sidewalls of the semiconductor dies. In some embodiments, the semiconductor die assembly includes a passivation layer attached to the interface die opposite to the stack of semiconductor dies. Further, the passivation layer may include a sidewall surface coplanar with an outer sidewall surface of the molding structure. The passivation layer may include a ledge underneath the molding structure, which is uncovered by the interface die. The semiconductor die assembly may include a NCF material at the sidewalls of the stack of semiconductor dies, where the molding structure surrounds the NCF material.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
67.
REPLACEMENT CHANNEL INTEGRATION FOR THREE DIMENSIONAL MEMORY CELL ARCHITECTURES
Methods, systems, and devices for replacement channel integration for three dimensional memory cell architectures are described. A method of manufacturing a memory architecture may include forming a stack of materials above a substrate. Trenches may be formed within the stack of materials, where each trench may include a gate oxide material lining the trench, and pairs of conductive pillars forming gate elements. The gate elements may form word lines associated with activating memory cells of the memory architecture. Another trench may be formed perpendicular to the trenches, and used for forming memory cells each including a selection element and a storage element within sacrificial layers of the stack of materials between the trenches. The trench may form a source line for accessing the memory cells adjacent to the trench. A digit line may be formed around the trenches and may be configured to access the memory cells.
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
68.
APPARATUSES AND METHODS T0 REFRESH MEMORY INCLUDING MEMORY BANKS
Apparatuses and methods for a refresh operation performed on a memory bank from a subset of memory of memory bank groups in a high bank-count memory device. The memory banks may be divided into memory bank groups. The memory device may receive an external refresh command. The refresh command may indicate that a memory bank from each of the memory bank groups is to be refreshed (e.g., a same bank refresh operation) rather than refreshing all of the memory banks of all the memory groups (e.g., an all bank refresh operation). Responsive to the refresh command and a mode register setting further indicating that a smaller subset is to be refreshed (e.g., a same bank subset refresh operation), the refresh control circuit will refresh a memory bank from a subset of memory bank groups. As a result, the number of available memory banks during a refresh operation increases.
A method includes issuing a program command to a logic unit (LUN) of a memory device, writing a plurality of commands to a transfer queue within the memory device, detecting a program failure for the LUN of the memory device, and maintaining a number of the plurality of commands in the transfer queue.
A semiconductor device assembly includes a first semiconductor device having front and rear surfaces, a plurality of front-side pads disposed over the front surface at a first distance from the rear surface, and a plurality of additional device pads disposed over the front surface at a second distance from the rear surface greater than the first distance; a second semiconductor device in contact with a top side of each of the additional device pads; an encapsulant material at least partially surrounding the second semiconductor device and covering a top side of the front-side pads; a first plurality of TSVs, each extending from the rear surface through the first semiconductor device to a bottom side of one of the front-side pads; and a second plurality of TSVs, each extending from the rear surface through the first semiconductor device to a bottom side of corresponding one of the additional device pads.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
Methods, systems, and devices related to field firmware update (FFU). A first memory of a memory module may receive an encrypted segment of a FW package associated with FFU. A decrypted segment of the FW package may be stored by the first memory. A re-encrypted segment of the FW package may be stored by the first memory. The re-encrypted segment of the FW package may be communicated to a second memory of the memory module.
A memory sub-system includes a memory device and one or more processing devices to perform operations. A failure exhibited by a set of memory cells of the memory device is detected. It is determined whether a subset of memory cells of the set of memory cells satisfies a first threshold condition based on a read level voltage corresponding to a per-cell memory density of the memory device. In response to determining that the subset of memory cells satisfies the first threshold condition, a first data recovery operation is selected from a set of data recovery operations. The first data recovery operation is performed on the set of memory cells.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
74.
CROSS-TEMPERATURE COMPENSATION IN A MEMORY SUB-SYSTEM
Control logic in a memory device receives, from a requestor, a request to read data from the memory array, the request comprising an indication of a segment of the memory array where the data is stored and performs, using previously configured read operation parameters, a first read operation to read the data and a write temperature associated with the data from the memory array. The control logic determines whether the previously configured read operation parameters satisfy a temperature criterion and responsive to determining that the previously configured read operation parameters do not satisfy the temperature criterion, configures the memory device with updated read operation parameters, and performs, using the updated read operation parameters, a second read operation to read the data from the memory array.
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
75.
REPLACEMENT CHANNEL INTEGRATION FOR THREE DIMENSIONAL MEMORY CELL ARCHITECTURES
Methods, systems, and devices for replacement channel integration for three dimensional memory cell architectures are described. A method of manufacturing a memory architecture may include forming a stack of materials above a substrate. Trenches may be formed within the stack of materials, where each trench may include a gate oxide material lining the trench, and pairs of conductive pillars forming gate elements. The gate elements may form word lines associated with activating memory cells of the memory architecture. Another trench may be formed perpendicular to the trenches, and used for forming memory cells each including a selection element and a storage element within sacrificial layers of the stack of materials between the trenches. The trench may form a source line for accessing the memory cells adjacent to the trench. A digit line may be formed around the trenches and may be configured to access the memory cells.
Systems, methods, and apparatus for memory management operations in a memory device. In one approach, wear leveling for the memory device is performed using a start-gap algorithm. The wear leveling is implemented using multiple gap locations in a single pool. In response to a memory management command, one or more gap locations and corresponding user data are moved. After moving the user data, one or more pointers to the gap locations are updated. A start location pointer for the pool is updated each time the gap locations complete a cycle of movement in the pool.
Methods, systems, and devices for memory architectures with partially filled piers are described. A stack of materials including alternating layers of nitride and oxide may be formed, and piers and pillars may be formed through the stack of materials. Layers of nitride may be etched for metallization and one or more piers may be removed, which may result in corresponding cavities being formed in the stack of materials. Memory cells may be formed between one or more pillars and corresponding electrodes, and the cavities (e.g., the cavities resulting from removing one or more piers) may be partially filled with a dielectric material such that an air gap is formed within the cavity, or with a low-k dielectric material, or both.
A processing device in a memory sub-system receives a request to generate a digital certificate associated with a memory device including a set of active components, where each active component of the set of active components is associated with an active component identifier. In response to the request, a set of active component identifiers are identified. Based on at least a portion of the set of active component identifiers, the digital certificate associated with the memory device is generated and provided to a host system, where the digital certificate is used to authenticate the memory device
G06F 21/73 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par création ou détermination de l’identification de la machine, p. ex. numéros de série
G06F 21/44 - Authentification de programme ou de dispositif
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
Methods, systems, and devices for improving continuity in memory arrays are described. A stack of materials may be formed into a continuous memory channel and connecting channel. For example, the stack may include a set of oxide layers and metal layers. A first stack may be formed. A pillar may extend through the first stack. A recess may be formed in a first layer of the pillar. A second stack may be formed on top of the first stack and the recess, and a cavity may extend through the second stack. Protective liners may be formed along the cavity and may protect various portions of the stack as materials are removed from the recess, pillar, and cavity to form a single pillar through both stacks. The protective liners may be removed and a conductive liner may be deposited along sidewalls of the pillar to form a continuous conductive channel.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
Methods, systems, and devices for methods for data prioritization in memory are described. A memory device may be configured to prioritize data such that high-priority data may remain in a cache to await operations while low-priority data may be transferred to higher-latency memory. For example, the memory device may receive a command to write data associated with one or more user operations to the memory system. The memory device may also receive an indication associated with the data that indicates to the memory device that the data is high priority. The memory device may store the data in a cache of the memory device to await operations. In response to a trigger, the memory device may transfer data not associated with the indication from the cache to multi-level memory cells (MLCs) of the memory device, such that the high-priority files may remain in the cache.
A memory device comprises multiple quad-level cell (QLC) block sets and multiple single-level cell (SLC) block sets. A processing device allocates an SLC block set from the multiple SLC block sets for storing data. The allocating of the SLC block set comprises selecting the SLC block set from the multiple SLC block sets based on a program/erase cycle count of the SLC block sets. Based on detecting a migration trigger condition, the processing device allocates a QLC block set from the multiple QLC block sets to store the data and migrates the data from the SLC block set to the QLC block set. Based on migrating the data from the SLC block set to the QLC block set, the processing device releases the SLC block set.
A memory device comprises multiple planes and each plane comprises multiple blocks. A processing device coupled to the memory device identifies good blocks in each plane of the memory device. The processing device generates multiple block sets by grouping the good blocks. Each block set comprises two blocks. The processing device generates a block set by grouping a first block from a first plane with a second block from a second plane.
Semiconductor devices with nano-vias, such as nano-through-silicon vias landing on middle-of-line (MOL) or back-end-of-line (BEOL) layers, are disclosed herein. In one embodiment, a semiconductor die includes a first side, a bond pad at the first side, a landing pad within an intermediate layer of the semiconductor die, and a via extending from the bond pad to the landing pad. The via can have an aspect ratio of height to width of 6: 1 or less. The intermediate layer can be positioned between the first side and a second side of the semiconductor die opposite the first side. In some embodiments, the intermediate layer is a MOL layer. In other embodiments, the intermediate layer is a BEOL layer. The semiconductor die can be a memory die, a logic die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a tensor processing unit (TPU) die, or another type of die.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
84.
Variable-length locked-raid for CXL devices with compression
In a locked RAID memory system, the present method generates variable-length compressed data in a RAID stripe, which is stored along with the inclusion of a single RAID parity segment (parity strip) for the entire stripe. If any one data segment (data strip) in the RAID stripe should fail, as determined by a CRC check, the data can be recovered by XORing the single RAID parity segment with all the non-errored data segments in the stripe. However, in order to determine which data segment has failed, successive data segments must be XORed, and the CRC check reperformed, until the CRC error stands corrected. In an embodiment, the successive data segments may be tested in parallel with suitable hardware. In an embodiment, the successive data segments may be tested sequentially, or semi-in-parallel and semi-sequentially.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
Systems and methods are provided for generating timing control signals for controlling the access to the memory cells of a memory device. The memory device employs a counter-based RAS chain circuit including multiple Match and Delay blocks to generate timing control signals with fine timing granularities. The Match and Delay blocks include circuits to enable area savings and improve area efficiency (AE) in the memory device as well as improve the flexibility for development chips and production parts.
A system and method for memory error recovery in CXL components is presented. The method includes determining that a memory component has sustained a hard failure in a Cyclic Redundancy Check-Redundant Array of Independent Devices (CRC-RAID) mechanism. The method further includes determining a location of the memory component failure, wherein the CRC-RAID mechanism comprises a plurality of memory components configured as a plurality of stripes and initiates a write operation of user data to a location within a particular stripe, wherein the particular stripe contains a failed memory component. The method includes compensating for the failed memory component, wherein the compensating comprises a plurality of read operations prior to a writing of the user data.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first substrate having first electrical traces and a second substrate having second electrical traces, where the second electrical traces are electrically coupled with the first electrical traces using at least one wire bond. The semiconductor device assembly includes an integrated circuit between the first substrate and the second substrate, where the integrated circuit is electrically coupled with the first electrical traces using at least one conductive structure.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H05K 1/14 - Association structurale de plusieurs circuits imprimés
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
88.
RADIATION MONITORING USING ACCUMULATED PARITY OF NON-PROTECTED LATCHES
Methods, systems, and devices for radiation monitoring using accumulated parity of non-protected latches are described. An array of non-protected latches store data over time and may be monitored using one or more latches to determine whether one or more errors occur. In some cases, the array may include multiple lanes of latches, where each lane may include a lane latch for parity testing and an output latch. During a parity scan, parity may be periodically generated for the data of each lane and compared to previous parity results to keep track of any soft error events that occur. The parity results for each lane may be combined to output an error flag. In some examples, the error flag may be output to a mode register, and parity testing may be performed based on one or more commands, modes, one or more counters, or with error correction operations.
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
G11C 29/48 - Dispositions dans les mémoires statiques spécialement adaptées au test par des moyens externes à la mémoire, p. ex. utilisant un accès direct à la mémoire [DMA] ou utilisant des chemins d'accès auxiliaires
Methods, systems, and devices for erase verify skip for fast cycling are described. A memory device may receive a command to perform an erase operation involving a first type of erase operation excluding an erase verify operation, and may apply a pre-programming pulse and an erase pulse to a block of memory cells while skipping an erase verify operation for one or more memory cells of the block based on the command. In some examples, the memory device may skip one or more erase verify operations based one or more internal trim settings. Additionally, or alternatively, erase verify skipping may be adaptive. For example, once a quantity of erase operations satisfies a threshold quantity, the memory device may receive a second command and may perform a second erase operation involving performing an erase verify operation for one or more memory cells of the block.
Methods, systems, and devices for memory system boot sequence with reduced latency are described. A host system may assert a signal (e.g., a fast boot signal) to a pin of a memory system, which may instruct the memory system to communicate data at a first data rate (e.g., a relatively lower data rate) before negotiating to a higher data rate (e.g., a highest data rate). The host system may output the fast boot signal to the memory system based on an estimated size of the data to be transferred, a dynamic measurement of the data, an application associated with the data, or any combination thereof. Based on transferring the data, the host system and the memory system may negotiate to an increased data rate (e.g., up to the highest supported data rate).
Methods, systems, and devices for memory system power management integrated circuitry monitoring are described. A system management controller may poll registers of a power integrated management circuit (PMIC) of a memory system in response to receiving an indication of a failure at the PMIC that may trigger a shutdown condition of the memory system. For example, despite the memory system being in a shutdown condition, power to the registers of the PMIC may remain enabled, and values from the PMIC register may be polled and stored by the system management controller. The values from the PMIC register may indicate a location of the failure of the PMIC or one or more operating parameters of the PMIC during the point of failure. The system management controller may output the stored values from the PMIC registers, which may support identification of root causes of failure at the PMIC.
The disclosed memory sub-system controller triggers read level voltage correction for reading a second portion of a memory based on errors encountered while reading data from a first portion of the memory. The controller reads a first portion of data from a first portion of a set of memory components using a set of read threshold levels and determines a read bit error rate (RBER) associated with the data read from the first portion of the set of memory components. The controller determines that the RBER associated with the data read from the first portion transgresses a threshold RBER. The controller selects an individual read level correction process from a plurality of read level correction processes and reads a second portion of data from a second portion of the set of memory components using the set of read threshold levels adjusted based on the selected individual read level correction process.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
93.
ON-CONTROLLER COMPRESSION OF DATA FROM MULTIPLE READS
Various embodiments provide for compression on a memory system controller of data generated by multiple reads performed on a set of pages of a memory device of the memory system. Such compression can be useful for storing and subsequently using data (e.g., comprising one-hard-two-soft (1H2S) information data) generated by the multiple reads to perform a management operation on the memory device, such as a read level calibration operation.
A variety of applications can include one or more memory devices having one or more memory cells containing a blocking dielectric separating a charge trap region from a control gate, where the blocking dielectric includes a high-k dielectric between and contacting a wide bandgap dielectric and the charge trap region. Another high-k dielectric can be positioned contacting the wide bandgap dielectric on a side of the wide bandgap dielectric opposite the side on which the first high-k dielectric is positioned, forming a sandwiched structure. Additional devices, systems, and methods are discussed.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
95.
MEMORY SYSTEMS AND DEVICES INCLUDING EXAMPLES OF ACCESSING MEMORY AND GENERATING ACCESS CODES USING AN AUTHENTICATED STREAM CIPHER
Examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
96.
NETWORK-READY STORAGE PRODUCTS WITH CRYPTOGRAPHY BASED ACCESS CONTROL
A storage product manufactured as a computer component and configured to have: a secure memory region to store cryptographic keys; a network interface; a local storage device having a storage capacity accessible via the network interface; and a host interface to be connected to a local host system. The local host system can control access, made via the network interface, to the storage capacity without receiving a portion of storage access messages received in the network interface. The storage product includes an access controller configured to determine whether a message, received in the network interface from the computer network or in the host interface from the local host system, has a valid verification code according to the cryptographic keys; and if not, the message can be rejected, deleted, discarded, or ignored without further processing.
In response to determining that a representative number of program erase cycles (PECs) for a set of blocks of the memory device satisfies a condition, one or more trim values associated with the set of blocks are set according to the representative number of PECs for the set of blocks, wherein each programmed block in the set of blocks having been programmed within at least one of a specified time window or a specified temperature window. In response to receiving a write command directed to a block of the set of blocks, the write command is executed according to the one or more trim values.
Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
A semiconductor device assembly includes a semiconductor die, a substrate, and a spacer directly coupled to the substrate. The spacer includes a flexible main body and a support structure embedded in the flexible main body, wherein the support structure has a higher stiffness than the flexible main body. The spacer carries the semiconductor die. The flexible main body of the spacer mitigates the effects of thermomechanical stress, for example caused by a mismatch between the coefficient of thermal expansion of the semiconductor die and the substrate. The embedded support structure provides strength needed to support the semiconductor die during assembly.
A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material sintering therein.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
