Methods, systems, and devices for methods for data prioritization in memory are described. A memory device may be configured to prioritize data such that high-priority data may remain in a cache to await operations while low-priority data may be transferred to higher‑latency memory. For example, the memory device may receive a command to write data associated with one or more user operations to the memory system. The memory device may also receive an indication associated with the data that indicates to the memory device that the data is high priority. The memory device may store the data in a cache of the memory device to await operations. In response to a trigger, the memory device may transfer data not associated with the indication from the cache to multi-level memory cells (MLCs) of the memory device, such that the high-priority files may remain in the cache.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
2.
WEAR LEVELING IN A ZONED NAMESPACE MEMORY SUB-SYSTEM
A memory device comprises multiple quad-level cell (QLC) block sets and multiple single-level cell (SLC) block sets. A processing device allocates an SLC block set from the multiple SLC block sets for storing data. The allocating of the SLC block set comprises selecting the SLC block set from the multiple SLC block sets based on a program/erase cycle count of the SLC block sets. Based on detecting a migration trigger condition, the processing device allocates a QLC block set from the multiple QLC block sets to store the data and migrates the data from the SLC block set to the QLC block set. Based on migrating the data from the SLC block set to the QLC block set, the processing device releases the SLC block set.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
A memory device comprises multiple planes and each plane comprises multiple blocks. A processing device coupled to the memory device identifies good blocks in each plane of the memory device. The processing device generates multiple block sets by grouping the good blocks. Each block set comprises two blocks. The processing device generates a block set by grouping a first block from a first plane with a second block from a second plane.
Systems and methods related to testing of designs for system-in-packages (SiP) comprising high-bandwidth memory (HBM) and system on a chip (SOC) devices are discussed herein. Live HBM devices may be used in combination with a silicon bridge to form a proxy SiP device. The silicon bridge has the same size and shape as the SOC that it replaces. The differences in electrical properties between the proxy and the actual SiP are reduced by using the silicon bridge instead of connecting the HBMs through the substrate. By comparison with using a live SOC, using the silicon bridge reduces the cost of producing the proxy. An external testing device may be coupled to access pins of the proxy SiP device and execute one or more tests.
A variety of applications can include one or more memory devices comprising an array of pillars of memory cells, where the memory cells are stacked in a vertical direction within the pillars and the array of pillars are organized in blocks. Separation regions between blocks can be defined by spacing of a single row of pillars, except for a number of dedicated separation regions providing spacing defined by three rows of pillars.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
6.
VENDOR SPECIFIC SUB BLOCK ACCESS ACCORDING TO SUB BLOCK DESCRIPTOR
A memory sub-system, having: a host interface configured to operate on a computer bus; non-volatile memory cells; and a controller to store, in a vendor specific log page, data indicating that the memory sub-system supports sub block access and providing a sub block granularity level for the sub block access. After receiving, from the host system, an access command with a sub block descriptor configured to identify a portion of a logical block identified by the access command, the controller is to transfer, over the computer bus according to an opcode provided in the access command, data for the portion of the logical block without transferring over the computer bus data of the logical block outside of the portion of the logical block identified by the sub block descriptor.
A computing device including a memory sub-system having storage resources organized in reclaim units, and a host system coupled to the memory sub-system to write data into the reclaim units. The host system is configured to: monitor a usage level of the reclaim units; start, responsive to the usage level reaching a first level, operations configured to reduce valid data stored in a reclaim unit allocated as storage media of a set of logical addresses; and complete, before the usage level reaching a second level, the operations. The memory sub-system is configured to refrain, before the usage level reaching the second level, from copying valid data from the reclaim unit to outside of the reclaim unit for erasure of the unit of storage resources.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
8.
SCHEDULE OPERATIONS OF A HOST SYSTEM TO REDUCE GARBAGE COLLECTION IN A DATA STORAGE DEVICE WITH MINIMAL COMMUNICATIONS OUTSIDE OF PROTOCOL FOR FLEXIBLE DIRECT PLACEMENT
A host system having at least one processing device to execute instructions configured to implement a garbage collection manager, which can: compute, based on write commands sent from the host system to the memory sub-system according to a protocol of flexible direct placement (FDP) to store data of storage space tenants, an indicator of usage level of reclaim units in the memory sub-system; identify, in response to a determination that the indicator meets a condition, at least one reclaim unit in the memory sub-system having valid data; and communicate with the storage space tenants having the valid data in the at least one reclaim unit to cause the storage space tenants to perform operations that reduce garbage collection in the memory sub-system in reclaiming storage resources of the at least one reclaim unit.
A memory sub-system, having: a host interface operatable on a computer bus; a non-volatile memory; and a controller. In response to a request to create a first namespace, the controller create the first namespace and a second namespace having a same storage capacity as the first namespace. The first namespace has a first granularity level; and the second namespace has a second granularity level different from the first granularity level. The first namespace and the second namespace represent a storage capacity provided by a same set of storage resources in the memory sub-system. The controller maintains a mapping between logical addresses defined in the first namespace and physical addresses of the set of storage resources, and process access to addresses in the second namespace via the mapping between logical addresses defined in the first namespace and physical addresses of the set of storage resources.
Various aspects of the present disclosure relate to adaptive memory device partition closure. In some aspects, a memory device may open a partition comprising a plurality of sets of memory cells. The memory device may program one or more sets of memory cells of the plurality of sets of memory cells. The memory device may update, based on an aggregated drive temperature, an accumulated value that is reflective of one or more physical parameters of the one or more sets of memory cells. The memory device may determine whether the accumulated value satisfies a threshold criterion. The memory device, responsive to determining that the accumulated value satisfies the threshold criterion, may close the partition.
A memory sub-system, having: a host interface configured to operate on a computer bus; non-volatile memory cells; and a controller. In response to a command to identify information about the memory sub-system, the controller is to provide structured data indicating that the memory sub-system supports sub block access and specifying a sub block granularity level for the sub block access. In response to an access command with a sub block descriptor embedded within the access command, the controller is to determine, based on the sub block descriptor provided within the access command, a portion of a logical block identified by the access command and implemented using a subset of the non-volatile memory cells. An operation is performed on the portion of the logical block according to an opcode specified by the access command.
Methods, systems, and devices for memory architectures with partially filled piers are described. A stack of materials including alternating layers of nitride and oxide may be formed, and piers and pillars may be formed through the stack of materials. Layers of nitride may be etched for metallization and one or more piers may be removed, which may result in corresponding cavities being formed in the stack of materials. Memory cells may be formed between one or more pillars and corresponding electrodes, and the cavities (e.g., the cavities resulting from removing one or more piers) may be partially filled with a dielectric material such that an air gap is formed within the cavity, or with a low-k dielectric material, or both.
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Methods, systems, and devices for charge loss weak die identification are described. The described techniques provide for a memory system to avoid sampling, during block family (BF) scans, blocks of memory cells associated with memory dies that are classified as read disturb charge loss (RDCL) weak dies. The memory system may identify a memory die as being an RDCL weak die based on a threshold quantity of blocks associated with the memory die experiencing relatively high charge loss. If the quantity satisfies a threshold value, the memory system may classify the memory die as an RDCL weak die and the memory system may refrain from selecting blocks from a BF that are associated with a memory die classified as an RDCL weak die.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
The present disclosure configures a memory sub-system controller to read virtual blocks using partial good block (PGBs) across different planes using different read voltages. The controller identifies a region of a set of memory components, the region comprising a plurality of planes across a plurality of decks of the set of memory components. The controller generates an individual virtual block (VB) using a first PGB on a first deck of the plurality of decks of the region associated with a first plane of the plurality of planes and a second RGB on a second deck of the plurality of decks associated with the first plane. The controller, in response to receiving the request to read the data, applies a first read voltage offset to read the individual VB from the first plane in parallel with applying a second read voltage offset to read an additional VB from a second plane.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
15.
FACILITATING WAFER DEBONDING BY INTRODUCING MOISTURE TO BONDING INTERFACE
A semiconductor wafer including a first dielectric layer disposed on top of the semiconductor wafer, the first dielectric layer having a first frontside surface, a second dielectric layer embedded in the first dielectric layer, the second dielectric layer containing moisture and having a second frontside surface horizontally aligned with the first frontside surface, and oxygen covalent dangling bonds and hydroxide dangling bonds disposed on the first frontside surface and the second frontside surface. Another semiconductor wafer including a first dielectric layer disposed on top of the semiconductor wafer, the first dielectric layer having a frontside surface, a second dielectric layer disposed underneath the first dielectric layer, the second dielectric layer containing moisture, and oxygen covalent dangling bonds and hydroxide dangling bonds disposed on the frontside surface.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
16.
CORROSION-SUSCEPTIBLE BONDING LAYER IN ASSISTING SEMICONDUCTOR WAFER DEBONDING
A bonded semiconductor structure including a product wafer having a first metal layer disposed on a first frontside surface of the product wafer, and a carrier wafer having a second metal layer disposed on a second frontside surface of the carrier wafer and a third metal layer disposed under the second metal layer, wherein the first metal layer is bonded to the second metal layer by metal-metal bonds disposed at a bonding interface between the first frontside surface and the second frontside surface, and wherein the third metal layer includes a corrosion portion extending from an edge of the carrier wafer to a center of the carrier wafer.
Methods, systems, and devices for replacement channel integration for three dimensional memory cell architectures are described. A method of manufacturing a memory architecture may include forming a stack of materials above a substrate. Trenches may be formed within the stack of materials, where each trench may include a gate oxide material lining the trench, and pairs of conductive pillars forming gate elements. The gate elements may form word lines associated with activating memory cells of the memory architecture. Another trench may be formed perpendicular to the trenches, and used for forming memory cells each including a selection element and a storage element within sacrificial layers of the stack of materials between the trenches. The trench may form a source line for accessing the memory cells adjacent to the trench. A digit line may be formed around the trenches and may be configured to access the memory cells.
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
18.
APPARATUSES AND METHODS T0 REFRESH MEMORY INCLUDING MEMORY BANKS
Apparatuses and methods for a refresh operation performed on a memory bank from a subset of memory of memory bank groups in a high bank-count memory device. The memory banks may be divided into memory bank groups. The memory device may receive an external refresh command. The refresh command may indicate that a memory bank from each of the memory bank groups is to be refreshed (e.g., a same bank refresh operation) rather than refreshing all of the memory banks of all the memory groups (e.g., an all bank refresh operation). Responsive to the refresh command and a mode register setting further indicating that a smaller subset is to be refreshed (e.g., a same bank subset refresh operation), the refresh control circuit will refresh a memory bank from a subset of memory bank groups. As a result, the number of available memory banks during a refresh operation increases.
Semiconductor devices with nano-vias, such as nano-through-silicon vias landing on middle-of-line (MOL) or back-end-of-line (BEOL) layers, are disclosed herein. In one embodiment, a semiconductor die includes a first side, a bond pad at the first side, a landing pad within an intermediate layer of the semiconductor die, and a via extending from the bond pad to the landing pad. The via can have an aspect ratio of height to width of 6: 1 or less. The intermediate layer can be positioned between the first side and a second side of the semiconductor die opposite the first side. In some embodiments, the intermediate layer is a MOL layer. In other embodiments, the intermediate layer is a BEOL layer. The semiconductor die can be a memory die, a logic die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a tensor processing unit (TPU) die, or another type of die.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
20.
TRANSISTOR WITH CHANNEL LAYER INCLUDING HEAVILY DOPED REGION
A transistor includes a source, a drain, a gate layer, an undoped or lightly doped channel layer, and a gate dielectric layer. The undoped or lightly doped channel layer extends between the source and the drain. The channel layer includes at least one heavily doped region to distribute channel potential along the channel layer. The gate dielectric layer is between the gate layer and the channel layer.
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
A variety of applications can include one or more memory devices having one or more memory cells containing a blocking dielectric separating a charge trap region from a control gate, where the blocking dielectric includes a high-k dielectric between and contacting a wide bandgap dielectric and the charge trap region. Another high-k dielectric can be positioned contacting the wide bandgap dielectric on a side of the wide bandgap dielectric opposite the side on which the first high-k dielectric is positioned, forming a sandwiched structure. Additional devices, systems, and methods are discussed.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
22.
MANAGEMENT COMMAND MICROCODE TECHNIQUES FOR MEMORY ARCHITECTURES
Methods, systems, and devices for management command microcode techniques for memory architectures are described. For example, interface circuitry of a memory system may be configured to determine that a management operation is to be performed, and may indicate a request to a controller of a host system to schedule aspects of the management operation. In response, the controller may indicate one or more commands to the interface circuitry to perform the management operation. Such techniques may involve the interface circuitry and controller being configured in accordance with a sequence of operations (e.g., a microcode), and respective management operations may each be associated with a pointer and a length of the sequence of operations. The controller may be configured to determine one or more commands for an indicated management operation by referencing the sequence of operations in accordance with the pointer and length associated with the indicated management operation.
Methods, systems, and devices for adjusted access operations for replay protected memory blocks (RPMBs) are described. A memory system may communicate one or more commands concurrently with performance of an access operation on a RPMB in response to receiving a first security protocol command. The first security protocol command may be a security protocol out (SPO) command transmitted from a host device. In combination with a ready to transfer response from the memory system and a data out UPIU from the host device, the first security protocol command may indicate a type of the access operation and corresponding data. The one or more commands may include additional SPO commands, security protocol in (SPI) commands, one or more other commands, or any combination thereof. In some cases, the memory device may transmit the data back to the host after the access operation is complete.
Methods, systems, and devices for manual dynamic word line start voltage (MDWLSV) prediction and a self-adapting cache program for memory operations are described. In some examples, a memory device may receive a sequence of write commands for a memory block, and the memory device may monitor an interval between two consecutive write commands in the sequence. The memory device may compare the interval to a threshold interval. The memory device may utilize a first programming mode associated with a combination of a set feature (SF) and a get feature (GF) for MDWLSV prediction if the interval exceeds the threshold. The memory device may utilize a second programming mode associated with the SF for MDWLSV prediction if the interval is less than the threshold. The described techniques may provide for the host device to transmit commands for MDWLSV prediction in advance by transmitting the MDWLSV commands via a previous write command.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
Systems and devices for semiconductor die coupling with inductive coils are described. A semiconductor device may include one or more inductive coils to enhance signal quality of signals communicated over conductive lines and to support improved processing bandwidth. The semiconductor device may include multiple dies and each die may include respective circuitry. The respective circuitry may be coupled with the one or more inductive coils. In some cases, each die of the semiconductor device may respectively include one or more inductive coils that couple die circuitry with a same channel. In some cases, a redistribution layer that is shared by each die may be configured with one or more inductive coils that are coupled with each die. Each die may be coupled with the one or more inductive coils based on a conductive pillar or based on a hybrid bond.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to debug a memory sub-system. The controller receives, from a host over a first bus, authentication information associated with unlocking the debugging component and, in response to successfully authenticating the host based on the authentication information, unlocks a debugging component. The debugging component receives one or more debug commands from the host via a second bus and transmits, to the host via the second bus, debugging information in response to receiving the one or more debug commands.
Aspects of the present disclosure configure a system component, such as memory sub-system controller, to transition a state of a memory sub-system into different panic handling modes. The controller detects failure of a memory sub-system and determines that self-recovery from the failure of the memory sub-system is unavailable. The controller, in response to determining that self-recovery from the failure of the memory sub-system is unavailable, incrementally transitions a state of the memory sub-system to different panic handling modes and returns the memory sub-system to a deployed mode from one of the different panic handling modes in response to successfully recovering the memory sub-system.
Methods, systems, and devices for security for read commands are described. The memory system receive a read command to read data from a read protected memory block (RPMB) region. The read command may include a first message authenticated code (MAC) key. In some cases, the memory system may authenticate the read command using the first MAC key and retrieving the data from the RPMB region. The memory system may transmit the data after retrieving the data from the RPMB region. In some cases, the memory system may determine whether a read protect flag associated with a logical unit identified by the read command indicates that reading of data stored in the logical unit is permitted. The memory system may read the data based on determining that the read protect flag permits reading the data.
Methods, systems, and devices for write temperature recovery from a memory system are described. A memory system may receive a command to provide write temperature information associated with data written to the one or more memory devices. The memory system may read, from the one or more memory devices based on the command, a write temperature indicative of a temperature of the memory system at a time of writing a subset of the data. The memory system may read, based on transmitting the write temperature to a host system, one or more subsets of the data.
Methods, systems, and devices for endurance group for tiered storage applications are described. A memory system may implement a single memory device with different types of memory and corresponding data access categories. The memory device may implement endurance groups, which may each include a set of memory cells configurable as single-level cells, triple-level cells, or quad-level cells. The endurance groups may be configured based on a capacity identifier selected for the memory device from a set of capacity identifiers supported by the memory system. Each capacity identifier of the set of capacity identifiers may be associated with a configuration of the endurance groups. The host system may transmit a capacity identifier to indicate a configuration of the memory system. The memory system may support data movement internal to the memory system between the endurance groups, without transferring data between the host system.
Methods, systems, and devices for multi-plane firmware image management are described. A memory system may store a primary firmware image across multiple planes. The memory system may read the firmware image from the planes using a multi-plane read operation. The memory system may store copies of the firmware image to separate, individual planes and the copies may be accessed (e.g., read) based on detecting an error in the primary firmware image.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
An apparatus including a multi-purpose communication mechanism and associated systems and methods are disclosed herein. The apparatus may include the multi-purpose communication mechanism that enables different circuits to process corresponding/different signals communicated through a shared direct access (DA) pad. The shared direct access (DA) pad connected to a vertically extending via and configured to facilitate communication of a first signal and a second signal with an external device.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
Methods, systems, and devices for forming an indium chalcogenide film are described. Precursors that include an indium-cyclopentadienyl compound may enable formation of indium chalcogenide films at a lower temperature as compared to other precursors including indium, as the reactivity of indium-cyclopentadienyl compounds may be higher than these other precursors. Additionally, using ammonia as a reagent during the atomic layer deposition process to form the indium chalcogenide film may enable an increased rate of formation of indium chalcogenide films for a given temperature. A method may include reacting an indium-cyclopentadienyl precursor and a second precursor that includes a selenium compound or a tellurium compound to form an indium chalcogenide.
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
C23C 16/30 - Dépôt de composés, de mélanges ou de solutions solides, p. ex. borures, carbures, nitrures
C23C 16/04 - Revêtement de parties déterminées de la surface, p. ex. au moyen de masques
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
Methods, systems, and devices for thermal vias for semiconductor components are described. A semiconductor component may be configured with conductor portions (e.g., thermal vias) that increase a degree of thermal conductivity through dielectric layers of the semiconductor component. In some examples, thermal vias may be implemented as conductor portions that are enclosed by a dielectric layer, and are therefore electrically floating relative to conductors of substrate circuitry, interconnection circuitry, or both. Additionally, or alternatively, thermal vias may be implemented as portions of conductive lines having a thickness portion that projects through at least some but not all of a respective dielectric layer. In various examples, at least some of such thermal vias may be implemented with a pitch dimension that is similar to conductive lines of one or more interconnection layers, or may implement similar processing as other features of the semiconductor component, among other implementations.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
35.
SEMICONDUCTOR DEVICE WITH BACKSIDE INTERFACE MECHANISM AND METHODS FOR MANUFACTURING THE SAME
Methods, apparatuses, and systems related to a memory device having on its backside one or more integrally-formed structures is described. A memory device may have on a backside of a semiconductor substrate an integral electrical connector that includes (1) a pad portion configured to connect to an external component and (2) a through- silicon via (TSV) portion that at least partially extends through the semiconductor substrate. The pad portion and the TSV portion may be connected through an integral joint. The TSV portion can have a narrowing shape with its cross-sectional width decreasing for portions farther away from the pad portion.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
36.
FERROELECTRIC MEMORY CIRCUITRY AND METHOD USED IN FORMING FERROELECTRIC MEMORY CIRCUITRY
H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique
G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
Processing a memory array with reduced drift is described herein. An example method includes forming, on a substrate material, a first conductive line material, forming, on the first conductive line material, a first electrode material and a second electrode material separated from one another by a sacrificial material, and forming a plurality of openings in the first conductive line material, first electrode material, sacrificial material, and second electrode material. An insulation material is formed in the plurality of openings. A second conductive line material is formed on the second electrode material and insulation material. An additional plurality of openings are formed in the first electrode material, sacrificial material, second electrode material, and second conductive line material. A plurality of recesses are formed between the first electrode material and the second electrode material by selectively removing the sacrificial material. A chalcogenide material is formed in the plurality of recesses.
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
38.
HEAT-MITIGATING HIGH-BANDWIDTH DEVICES IN SYSTEM-IN-PACKAGE DEVICES AND ASSOCIATED SYSTEMS AND METHODS
System-in-package (SiP) devices, and associated systems and methods are disclosed herein. In some embodiments, a SiP device can include a base substrate, as well as a host device and a heat-mitigating high-bandwidth memory (HBM) device each integrated with the base substrate. The heat-mitigating HBM device can include a stack of one or more memory dies and an interface die carried by the stack of one or more memory dies. The interface die includes an input/output (IO) circuit that is accessible through an upper surface of the interface die. The SiP device can also include a communication substrate carried by the host device and the heat- mitigating HBM device, as well as a thermal interface material carried by the communication substrate. The communication substrate can include one or more communication channels communicably coupling the IO circuit of the interface die to the host device.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
39.
APPARATUSES AND METHODS FOR ACTIVATION COUNTER INITIALIZATION
Embodiments of the disclosure are drawn to apparatuses, systems, and methods for activation counter initialization (ACI). A memory may be placed in an ACI mode. During the ACI'mode, an ACI control circuit initializes the access count values of the memory array to an initialization value. For example, the ACI mode may work through the array on a row-by-row basis initializing, the access count values along each of the rows. By controlling the initial state of the access count values, it is less likely to have a false aggressor alert because none of the access count values start at a randomly high number, simulating an aggressor even after a small number of accesses.
Methods, systems, and devices for reconstructed semiconductor die evaluation in stacked memory architectures are described. A semiconductor device may be formed based on reconstructed wafers of operable dies. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. The interface block may also be formed with one or more conductive pads in a second side of the interface block which may provide an evaluation interface for the interface block and the one or more volatile memory stacks. The second side of the interface block may then be bonded to a host chip, and the host chip may be operable to couple with the interface block and control one or more functions of the interface block and the one or more volatile memory stacks.
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
41.
MEMORY DEVICE WITH A THREE-DIMENSIONAL VERTICAL STRUCTURE, AND METHOD FOR DRIVING WORD LINES OF THE MEMORY DEVICE
It is disclosed a memory device comprising a plurality of memory cells arranged in a three-dimensional array having a plurality of levels above a substrate, comprising a plurality of conductive word lines extending over a respective level and coupled to said plurality of memory cells, each word line being connected to a respective step of a staircase positioned in a staircase area outside an active area of the array of the plurality of memory cells. The memory device further comprises a plurality of word line drivers for the corresponding plurality of word lines and comprises a plurality of Through Array Via elements for the corresponding plurality of word lines. The plurality of word line drivers and the plurality of Through Array Via elements are positioned in the staircase area.
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
It is disclosed a memory device comprising a plurality of memory cells arranged in a three-dimensional array having a plurality of levels above a substrate, comprising a plurality of conductive word lines extending over a respective level and coupled to said plurality of memory cells, each word line being connected to a respective step of a staircase positioned in a staircase area outside an active area of the array of the plurality of memory cells. The memory device further comprises a plurality of word line drivers for the corresponding plurality of word lines, comprises a first plurality of Through Array Via elements for the corresponding plurality of word lines and comprises a second plurality of Through Array Via elements for the corresponding plurality of word lines. The first plurality of Through Array Via elements are positioned in the staircase area and the second plurality of Through Array Via elements are positioned in another area adjacent to the staircase area.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
G11C 8/14 - Organisation de lignes de motsDisposition de lignes de mots
A stacked hybrid memory architecture includes a dynamic random-access memory (DRAM) device. The DRAM device stores a plurality of weights associated with an artificial neural network. The stacked hybrid memory architecture also includes a static random-access memory (SRAM) device bonded to the DRAM device. The SRAM device receives, from the DRAM device through a plurality of through silicon vias (TSVs), the plurality of weights associated with the artificial neural network. The SRAM device also performs a plurality of operations utilizing the plurality of weights. The stacked hybrid memory architecture also includes logic configured to perform a summation operation on a result of the plurality of operations.
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice
G11C 11/413 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
44.
RECONSTRUCTED SEMICONDUCTOR DIE EVALUATION AND POWER DELIVERY
Methods, systems, and devices for reconstructed semiconductor die evaluation and power delivery are described. A semiconductor device may be formed based on reconstructed wafers of operable dies and may support improved architectures for power delivery. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. An evaluation procedure may be performed by probing one or more conductive pads in a second side of the interface block. The second side of the interface block may then be bonded to a first side of a host chip, and the host chip may be operable to control one or more functions of the interface block and the one or more volatile memory stacks. In some examples, a redistribution layer may be formed above a second side of the host chip to provide a power interface for the semiconductor device.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
45.
BACKSIDE POWER DELIVERY TO LOGIC OF A MEMORY ARCHITECTURE
Methods, systems, and devices for backside power delivery to logic of a memory architecture are described. A semiconductor system may implement logic chips stacked above stacks of memory chips, where the stacks of memory chips are positioned above circuitry associated with providing power to the semiconductor system. The semiconductor system may include a dielectric layer above the logic chips including conductive channels. For example, the circuitry may deliver power to the logic chips based on transferring power along power delivery vias to the conductive channels which may provide the power to the logic chips. In some examples, a front side of the logic chips may be bonded with a backside of the stacks of memory chips, and a backside of the logic chips may be bonded with the conductive channels, such that power is delivered to the backside of the logic chips.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
Methods, systems, and devices for memory device staircase formation are described. A memory device may include a stack of materials that includes a first staircase portion, at a first surface of the stack, having first contact surfaces for a first subset of word lines and a second staircase portion, at a second surface of the stack, which includes second contact surfaces for a second subset of the word lines. Conductive pillars may couple the word lines of the first subset and the second subset to the supporting circuitry. For example, a first conductive pillar may extend, in a first plane, from a first word line of the first subset toward the first surface of the stack and a second conductive pillar may extend, in the first plane, from a second word line of the second subset toward the second surface of the stack.
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec mémoire cache dédiée, p. ex. instruction ou pile
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
47.
TECHNIQUES FOR SURFACE MODIFICATIONS DURING BONDING PROCEDURES
Methods, systems, and devices for surface modifications during bonding procedures are described. A memory device may be manufactured by polishing a first semiconductor and a second semiconductor, where the first semiconductor has a first surface and a second surface, and the second semiconductor has a third surface and a fourth surface. The first surface and the third surface may be polished to have a first roughness. Accordingly, a portion of the first surface may be etched according to a pattern, where the portion of the first surface has a second roughness that is different than the first roughness. Similarly, a portion of the third surface may be etched according to a second pattern, where the portion of the third surface has the second roughness. Based on etching the first surface and the third surface, the first surface and the third surface may be bonded.
H01L 21/18 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs ayant des barrières de potentiel, p. ex. une jonction PN, une région d'appauvrissement ou une région de concentration de porteurs de charges les dispositifs ayant des corps semi-conducteurs comprenant des éléments du groupe IV du tableau périodique, ou des composés AIIIBV, avec ou sans impuretés, p. ex. des matériaux de dopage
H01L 21/304 - Traitement mécanique, p. ex. meulage, polissage, coupe
H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
A system includes a memory comprising a memory cell array configured to store data and a logging logic circuit configured to generate a log of detected faults or attacks on the memory cell array, and a host hosting a hypervisor. The hypervisor is configured to host a virtual machine, including managing data allocation for processes of the virtual machine to a first region of the memory cell array. The hypervisor is further configured to receive the log of detected faults or attacks? generated by the logging logic circuit. In response to a determination that the first region of the memory cell array has a detected fault or attack based on the log of detected faults or attacks, re-direct data allocation for the virtual machine to a second region of the memory cell array.
A memory device is provided. The memory device includes a plurality of Command/Address (CA) inputs, a plurality of data inputs/outputs (DQs), and a fine- grained CA training mode (CATM) circuit coupled to the CA inputs and coupled to the DQs. The fine-grained CATM circuit is configured to capture a CA sample from the CA inputs and perform a plurality of operations on the CA sample. Each operation is performed on an exclusive subset of the CA sample, and each operation generates an output value. The fine-grained CATM circuit is additionally configured to drive the plurality of output values over the plurality of DQs.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p. ex. compteurs de rafraîchissement défectueux
50.
REDUNDANCY TECHNIQUES FOR MULTI-CHANNEL MEMORY DEVICES
Methods, systems, and devices for redundancy techniques for multi-channel memory devices are described. A memory device may be configured with multiple channels (e.g., channel sets) that can be operated in different modes, such as a two-channel mode and a one-channel redundancy mode. In the two-channel mode, the memory device may be configured to access each of multiple memory arrays using a respective channel. In the one-channel redundancy mode, the memory device may be configured to access multiple memory arrays using a single channel which may otherwise be accessed using separate channels, and the memory device may store copies of data on the multiple memory arrays. For example, the memory device may store a first copy of data communicated via a channel in a first memory array and may store a second copy of the data communicated via the channel in a second memory array.
Methods, systems, and devices for on-die heating for a memory device are described. A system may monitor a temperature associated with a memory die that includes a set of heating blocks. The set of heating blocks may heat the memory die and generate an activation signal based on the temperature associated with the memory die satisfying one or more thresholds. Further, the system may activate one or more heating blocks of the set of heating blocks based on the activation signal. In some examples, activating the one or more heating blocks may provide for an adjustment of the temperature associated with the memory die.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
52.
SEMICONDUCTOR PACKAGE HAVING AN ARRAY OF MULTI-SIZED INTERCONNECT STRUCTURES
Implementations described herein relate to various semiconductor device assemblies. In some implementations, an apparatus includes an interconnect array structure including a first metallization layer having a first pad structure, a second metallization layer having a second pad structure, and at least one dielectric layer between the first metallization layer and the second metallization layer. The apparatus includes a first pillar bump structure connected with the first pad structure, where the first pillar bump structure includes a first bump structure having a first volume. The apparatus includes a second pillar bump structure connected with the second pad structure, where the second pillar bump structure includes a second bump structure having a second volume that is greater than the first volume.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p. ex. contacts planaires
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
53.
DETECTING HOST WRITE PATTERNS FOR IMPROVING STORAGE MEDIA ENDURANCE
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive, from a host system, a memory write request specifying a data item to be stored on the memory device; identify a start logical address and an end logical address associated with the data item; responsive to determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU), store a corresponding misaligned portion of the data item in a cache line; and store an identifier of the respective IU in a metadata item associated with the cache line.
Methods, systems, and devices for accurate capacity adjustment factor are described. A request for a memory system to signal a capacity of the memory system may be received. Based on the request, a message indicating a capacity of a section of memory in the memory system that includes multiple-level cells may be transmitted to the host system. The message may include a first indication of a potential capacity of the multiple-level cells and a second indication of a configured capacity of the multiple-level cells.
A memory device receives a command, address, or combination thereof as part of an access operation which indicates an opportunity to perform a refresh background operation. The memory device may determine whether or not to perform the background refresh operation. If a background refresh operation is performed, the memory accesses a word line in a first section of a memory bank and refreshes a word line in a different section of the memory bank. In some embodiments, an opportunity background refresh operation may be signaled by an access command with an extended timing window.
A memory device receives a command, address, or combination thereof as part of an access operation which indicates an opportunity to perform a refresh background operation. The memory device may determine whether or not to perform the background refresh operation. If a background refresh operation is performed, the memory accesses a word line in a first section of a memory bank and refreshes a word line in a different section of the memory bank. In some embodiments, an opportunity background refresh operation may be signaled by an access command with an extended timing window.
A method for manufacturing a heterogenous reconstructed wafer is provided. The method includes bonding a plurality of previously-tested main dies to a side of a silicon carrier wafer. The method also includes bonding a plurality of support dies to the side of the silicon carrier wafer such that the plurality of support dies is disposed in gaps between the plurality of main dies. The method also includes filling gaps between the plurality of main dies and the plurality of support dies with a gap-fill material such that the gap-fill material forms a gap-fill layer around and above each of the plurality of main dies and each of the plurality of support dies. The method then includes removing the silicon carrier wafer to form a heterogenous reconstructed wafer.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to perform operations including determining that a scan triggering condition has been satisfied for a block of the memory device. The operations further include setting a scan flag associated with the block to a first value indicative of satisfaction of the scan triggering condition. The operations further include delaying a scan operation of the block until an erase operation is performed on the block. The operations further include, responsive to performing the erase operation on the block, performing the scan operation on the block. The operations further include setting the scan flag associated with the block to a second value.
This disclosure is directed to a latch circuit (74) of a decision feedback equalizer (DFE) (72). The latch circuit (74) may sample (e.g., clock-in) each input data bit during a respective sampling time of each latch circuit (74) operation cycle after a reduced propagation delay compared to other latch circuits (74). The latch circuit (74) may have a reset time and a tracking time before each sampling time that may reduce the propagation delay of each data bit being received during the sampling time. During the track time, the latch circuit (74) may combine (e.g., add, subtract) an offset voltage, generated based on based on one or more previously received data bits and/or characteristics of the latch circuit (74), with a baseline voltage of the latch circuit (74). The latch circuit (74) may sense a logic level of each data bit being received during the sampling time based on detecting changes to the baseline voltage combined with the offset voltage.
A memory device receives a command, address, or combination thereof as part of an access operation which indicates an opportunity to perform a refresh background operation. The memory device may determine whether or not to perform the background refresh operation. If a background refresh operation is performed, the memory accesses a word line in a first section of a memory bank and refreshes a word line in a different section of the memory bank. In some embodiments, an opportunity background refresh operation may be signaled by an access command with an extended timing window.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
61.
ADVANCED FILE SYSTEM WITH DYNAMIC BLOCK ALLOCATION
Systems, methods, and computer readable media for moving data blocks from a user area to a file system area. The method includes receiving a command from a host system and determining a number of free data blocks in a file system area of a memory device. The method further includes determining that the number of free data blocks in the file system area does not satisfy a threshold criterion, and allocating one or more data blocks from a user data area to the file system area.
A memory device for use in immersion cooling comprises a printed circuit board, one or more surface-mounted devices coupled to the printed circuit board, and one or more coolant outlets coupled to the printed circuit board to deliver coolant to the one or more surface-mounted devices. A system for cooling electronic devices comprises a tank for receiving a coolant liquid into which the electronic devices can be immersed in use, a manifold comprising a fluid inlet coupleable to a supply of pressurized coolant and a plurality of spigots to deliver coolant liquid to coolant outlets located at or on printed circuit board.
A memory device for use in immersion cooling comprises a printed circuit board, one or more surface-mounted devices coupled to the printed circuit board, and an electrically non-conductive and thermally-conductive container surrounding the surface-mounted devices. The container may comprise a polymer bag or a Graphene-Reinforced Polymer enclosure. The polymer bag may be a polydimethylsiloxane film bag including a ceramic filler. The container is sealed to the printed circuit board at one or more sides of the printed circuit board, for example next to an M.2 connector.
Memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a horizontal transistor comprising a gate. The gate comprises part of a one of a plurality of horizontal conductive access lines that individually directly electrically couple together multiple of the gates of different ones of the horizontal transistors that are in the same memory-cell tier. The gates and access lines individually comprise conductive first and second different composition metal materials that are laterally aside and directly against one another. Methods are disclosed.
In some implementations, a memory system may receive a first indication of one or more memory address ranges to be monitored and a second indication of a memory unit size. The memory system may determine one or more memory units associated with the one or more memory address ranges. The memory system may determine, using an access counter for each memory unit, a quantity of accesses to that memory unit during a monitoring period. The memory system may determine that a corresponding access counter for each memory unit, of a subset of the one or more memory units, satisfies an access threshold. The memory system may add an identifier of, and an indication of the corresponding access counter for, each memory unit, of the subset of the one or more memory units, to a data structure based on determining that the corresponding access counter satisfies the access threshold.
Methods, systems, and devices for thermal throttling of a memory system are described. The method may include the memory system operating according to a first performance state and determining, while the memory system operates according to the first performance state, whether a temperature metric of the memory system satisfies a first threshold corresponding to a second performance state. Further, the memory system may select, based on the temperature metric satisfying the first threshold, the second performance state from a set of three or more performance states and operate the memory system according to the second performance state based on selecting the second performance state.
The disclosure configures a memory sub-system controller to operate a memory sub-system using one or more shuttle buffers. The controller receives, from a host, a request to program a collection of data, the collection of data having a size corresponding to an individual unit size of an individual component of a set of memory components. The controller places the collection of data in an individual shuttle buffer of one or more shuttle buffers and stores the collection of data from the individual shuttle buffer to the individual component of the set of memory components without waiting for additional data to be received from the host.
This disclosure configures a memory sub-system controller to dynamically perform read disturb scan operations. The controller reads data from an individual page stored on an individual memory component using a first set of read levels. The controller determines that a first error rate associated with reading the data from the individual page using the first set of read levels is greater than a first threshold. The controller reads the data from the individual page using a second set of read levels different from the first set of read levels. The controller selectively folds the individual page stored on the individual memory component based on a second error rate associated with reading the data from the individual page using the second set of read levels.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/10 - Circuits de programmation ou d'entrée de données
Control logic in a memory device comprising a plurality of memory cells, wherein respective pairs of the memory cells are grouped into super cells to store an odd number of data bits, performs, for each of the odd number of data bits, respective sets of strobe reads on a pair of memory cells that form the at least one super cell and generates soft-bit read information corresponding to the at least one super cell based on combined cell state information obtained from the respective sets of strobe reads. The soft-bit read information can indicate a likelihood of the at least one super cell being misread and can be provided to error correction logic for use in error correction operations.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle
The PU of a memory device can receive a matrix of data values and a vector of data values stored in the bank. The PU can perform a first plurality of multiplication operations on a first data value of the vector utilizing a first plurality of data values of a first column of the matrix. The first plurality of multiplication operations can be performed by a plurality of multiply-accumulate (MAC) units. Each of the first plurality of multiplication operations can be performed by a different MAC unit of the plurality of MAC units. The PU can perform a second plurality of multiplication operations on a second data value of the vector utilizing a second plurality of data values of a second column of the matrix. Each of the second plurality of multiplication operations can be performed by a different MAC unit of the plurality of MAC units.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to perform operations including setting a partial translation unit (TU) pointer to identify a first partial-TU of an ordered sequence of partial-TUs, the ordered sequence spanning over a plurality of dies of the memory device. The operations further include, responsive to determining that the first partial-TU has a good health status, appending the first partial-TU to a partial-TU stripe and incrementing the partial-TU pointer to identify a second partial-TU. The operations further include, responsive to determining that the second partial-TU has a bad health status, incrementing the partial-TU pointer without adding the second partial-TU to the partial-TU stripe. The operations further include performing one or more write operations on a plurality of TUs comprised by the partial-TU stripe.
Aspects of the present disclosure are directed to a memory sub-system with isothermal cooling of components. A PCB assembly may be secured between a heat spreader and a heat sink that arc thermally coupled. The heat sink radiates heat absorbed from both sides of the PCB assembly. By connecting the heat spreader to the heat sink, heat is more effectively transferred from the side of the PCB assembly not directly connected to the heat sink. The PCB assembly may be secured between a top enclosure and a bottom enclosure. The top enclosure and the bottom enclosure may be thermally coupled using a vapor chamber. The vapor chamber pumps heat from a higher- temperature side of the PCB assembly to a lower-temperature side of the PCB assembly. By using the vapor chamber to thermally couple the top and bottom enclosures, creation of hot spots is avoided.
A log of memory access requests initiated by a computer and directed to a memory device are received from a host system. A memory address map associated with the computer program is received. A memory access request in the log of memory access requests is identified. The identified memory access request is associated with an address. An object of the computer program is identified based on the memory address map. At least a part of the object resides at a memory location referenced by the address. One or more values of respective one or more memory access metrics associated with the object are determined.
One or more edge blocks of a die of a memory device are identified. A block assignment data structure associated with the memory device is identified. The block assignment data structure comprises a plurality of records, each record mapping one or more specific blocks of the memory device to a corresponding cell type of a plurality of cell types. The one or more identified edge blocks are assigned, by the block assignment data structure, to a single level cell (SLC) cell type.
Control logic in a memory device initiates a memory access operation associated with a memory block of a memory device, wherein the memory block includes a first subset of sub-blocks and a second subset of sub-blocks. During the memory access operation, the control logic causes transmission, via a first sense module coupled to the first subset of sub-blocks, of first data between a page buffer circuit and a first memory cell of the first subset of sub-blocks. During the memory access operation, the control logic causes transmission, via a second sense module coupled to the second subset of sub-blocks, of second data between the page buffer circuit and a second memory cell of the second subset of sub-blocks.
Control logic in a memory device initiates a read operation associated with a memory block of a memory device. During the read operation, the control logic causes transmission, via a sense module, of first data from a first memory cell of a first sub-block of the set of sub-blocks to a page buffer circuit. During the read operation, the control logic causes transmission, via the sense module, of second data from a second memory cell of a second sub-block of the set of sub-blocks to the page buffer circuit.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
77.
THREE-DIMENSIONAL PHASE-CHANGE MEMORY ARRAY OPERABLE TO PERFORM MULTIPLICATION ACCUMULATION OPERATIONS
A memory device having: a first local digit line configured to extend in a first direction; a second local digit line configured in parallel with the first local digit line; a plurality of unit cells stacked in the first direction and sandwiched between the first local digit line and the second local digit line, each respective unit cell among the plurality of unit cells configured to connect the first local digit line to the second local digit line in a second direction that is perpendicular to the first direction, the respective unit cell having a transistor and a memory cell; and a plurality of wordlines configured to extend in a third direction that is perpendicular to the first direction and the second direction, where transistors in the plurality of unit cells are connected to the wordlines.
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
78.
MEMORY DEVICE USING WEAR LEVELING WITH SHARED SCRUB LOOP
Systems, methods, and apparatus for memory management operations in a memory device. In one approach, each of multiple banks in a memory array includes a scrub holding register and a source holding register. Data is scrubbed in the background by moving data from a source page to the scrub holding register. Data in the scrub holding register is scrubbed by error correction circuitry shared by the multiple banks. Any writes that occur to the address of the source page during the scrubbing are made to the source holding register. Status data is recorded regarding any such writes that occur. After scrubbing is complete, the scrubbed data is moved to a target page by combining data from the scrub and source holding registers as guided by the status data.
A system includes a plurality of memory devices and a processing device operatively coupled with the plurality of memory devices, to perform operations including: receiving a request to perform a memory access operation at a first memory region of a first memory device; determining, based on a data structure referencing a namespace, a mapping between an identifier of the first memory region and an identifier of a metadata region associated with the first memory region; identifying, based on an operation type of the memory access operation, one or more corresponding actions associated with the metadata region; and, responsive to causing the memory access operation to be performed on a first plurality of memory cells at the first memory device, causing at least one of the one or more corresponding actions to be performed on a second plurality of memory cells corresponding to the metadata region.
This disclosure configures a memory sub-system controller to dynamically set a die-on-hold flag. The controller computes one or more defectivity criteria associated with an individual memory component of the set of memory components. The controller determines that the defectivity criteria associated with an individual memory component satisfy one or more thresholds. The controller, in response to determining that the defectivity criteria satisfy a first set of thresholds, asserts a die¬ on-hold flag associated with the individual memory component to prevent programming operations from being performed on the individual memory component. The controller, in response to determining that a read trigger associated with the individual memory component satisfies a second set of thresholds, clears the die-on-hold flag to resume performing the programming operations on the individual memory component.
A method of forming a semiconductor wafer is provided. The method includes providing a wafer with an upper surface and a back surface, patterning a backside stop pattern on the upper surface, etching backside stop pins and wafer-bond vias in the upper surface of the wafer, wherein the pins are placed according to the backside stop pattern, and wherein the pins have a depth that is greater than a depth of the wafer-bond vias, filling the backside stop pins with a stopping material, polishing the upper surface to remove excess stopping material, polishing the back surface at a first speed until contacting the backside stop pins; and polishing the back surface at a second speed until contacting the wafer-bond vias, wherein the second speed is slower than the first speed.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
82.
MEMORY CIRCUITRY AND METHODS USED IN FORMING MEMORY CIRCUITRY
Memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a capacitor and a horizontally-oriented transistor. Semiconductor material is directly below the vertically-alternating tiers, Insulative vertical walls extend through the vertically-alternating tiers into the semiconductor material there-below. Individual of the insulative vertical walls below a top of the semiconductor material comprise an upper portion directly above and joined with a lower portion, The individual insulative vertical walls comprise at least one external jog surface in a vertical cross-section in and below the top of the semiconductor material where the upper and lower portions join. The lower portion is wider in the vertical cross-section in the semiconductor material than the upper portion where the upper and lower portions join in the semiconductor material. Method embodiments are disclosed.
This disclosure configures a memory sub-system controller to dynamically compute a select gate (SG) scan threshold. The controller accesses a default cadence criterion associated with an individual portion of a set of memory components and computes a new cadence criterion for the individual portion of the set of memory components based on the default cadence criterion. The controller determines that current cadence information for the individual portion of the set of memory components satisfies the new cadence criterion. The controller, in response to determining that current cadence information for the individual portion of the set of memory components satisfies the new cadence criterion, applies a memory operation to test reliability of the individual portion and selectively retires the individual portion based on a result of testing the reliability of the individual portion.
Aspects of the present disclosure configure a memory sub-system controller to perform a low-stress refresh erase (LSRE) in response to NAND detect empty page (NDEP) operations. The controller performs a first type of erase operation on a portion of a set of memory components. The controller performs a set of memory operations for detecting an empty page in the portion of the set of memory components. The controller, in response to determining that the set of memory operations for detecting the empty page in the portion of the set of memory components has failed, performs a second type of erase operation on the portion of the set of memory components.
Control circuitry (e.g., for a memory device in a system such as a CXL system) can receive counter values indicating a count of available repair resources for addressable portions of a memory device array. The control circuitry can store the counter values as repair flag tokens associated with respective corresponding portions of the addressable portions of the memory device array. Responsive to detecting an error in a first addressable portion of the addressable portions of the memory device array, the control circuitry can change the repair flag token associated with the first addressable portion where the error was detected.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
86.
MEMORY ARCHITECTURES WITH REPLACEMENT GATE THROUGH PIERS
Methods, systems, and devices for memory architectures with replacement gate through piers are described. A memory architecture with relatively uniform memory cell thickness may be formed by forming a stack of materials including alternating layers of sacrificial material and dielectric material. The processing steps may include forming piers and forming cavities for pillars through the stack of materials. The pillars and electrodes may be formed within the cavities, and a subset of the piers may be removed. The layers of sacrificial material may be removed. A protective liner may be deposited around the electrodes and the remaining piers before depositing layers of metal in place of the sacrificial material. The cavities exposed by removing the subset of piers may be filled with new piers. The remaining piers are removed, and memory cells may be formed between the pillars and the electrodes. Then the removed piers are replaced.
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
A command to read data stored in a block of a memory device is received. The block is determined to be a partial block based on the block having one or more unprogrammed pages. Based on the block being a partial block, a partial block offset table is accessed. The partial block offset table comprises a mapping between word line numbers and read-level voltage offsets for partial blocks. A last written page in the block is identified and a word line type is determined based on the last written page. A first read-level voltage offset for the block is determined from the partial block offset table based on the last written page and the word line type. The first read-level voltage offset is applied to the block before performing a read-level voltage calibration process that includes determining second read-level voltage offsets for the block.
A processing device receives a firmware update for a memory sub-system comprising a memory device. Based on the firmware update, the processing device stores a private key of a first device identity key pair in a non-volatile memory component of the memory sub-system such that the private key is persisted upon reset. The first device identity key pair is based on a first device identifier. Upon reset of the memory sub-system, the processing device generates a second device identifier based on the firmware update and generates a second device identity key pair based on the second device identifier. The processing device generates a new device identity certificate based on a public key of the second device identity key pair and signs the new certificate using the private key of the first device identity key pair. The processing device injects the new certificate into a certificate chain for the memory device.
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a media scan on a portion of the memory device to obtain a metrics dataset comprising a plurality of data state metric values; generating, for the metrics dataset, a plurality of data state metric bins comprising a first set of bins having a first bin width and a second set of bins having a second bin width; associating a first data state metric value of the plurality of data state metric values with a first bin of first set of bins, and a second data state metric value of the plurality of data state metric values with a second bin of the second set of bins; and generating a histogram reflecting the data associated with the plurality of data state metric bins.
A processing device in a memory sub-system receives, from a host system, a plurality of memory access requests associated with a plurality of processing threads executed by a plurality of processing cores on the host system, identifies the plurality of processing threads with which the plurality of memory access requests are associated, and tracks respective numbers of the plurality of memory access requests that are associated with each of the plurality processing threads in a given period of time. The processing device further selects, based on the tracking, a subset of the plurality of processing threads, prefetches data associated with the subset of the plurality of processing threads from a memory device and stores the data in a cache memory.
A memory device includes processing logic to perform operations including receiving a data (DQ) circuitry activation command via a command address (CA) bus operatively coupled with CA circuitry of the memory device, wherein the DQ circuitry activation command includes data identifying a die of the memory device, in response to receiving the DQ circuitry activation command, causing DQ circuitry of the memory device to transition from a standby state to an idle state, receiving, via the CA bus, a data transaction initialization command of a data transaction, and in response to receiving the data transaction initialization command, causing the DQ circuitry to transition from the idle state to an active state.
Various embodiments provide for performance of a coarse threshold estimate (CTE) read on a memory device of a memory system under multi-plane mode, such as a memory sub-system. A system comprising: a memory device comprising a plurality of memory cells across a plurality of planes; and a processing device, operatively coupled to the memory device, configured to perform operations comprising: performing a multi-plane coarse threshold estimate read on a subset of the plurality of memory cells across at least a sub-plurality of the plurality of planes, the multi-plane coarse threshold estimate read comprising: performing a read strobe using a read voltage level on the subset of the plurality of memory cells across the at least sub-plurality of planes; and determining a count of non-conducting bitlines connected to the subset of the plurality of memory cells on a single plane of the at least sub-plurality of the plurality of planes, the count of non-conducting bitlines on the single plane being representative of all of the at least sub-plurality of planes; and receiving, from the memory device, the count of non-conducting bitlines on the single planes.
The disclosure configures a memory sub-system controller to store data in a host memory buffer. The controller accesses data that identifies a host memory buffer (HMB) portion of a temporary storage device that has been allocated to a memory sub-system by a host. The controller generates a virtual address space associated with the memory sub-system, the virtual address space comprising a first set of physical storage locations on one or more storage devices of the memory sub-system and a second set of physical storage locations on the HMB. The controller performs one or more memory operations on user data received from the host using the virtual address space and a set of memory components of the memory sub- system.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
94.
APPARATUSES AND METHODS FOR STAGGERED REFRESH OPERATIONS ACROSS MEMORY DEVICES OF A MODULE
A memory module includes a number of memory devices which receive refresh commands. Each memory device determines if it is that device's turn in a sequence, for example by counting the refresh commands. When it is not a device's turn, it performs refresh operations at a first rate responsive to the refresh commands. When it is the device's turn, it performs refresh operations at a second, lower, rate responsive to the refresh commands, for example by skipping refresh operations.
Methods, systems, and devices for front-to-front bonding in a stacked memory system are described. The stacked memory system may include a package substrate and a volatile memory die with a front side. The stacked memory system may also include a logic die with a front side that is bonded with the front side of the volatile memory die. The back side of the stacked memory system may be coupled with a conductive bump that in turn is coupled with the package substrate.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/498 - Connexions électriques sur des substrats isolants
Systems and methods are provided for using a 2.5D PHY and a 3D PHY for communications between a memory device and a host device. The memory device includes a 2.5D PHY for communications with the host device through a predefined communication interface and a 3D PHY for communications with the host device through a customized communication interface. The 2.5D PHY of the memory device is used for communications through the predefined communication interface when the customized communication interface is not available or undesired (e.g., during testing of the memory device).
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
97.
SEMICONDUCTOR DEVICE WITH BACKSIDE CONNECTION MECHANISM AND METHODS FOR MANUFACTURING THE SAME
Methods, apparatuses, and systems related to a memory device having on its backside one or more integrally-formed structures is described. A memory device may include a backside pad- via structure, a backside redistribution layer structure, or a combination thereof. Such backside structures may include integrally-formed portions that extend in different directions to laterally route electrical signals on the backside.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Methods, systems, and apparatuses include receiving, by a memory subsystem, a power down notification. A memory usage pattern for the memory subsystem is retrieved in response to receiving the power down notification. A power mode is selected using the current time and the memory usage pattern. The selected power mode is enabled.
Systems, apparatuses, and methods related to a memory device with enhanced thermal conductivity are described. Embodiments of the present technology can include thermal paths, such as material with a thermal conductivity value less than a threshold value, added into one or more layers in a memory device structure. The added material can provide a path for the thermal energy to dissipate from the memory device.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
Methods, systems, and devices for techniques for memory cell degradation protection are described. In some cases, a memory system may perform a protection operation on blocks of memory cells in response to monitoring the temperature of the memory system. For example, the memory system may monitor the temperature associated with the system over a duration. If the temperature exceeds a threshold, a counter may be adjusted by a first value. If the counter exceeds a second threshold, the memory system may trigger one or more protection operations on the blocks of memory cells. These protection operations may include programming a data pattern to each block of memory cells.
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
brevets
