A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
3.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE
A semiconductor device of an embodiment includes a seed generator circuit configured to generate a seed from inputted data by using first random number sequence data generated by an XorShift circuit; and a random number generator circuit configured to receive the seed as input to generate second random number sequence data by a second XorShift circuit.
A memory system according to one embodiment includes a memory device and a memory controller. The memory device includes memory cells. The memory controller executes a tracking operation. In the tracking operation, the memory controller is configured to cause the memory device to execute a plurality of times of read operations using a plurality of read levels. In the tracking operation, the memory controller is further configured to set a first voltage difference between two adjacent read levels of the read levels in a fourth voltage range lower than a first voltage in a third voltage range and a second voltage difference between two adjacent read levels of the read levels in a fifth voltage range higher than the first voltage in the third voltage range. The first and second voltage differences are different from each other.
According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving from a host a write request designating a first address for identifying data to be written, the controller encrypts the data with the first address and a first encryption key, and writes the encrypted data to the nonvolatile memory together with the first address. In response to receiving from the host a read request designating a physical address indicative of a physical storage location of the nonvolatile memory, the controller reads both the encrypted data and the first address from the nonvolatile memory on the basis of the physical address, and decrypts the read encrypted data with the first encryption key and the read first address.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 21/71 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information
According to one embodiment, in response to receiving a read command from a host, a controller executes a command process of reading data from a nonvolatile memory. The controller executes an address translation process of translating a virtual address specified in the read command to a physical address for accessing a memory of the host. In the address translation process, the controller transmits an address translation request to the host. In response to receiving from the host a response indicating that obtainment of address translation information fails, the controller suspends the command process until the address translation information is obtained, and after the address translation information is obtained, resumes the command process.
A selector includes a base material including carbon; and a dopant implanted into the base material. A method for fabricating a selector includes forming a carbon layer and implanting a dopant into the carbon layer. A semiconductor device includes a selector pattern including carbon as a base material and a dopant implanted through an ion implantation process; and a memory pattern disposed in an upper portion or a lower portion of the selector pattern.
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
8.
BIT ERROR RATE ESTIMATION AND CLASSIFICATION IN NAND FLASH MEMORY
A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
H03M 13/01 - Hypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/43 - Décodage par logique majoritaire ou selon le seuil
A semiconductor memory device includes: a memory cell array including a plurality of bit lines, a source line, a plurality of NAND strings, a first and a second sub block, a first word line group included in the first sub block, a second word line group included in the second sub block, and a dummy word line located between the first and second sub blocks; and a control circuit capable of applying predetermined voltages to the first word line group, the second word line group, and the dummy word line. When a specific word line belonging to the first word line group is selected for the execution of a write operation, a voltage higher than voltages applied to an unselected word line belonging to the first word line group and the second word line group is applied to the dummy word line.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
10.
POLYNOMIAL RING VECTOR INNER PRODUCT COMPUTATION CIRCUIT, COMPUTATION PROCESSING CIRCUIT, AND CONTROL METHOD
According to one embodiment, the polynomial ring vector inner product computation circuit computes an inner product between a first frequency domain polynomial ring vector and a second frequency domain polynomial ring vector, based on the first frequency domain polynomial ring vector obtained by preliminarily executing a process of multiplying each of one or more constant polynomials by 1/N and a process of applying the number theoretic transform to each of the one or more constant polynomials, and outputs a time domain polynomial obtained by applying inverse number theoretic transform to the computed inner product as an inner product between a first polynomial ring vector and a second polynomial ring vector.
According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.
A method of storing data on a storage appliance with at least one non-volatile memory. The method comprising associating a first portion of a storage capacity of the at least one non-volatile memory to a first application of a plurality of applications, and associating a second portion of the storage capacity of the at least one non-volatile memory to a second application of the plurality of applications. The method also comprises receiving a request to write data associated with the first application to the at least one non-volatile memory and determining that the first portion does not have capacity to store the write data. Additionally, the method comprises requesting the second application to remove data stored in the second portion, reassociating a portion of the storage capacity of the second portion to the first portion, and storing the write data in the first portion.
Disclosed herein is a device and method for dynamically processing of a command within a storage system. This includes identifying a plurality of non-volatile memory storage locations of the storage system that have at least one operation parameter associated with the plurality of non-volatile memory storage locations. For each identified plurality of non-volatile memory storage locations, there is a determination whether a value of the at least one operation parameter exceeds a predetermined threshold value. That value is representative of operation effects of the storage system on a corresponding storage location of the identified plurality of non-volatile memory storage locations. During operation of the storage system, there is a throttling of execution of the command to access a storage location of the identified plurality of non-volatile memory storage locations that has the value determined to exceed the predetermined threshold value by a throttle amount determined to mitigate an effect of the value exceeding the predetermined threshold value.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
14.
DATA EXCHANGE BETWEEN HOST AND STORAGE DEVICE USING COMPUTE FUNCTIONS
Various implementations described herein relate to systems and methods for a storage device (e.g., a Solid State Drive (SSD)) to perform a Compute Function (CF), including receiving a command from a host, the command identifying the CF, and in response to receiving the command, performing the CF on at least one of internal data stored in the storage device or external data transferred from the host to determine the computation result of the CF.
According to one embodiment, in response to restoration of power to a memory system, a controller in the memory system notifies a host that the memory system is ready. When an input/output command specifying a logical address belonging to a logical address range is received, the controller selects a block corresponding to the logical address range and rebuilds, based on address translation information and an update log which are stored in the selected block, the latest address translation information corresponding to the logical address range. The controller updates the rebuilt latest address translation information, based on a list of logical addresses corresponding to lost write data, stored in the selected block.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB]
According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.
An imaging device includes a stage holding a subject; a detector including a first pixel layer, an insulating layer, and a second pixel layer stacked on top of one another; an image formation optical member configured to form an image of imaging light transmitted through the subject; and an image processor configured to reconstruct an image of the subject based on a detection intensity of the imaging light. The first pixel layer includes first linear pixels having linear light receiving surfaces extending in a first direction, and the first linear pixels are arranged with equal intervals from one another in a direction orthogonal to the first direction. The second pixel layer includes second linear pixels having linear light receiving surfaces extending in a second direction, and the second linear pixels are arranged with equal intervals from one another in a direction orthogonal to the second direction.
H04N 23/30 - Caméras ou modules de caméras comprenant des capteurs d'images électroniquesLeur commande pour générer des signaux d'image à partir de rayons X
H04N 23/80 - Chaînes de traitement de la caméraLeurs composants
H04N 25/711 - Registres à report et intégration [TDI]Registres à décalage TDI
H04N 25/768 - Capteurs adressés, p. ex. capteurs MOS ou CMOS pour le report et l’intégration [TDI]
18.
SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CHIP BONDED TO A CMOS CHIP INCLUDING A PERIPHERAL CIRCUIT
A semiconductor device includes plural storage portions, plural wirings each extending in a first direction, plural circuits each configured to sense a voltage of a respective one of the plural wirings, and plural pads each provided between one of the wirings and a corresponding one of the circuits. A first circuit and a second circuit among the plural circuits belong to a first group, are adjacent to each other, and are arranged in a second direction intersecting the first direction. A third circuit among the plural circuits belongs to a second group. The first group and the second group are adjacent to each other and arranged in the first direction. The plural pads are adjacent to each other and are arranged in the first direction or a third direction intersecting the first direction and the second direction.
According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
20.
NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME
According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
A method for writing data to a solid-state drive (SSD) configured to store data in a plurality of memory dies each comprising a plurality of memory blocks. The plurality of memory blocks are logically organized as a plurality of superblocks. The method is performed by a controller in communication with the plurality of memory dies. The method comprises associating a superblock of the plurality of superblocks with a data stream of a plurality of data streams received via a write command from a host interface. The method also comprises writing each data stream to the memory blocks of the respective superblock. The method also includes identifying a superblock as a bad superblock if the data stream written to the memory blocks of the superblock does not satisfy a predetermined criteria. Further, the method includes executing garbage collection only on the memory blocks of the bad superblocks.
A system may include a non-volatile memory (NVM), a first memory, a second memory that has a higher speed than the first memory, and a controller. The controller may be configured to receive a first read command from a host computer, and determine a size of one or more buffers that are allocated for one or more read commands that have been received and not returned read data to the host computer. The controller may be configured to determine a number of the one or more read commands, and determine, based on at least the size of the one or more buffers and the number of the one or more read commands, whether to start processing the first read command. In response to determining to start processing the first read command, the controller may be configured to allocate, in the first memory, a first buffer for the first read command.
A controller sets a designated region for a data size, which has consecutive physical addresses, in a storage region of a first memory and stores in a second memory address conversion information in which a head physical address of the consecutive physical addresses is associated with a head logical address of consecutive logical addresses and the data size, in response to a region designation command to which the consecutive logical addresses and the data size are assigned, from a host device. The controller, in response to a read command received from the host device that has a logical address assigned thereto and correspond to data stored in the designated region, determines a physical address corresponding to the logical address assigned to the read command, using the address conversion information stored in the second memory.
A system may include a controller, a write buffer, and a device. The device may include a non-volatile memory (NVM), a first data buffer, and a second data buffer. The controller may be configured to transfer data from the write buffer to the first data buffer and the second data buffer and determine whether a power failure occurs. In response to determining that a power failure does not occur, the controller may configure the device to program data stored in at least one of the first data buffer or the second data buffer to the NVM in a first mode. In response to determining that the power failure occurs, the controller may configure the device to program data stored in at least one of the first data buffer or the second data buffer to the NVM in a second mode different from the first mode.
A method for writing data to an SSD configured to store data in a plurality of memory dies each comprising a plurality of memory blocks. The plurality of memory blocks are logically organized as a plurality of superblocks. The method is performed by a controller in communication with the plurality of memory dies. The method comprises generating, from accumulated write data, a plurality of commands. The method also comprises assigning, to each of the plurality of generated commands, an identifier corresponding to a superblock of the plurality of superblocks associated with the command. The method further comprises tracking a number of commands in each of a plurality of command queues corresponding to the dies of the superblock. The method additionally comprises queuing at least one of the plurality of generated commands to a die of the superblock having a corresponding command queue containing the smallest number of commands.
A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/20 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
A memory device includes a transistor, a capacitor, a plate line, and a bit line. The transistor includes an oxide semiconductor and includes a first end, a second end, and a gate. The capacitor includes a third end and a fourth end. The fourth end is coupled to the second end. The plate line is coupled to the third end. The bit line is coupled to the first end. A second voltage lower than a first voltage is applied to the plate line during a first period over which the first voltage is applied to the gate. A fourth voltage higher than the second voltage is applied to the plate line during at least a part of a second period over which a third voltage lower than the first voltage is applied to the gate.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G11C 11/4099 - Traitement de cellules facticesGénérateurs de tension de référence
28.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE
According to one embodiment a semiconductor device includes an oxide semiconductor column that extends in a first direction. A first electrode contacts a first end of the oxide semiconductor column and a second electrode contacts a second end. A gate electrode surrounds a portion of the oxide semiconductor column. A first insulating film is between the gate electrode and the oxide semiconductor column. A second insulating film is between the gate electrode and the first electrode in the first direction and surrounds the oxide semiconductor column via the first insulating film. A region in which at least a part of the oxide semiconductor column is accommodated is formed by the gate electrode and the second insulating film, and the region has a stepped surface facing towards the second electrode.
A semiconductor memory device includes finger structures arranged in a first direction. The finger structures include a first structure and a second structure different in position in a stacking direction. The first structure and the second structure include insulating member rows including insulating members. Among the insulating member rows in the first structure and the second structure of a first finger structure, one closet to a second finger structure includes a first insulating member and a second insulating member. Among the insulating member rows in the first structure and the second structure of the second finger structure, one closet to the first finger structure includes a third insulating member and a fourth insulating member. A distance in the first direction between the first insulating member and the third insulating member is smaller than a distance in the first direction between the second insulating member and the fourth insulating member.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
30.
FILE TRANSMISSION/RECEPTION DEVICE AND CONTROL METHOD OF FILE TRANSMISSION/RECEPTION DEVICE
According to one embodiment, a file transmission/reception device includes a communication direction managing unit and an application unit. The communication direction managing unit, in near field communication, cuts off a connection with an opposing device in a case where a conflict occurs with the opposing device, and, after being reconnected to the opposing device, switches the file transmission/reception device to any one mode of a master mode and a slave mode. The application unit performs transmission, reception, or transmission/reception of a file between the opposing device and the file transmission/reception device in the master mode or the slave mode in accordance with a mode specified by the communication direction managing unit.
H04B 5/72 - Systèmes de transmission en champ proche, p. ex. systèmes à transmission capacitive ou inductive spécialement adaptés à des fins spécifiques pour la communication locale à l'intérieur d’un dispositif
H04B 5/70 - Systèmes de transmission en champ proche, p. ex. systèmes à transmission capacitive ou inductive spécialement adaptés à des fins spécifiques
H04L 67/06 - Protocoles spécialement adaptés au transfert de fichiers, p. ex. protocole de transfert de fichier [FTP]
H04M 1/72412 - Interfaces utilisateur spécialement adaptées aux téléphones sans fil ou mobiles avec des moyens de soutien local des applications accroissant la fonctionnalité par interfaçage avec des accessoires externes utilisant des interfaces sans fil bidirectionnelles à courte portée
Various implementations described herein relate to systems and methods for transferring data from a source device to a destination device including receiving, by the destination device, a copy request from a host, performing, by the destination device, transfer with the source device to transfer data from buffers of the source device to buffers of the destination device, and writing, by the destination device, the data to a non-volatile storage of the destination device.
An electronic apparatus includes a first substrate, a second substate, and an elastic member. The first substrate has a first surface on which a metal member is provided. The second substrate is coupled to the first substrate above the first surface and on which a plurality of electronic components is mounted. The second substrate has a second surface that faces away from the first surface. The elastic member has an inner surface that contacts the second surface or at least one of the electronic components and an outer surface that faces the first surface and is in thermal contact with the metal member.
First conductors and first insulators are alternately arranged one by one in a first direction in a first region. The first insulators and second insulators are alternately arranged one by one in the first direction in a second region. The memory pillar penetrates the first conductors and the first insulators in the first region and includes a semiconductor. A second conductor includes first to third portions. The second portion electrically couples the first portion and the third portion. A side surface of the third portion is electrically coupled to the semiconductor. A first film extends along the first direction in the second region. A second film contacts the first film, extends along the first direction, and includes carbon or metal. One of the second insulators includes a portion extending along the first and second films in the second region and being distanced from the second film.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
A manufacturing method includes loading a substrate into a chamber, the substrate including oxide semiconductor; configuring a temperature in the chamber to a first temperature; supplying an oxidizing gas into the chamber; lowering the temperature in the chamber from the first temperature; stopping supplying the oxidizing gas into the chamber after lowering the temperature; and unloading the substrate from the chamber after the temperature in the chamber reaches a second temperature lower than the first temperature.
A semiconductor device includes a first electrode, a first oxide semiconductor in contact with the first electrode at one end of the first oxide semiconductor, the first oxide semiconductor extending in a first direction that intersects with a surface of the first electrode, a first insulator surrounding a side surface of the first oxide semiconductor, a first conductor surrounding at least a part of a side surface of the first insulator, a second conductor in contact with another end of the first oxide semiconductor, a third conductor on the second conductor, and a fourth conductor on the third conductor. The third conductor and the fourth conductor include a first metallic element, and the second conductor and the third conductor include oxygen.
A semiconductor device, a circuit board, and a semiconductor device manufacturing method, capable of preventing an unexpected short circuit between wires connected to the circuit board are provided. The semiconductor device comprises: a circuit board including a first surface and a second surface on an opposite side of the circuit board as the first surface; a semiconductor chip provided on the first surface of the circuit board; a passive component connected to an electrode that is provided on the first surface of the circuit board via solder; and sealing resin covering the first surface of the circuit board and surfaces of the semiconductor chip and the passive component. A trench is formed through the first surface of the circuit board along at least a part of a peripheral edge of the electrode, and a plated layer is formed on an inner wall of the trench.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
A semiconductor memory device includes a memory cell array, a well voltage control circuit, and a source voltage control circuit. Before writing data, first and second transistors respectively connected to a select gate line and a word line are turned on at a first timing, and a ground voltage is applied to the first transistor at a second timing and to the second transistor at a third timing. The source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing, and the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing.
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
H10B 69/00 - Dispositifs de mémoire morte reprogrammable [EPROM] non couverts par les groupes , p. ex. dispositifs de mémoire morte reprogrammable aux ultraviolets [UVEPROM]
39.
SEMICONDUCTOR MEMORY DEVICE WITH A THREE-DIMENSIONAL STACKED MEMORY CELL STRUCTURE
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 7/18 - Organisation de lignes de bitsDisposition de lignes de bits
G11C 8/12 - Circuits de sélection de groupe, p. ex. pour la sélection d'un bloc de mémoire, la sélection d'une puce, la sélection d'un réseau de cellules
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
40.
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
According to one embodiment, a memory system includes a non-volatile memory and a data map configured to manage validity of data written in the non-volatile memory. The data map includes a plurality of first fragment tables corresponding to a first hierarchy and a second fragment table corresponding to a second hierarchy higher than the first hierarchy. Each of the first fragment tables is used to manage the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second fragment table is used for each of the first fragment tables to manage reference destination information for referencing the first fragment table.
A nonvolatile memory includes a memory cell transistor storing information of a plurality of bits including first through third bits, a word line, a sense amplifier unit, and a control circuit which controls the word line and the sense amplifier unit. The control circuit includes first through third latch circuits, and performs plural read operations including a first read operation to read out the first bit into the first latch circuit and generate data in the second and third latch circuits, a second read operation performed after the first read operation to read out the second bit into the first latch circuit and update the data in the second and third latch circuits, and a third read operation performed after the second read operation to read out the third bit into the first latch circuit and update the data in the second and third latch circuits.
In a memory system, a switch is connected between a controller and multiple non-volatile storage units, where the switch comprises first and second pins, a data bus, and a plurality of enable outputs. The switch is configured to transmit a signal to enable a communication path between the controller and one of the non-volatile storage units and to receive data over the data bus to be stored in one of the non-volatile storage units when the first and second pins are not asserted. In addition, the switch is configured to receive a command to be executed by one of the non-volatile storage units when the first pin is not asserted and the second pin is asserted. The switch is also configured to receive an address of a storage location within one of the non-volatile storage units when the first pin is asserted and the second pin is not asserted.
A semiconductor device includes an interposer substrate including a plurality of wiring layers inside, a first semiconductor chip disposed on the interposer substrate, and a power circuit configured to transform externally supplied voltage and supply the transformed voltage to the first semiconductor chip. The power circuit includes an inductor and a capacitor, the inductor being constituted by a plurality of coil patterns respectively formed in at least two of the plurality of wiring layers.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
According to one embodiment, a memory device includes: a first semiconductor and a first insulator provided at a first position in a first direction intersecting a substrate; a first conductor extending in the first direction and having a first portion facing the first semiconductor without interposing the first insulator and a second portion facing the first insulator without interposing the first semiconductor; and a first charge storage film provided between the first portion and the first semiconductor and not provided between the second portion and the first insulator.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller verifies safety of a request source requesting to write data to or read data from the nonvolatile memory using a challenge-response type attestation.
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures
A controller of a memory system issues a first memory read request for reading first data at a head of data to be read from a first memory die to the first memory die. When remaining data following the first data is included in the data to be read, the controller transfers a first identifier from a first command queue to a second command queue corresponding to a second memory die in which second data at a head of the remaining data is stored. The controller issues a second memory read request for reading the second data from the second memory die to the second memory die in response to transferring the first identifier to the second command queue.
An electronic device includes a first control circuit and a second control circuit. The first control circuit can acquire, when a first reception circuit and a first transmission circuit transition from a first state of communicating at a first communication speed conforming to a first specification to a second state of communicating at a second communication speed conforming to a second specification, a first adjustment value related to one setting value applied to a third transmission circuit, and transmit the first adjustment value to the second control circuit. The second control circuit can determine, when a second reception circuit and a second transmission circuit transition from the first state to the second state, a second adjustment value which is one setting value applied to a fourth transmission circuit, based on the first adjustment value transmitted from the first control circuit.
A semiconductor storage device of an embodiment includes a substrate, a seal member, a first memory chip, and a non-signal wiring. The non-signal wiring has a wiring main body. The wiring main body includes a first portion, a second portion, a third portion. The first portion extends in a second direction intersecting the first direction. The second portion is folded back from an end of the first portion to a first side in the second direction. The second portion extends parallel to the first portion. The third portion is folded back from an end of the second portion to a second side in the second direction. The second side is a side opposite to the first side in the second direction. The third portion extends parallel to the second portion.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
A storage device includes: a first wiring; a second wiring; a memory cell provided between the first wiring and the second wiring, the memory cell including a resistance change storage element configured in a first resistance state or a second resistance state, and a selector connected to the resistance change storage element and configured to shift from off-state to on-state when voltage higher than a first threshold voltage is applied; a switching element configured to input a first signal from the second wiring and output a second signal to a third wiring; a voltage application circuit configured to apply a first voltage to the first wiring at a first time point; and a determination circuit configured to determine the resistance state of the resistance change storage element based on the second signal output to the third wiring at a second time point after the first time point.
In one embodiment, a prober includes a stage configured to hold a substrate as an inspection object. The prober further includes a housing configured to hold a probe card that can be electrically connected to the substrate, and hold a performance board that can be electrically connected to the probe card. Moreover, the housing is configured to function as a ground line, and includes a connection path configured to electrically connect the probe card and the performance board.
A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to read data from the non-volatile memory, obtain a plurality of decoded words based on a syndrome calculated from a soft decision input data based on the read data, calculate a plurality of metrics for the plurality of decoded words, generate a metric array using the calculated metrics. Further, the memory controller is configured to, based on a relationship of each value of the metric array with a smallest one of the metrics and a second smallest one of the metrics, obtain a soft decision output data corresponding to the soft decision input data.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
53.
APPROXIMATE NEAREST NEIGHBOR SEARCH OF DATA FROM STORAGE
A method for searching data from a storage is provided. The method includes, in response to a query, selecting one or more candidate posting lists among a plurality of posting lists, based on a distance between a query vector corresponding to the query and a representative vector of each of the plurality of posting lists, acquiring the one or more candidate posting lists from the storage, decompressing one or more compressed posting lists included in the one or more candidate posting lists, after the decompressing, selecting one or more vectors included in the one or more candidate posting lists based on a distance between the query vector and each of vectors included in the one or more candidate posting lists, and outputting one or more searchable data pieces corresponding to the selected one or more vectors as an answer to the query.
A semiconductor memory device includes a memory cell array, a control circuit, and a voltage generation circuit. The control circuit is configured to perform a first operation to access the memory cell array and then a second operation to access the memory cell array. The voltage generation circuit is configured to generate a first operation voltage, which is supplied from an output terminal of the voltage generation circuit to the memory cell array during the first operation, and a second operation voltage, which is supplied from the output terminal to the memory cell array during the second operation. The control circuit is configured to control the voltage generation circuit to maintain a voltage output from the output terminal to be at the first operation voltage after the first operation until the second operation voltage starts to be supplied to the memory cell array for the second operation.
A semiconductor manufacturing apparatus includes a chamber, an opening/closing portion, and a pressure control circuit. The chamber includes first and second portions, both of which are capable of accommodating a wafer. The opening/closing portion is provided between the first portion and the second portion, and is movable to open and close a space between the first and second portions. The pressure control circuit is configured to control a pressure difference between the first portion and the second portion.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
A memory system includes a non-volatile memory and a controller that is configured to: write N pieces of address translation information repeatedly in a first block according to a first order; write the N pieces of address translation information repeatedly in a second block of the non-volatile memory according to a second order that is offset from the first order by N/2; write an update log in the first and second blocks each time one of the N pieces is written; and in response to power to the memory system being restored after shutdown, read from the first block, N/2 pieces of address translation information and N/2 update logs last written thereinto, read from the second block, N/2 pieces of address translation information and N/2 update logs last written thereinto, and reconstruct a logical-to-physical address translation table from the information read from the non-volatile memory.
According to one embodiment, a semiconductor memory device includes first and second stacked bodies. In each of the first and second stacked bodies, conductive layers and insulating layers are alternately stacked one by one. The semiconductor memory device includes first and second bridging members. The first bridging member penetrates the first stacked body and connects first interlayer insulating films covering a first staircase part on both sides. The first bridging member is provided on an upper end of a first platy member. The second bridging member penetrates the second stacked body and connects second interlayer insulating films covering a second staircase part on both sides. The second bridging member is provided on an upper end of a second platy member. Lower ends of the first and second bridging members are positioned above uppermost conductive layers of the first and second stacked bodies, respectively.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
58.
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS
A semiconductor device manufacturing method of embodiments includes: forming a first conductive film containing indium on a substrate; forming a first insulating film; forming a second conductive film; forming a second insulating film; forming an opening penetrating the second insulating film, the second conductive film, and the first insulating film to reach the first conductive film; forming a third insulating film in the opening so as to be in contact with bottom and side surfaces of the opening; removing the third insulating film at a bottom of the opening to expose the first conductive film at the bottom of the opening; performing a first treatment using a first gas containing silicon or a second treatment using a second gas containing oxygen; and forming a semiconductor film in the opening without exposing the substrate to an atmosphere with a pressure equal to or more than atmospheric pressure.
H01L 29/26 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, des éléments couverts par plusieurs des groupes , , , ,
C23C 16/52 - Commande ou régulation du processus de dépôt
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 29/66 - Types de dispositifs semi-conducteurs
According to one embodiment, a memory device includes: a memory cell array including first to ninth areas; first and second column switch circuits; first and second row switch circuits. In a case where a cell in the sixth area is selected, the first and second column switch circuits and the first row switch circuit are activated, and in a case where a cell in the seventh area is selected, the second column switch circuit and the first and second row switch circuits are activated, and in a case where a cell in the eighth area is selected, the first and second column switch circuits and the second row switch circuit are activated, and in a case where a cell in the ninth area is selected, the first column switch circuit and the first and second row switch circuits are activated.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
According to one embodiment, a magnetic memory device includes a first ferromagnetic layer having a fixed magnetization direction, a second ferromagnetic layer having a variable magnetization direction, a first nonmagnetic layer provided between the first ferromagnetic layer and the second ferromagnetic layer, and a second nonmagnetic layer provided on an opposite side to a side on which the first nonmagnetic layer is provided with respect to the second ferromagnetic layer. At least one of the first nonmagnetic layer and the second nonmagnetic layer is an oxide layer including magnesium (Mg) and a group 4 element. The group 4 element includes at least one element selected from a group consisting of zirconium (Zr), hafnium (Hf), and rutherfordium (Rf).
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
According to one embodiment, a communication device connected in a ring shape, the communication device comprising: receiving circuitry; first circuitry configured to be capable of executing insertion and extraction of data; and transmitting circuitry configured to transmit a communication frame based on a result of the first circuitry, wherein after the receiving circuitry receives a first container including, as transmission destinations, the communication device and a first device, the transmitting circuitry is configured to transmit a second communication frame including the first container including the first device as a new transmission destination, with the communication device being excluded from the transmission destinations of the first container.
According to an embodiment, a first data set is a set of inspection results for chips formed on a wafer or cut out from the wafer. The inspection results are obtained by executing a first inspection on the chips. A second data set indicates, for each chip, presence or absence of early failure obtained by executing a second inspection on the chips. A processor determines, based on the first data set, a cluster of chips not satisfying a first criterion. The processor calculates a third data set being a set of feature amounts of chips related to a distance to the cluster. The processor executes training of a machine learning model by using, as input data, the first data set and the third data set and using the second data set as correct answer data. The processor outputs the machine learning model of which the training has been executed.
A storage device includes a memory cell including a first layer, a second layer, and a memory layer between the first and second layers and can switch between states including a first state and a second state in which electrical resistance is higher, and a circuit executing a write process. The control circuit is configured to, in the process to switch the memory layer from the second to first state, alternately apply to the second layer a first voltage having positive polarity and a second voltage having negative polarity, an absolute value of the second voltage being larger than the first voltage, and in the process to switch the memory layer from the first to second state, alternately apply to the second layer a third voltage having negative polarity and a fourth voltage having positive polarity, an absolute value of the fourth voltage being larger than the third voltage.
According to one embodiment, a communication system includes a host controller, a plurality of communication devices, and a communication path coupling the host controller and the communication devices in a ring shape and configured to transmit a communication frame for serial communications, wherein the host controller and the communication devices each includes an ECC circuit configured to detect and correct an error and having a variable error correction capability, and the host controller is configured to set an error correction capability of the ECC circuit in accordance with an error caused in the communication path.
According to an embodiment a semiconductor memory device includes a laminated structure with first layers and second layers alternately stacked in a first direction. A first and second bit line extends through the laminated structure. The second bit line is spaced from the first bit line in a second direction. Each first layer has a word line that extends in the second direction, a first semiconductor layer that extends alongside word line and is connected to the first bit line, a second semiconductor layer that extends alongside the word line and is spaced from the first semiconductor layer in the second direction, a gate insulating layer between the word line and the first or second semiconductor layer, a part of a first capacitor connected to the first semiconductor layer, and a part of a second capacitor connected to the second semiconductor layer.
A semiconductor storage device includes a memory cell and a control circuit. In an overall read operation, the control circuit performs a first read operation to detect a first voltage and determine first data from the detected first voltage, writes second data to the memory cell, performs a second read operation to detect a second voltage and determine the second data from the detected second voltage, and compares the first data and the second data based on the first voltage and the second voltage to determine a value of the first data. When the first data and the second data are different, the control circuit performs a sequence of operations that includes a second write operation to write the first data and a verify read operation. Based on third data detected by the verify read operation, the control circuit ends the overall read operation or repeats the sequence of operations.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
According to one embodiment, a semiconductor storage device has a laminated body comprising conductive layers alternating with insulating layers in a first direction. A column extends into the laminated body and includes a first polycrystalline semiconductor film extending along the column in the first direction and a first insulating film extending along the column in the first direction. The first insulating film is between the conductive layers and the first polycrystalline semiconductor film. The first polycrystalline semiconductor film includes a first section corresponding in position along the first direction to an uppermost conductive layer among the conductive layers in the laminated body and a second section that is between the first section and a substrate in the first direction. An average grain diameter of the first section is smaller than an average grain diameter of the second section.
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
68.
SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE UNIT
A semiconductor storage device includes a first substrate including a first layer and a second layer on the first layer, a memory chip on the first layer, a controller disposed on the first layer and configured to control the memory chip, and molding resin that covers the first layer, the memory chip, and the controller. The second layer of the first substrate includes a conductive pattern including a plurality of terminals, and an insulating layer partially covering the conductive pattern and the first layer, and at a part of the first layer not covered by the insulating layer, one or both of the conductive pattern and the insulating layer form first concaves at predetermined intervals.
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
According to one embodiment, a magnetic memory device includes a first wiring line extending along a first direction, a second wiring line provided on an upper layer side of the first wiring line and extending along a second direction, a memory cell provided between the first wiring line and the second wiring line, including a bottom surface connected to the first wiring line and a top surface connected to the second wiring line, and including a magnetoresistance effect element and a switching element stacked in a third direction, and a contact including a top surface connected to the second wiring line, the top surface of the contact being located higher than the top surface of the memory cell.
G11C 5/08 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage pour interconnecter des éléments magnétiques, p. ex. des noyaux toroïdaux
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
An array controller for connection between a solid state drive controller and multiple non-volatile storage units is provided. The array controller comprises a plurality of enable outputs, each of which is connected to an enable input of one of the non-volatile storage units, and a buffer in which data to be written into or read from the non-volatile storage units is stored. The array controller further comprises a control unit configured to enable a communication path between the solid state drive controller and one of the non-volatile storage units according to an address received from the solid state drive controller.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
71.
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE THAT INCLUDES A PLURALITY OF STRINGS
According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
G11C 29/52 - Protection du contenu des mémoiresDétection d'erreurs dans le contenu des mémoires
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes combinant plusieurs codes ou structures de codes, p. ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
According to one embodiment, a semiconductor memory device includes first to second areas, a plurality of conductive layers, first to fourth members, and a plurality of pillars. The second area includes a first contact area including first to third sub-areas. The conductive layers include first to fourth conductive layers. The first conductive layer includes a first terrace portion in the first sub-area. The second conductive layer includes a second terrace portion in the third sub-area. The third conductive layer includes a third terrace portion in the first sub-area. The fourth conductive layer includes a fourth terrace portion in the third sub-area.
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
A semiconductor memory device includes plural planes each including plural blocks each including a memory cell, a voltage generator which supplies power to the plural planes, an input/output circuit which receives a command set sent from a memory controller to the semiconductor memory device, and a sequencer which executes an operation in response to the command set. Upon receiving a first command set instructing execution of a first operation, the sequencer executes the first operation. Upon receiving a command set instructing operation of a second operation during execution of the first operation, the sequencer executes the first and second operations in parallel. Upon receiving a third command set instructing execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
According to one embodiment, an information processing apparatus includes a connecting portion connectable to a removable memory device and a power supply circuit configured to apply a first voltage and a second voltage to the removable memory device. When the removable memory device is connected to the connecting portion, one of a pair of first feedback wires is electrically connected to one of the first power supply terminals to which the first voltage is applicable, and the other of the pair of first feedback wires is electrically connected to one of the power supply ground terminals connectable to a ground level, the power supply circuit is configured to control the first voltage, based on a voltage between the pair of first feedback wires.
H02M 3/04 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques
A semiconductor memory device includes: a substrate; a first wiring; a first semiconductor layer disposed between the substrate and the first wiring; second semiconductor layers disposed between the first semiconductor layer and the first wiring; a first via-wiring connected to the first and the second semiconductor layers; a first memory portion connected to the first semiconductor layer; a first gate electrode opposed to the first semiconductor layer; a second wiring connected to the first gate electrode; connection electrodes connected to the second semiconductor layers; second gate electrodes opposed to the second semiconductor layers; third wirings disposed between the second and the first wiring and connected to the second gate electrodes; a fourth wiring connected to the first memory portion; a fifth wiring connected to the connection electrodes in common; and an insulating layer disposed between the fourth wiring and the fifth wiring.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
76.
MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
According to an embodiment, a memory system includes a nonvolatile memory including memory cells and a memory controller coupled to the nonvolatile memory. Each of the plurality of memory cells is configured to store, in a nonvolatile manner, a plurality of bits of data. The memory controller is configured to, in a case where a first memory cell stores valid first bit data as a first bit and does not store data as a second bit, and a second memory cell stores valid second bit data as the first bit and does not store data as the second bit, and upon reception of a flush command from a host, read the second bit data from the second memory cell and write the second bit data read from the second memory cell to the first memory cell as the second bit.
According to one embodiment, a controller of a memory system provides a host with logical address spaces. A plurality of queues of the host include one or more queues allocated to each of the logical address spaces. The controller calculates first use amounts of a nonvolatile memory corresponding to the logical address spaces, respectively, selects a queue from which a command is to be fetched among the plurality of queues, based on the first use amounts, fetches a command from the queue, calculates a predicted use amount of the nonvolatile memory in accordance with the command, and updates a second use amount corresponding to a first logical address space to which the first queue is allocated among the first use amounts by using the predicted use amount.
According to one embodiment, a controller includes a counter counting a number of accesses of data in a nonvolatile memory, in a first unit which is a unit of access to data from the host. The controller determines whether a received read command is a sequential read command or a random read command, increments a value of the counter, which corresponds to data specified by the received read command, when the received read command is the random read command, and in a process of moving first data of a first block to a second block, controls rearrangement of the first data of the first block to the second block based on the value of the counter when the first data has a size of the first unit and needs to be arranged across two pages in the second block.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
According to one embodiment, in a test apparatus, a controller obtains a threshold voltage of a memory cell by performing first processing on a read characteristic. The first processing is processing of, when a subthreshold region in the read characteristic is defined as a first region, focusing on a second region being a region of a read voltage larger than a maximum read voltage of the first region. The controller calculates a first slope in a first threshold characteristic indicating a relationship between a write voltage and the threshold voltage in the write processing, based on the threshold voltage obtained in the first processing. The controller subtracts the first slope from a slope in a predetermined threshold characteristic to obtain a first slope degradation component.
According to one embodiment, a substrate peeling device including an adsorption stage and a light source is provided. A bonded body including multiple substrates is adsorbed to the adsorption stage. The adsorption stage includes a first region and a second region. The second region is inside the first region. The light source can sequentially apply a laser beam toward the first region and the second region. The adsorption stage has weaker power of adsorbing the bonded body in the second region than in the first region.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces
81.
SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND CONTROL METHOD
A semiconductor memory device includes memory cell transistors and a control circuit. The control circuit is configured to set a threshold voltage of each memory cell transistor to be in one of voltage ranges to store multi-bit data in each memory cell transistor. The voltage ranges include a first range corresponding to a first multi-bit value, a second range lower than the first range and corresponding to a second multi-bit value, and a third range that is the lowest. When a target memory cell transistor in which data of the second multi-bit value is to be written currently stores data of the first multi-bit value, the control circuit is configured to apply a first voltage to a gate of the target memory cell transistor, to shift the threshold voltage of the target memory cell transistor to be in the second range without dropping into the third range.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/12 - Circuits de commutation de la tension de programmation
A semiconductor storage device includes a substrate, a semiconductor memory, a controller, and an electronic part. The substrate has opposing first and second faces extending in a first direction, a third face extending in a thickness direction of the substrate, a recess provided in the third face and extending in the thickness direction, and a conductive portion provided on an inner face of the recess. The electronic part has a main body and a lead protruding from the main body. The lead has a first portion, which protrudes linearly from the main body toward the recess in the first direction, and a second portion bent from the first portion and extending linearly along the inner face of the recess in the thickness direction, and the second portion is fixed to the conductive portion such that one portion of the first portion overlaps the recess when viewed in the first direction.
According to embodiments, a semiconductor memory device includes a memory string including a first select transistor, a first memory cell, and a second memory cell, a bit line, a first word line, a second word line, and a control circuit configured to execute a write operation including a program operation and a program verify operation. The control circuit is configured to raise a voltage of the second word line to a first voltage based on a first condition, in a case of executing the program verify operation of the first memory cell, and to raise a voltage of the first word line to the first voltage based on a second condition different from the first condition, in a case of executing the program verify operation of the second memory cell.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
84.
SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
According to an embodiment, a clock signal is input to clock terminals of first and second FFs. A first signal from a Q terminal of the first FF is input to a D terminal of the second FF. A first inverter performs inversion calculation on a second signal from a Q terminal of the second FF. A signal from the first inverter is input to a D terminal of the first FF. A second inverter performs inversion calculation on the first signal. (L−1) adders each calculate a different bit of a Gray code by an addition operation based on a carry signal. A circuit block generates a carry signal for a first adder based on a logical product of the first/second signals. The circuit block generates carry signals of second to (L−1)th adders based on the second signal and a signal from the second inverter.
H03K 19/21 - Circuits OU EXCLUSIF, c.-à-d. donnant un signal de sortie si un signal n'existe qu'à une seule entréeCircuits à COÏNCIDENCES, c.-à-d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
According to one embodiment, a charge pump circuit includes: a current source; a first current mirror including an input terminal connected to the current source; a second current mirror including an input terminal connected to an output terminal of the first current mirror; a third current mirror including an input terminal connected to a first output terminal of the second current mirror; a first switch including a first end connected to a second output terminal of the second current mirror via a first node, and including a second end; and an output terminal connected to an output terminal of the third current mirror and the second end of the first switch via a second node.
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
A semiconductor memory device includes: a first conductive layer; and a second conductive layer adjacent to the first conductive layer. Write loops each include: a first program operation that applies the first conductive layer with a program voltage and applies a bit line with a first bit line voltage; and a second program operation that applies the first conductive layer with the program voltage and applies the bit line with a second bit line voltage larger than the first bit line voltage. The write operation includes a state judging operation that judges whether a memory cell corresponding to the semiconductor layer and the second conductive layer has been controlled to a Low-state, or not. When the memory cell has been controlled to the Low-state, the first program operation is executed, and when the memory cell has not been controlled to the Low-state, the second program operation is executed.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
According to one embodiment, a manufacturing apparatus includes: a wafer holding unit configured to hold a wafer; an ion source configured to output an ion beam; a shutter holding unit configured to hold a shutter and place the shutter between the wafer holding unit and the ion source in a case of preventing irradiation of the wafer with the ion beam; and a target holding unit configured to hold a target including a through hole, and place the target between the wafer holding unit and the ion source in a case of forming, on the wafer, a first layer including a member of the target.
In one embodiment, a semiconductor memory device includes a stacked body of a first conductive films and first insulation films alternately stacked with each other in a first direction. A plurality of columnar bodies is in the stacked body. Each columnar body includes a first semiconductor part extending in the first direction, a first insulation part between the first semiconductor part and the stacked body, a second insulation part between the first insulation part and the stacked body, third insulation parts between the second insulation part and the first conductive films, and fourth insulation parts between the second insulation part and the first insulation films. Each second insulation part has first portions between the first insulation part and the first conductive films and second portions between the first insulation part and the first insulation film. The second portions are thinner than the first portions in a second direction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
A semiconductor memory device includes: a first via-wiring extending in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the first via-wiring; memory portions arranged in the first direction and electrically connected to the first semiconductor layers; first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers; first wirings arranged in the first direction and electrically connected to the plurality of first gate electrodes; second semiconductor layers arranged in the first direction and electrically connected to the first wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; a second via-wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and second wirings arranged in the first direction and electrically connected to the second semiconductor layers.
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
H10B 51/10 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la configuration vue du dessus
H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
90.
MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP
A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/18 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire avec commande prioritaire
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
91.
THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
A memory system includes a memory device including a plurality of memory cell transistors, and a memory controller. The memory controller is configured to write data to each of the plurality of memory cell transistors, the data having one of a plurality of bit values, read the data from the plurality of memory cell transistors, and measure a number of errors included in the read data with respect to two of the bit values of which corresponding threshold voltage distributions are adjacent to each other. The memory controller is further configured to adjust a difference between the threshold voltage distributions corresponding to the two of the bit values based on the measured number of errors.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 29/52 - Protection du contenu des mémoiresDétection d'erreurs dans le contenu des mémoires
93.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes: a first semiconductor layer; a second semiconductor layer provided above the first semiconductor layer; a third semiconductor layer interposed between the first and second semiconductor layers; a stacked body provided above the second semiconductor layer, in which a plurality of conductive layers are stacked one by one while being separated from each other; and a pillar including a channel layer that extends through the stacked body, the second semiconductor layer, and the third semiconductor layer in a stacking direction of the stacked body and reaches a predetermined depth of the first semiconductor layer. The channel layer is electrically connected to the third semiconductor layer on a side surface. The pillar has a cross-sectional area as viewed from the stacking direction that is larger at a height position of the first semiconductor layer than at a height position of the third semiconductor layer, and has a stepped portion at a height position of an interface between the first semiconductor layer and the third semiconductor layer.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
94.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device of an embodiment includes: first and second regions that are provided in a substrate, the first and second regions containing impurities of a first conductivity type; a gate electrode disposed above the substrate between the first and second regions; first and second metal silicide layers disposed in the first and second regions, respectively; and first and second contacts connected to the first and second regions via the first and second metal silicide layers, respectively, in which the first and second contacts include: first and second oxidized silicide layers that are disposed at lower end portions of the first and second contacts and contain a predetermined metal different from metals included in the first and second metal silicide layers, respective; and metal layers that are in contact with the first and second oxidized silicide layers and extend in a second direction that intersects the first direction, respectively.
According to one embodiment, a storage device includes a stacked layer structure including a switching element, an electrode including a first electrode portion, and a variable resistance element, which are stacked in a first direction, wherein the switching element and the electrode are in contact with each other in the first direction, and a first face of the first electrode portion on a side of the switching element is in contact with a second face that is inside the stacked layer structure and that is larger than the first face.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
G11C 5/08 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage pour interconnecter des éléments magnétiques, p. ex. des noyaux toroïdaux
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
96.
SEMICONDUCTOR PRODUCT EVALUATION DATA MANAGEMENT SYSTEM, SEMICONDUCTOR PRODUCT EVALUATION DATA MANAGEMENT METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM STORING A SEMICONDUCTOR PRODUCT EVALUATION DATA MANAGEMENT PROGRAM
According to one embodiment, a semiconductor product evaluation data management system includes a computer server that manages evaluation data of a semiconductor product and a plurality of storage devices that store the evaluation data. The computer server includes a storage data index file configured to store an index attached to the evaluation data to be stored in the computer server and the plurality of storage devices; a storage data index updating unit configured to store and update manufacturing information of semiconductor product in the index; and a storing method updating unit configured to control movement of the evaluation data to a specific storage device among the plurality of storage devices in a unit of the manufacturing information of the semiconductor product in accordance with the index.
A semiconductor storage device of an embodiment includes: a plurality of memory strings each including a plurality of memory cell transistors, the plurality of memory strings being connected in parallel to one another; and a control circuit configured to control a write operation on at least part of the plurality of memory cell transistors. The write operation is executed in response to reception of the write command and the address. The control circuit determines, based on the address, whether to perform a first voltage application operation before the write operation ends. The first voltage application operation applies a predetermined voltage to the plurality of word lines.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
98.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor substrate; a transistor formed on the semiconductor substrate; a first insulating layer adjacent to the transistor in a first direction along a main surface of the semiconductor substrate, the first insulating layer being formed toward an inside of the semiconductor substrate; a first conductive layer connected to a gate of the transistor, a part of the first conductive layer being opposed to the first insulating layer; a second insulating layer disposed between the first insulating layer and the first conductive layer; and a first semiconductor layer disposed between the second insulating layer and the first conductive layer.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
A semiconductor device includes: an oxide semiconductor including a first end and a second end and extending in a first direction oriented from the second end to the first end; a first electrode configured to come into contact with the first end of the oxide semiconductor; a second electrode configured to come into contact with the second end of the oxide semiconductor; a gate electrode configured to enclose the oxide semiconductor with a first insulating film interposed therebetween between the first and second ends of the oxide semiconductor; and a metal film including a cylindrical portion that comes into contact with the gate electrode in the first direction and encloses the oxide semiconductor with the first insulating film interposed therebetween.
brevets
