A computer implemented method for filtering a spatial index is provided. When implemented in a rendering loop, the computer implemented method reduces a number of client server calls by removing item paths that are not visible in the configured product early in the rendering loop. The method includes identifying a subset of spatial bounding boxes that are visible from a given viewpoint of a scene displayed on a client device, communicating a request to a product management server to obtain model data for each of the spatial bounding boxes in the subset, receiving a message from the product management server in response to the request, and filtering the subset based on the message
A system and method for managing queries pertaining to a product are provided. The method includes receiving, by a processing unit, a user query from a user device. Further, one or more contexts are identified from a plurality of contexts by comparing the user query with each context among the plurality of contexts. Each of the contexts includes values of one or more attributes characteristic to at least a part of the product. Further, a prompt is generated by updating the user query based on the one or more contexts identified. The prompt is provided as input to a Large Language Model to generate a natural language output, on an output device.
A computer-implemented method in a manufacturing process to manufacture an object using at least one manufacturing machine is disclosed. The method comprises, obtaining model data representing the object, determining one or more features of the object represented by the model data by generating for each feature a respective feature descriptor in the form of a vector of numbers describing characteristics of the respective feature and performing a machine-learning model on each feature descriptor to classify the respective feature and determining the one or more features based on the classifications, determining machine operations to manufacture the determined features, and determining an order of performance of the determined machine operations to manufacture the determined features.
Embodiments of the present disclosure provide a method and apparatus for designing a cooling channel, an electronic device and a computer storage medium. The method includes: acquiring a product molding line contained in a mold; receiving cooling channel quantity information, the cooling channel quantity information representing a quantity of cooling channels; generating a target polygon in the mold for an enclosed area formed by the product molding line, the target polygon being located inside the enclosed area, or, the target polygon containing the enclosed area, the target polygon having the quantity of sides matching the quantity of the cooling channels; and determining positions of the cooling channels in the mold based on positions of sides of the target polygon, to generate the cooling channels based on the positions of the cooling channels in the mold. The solution provided by the embodiments of the present disclosure may improve a design efficiency and a cooling effect.
Methods for use in integrated circuit design and corresponding systems and computer- readable mediums. A method includes receiving (902) a mask pattern for a semiconductor layer. The method includes creating (904) edge grids (322, 324, 326, 328, 330) corresponding to the mask pattern and creating (906) proximity grids (1002) corresponding to the mask pattern. The method includes convolving (908) each edge grid (322, 324, 326, 328, 330) and each proximity grid (1002) with a corresponding kernel (700) and summing (910) the convolutions and a rastered mask grid to produce a final mask pattern. The method includes performing (912) a simulation of a manufacturing process using the final mask pattern.
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p. ex. correction par deuxième itération d'un motif de masque pour l'imagerie
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
6.
ANALOG SIMULATION OF CIRCUIT DESIGNS WITH TEMPORAL PARALLELISM AND TIME-VARIANT REDUCTION
A computing system (101) implementing a design verification system (300) to alter (401) a circuit design (301) describing an electronic system into a simplified representation of the circuit design (313), and also implement an analog simulator (340) to perform (402) a simulation of the simplified representation of the circuit design. The design verification system can identify (403) circuit activity (317) corresponding to the electronic system in different temporal windows during the simulation of the simplified representation of the circuit design, perform (404) a topological analysis of the circuit design based, at least in part, on the identified circuit activity in the different temporal windows. The design verification system can modify (405) the circuit design into a plurality of circuit design subsets corresponding to the different temporal windows based, at least in part, on the topological analysis.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
7.
DETERMINING PARASITIC ELEMENTS OF AN INTERCONNECT OF AN ELECTRONIC CIRCUIT LAYOUT
The invention relates to a method for determining parasitic elements of an interconnect of an electronic circuit layout. To facilitate determining the parasitic elements, the method includes determining an interconnect parasitic model from a plurality of interconnect parasitic models of the interconnect based on a comparison between at least one performance indicator associated with each one of the interconnect parasitic models, and determining the parasitic elements of the interconnect based on the determined interconnect parasitic model.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 30/333 - Conception en vue de la testabilité [DFT], p. ex. chaîne de balayage ou autotest intégré [BIST]
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
A circuit configured to monitor functional signals comprises a signal selection unit configured to select signals for monitoring from one or more signal sources and a signature generation unit configured to generate signatures for the selected signals. The signature generation unit comprises one or more multiple-input signature registers. Each of the one or more multiple-input signature registers being constructed based on an n-bit hybrid ring generator.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
9.
REGION-BASED FILTERING OF PARASITIC NETWORKS FOR CIRCUIT TEST SIMULATIONS
Systems and methods are presented for region-specific filtering of parasitic networks for circuit test simulations. A method may include performing a circuit test through a parasitic network extracted for a circuit design, including by defining a region of the circuit design based on test locations specified for the circuit test and performing a tile filtering to remove any tiles for the specific nets that do not intersect with the region. Performing the circuit test may also include, for remaining tiles after the tile filtering, performing a resistor-filtering to remove any parasitic resistors in the remaining tiles that do not intersect with the region, obtaining a filtered parasitic network by performing a network-filtering on the parasitic network to remove network portions that do correspond to remaining parasitic resistors in the remaining tiles after the resistor-filtering, and performing a simulation for the circuit test through the filtered parasitic network.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 115/12 - Cartes de circuits imprimés [PCB] ou modules multi-puces [MCM]
10.
FAULT PARTITION NODE SYSTEMS FOR CIRCUIT DESIGN, TEST AND DIAGNOSIS
Fault Partition Node Systems for Circuit Design, Test and Diagnosis Techniques for generating a fault partition node system (also referred to as asymmetric partition tree (APT)) for a circuit design (330). The fault partition node system comprise equivalent fault group information extracted from a huge amount of fault simulation data for the circuit design. The related equivalent fault group information allows the fault partition node system to shrink or expand under certain conditions. Based on the fault partition node system, diagnosis coverage values can be predicted for various constraints, which can be employed to make circuit designs diagnosis friendly (350). The fault partition node system can also comprise diagnose-care bit information. Dictionary-like diagnosis can be performed more efficiently using the fault partition node system (360).
A scan chain comprises two neighboring scan cells (K + 1) and K and a controllable inverting device inserted between a serial output of the scan cell (K + 1) and a serial input of the scan cell K. The selection of the scan cell K for the insertion of the controllable inverting device (diagnosis point insertion) is determined based on a diagnosis coverage analysis process. The scan cell K is configured to operate in one of a plurality of test-related modes based on a regular scan enable signal and a diagnosis mode signal. The plurality of test-related modes comprises a diagnosis capture mode in which the scan cell K is configured to capture the inverted version of a bit received at the data input of the controllable inverting device. The diagnosis mode signal may be provided by a storage device.
A fault partition node system is created for a circuit design based on fault simulation for each of a plurality of test patterns. Based on the fault partition node system, a diagnosis coverage contribution value for each of the plurality of test patterns is determined. Test patterns in the plurality of test patterns are then reordered based on the diagnosis coverage contribution value. The above operations of creating, determining, and reordering can be repeated. The fault partition node system can also be used for selective chain diagnosis for performance improvement.
Various aspects of the present disclosed technology relate to techniques for test pattern generation for diagnosis. A fault partition node system or a failing bit node system is created for a circuit design based on fault simulation for each of a plurality of test patterns. Based on the fault partition node system or the failing bit node system, a plurality of faults are updated by removing, from the plurality of faults, faults of which each becomes a fault in an equivalent fault group alone. One or more test patterns are then generated targeting some of equivalent faults in the updated plurality of faults to increase diagnosis coverage. The fault partition node system or the failing bit node system is expanded based on fault simulation for each of the one or more test patterns. The above operations of updating, generating, and expanding are repeated.
Systems and methods are provided for propagation determinations of unknown values in logic simulations of digital circuit designs. A method may include accessing (402) a digital circuit design (210) and parsing (404) the digital circuit design (210) to detect state elements. The method may also include performing (406) a logic simulation on the digital circuit design (210) that includes tracking propagation of x-values in the digital circuit, wherein the x-values represent an unknown value for an output of a digital circuit design element. During the logic simulation, method steps can include tracking (408) the state elements of the digital circuit design (210) to determine when any output of the state elements is the x-value during the logic simulation and triggering (410) an x-propagation response when an x-propagation criterion is satisfied based on detected x-value outputs for the state elements of the digital circuit design (210).
Techniques for generating a failing bit node system for a circuit design (330). The failing bit node system comprise equivalent fault group information extracted from a huge amount of fault simulation data for the circuit design. The related equivalent fault group information allows the failing bit node system to shrink or expand under certain conditions. Based on the failing bit node system, diagnosis coverage values are be predicted for various constraints, which can be employed to make circuit designs diagnosis friendly (350). The failing bit node system can be converted into a fault partition node system. Dictionary-like diagnosis are performed based on the failing bit node system (360).
Systems and methods are presented in support of cross-mask error enhancement factor (MEEF)-based optical proximity correction (OPC) for curvilinear masks. In some examples, a method may include the steps of accessing a curvilinear mask and a cross- MEEF matrix for the curvilinear mask. The curvilinear mask may be represented through a set of vertices and the cross-MEEF matrix may specify edge placement error (EPE) changes to the set of vertices of the curvilinear mask when a given vertex of the set of vertices of the curvilinear mask is moved by a distance unit. The method may also include a step of performing an OPC operation using the cross-MEEF matrix.
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p. ex. correction par deuxième itération d'un motif de masque pour l'imagerie
G03F 1/78 - Création des motifs d'un masque par imagerie par un faisceau de particules chargées [CPB charged particle beam], p. ex. création des motifs d'un masque par un faisceau d'électrons
G03F 1/86 - Inspection au moyen d'un faisceau de particules chargées [CPB charged particle beam]
G06F 17/18 - Opérations mathématiques complexes pour l'évaluation de données statistiques
17.
CREATING A LAYOUT OF A PRINTED CIRCUIT BOARD (PCB) INCLUDING ELECTRICAL COMPONENTS USING A MODEL FOR ASSIGNING THE ELECTRICAL COMPONENTS ONTO POSITIONS OF A PCB ARRAY
The invention relates to a method for creating a layout of a PCB including a plurality of electrically connected, electrical components. To facilitate creating the PCB layout, the method includes: providing an array of a board canvas of the PCB; providing a list of components and electrical connections of the components; providing feature information of the respective component and of the respective connection; providing a model incorporating the array, the list, and the feature information, where the model describes a sequence of consecutive actions of assigning one of the components of the list onto a respective position of the array; determining a respective probability distribution for assigning one of the components onto a respective position of the array using the model; composing the layout of the components on the array using the respective assigning action with the highest respective probability in the respective probability distribution; and outputting the composed layout.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
A, preferably computer-implemented, method comprising the step of determining one or more latent defects in an integrated circuit based on a stress target, the integrated circuit comprising at least one instance of a library cell, preferably from a plurality of library cells, wherein the library cell comprises or is associated with the stress target, wherein the stress target of the library cell is indicative of one or more stress states of at least one transistor of the library cell.
The present invention discloses a method and a system for an automatic classification of the solder printer tooling in the preparation of a printed circuit board, the method comprising: - providing the printed circuit board and placing a stencil layer on the printed circuit board thereby covering the printed circuit board with a stencil layer; said stencil layer comprising a variety of openings that fit to positions of the printed circuit board where a solder past pad has to be deposited; - bringing the solder past onto the stencil layer and wiping the squeegee over the stencil layer wherein the squeegee is used to bring the solder past into the openings of the stencil layer by exposing a predetermined pressure to the solder past and the stencil layer in a direction substantially perpendicular to the plane of the printed circuit board; - positioning in alignment with the squeegee an array of distance sensors in proximity to the squeegee and measuring the distance between the distance sensors and the stencil layer while wiping with the squeegee over the stencil layer; and - evaluating the measured distances with respect to a predetermined threshold for the distance between the stencil layer and the distance sensors.
H05K 3/12 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché utilisant la technique de l'impression pour appliquer le matériau conducteur
A method for computer-based simulating a system (SYS) by co-simulation of subunits (SSY) of the system (SYS) includes (a) generating dedicated models (MDL) for the simulation of the subunits (SSY) using at least partially different simulation tools (SMT). The method also includes (b) exchanging simulation data (SMD) between the dedicated models (MDL) according to a communication format standard (FMI) during co-simulation in the form of a standard simulation communication (SSC). At least one dedicated model (MDL) is a foreign model (FMD), so it was generated using a non-preparing tool (NPT), which is a simulation tool (SMT) that does not prepare models for communication according to the communication format standard (FMI). The method also includes (c) representing the foreign model (FMD) using a substitution module (SBM) in the simulation data (SMD) exchange, (d) providing an interface service (IFS) to the non-preparing tool (NPT), which converts the standard simulation communication (SSC) into communication according to the non-preparing tool's (NPT) application programming interface (1), and vice versa, and (e) operating the foreign model (FMD) in an environment of the non-preparing tool (NPT) according to the converted communication input (CVC) received from the interface service (IFS) and (f) the foreign model (FMD) sending simulation data (SMD) via the conversion of the interface service (IFS) and via the substitution module into (FMU) the standard simulation communication (SSC).
G05B 17/02 - Systèmes impliquant l'usage de modèles ou de simulateurs desdits systèmes électriques
G05B 19/418 - Commande totale d'usine, c.-à-d. commande centralisée de plusieurs machines, p. ex. commande numérique directe ou distribuée [DNC], systèmes d'ateliers flexibles [FMS], systèmes de fabrication intégrés [IMS], productique [CIM]
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06G 7/66 - Calculateurs analogiques pour des procédés, des systèmes ou des dispositifs spécifiques, p. ex. simulateurs de systèmes de commande
21.
GENERATING AN AUTOMATIC BLEND BETWEEN TWO COMPONENTS IN A COMPUTER MODEL
A computer-implemented method for generating a computer model representation of an object includes obtaining a density grid representation of at least part of the object, generating a computer model representation based on the density grid, and determining a portion of the computer model representation. The computer-implemented method also includes interpolating values in the density grid, determining a portion of the interpolation of the density grid corresponding to the portion of the computer model representation, and modifying the computer model representation based on the portion of the interpolation of the density grid
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06T 17/20 - Description filaire, p. ex. polygonalisation ou tessellation
G06F 111/06 - Optimisation multi-objectif, p. ex. optimisation de Pareto utilisant le recuit simulé, les algorithmes de colonies de fourmis ou les algorithmes génétiques
G06F 119/18 - Analyse de fabricabilité ou optimisation de fabricabilité
22.
LIGHTWEIGHT STREAM CIPHER FOR HARDWARE ROOT OF TRUST
A circuit comprises a first device comprising a nonlinear feedback shift register, a second device comprising a nonlinear feedback shift register, a third device comprising a ring generator, selection-combination devices, and an encryption device. Each of the selection-combination devices is configured to output one of bits of a keystream which is derived from a combination of first one or more bits and second one or more bits. The first one or more bits are generated based on a first group of bits outputted from the first device and a third group of bits outputted from the third device. The second one or more bits are generated based on a second group of bits outputted from the second device and a fourth group of bits outputted from the third device. The encryption device is configured to combine bits for encryption with bits of the keystream to generate encrypted bits.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
H04L 9/12 - Dispositifs de chiffrement d'émission et de réception synchronisés ou initialisés d'une manière particulière
23.
METHOD AND SYSTEM FOR MODELLING AND MANUFACTURING COMPOSITE PARTS
A method for modelling a composite part is provided. The method includes accessing a model in a modelling system where the model includes a representation of a selected layer forming the composite part and the selected layer includes one or more plies of composite fabric material. The method includes simulating a manufacturing process for the selected layer based on the model. The method also includes, for each ply in the selected layer, evaluating simulation data from simulating the manufacturing process to quantitatively determine a deviation of the ply in the manufactured selected layer from the model, identifying a set of regions of the ply in the model, based on the deviation, and automatically modifying the model based on the identified set of regions, before manufacturing the composite part.
A computer-implemented method in a computer aided design (CAD) system is provided. The method includes accessing a first facetted model representing a shape element, connecting instances of the facetted model to obtain a second facetted model, applying a nonlinear transformation to the second facetted model to obtain a third facetted model, and determining a distortion of a pair of facets between the second facetted model and the third facetted model. A topology of the third facetted model is modified based on the distortion
A method for generating a mesh for a blended rod and ball lattice is provided. The method includes obtaining, from a first lattice, a second lattice by offsetting the first lattice by a predetermined distance. The method includes marking portions of rods in the second lattice with a first identifier or a second identifier based on intersections with other lattice topologies, marking balls in the second lattice with the first identifier or the second identifier or leaving the balls unmarked, and identifying regions of the first lattice corresponding to marked regions of the second lattice. The method includes applying a blend to the first lattice to obtain a third lattice and incarnating the third lattice as a mesh. Different mesh incarnation methods are applied in the marked regions, based on whether the regions are marked with the first identifier or the second identifier.
A method for modifying a model of a shape element in a computer-aided design (CAD) system. The method comprises accessing the model in the CAD system and generating an arrangement comprising a plurality of instances of the model. A set of modifications to the model are identified to enable the plurality of instances to connect seamlessly. The modifications are implemented on the model to obtain a modified model which can be used to form a patterned CAD object.
RR as a plurality of polylines based on a pre-determined threshold. The method includes generating a set of line segments, each line segment in the set of line segments extending radially from a surface of an unblended rod and ball lattice and terminating on a bounding sphere that contains the identified constraint curves. The method includes intersecting each line segment in the set of line segments with the blended lattice surface to obtain a set of points lying on the blended lattice surface and triangulating the set of points to obtain a mesh representation of a region of the hub.
A system and method for managing real-time multi-user collaboration in a file based CAX application is disclosed herein. The method comprises receiving, by a processing unit, a plurality of inputs indicative of a plurality of operations to be performed on one or more objects in a CAX file. Each of the inputs is received from one of a plurality of user sessions as-sociated with the file based CAX application, in real time. Further, a chronological sequence of execution of each of the operations is determined, based on an order of receipt of each of the inputs. based on the chronological sequence of execution determined, each of the operations is executed on the CAX file. Furthermore, an output is generated on each of the user sessions, based on execution of each of the operations on the CAX file in the chronological sequence.
A computer-implemented method for generating a finite element mesh of a component for the numerical solution of partial differential equations for the description of technical-physical circumstances to which the component is subjected in its intended operation. The invention further relates to a method for improving the components design and generating the component. Furthermore, the invention relates to a system for performing such method. Furthermore, the invention relates to a computer-readable medium encoded with executable instructions, that when executed, cause the computer system to carry out a method according to the invention.
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06F 17/13 - Opérations mathématiques complexes pour la résolution d'équations d'équations différentielles
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06T 19/00 - Transformation de modèles ou d'images tridimensionnels [3D] pour infographie
G06F 30/00 - Conception assistée par ordinateur [CAO]
A method and system for configuring a product is disclosed. The method comprises obtaining, by a processor (102) of the PDM system (100), a plurality of options and one or more constraints defined for the product from a product database (116), wherein each of the options has one or more variants. Further, ordered logical groups are generated from the plurality of options obtained, based on a weight associated with each of the options. Furthermore, a branch and bound algorithm is used to determine one or more buildable product configurations based on the ordered logical groups and one or more of the constraints applicable to the options, wherein applicability of the one or more constraints is determined using a Satisfiability Modulo Theory-based solver. The one or more buildable product configurations are further outputted on an output device (110).
Method of machining a workpiece (WPC) by means of a B-axis lathe machine (MCH), where the method, involves the continuous change of the angular position (AGP) of a turning tool (TTL), the method comprising the following steps: (a) Providing a workpiece (WPC) raw contour geometry (RCG), (b) Providing a. workpiece (WPC) target contour geometry (TCG), (c) Providing a predetermined chip thickness (CPT) as target chip thickness (CPT) during machining, (d) Providing a tool path (TPT) of the turning tool (TTL), (e) Providing preset angular positions (PAP) of the turning tool (TTL), characterized, by the method including the additional steps: (f) Providing a. feed, map (FMP) that provides a. feed. rate (FDR), (g) Splitting the tool path (TPT) segments (SGT) into tool path (TPT) subsegments (SSG) with a predefined, segment length (SGL), (n) Determining angular positions (AGP) at the segment (SGT) end positions (EPT) by interpolating (ITP) between the positions of specified tool angle (TAP), Determination of the feed rate (FDR) at the segment end. positions (SGT) by specifying the respective preset local angular positions (PAP) to the feed map (FMP), (j) Determining of a dynamic feed rate (DFR) and a. dynamic angular position change (DAP) from an interpolation (TTP) along the segment (SGT) tool path (TPT) between the respective segment (SGT) end position (EPT) parameters, and machining the workpiece (WPC) in such a way that the tool position is continuously changed between the preset angle positions, while the tool is moved along a tool path (TPT) according to a feed calculation based, on. the specified chip thickness (CPT).
G05B 19/416 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par la commande de vitesse, d'accélération ou de décélération
G05B 19/41 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par l'interpolation, p. ex. par le calcul de points intermédiaires entre les points extrêmes programmés pour définir le parcours à suivre et la vitesse du déplacement le long de ce parcours
32.
DETERMINING A SURFACE OF AN OBJECT IN A COMPUTER MODEL
A computer-implemented method for determining a surface of an object in a computer model of the object is disclosed. The method comprises: determining a position on a surface of the computer model of the object; determining a reference point that is intersected by an axis projecting from the surface near to the position on the surface; determining one or more portions of the surface near to the position on the surface or near to another of the one or more portions of the surface; determining whether an uninterrupted line-of-sight exists between the one or more portions and the reference point; and determining that the one or more portions constitute the surface in response to determining that the uninterrupted line-of-sight exists between the one or more portions and the reference point.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
A computer-implemented method for evaluating power dissipation of an electronic circuit design including at least one logic gate is disclosed. The method includes receiving one or more data files descriptive of the electronic circuit design, descriptive of waveform data descriptive of signal activity for logic gates used in the electronic circuit design, and descriptive of power dissipation values for internal cells of the logic gates of the electronic circuit design (701). Waveform data is extracted from the one or more data files descriptive of signal activity at primary inputs of the electronic circuit design and descriptive of outputs of registers and memories of the electronic circuit design (702). Simulation of the logic gates is performed using the extracted waveform data to generate simulated waveform data descriptive of simulated logic transitions for the internal cells of the logic gates (703), and event-based evaluation of the power dissipation of the electronic circuit design is performed based on the extracted waveform data, the simulated waveform data, and the power dissipation values (704).
A monitor device for monitoring a propagation delay of a signal along a path through an integrated circuit is disclosed. The monitor device comprises a delay device configured to receive the signal and generate a delayed signal being a version of the received signal that is time-delayed relative to the received signal, a detection window device configured to generate a detection window signal based on a clock signal of the integrated circuit, and a determination device configured to determine whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal, and to generate a determination signal based on the determination.
Systems and methods are presented for determination of layout-based systematic defect candidates based on design uniqueness and repeater overlap. A method may include accessing diagnosis reports (220) generated for physical circuits and identifying multiple repeater sets (230) from the diagnosis reports (220). The method may also include extracting layout patterns (250) from the diagnosis reports (220) and determining (608) a layout-based systematic defect candidate (510) from among the layout patterns (250) based on a design uniqueness factor and a repeater overlap factor. The design uniqueness factor may be based on a degree to which other layout patterns similar to a given layout pattern do not otherwise occur among layout patterns (320) for the circuit design (310). The repeater overlap factor may be based on a degree to which other layout patterns similar to the given layout pattern occur among layout patterns for other repeater sets of the multiple repeater sets (230).
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 119/02 - Analyse de fiabilité ou optimisation de fiabilitéAnalyse de défaillance, p. ex. performance dans le pire scénario, analyse du mode de défaillance et de ses effets [FMEA]
A computer-implemented method for determining placement of monitors for monitoring propagation delays in paths through an integrated circuit is disclosed. The method comprises: determining one or more paths through an integrated circuit which terminate at a same flip flop of the integrated circuit (706 a ii); determining logical cells in the one or more paths terminating at that flip flop (706 a ii); determining a measure of the number of those logical cells that are also in one or more alternative paths terminating at one or more alternative flip flops monitored by one or more monitors (706 a iii); determining whether the measure of the number of those logical cells that are also in the alternative paths satisfies a threshold condition (706 a iii); and determining, based on a determination that the number of logical cells that are also in the alternative paths does satisfy the threshold condition, placement of a monitor to monitor the flip flop.
A monitor device for monitoring a propagation delay of a signal along a path through an integrated circuit is disclosed. The monitor device comprises a delay device configured to receive the signal and generate a delayed signal being a version of the received signal that is time-delayed relative to the received signal, a detection window device configured to generate a detection window signal based on a clock signal of the integrated circuit, and a determination device configured to determine whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal, and to generate a determination signal based on the determination.
A system and method for managing replacement of parts in a computer-aided design (CAD) environment is disclosed. The method includes identifying, by a processing unit, a user intent for replacing a first part with a second part in the CAD environment. A plurality of face pairs for the second part and the base part is determined. A face pair vector corresponding to each face pair of the plurality of face pairs is computed. A machine learning model is further used to compute a constraint creation probability for each face pair of the plurality of face pairs based on the corresponding face pair vector. A plurality of placement solutions is generated based on the plurality of face pairs, and one or more relationships that existed between the first part and the base part. The computed constraint creation probabilities for the face pairs in the placement solutions are further used for providing one or more recommendations on a display device.
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 111/20 - CAO de configuration, p. ex. conception par assemblage ou positionnement de modules sélectionnés à partir de bibliothèques de modules préconçus
A, preferably computer-implemented, method of test case prioritization, the method comprising: obtaining a test case coverage for each one of a plurality of the test cases, wherein the test cases serve for testing an integrated circuit, e.g., in a hardware description language, preferably on the register transfer level, determining a priority of each test case based on the respective test case coverage, wherein the priority indicates an execution sequence of the test cases.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06N 3/00 - Agencements informatiques fondés sur des modèles biologiques
Systems and methods are presented for stepover-based generation toolpaths for additive manufacturing processes. A method may include automatically generating a toolpath (130) for a slice region (120) based on an allowable stepover range specified for an additive manufacturing process, including by determining a medial axis (210) of the slice region (120), partitioning the slice region (120) into multiple subsections (231, 232, 233, 234) based on the medial axis (210), modifying a given subsection responsive to a determination that a sub-toolpath for the given subsection would violate the allowable stepover rang, generating sub-toolpaths for each of the multiple subsections of the partitioned slice region, including any modified subsections, and generating the toolpath (130) for the slice region (120) as a combination of the sub-toolpaths generated for each of the multiple subsections of the partitioned slice region.
A computer-implemented method and system extract surface feature information from point cloud data. A 3D topology reconstruction engine receives point cloud data comprising one or more point cloud representations of an object and generates a curvature-based segmentation and region growing segmentation of the point cloud data. A feature removal module identifies and removes isolated clusters to correct over- segmentation.
G06T 7/187 - DécoupageDétection de bords impliquant des croissances de zonesDécoupageDétection de bords impliquant des fusions de zonesDécoupageDétection de bords impliquant un étiquetage de composantes connexes
42.
SELECTIVE REUSE IN ANALOG SIMULATION OF AN INTEGRATED CIRCUIT
A computing system can identify result data corresponding to a simulation of a first circuit design (301) utilizing a set of samples from a distribution describing manufacturing variation for integrated circuitry (302), determine a second circuit design describing an integrated circuit is compatible with the first circuit design based on a comparison of variables for manufacturing variation in the first circuit design to variables for manufacturing variation in the second circuit design (342), and reuse at least a portion of the result data when simulating the second circuit design utilizing values from the distribution describing the manufacturing variation identified based, at least in part, the result data corresponding to the simulation of the first circuit design. The computing system can estimate a yield for an output of the integrated circuit described by the second circuit design based on a response of the second circuit design to the simulation (306).
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
11,...,BM}, wherein the module A (110) is configured for operating in synchronicity with a clock signal CK_A (210) of period T and the module Bj (120) is configured for operating in synchronicity with a clock signal CK Bj of said period T, the method comprising: - adjusting or controlling, by a phase adjustment circuit, for each couple of modules formed by the module A (110) and one of said modules Bj (120) and in function of a total adjustment time TT_ Dj calculated for each couple, a relative time between an arrival time of signal S_Aj data at the sampling location of the sampling component of the module Bj (120) and a sampling time of said data by the sampling component of module Bj, wherein said sampling time is temporally directly adjacent to the arrival time; wherein said total adjustment time TT_Dj is configured for increasing, for both a sampling by a sampling component of module A (110) of data values of a signal S_Bj sent by the module Bj (120) to the module A and the sampling by the sampling component of module Bj (120) of data values of the signal S_Aj, a time separation between data arrival at a sampling location of the concerned sampling component and data sampling by said concerned sampling component, wherein the time at which said data sampling takes place is temporally directly adjacent to the time at which the data arrive at said sampling location of the concerned sampling component.
A method and system for predicting overheating in layers of build material in an additive manufacturing system are provided. The method comprises accessing a representation of a three-dimensional object as a plurality of cross-sectional layers for printing in an additive manufacturing system, accessing scan path data for a region of a selected one of the plurality of cross-sectional layers, sub-dividing the region into a plurality of cells and for each cell, generating a vector of features based on the representation of the object and scan path data and evaluating a trained predictive model based the vector of features, to obtain an output comprising a predicted melting time for the cell.
A method and a system for managing gate level simulation of an electronic circuit are provided. The method includes identifying at least one circuit topology from a plurality of circuit topologies in an electronic circuit design, based on a netlist and a timing data file. Further, one or more non-critical pins are determined from the identified circuit topology, based on delay corresponding to each of the pins in the identified circuit topology. Based on determination of the one or more non-critical pins, a modified timing data file is generated. The delay associated with each of the non-critical pins is set to zero in the modified timing data file. The method may further include performing a gate-level simulation based on the modified timing data file
A, preferably computer-implemented, method of processing in- phase and quadrature data, IQ data, the method comprising the steps of : determining a plurality of IQ samples from the IQ data, determining a constellation error of each one of the plurality of IQ samples, and identifying a (de-)compression method and/or IQ bit width of the IQ data based on the constellation error.
H03M 7/30 - CompressionExpansionÉlimination de données inutiles, p. ex. réduction de redondance
H04L 1/24 - Tests pour s'assurer du fonctionnement correct
H04L 27/22 - Circuits de démodulationCircuits récepteurs
H04L 27/38 - Circuits de démodulationCircuits récepteurs
H04W 24/00 - Dispositions de supervision, de contrôle ou de test
H04B 10/07 - Dispositions pour la surveillance ou le test de systèmes de transmissionDispositions pour la mesure des défauts de systèmes de transmission
H04L 27/20 - Circuits de modulationCircuits émetteurs
H04L 27/34 - Systèmes à courant porteur à modulation de phase et d'amplitude, p. ex. en quadrature d'amplitude
47.
STATISTICAL CHANNEL ANALYSIS WITH FEEDBACK BURST ERROR
This application discloses a computing system configured to measure a step response of a channel in an electronic device, determine a feedback voltage that a decision feedback equalizer adds to the channel in response to detecting inter-symbol interference in received symbols, and predict a signal integrity of the channel based, at least in part, on the step response of the channel and the feedback voltage. The computing system can utilize the predicted signal integrity to determine a probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous, and determine the signal integrity of the channel based, at least in part, on the step response of the channel, the feedback voltage, and the probability that the feedback voltage added by the decision feedback equalizer to the channel was erroneous.
The present invention discloses a method and a system for an automatic layer classification in the preparation of PCB design Gerber data that is intended to support the design process for a printed circuit board, the method and the system comprising: - providing a list of the Gerber data for a process preparation layer stackup tool, said Gerber data comprising at least a number of electronic layer designs and related information to the manifestation of the electronic layer designs in the printed circuit board; - importing the list of Gerber data into the process preparation layer stackup tool and converting the list of Gerber data by the process preparation layer stackup tool into fabrication data thus enabling the production of the printed circuit board; wherein: - the conversion being supported by a machine learning process that has been executed for training a conversion algorithm; said machine learning process comprising a number of training steps wherein as a result of the training steps a predetermined set of the Gerber data is automatically recognized and converted into the respective fabrication data; and - preparing the execution of the production of the printed circuit board according to the so-yielded production data.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 115/12 - Cartes de circuits imprimés [PCB] ou modules multi-puces [MCM]
49.
A METHOD FOR THE GENERATION OF A META-MODEL DRIVEN DYNAMIC USER INTERFACE
It is the objective of the present invention to define a method that provides a simple and effective way to create and/or customize a user interface at client side, particularly enabling the option of doing this on the fly while the production is running would be highly desirable. This objective is achieved according to the present invention by a method for generating a user interface (MMOM UI) in at least one MOM system, said at least one MOM system controlling a manufacturing environment of a variety of manufacturing resources present in a number of business domains, comprising the steps of: a) providing for each business domain a business domain model, said business domain model comprising beside other information all relevant information to the resources and objects in the specific business domain and their attributes that are potentially a subject for a UI tag (UI Tags); b) generating from all business domain models a set of metadata (MOM Metadata); said set of metadata comprising the relevant information to the resources and objects and their related attributes; c) enhancing the set of metadata to comprise additional UI-related information on how these business domain models shall be presented; d) utilizing this set of metadata about the business domain models including the enrichment with the UI related information by a dynamic rendering engine which is executed in the manufacturing environment on the client side; e) selecting according to the available set of metadata the information that shall be displayed in the user interface (MMOM UI) via an interface provided by a web framework (SWF); said web framework (SWF) offering the set of metadata in a selectable way to a user; and f) using the selected information by the dynamic rendering engine to generate the user interface (MOM UI) showing the selected information 2023P06594WO according to the rendering data in the set of metadata and the enhanced UI related information. Thus, the present method eliminates the need for an intermediate design phase which requires a running application to design or develop the UI pages. With the present invention the client user can design and configure the UI along with the rest of the business domain models in one phase without having a running software development system. Both the business domain models and the corresponding UIs are developed/deployed/published together in one go.
Systems and methods are presented for criticality determinations for elementary subparts of a circuit design. Determination of criticality values (220) for elementary subparts (e.g., registers) in a logic-level circuit design (210) may be based on an input flop factor, an input combinational logic factor, and an output flop factor. The input flop factor may be based on a number of other registers in the logic-level circuit design (210) that affect to an input signal to a given register, the input combinational logic factor may be based on a number of logic gates that affect the input signal, and the output flop factor may be based on a number of other registers in the logic-level circuit design (210) with input signals that are affected by an output signal of the given register. Determined criticality values (220) may be used to set physical designs of corresponding elementary subparts.
G06F 119/02 - Analyse de fiabilité ou optimisation de fiabilitéAnalyse de défaillance, p. ex. performance dans le pire scénario, analyse du mode de défaillance et de ses effets [FMEA]
51.
AUTOMATIC CELL AND MACRO PLACEMENT IN VLSI LAYOUT DESIGN
Systems (101) and methods (300) for generation of a very-large-scale-integration floorplan (400). A method includes receiving (302) inputs (322, 324, 326) for automatic placements of macros in a floorplan (400). The method includes performing (304) an automatic macro placement process based on the received inputs (322, 324, 326). The method includes generating (308) the floorplan (400) according to the automatic macro placement process. The floorplan (400) can thereafter be used to generate a physical layout and a physical chip can thereafter be manufactured according to the generated physical layout.
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 111/06 - Optimisation multi-objectif, p. ex. optimisation de Pareto utilisant le recuit simulé, les algorithmes de colonies de fourmis ou les algorithmes génétiques
G06F 115/08 - Blocs propriété intellectuelle [PI] ou cœur PI
52.
THREE-DIMENSIONAL PHOTOMASK TRANSMISSION WITH KERNEL-BASED MODELING
This application discloses a computing system to simulate three-dimensional light transmission in a near-field of a lithographic mask using a thin mask approximation of the lithographic mask rasterized from a mask layout design describing the lithographic mask and using a compact mask model including a plurality of directional kernels representing light diffraction in the near-field of the lithographic mask. The computing system can generate a wafer image or resist contours based on the simulated three-dimensional light transmission in the near-field of the lithographic mask, and utilize an optical proximity correction (OPC) process to modify the mask layout design based on the wafer image or the resist contours. The lithographic mask corresponding to the mask layout design is configured for use in the manufacturing of an integrated circuit.
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
A method and data processing system for extracting a path with a longest delay time through an integrated circuit is provided. The method comprises obtaining a dataset for the integrated circuit comprising a maximum arrival time and maximum propagation delay, selecting a logical cell in the integrated circuit, identifying a longest arrival path from a start point in the integrated circuit to an output pin, O, of the selected logical cell based on the dataset, identifying a longest propagation path from an input pin, I, of the selected logical cell to an end point in the integrated circuit and extracting a longest path through the selected logical cell based on the identified longest arrival path and longest propagation path.
G01R 31/3183 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test
G01R 31/3193 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
A method and data processing system for characterizing a logical cell in an integrated circuit are provided. The method comprises identifying an input pin and output pin of the cell as a selected input pin and output pin, evaluating a model of the logical cell for each pair of input signals from a set comprising pairs of input signals, identifying a subset of the set based on the evaluation, and determining a propagation delay for each pair in the subset.
A method, system, device, and medium for generating 3D model of industrial scene are disclosed. The method comprises: acquiring point cloud data for an industrial scene; determining a domain of the industrial scene; acquiring a trained semantic segmentation model associated with the domain from a model library, wherein the model library comprises multiple trained semantic segmentation models associated with respective domains; performing semantic segmentation on the point cloud data to obtain multiple segmented objects, based on the trained semantic segmentation model associated with the domain; meshing the multiple segmented objects; and generating a 3D model of the industrial scene based on the meshed multiple segmented objects. A flexible domain-specific model library is provided to meet the needs from different industrial scenes, thus improving modeling efficiency.
A hashing circuit comprises: an n-bit hybrid ring generator configured to implement a primitive polynomial of degree n, a phase shifter coupled to outputs of the n-bit hybrid ring generator, and an m-bit nonlinear sequential device coupled to outputs of the phase shifter. The n-bit hybrid ring generator comprises n state elements coupled to each other to form an n-bit ringlike structure, k feedback-enable devices, and injection devices configured to inject bits of the binary value into the n-bit ringlike structure. The n-bit ringlike structure has a top row and a bottom row, of which each has at least one of the n state elements and at least one of the k feedback- enable devices. The m-bit nonlinear sequential device comprises m state elements coupled to each other to form an m-bit ringlike structure and one or more feedback paths comprising nonlinear devices implementing nonlinear functions.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
57.
PINN-BASED SURROGATE MODELING USING LOCAL TURBULENCE ESTIMATES
System and method optimize fluid dynamics modeling using a physics informed neural network (FINN) and a deep neural network (DNN). The DNN is trained to create a data driven mapping for invariants and Reynolds stress tensors associated with the fluid field based on simulation data. The FINN is trained using Navier Stokes and continuity equation based losses, using Reynolds stress tensor correction terms derived from the mapping and from invariants and tensors derived from estimated flow field variables. The FINN inputs include boundary conditions, and time-space coordinates for sampling points in the fluid flow field which describe time evolution of the turbulence problem depending on geometric bounds for the flow field.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/28 - Optimisation, vérification ou simulation de l’objet conçu utilisant la dynamique des fluides, p. ex. les équations de Navier-Stokes ou la dynamique des fluides numérique [DFN]
A computer-implemented method for offsetting a mesh in a three-dimensional model is provided. A first mesh offsetting method is applied to a mesh to obtain a first offset mesh. A self-intersecting portion of the first offset mesh, where either a topological or geometric condition is met, is identified. Facets of the mesh that map to facets of the first offset mesh containing the self-intersecting portion are identified. A region of the mesh where facets at the boundary of the region satisfy a predefined set of boundary conditions is generated. A second mesh offsetting method is applied to the region of the mesh to obtain a second offset mesh. Facets of the first offset mesh corresponding to the facets of the region are removed from the first offset mesh and the first offset mesh and the second offset mesh are combined to obtain a third offset mesh.
A method for identifying message end points in real-time in a data transmission of contiguous multibyte messages in an integrated circuit is provided. The method includes receiving a data transmission of bytes over one or more clock cycles. The data transmission includes a plurality of contiguous multibyte messages. The method also includes generating an array of data values for each of the one or more clock cycles, storing the arrays, and identifying end points of one or more messages of the plurality of contiguous multibyte messages based on the stored arrays.
A method and apparatus for decoding trace data output by monitoring circuitry configured to monitor execution of a program on a computing system are provided. The method includes receiving trace data including a sequence of packets from the computing system, identifying a first synchronization packet in a first predefined format, and identifying one or more further synchronization packets. The method also includes partitioning the sequence of packets into subsequences based on the identified synchronization packets, and decoding the plurality of subsequences.
A computer-implemented method for identifying topological structures in a three-dimensional model is described. A signature including characteristics of a first set of topological structures of the three-dimensional model is obtained. A selection of a second topological structure by a user is received via a user input device. The signature is modified based on the selection to include characteristics common to the first set of topological structures, the second topological structure, and a topological neighborhood of the second topological structure. Further topological structures are identified based on the modified signature.
G06F 3/048 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI]
G06F 3/04815 - Interaction s’effectuant dans un environnement basé sur des métaphores ou des objets avec un affichage tridimensionnel, p. ex. modification du point de vue de l’utilisateur par rapport à l’environnement ou l’objet
A computer implemented method for generating a vector representation of shape characteristics of a component that forms part of a computer-aided design (CAD) model is provided. The method includes generating a mesh representation comprising a plurality of triangular facets; determining a set of points that are quasi-randomly distributed on the mesh; portioning a domain containing the component into a plurality of concentric spheres; identifying a subset of points in each sphere; and determining a vector representation of shape characteristics of the component based on the variance of points along principal axes in each sphere.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
G06F 18/2411 - Techniques de classification relatives au modèle de classification, p. ex. approches paramétriques ou non paramétriques basées sur la proximité d’une surface de décision, p. ex. machines à vecteurs de support
Computer-implemented method and system enable rendering scalable vector icons used in a computer application. An icon engine retrieves a single icon file from a library, the icon file having graphic information for a plurality of defined icon sizes and color themes defined using vectors for each of a plurality of icon sizes with unique elements assigned to a respective size layer. Icon modes of an active computer application are identified, such as size mode and color theme mode. Layer activation for features assigned to a size mode for the icon is based on the identified icon mode. Color theme for the icon is based on the identified color theme mode. The icon data file is configured according to the selected layer activation and color theme and rendered on a computer display.
It is the objective of the present invention to define a method that uses semantic technology to manage a single abstract level data model of different applications and automatize the process of producing the interoperability rules when necessary. Further, it would be desirable when an intuitive user interface could be provided that opens a natural and intuitive way of exploring the ontology for the user while shielding the user at the same time from the technical aspects such as executing SPARQL queries, etc. This objective is achieved according to the present invention by a method for providing an intuitive user interface in at least one MOM system, said at least one MOM system controlling a manufacturing environment of autonomous factories, said method comprising the steps of: a) encoding manufacturing domain knowledge for the autonomous factories in a democratic network of extensible and configurable ontologies, b) defining the ontology of a MOM domain through a semantic conceptualization of the manufacturing domain knowledge; c) providing a web-based framework to create an intuitive user interface for navigating the ontologies and for associating concepts comprised in the ontologies to logical data structures coming from existing applications that are comprised in the MOM system, wherein: c1) the user interface being enabled to allow a user to select an ontology and to use common terms for searching for a concept associated with said ontology the user is interested in; c2) the user interface being further enabled to provide a list of concepts that match the respective search; c3) the user interface being further enabled to allow a user to select at least one concept out of the list of concepts and to provide a list of entities related to the selected concept; c4) the user interface being further enabled to allow a user to select at least one entity out of the list of entities and to provide a visualization of the selected entity; and c5) the user interface being further enabled to allow a user to select a number of entities referring to the same concept over manufacturing domains thereby generating transformation rules to handle the logical data structure across said factories and/or domains with respect to the selected entities in the manufacturing environment of autonomous factories.
A method for determining a mass property of a rod and ball lattice (400) is provided. The method comprises determining the mass property for each ball (410,420,430) in the lattice, determining, for each rod (440,450), the mass property of a portion comprising the inter-body volume between the terminal balls (410,420,430) of the rod (440,450), generating an initial estimate of the mass property for the lattice (400) based on the mass properties of the balls (410,420,430) and portions of the rods (440,450), and for each ball (410,420,430), identifying overlapping portions (460) between pairs of rods (440,450) that terminate at the ball (410,420,430) and estimating the mass property for each identified overlapping portion (460) and modifying the initial estimate of the mass property of the lattice (400) based on the estimation of the mass properties of the overlapping portions (460).
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06T 7/62 - Analyse des attributs géométriques de la superficie, du périmètre, du diamètre ou du volume
G06T 7/66 - Analyse des attributs géométriques des moments d'image ou du centre de gravité
G06T 17/20 - Description filaire, p. ex. polygonalisation ou tessellation
G06F 113/10 - Fabrication additive, p. ex. impression en 3D
66.
AUTOMATED CONTROL OF ACCESS TO AN ASSET IN INDUSTRIAL POINTCLOUD-BASED REPRESENTATION
Systems and a method for receiving data of an engineering model and data of a pointcloud-based representation of a same given industrial environment. Data on a selection of at least two dimension-sizes of an asset of the engineering model is received; whereby a view access to the asset is to be controlled for at least one user. For the asset, the third dimension-size is received or extrapolating it from spatial information. An asset volume whose access is to be controlled is defined, herein called ACA-volume. Within the pointcloud-based representation a volume corresponding to the ACA-volume is identified.
A computing system (100) may include a point identification engine (108) configured to identify a point (220, 320, 610, 620) on a computer-aided design (CAD) face (210) of a CAD object and a point-based meshing engine (110) configured to construct an imprint shape (530) that surrounds the identified point (220, 320, 610, 620) by performing an iterative imprint shape determination process. The point-based meshing engine (110) may construct a candidate imprint shape (510, 520) for a given iteration, orient the candidate imprint shape, and perform an intersection check for the candidate imprint shape (510, 520). When the intersection check indicates an intersection, the point-based meshing engine (110) may determine a candidate imprint shape from a previous iteration as the imprint shape (530). The point-based meshing engine 110 may also be configured to mesh (414) the determined imprint shape (530) that surrounds the identified point (220, 320, 610, 620).
A method for inferring a program counter of a program executed by a computing system is provided. The method includes identifying, based on a program counter value including an address of a sequential instruction in the program, a sequential execution path containing the sequential instruction. The method also includes inferring a further program counter value based on the identified sequential execution path. The further program counter value includes an address of a last sequential instruction in the identified sequential execution path.
A system (100) may include a verification platform (120) configured to represent a design-under-test (DUT) (122) to verify operation of the DUT (122). The system (100) may also include a computing system (102) comprising a data construction engine (110) configured to construct management data (210) to configure the DUT (122) in a given manner and a data blending engine (112). The data blending engine (112) may be configured to access synthetic traffic data (220) to test the operation of the DUT (122), blend the management data (210) and the synthetic traffic data (220) into a blended data stream (230), and communicate the blended data stream (230) comprising the management data (210) and the synthetic data across a physical communication link to the verification platform (120) that represents the DUT (122).
G06F 30/331 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation avec accélération matérielle, p. ex. en utilisant les réseaux de portes programmables [FPGA] ou une émulation
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G06F 13/362 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée
71.
MEMORY BUILT-IN SELF-TEST WITH AUTOMATED DETECTION OF MAGNETIC TUNNELING JUNCTION DEGRADATION FOR REPAIR
This application discloses a memory device having multiple memory cells, each configured to store different values of data using different resistance states. A memory built-in self-test system can prompt the memory device to perform memory read operations for the memory cells storing the data in the different resistance states, determine a separation between the different resistance states of at least a subset of the memory cells, and detect one or more of the memory cells has a degraded tunneling layer in a magnetic tunneling junction based on the separation between the different resistive states in the at least the subset of the memory cells. A built-in repair analysis circuit can perform a repair of a group of the memory cells including at least on one of the detected memory cells based on the detection of the memory cells having degraded tunneling layers in the magnetic tunneling junctions.
G11C 29/50 - Test marginal, p. ex. test de vitesse, de tension ou de courant
G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p. ex. compteurs de rafraîchissement défectueux
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
G11C 29/16 - Mise en œuvre d'une logique de commande, p. ex. décodeurs de mode de test utilisant des unités microprogrammées, p. ex. machines à états logiques
G11C 29/24 - Accès à des cellules additionnelles, p. ex. cellules factices ou cellules redondantes
G11C 29/44 - Indication ou identification d'erreurs, p. ex. pour la réparation
A method of generating a master recipe including resources and describing a process flow for a specific production in a specific plant includes obtaining a general recipe including information related to the process flow without identifying the resources to be used to perform the process. The method includes: determining required capabilities of the general recipe in the form of a first semantic graph; determining provided capabilities of at least one plant in the form of a second semantic graph labeled with the capabilities of resources of the one or more plants and/or based on an equipment topology of the respective plant also in the industry specific language or ontology; semantically matching the required capabilities with the provided capabilities by identifying one or more sub-graphs in the second semantic graph comprising the resources for carrying out the process flow; and outputting the one or more sub-graphs as a master recipe.
Thus, it is the objective of the present invention to define a method that uses semantic technology to manage a single abstract level data model of different applications and automatize the process of producing the interoperability rules among different manufacturing sites. This objective is achieved according to the present invention by a method for enabling MOM systems for autonomous factories by encoding manufacturing domain knowledge in a democratic network of extensible and configurable ontologies, said method comprising the steps of: a) defining an ontology of a MOM domain through a semantic conceptualization of the manufacturing domain knowledge; b) representing the ontology through a least one knowledge graph; c) implementing the ontology in owl format; d) providing a web-based framework to provide a set of intuitive user friendly user interfaces to navigate the ontology and associate concepts comprised in the ontology to logical data structures coming from existing applications that are comprised in the MOM systems; e) mapping of the logical data structures through semantic matches of the semantic conceptualization; f) generating an interoperability code between the data structures of different applications thereby mapping data structure of the different applications within the same MOM system and/or over a number of distributed MOM systems of the autonomous factories.
A memory-testing circuit in a circuit configured to perform a test on one or more memories in the circuit, of which each has a plurality of logical ports. The memory-testing circuit comprises: a test algorithm control unit configured to implement a test algorithm, a reference address generator configured to generate, based on the test algorithm, a reference address, one or more concurrent address generators configured to generate, based on the reference address, one or more concurrent addresses, and address selecting circuitry for each of the one or more memories configured to select, based on an address selection signal, the reference address or one of the one or more concurrent addresses for each of the plurality of logical ports. One logical port is configured to receive an algorithm command and the reference address, while the other logical ports are configured to receive concurrent commands and the concurrent addresses.
G11C 29/18 - Dispositifs pour la génération d'adressesDispositifs pour l'accès aux mémoires, p. ex. détails de circuits d'adressage
G11C 29/20 - Dispositifs pour la génération d'adressesDispositifs pour l'accès aux mémoires, p. ex. détails de circuits d'adressage utilisant des compteurs ou des registres à décalage à rétroaction linéaire [LFSR]
G11C 29/28 - Réseaux multiples dépendants, p. ex. réseaux multi-bits
G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes
G11C 8/16 - Réseau de mémoire à accès multiple, p. ex. adressage à un élément d'emmagasinage par au moins deux groupes de lignes d'adressage indépendantes
75.
MEMORY BUILT-IN SELF-TEST WITH AUTOMATED WRITE TRIM TUNING
This application discloses a memory device configured to store data using a write voltage having a voltage level corresponding to a write trim. A memory built-in self-test system can prompt the memory device to perform memory write operations to store the data using selected test values for the write trim, determine when the memory device fails to correctly store the data with the write voltages corresponding to each of the selected test values for the write trim, and set the write trim for the memory device based, at least in part, on the determination of failures of the memory device to correctly store the data. The memory built-in self-test system is configured to iteratively select one or more of the test values for the write trim based on the determination of failures of the memory device to correctly store the data.
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p. ex. compteurs de rafraîchissement défectueux
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
76.
METHOD FOR GENERATING TOOLPATH, AND SYSTEM FOR GENERATING TOOLPATH AND COMPUTER-READABLE STORAGE MEDIUM THEREOF
Disclosed is a method for generating a toolpath of a tool for fixed shaft milling. The method includes: inputting a workpiece geometry, the workpiece geometry including a milling region; defining a region falling within the same range of height and communicated with the milling region on the workpiece geometry as an auxiliary region, the height being a height defined along an orientation of a tool axis; defining a combined region of the milling region and the auxiliary region as a transition region; generating a spiral toolpath of the transition region; and replacing a portion for milling the auxiliary region in the spiral tool path with a non-milling toolpath. The method is favorable to improving uniformity of the toolpath. Further disclosed is a system for generating a toolpath and computer-readable storage medium thereof.
G05B 19/19 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par systèmes de commande de positionnement ou de commande de contournage, p. ex. pour commander la position à partir d'un point programmé vers un autre point ou pour commander un mouvement le long d'un parcours continu programmé
77.
CHARACTERIZATION OF LITHOGRAPHIC PROCESS VARIATION FOR MANUFACTURING PROCESS CALIBRATION USING IMPORTANCE SAMPLING
A computing system can characterize stochastic variation in a lithographic process for manufacturing an integrated circuit using importance sampling. The computing system can select a modification to the lithographic process, and identify structures of the integrated circuit that, when manufactured using the modified lithographic process, correspond to manufacturing failures. The computing system can determine a likelihood ratio based on the modification to the lithographic process relative the unmodified lithographic process for manufacturing the integrated circuit, and utilize the likelihood ratio to weigh the manufacturing failures of the structures manufactured using the modified lithographic process to characterize the stochastic variation in the unmodified lithographic process. The computing system can utilize the characterization of the stochastic variation in the unmodified lithographic process to calibrate an electronic design automation tool configured to modify a layout design for the integrated circuit or a mask design for manufacturing of the integrated circuit.
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
78.
EXPERT-BASED GUIDANCE THROUGH VIRTUAL AVATARS IN AUGMENTED REALITY AND VIRTUAL REALITY ENVIRONMENTS
A system may include a semantic actions database configured to reference a working context knowledge graph to specify target actions to perform a task and environment conditions of an environment in which an individual performs the task. The system may also include an expert avatar engine configured to access a posture set from a digital data stream of a target individual performing the task in an environment, classify the postures of the posture set into discrete actions, retrieve target actions from the semantic actions database for performing the task in the environment, generate guidance for the target individual based on a comparison between the discrete actions classified for the target individual and the target actions retrieved from the semantic actions database, and provide the guidance to the target individual to assist the target individual in performing the task.
A computer-implemented method is provided for generating a blend surface for a model of a component. The method comprises: determining a first curve in three-dimensional space, wherein, for each point on the first curve, the distance of the point from a first surface and the distance of the point from a second surface is within a threshold of a pre-determined parameter; determining a second curve comprising a projection of the first curve on to the first surface; determining a third curve comprising a projection of the first curve on to the second surface; generating, based on the first curve, the second curve, and the third curve, a first field function comprising a signed distance from a point in three-dimensional space to a blend surface between the first surface and the second surface; and generating the blend surface based on the first field function.
Chain pattern results are analyzed to identify a faulty scan chain in a circuit and a fault associated with the faulty scan chain. Scan pattern results are analyzed to identify one or more faulty scan element candidates on the faulty scan chain. Analog simulation is then performed to identify faulty component candidates in the one or more faulty scan element candidates. During the process, components in each of the one or more faulty scan element candidates sensitive to a signal change at an input of the each of the one or more faulty scan element candidates can be determined. Physical failure analysis can be performed on the circuit to locate one or more defective components in the faulty component candidates.
A method, (e.g., a computer-implemented method), of generating a production plan (BOP) is provided. The method includes obtaining one or more product and/or production characteristics (E-BOM, CAD-BOM, M-BOM), (e.g., a production content, a production time, and/or a production quantity, for example in a E-BOM, M-BOM, and/or CAD file format), for a product to be manufactured. The method further includes determining, by a rule engine (10), based on the characteristics one or more library elements from a plurality of library elements (11a, 11b), wherein each library element includes one or more process descriptions relating to the characteristic. The method further includes arranging, by the rule engine (10), the one or more process descriptions into a production plan (BOP).
G06Q 10/06 - Ressources, gestion de tâches, des ressources humaines ou de projetsPlanification d’entreprise ou d’organisationModélisation d’entreprise ou d’organisation
G06Q 10/04 - Prévision ou optimisation spécialement adaptées à des fins administratives ou de gestion, p. ex. programmation linéaire ou "problème d’optimisation des stocks"
G06Q 10/08 - Logistique, p. ex. entreposage, chargement ou distributionGestion d’inventaires ou de stocks
Obfuscation types are assigned to strings related to a circuit design. The obfuscation types determine whether and how the strings are obfuscated. An obfuscation-related operation is then performed on the strings based on the obfuscation types. An interface unit determines whether a string to be written into an output file has one or more obfuscation types, wherein the output file is to be used in a process related to testing circuits fabricated based on the circuit design. The interface unit request access to the output file from an output file managing unit. Upon determining that the interface unit has a predefined security mechanism, the output file managing unit provides to the interface unit the access. Here, the predefined security mechanism comprises determining whether a string has one or more obfuscation types. The interface unit then generates the output file.
G06F 21/75 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par inhibition de l’analyse de circuit ou du fonctionnement, p. ex. pour empêcher l'ingénierie inverse
G06F 21/14 - Protection des logiciels exécutables contre l’analyse de logiciel ou l'ingénierie inverse, p. ex. par masquage
A virtual space mouse is provided which comprising three virtual 2D graphic objects called central knob, top knob and side knob. The three knobs are placed on a navigation area reachable by finger gestures. Each knob is configured for being draggable via substantially vertical/horizonal direction movements so as to define six basic mouse manipulation gestures each one associated to a corresponding basic 6DOF change which is a basic manipulation of a position or of a rotation of a given virtual entity in the 3D space in six degrees of freedom. Receive a drag gesture input applied to one or more of its three knobs and a corresponding 6DOF manipulation of the given virtual entity in the 3D space is performed.
G06F 3/0346 - Dispositifs de pointage déplacés ou positionnés par l'utilisateurLeurs accessoires avec détection de l’orientation ou du mouvement libre du dispositif dans un espace en trois dimensions [3D], p. ex. souris 3D, dispositifs de pointage à six degrés de liberté [6-DOF] utilisant des capteurs gyroscopiques, accéléromètres ou d’inclinaison
G06F 3/033 - Dispositifs de pointage déplacés ou positionnés par l'utilisateurLeurs accessoires
G06F 3/03 - Dispositions pour convertir sous forme codée la position ou le déplacement d'un élément
G06F 3/02 - Dispositions d'entrée utilisant des interrupteurs actionnés manuellement, p. ex. des claviers ou des cadrans
A method for generating a mesh for a lattice structure in a three-dimensional model is provided. A first mesh incarnation method is applied to a first lattice to generate a first mesh. A region of the first lattice is identified where the first mesh incarnation method fails to generate mesh facets. A second lattice is extracted from the first lattice, including bodies of the first lattice in the region where the first mesh incarnation method fails to generate mesh facets. Polylines on the first mesh of the first lattice where an offset of the second lattice intersects with the first mesh are identified. A third lattice is generated based on the polylines. A second mesh incarnation method is applied to generate a first mesh of the third lattice. The first mesh of the first lattice and the first mesh of the third lattice are trimmed and combined to generate a second mesh with mesh facets in the region where the first mesh incarnation method fails to generate facets.
A method and system for assembling one or more geometric components in a computer-aided design (CAD) environment is disclosed. In one embodiment, a method includes generating a first set of points corresponding to geometric feature(s) of a first geometric component, and generating a second set of points corresponding to geometric feature(s) of a second geometric component. The method includes determining whether there is a match between the first set of points and the second set of points based on distances between the first set of points and distances between the second set of points. Furthermore, the method includes generating assembly solution(s) for assembling the first geometric component and the second geometric component based on the match between the first set of points and the second set of points. Moreover, the method includes generating a CAD model including the first geometric component constrained with the second geometric component.
A computer-implemented method of generating a volume mesh between two proximate, disjoint, and opposing mesh surfaces of a three-dimensional object in a modelling system is described. A projected volume is determined, wherein a mesh volume having a first topology is generated when the volume reaches the opposing mesh surfaces within a distance determined by the local mesh size. A second volume mesh with a different topology is generated when the projected volume does not reach the opposing mesh surface.
A computer-implemented method of optimizing vertex chains in a stack of disjoint mesh surfaces in a three-dimensional object in a modelling system is described. A vertex chain includes nearest-neighbor mesh vertices in adjacent surface meshes in the stack terminated by first and second endpoints. The modelling system is configured to render an image of the object including the meshed surfaces to a user. Aa stack of disjoint surface meshes describing a thin volume of an object, the stack containing at least one vertex chain is retrieved, and the alignment between the mesh vertices is constrained by an optimal Bézier curve.
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06F 30/28 - Optimisation, vérification ou simulation de l’objet conçu utilisant la dynamique des fluides, p. ex. les équations de Navier-Stokes ou la dynamique des fluides numérique [DFN]
The present invention proposes a system and a method for detecting and locating an object (310) in a physical environment (300), the method comprising: - - receiving (210) a first image (301) representing said physical environment (300), wherein said first image is a 3D point cloud image comprising location data for points in the point cloud image; - receiving (220) a second image (302) representing said physical environment (300), wherein said second image (302) is a 2D pixel image of said physical environment (300); - detecting (230) said object (310) in one or several regions in the second image (302); - for each region where said object (310) has been detected in the second image (302), finding (240) a corresponding region in the first image (301); - providing (250), via an interface, said corresponding region in the first image (301) as a location where said object (310) has been detected.
A computer-implemented method and a system for capturing and managing changes to a history-based part model are described. The changes are generated external to the part and are stored as a feature within the history-based modelling system. The method and system are used in the context of a part assembly edit. A user supplies a generic change to the part assembly in the form of an initial driving change. This is analyzed to determine consequential changes within the model that need to be made to preserve the consistency of the model of the part assembly. For each part affected by the generic change, part-level shape-changes generated external to the part are captured in a new shape-change feature and stored at the end of the current feature history of the part
A circuit comprises scan chains comprising scan cells and one or more observation scan chains. The scan chains comprise scan cells. The one or more observation scan chains comprises observation scan cells. Testing the circuit comprises a scan-capture phase and an observation scan phase. During the scan-capture phase, both the scan cells and the observation scan cells operate in a shift mode and a capture mode alternately. During the observation scan phase, the scan cells operating in the shift mode and the observation scan cells operating in a shift-observation mode.
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06F 113/10 - Fabrication additive, p. ex. impression en 3D
The invention provides an apparatus for monitoring an operability of a production system, the apparatus comprising: - an input unit configured to input production-related data of the production system, - a mapping engine configured to map the production-related data to instance data of a first knowledge graph according to a given mapping definition, - a first validation unit configured to validate a consistency and/or an integrity of the instance data by means of declarative constraints and to output a first validation result, - a simulator configured to generate a computer-implemented material flow simulation model of the production system based on the instance data and depending on the first validation result, - a generator configured to generate simulated production logs using the material flow simulation model, - a second validation unit configured to validate the simulated production logs against measured production logs of the production system and to output a second validation result, and - an output unit configured to output the second validation result for monitoring the operability of the production system.
An integrated circuit including at least two interconnected sub-blocks in a System-on-Chip (SoC) arrangement and a method for communicating data in the integrated circuit are provided. The method includes transmitting a first signal asserting that a first sub-block is ready to transmit data to a second sub-block, receiving a second signal asserting that the second sub-block is ready to receive data from the first sub-block and transmitting data including one or more contiguous messages via a third signal from the first sub-block to the second sub-block. The first signal includes information that enables the second sub-block to determine a position of the end of the last message in the contiguous messages.
A method for an integrated circuit including a plurality of interconnected sub-blocks in a System-on-Chip (SoC) arrangement is provided. The method includes transmitting a message from a first sub-block to at least one sub-block of the plurality of interconnected sub-blocks, in response to an event on the integrated circuit and transmitting a signal from the first sub-block to the at least one sub-block of the plurality of interconnected sub-blocks. The signal includes information identifying a class of the event based on a classification of events associated to the integrated circuit into one or more classes.
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06F 113/10 - Fabrication additive, p. ex. impression en 3D
97.
MACHINE LEARNING-BASED CONVERSION OF SCHEMATIC DIAGRAMS
A computing system can parse a schematic diagram illustrating an electronic system to identify design blocks and wire lines coupled to the design blocks in the schematic diagram. The computing system, implementing at least one supervised machine-learning classification algorithm, can classify the design blocks and the wire lines. The classification of the design blocks can correspond to one or more symbols representing components of the electronic system. The classification of the wire lines can correspond to one or more links representing connectivity for at least one of the components of the electronic system. The computing system can generate a system design describing the electronic system based, at least in part, on the symbols representing the components of the electronic system classified to the design blocks and the links representing connectivity for at least one of the components of the electronic system classified to the wire lines.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 113/16 - Câbles, arbres de câblage ou faisceaux de fils électriques
98.
USER CREDENTIAL PARAMETER SPACE PARTITIONING IN A RULE BASED ACCESS CONTROL SYSTEM
This application discloses a computing system to process rules defining access privileges for product data stored in a product data management system, which identifies accessor parameters capable of satisfying the rules for accessing the product data. The computing system can identify session parameters corresponding to user characteristics in an organization for a plurality of users, and correlate the accessor parameters for the product data to the session parameters for the users, which can partition a parameter space of the session parameters for the plurality of the users. The computing system can selectively evaluate the access privileges to the product data for at least one of the users by selecting one of the users in each partition, evaluating the access privileges to the product data using the session parameters of the selected users, and skipping evaluation of the access privileges to the product data using the session parameters of non-selected users.
Computer-implemented system and method are provided for generating an additive manufacturing (AM) build program used to build an object having a manifold boundary body. A manufacturing definition module merges build information and AM machine schema information for a manufacturing definition. The build information includes specification of region-based build parameters and the machine schema information includes AM machine specific parameters related to material build by layers. Slice generation module performs a direct slicing algorithm of a 3D CAD model defining the geometry for the object, wherein slices of the model are defined according to layer thickness along a slicing direction. A region based recipe module is configured to generate annotated slices, wherein each slice is annotated with information based on the manufacturing definition. The annotated slices are sent to an edge computing device controlling the AM machine to be converted to a final build file with tool path and process parameters.
A computing system (100) may include a database identification engine (108) configured to identify databases (111, 112) of different systems (121, 122). The computing system (100) may also include a link discovery engine (110) configured to construct a supergraph (220) that represents the data elements stored in the databases (111, 112), including by constructing graphs (211, 212) for tables in the databases (111, 112) and merging the graphs (211, 212) into the supergraph (220), including by performing a cell fusion to merge multiple nodes (311, 312) from the graphs (211, 212) with an identical data element value into a fused node (320) in the supergraph (220). The link discovery engine (110) also be configured to process the supergraph (220) according to cross-domain linking criteria to determine cross-domain links (410) for data stored in the databases (111, 112) of the different systems (121, 122).
brevets
