A computer-implemented method for reporting an electrostatic discharge (ESD) violation in an integrated circuit (IC) design is provided. The IC design includes a plurality of metal layers arranged in a metal layer stack from a bottom metal layer to an upper metal layer. The IC design includes a plurality of cells. The respective cell includes at least one device. The respective cell is arranged on one or more of the metal layers. The respective device includes at least one device probe point arranged on an ESD path in the IC design. The method includes mapping the respective device probe point to a respective cell port according to mapping rules, determining the ESD violation of the IC design using the device probe points and the mapped cell ports, and reporting the determined ESD violation of the IC design to a user.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 115/12 - Cartes de circuits imprimés [PCB] ou modules multi-puces [MCM]
2.
CHANGE-AWARE LAYOUT-VERSUS-SCHEMATIC (LVS) PROCESSES IN ELECTRONIC DESIGN AUTOMATION (EDA)
Systems and methods are presented in support of change-aware layout-versus-schematic (LVS) processes. A method may include steps of identifying a set of modified corresponding cells indicative of modifications made to a source circuit design or a layout circuit design and performing a change-aware LVS process. Performing of the change-aware LVS process may include determining a common corresponding cell of the source circuit design and the layout circuit design, wherein the common corresponding cell comprises equivalent hierarchical cells that correspond between the source circuit design and the layout design, and wherein the equivalent hierarchical cells of the common corresponding cell include, as internally-referenced lower hierarchy cells, the set of modified corresponding cells and performing a LVS process on circuit design portions included in the common corresponding cell.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
3.
ACCURATE PORT CROSS-REFERENCES FOR CIRCUIT COMPARISONS IN ELECTRONIC DESIGN AUTOMATION (EDA)
Systems and methods are presented for accurate port cross-reference determinations in different instances of a cell correspondences in circuit comparisons. A method may include accessing a source circuit design and a layout circuit design and identifying a cell correspondence. The cell correspondence may specify that a given cell in the source circuit design corresponds to a given cell in the layout circuit design. The method may also include performing a circuit comparison between the source circuit design and the layout circuit design, including by detecting a correspondence conflict in which multiple cell correspondence placements of the cell correspondence in the source circuit design and the layout circuit design have different port cross-references and creating different port cross-references for the multiple cell correspondence placements. The method may further include adjusting the source circuit design, the layout circuit design, or both, based on the performed circuit comparison.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
4.
METHOD AND SYSTEM FOR GROUPING COMPONENTS FOR ELECTRONIC DESIGN AUTOMATION
The invention relates to grouping electrical components for the creation of a layout of a printed circuit board. A sheet grouping module (SG) processes a schematic (S) and filters a netlist (N) by identifying for each sheet of the schematic component nodes in the netlist that are depicted on that sheet. A one-hop seed assignment module (1H-AA) assigns to every component node a set of seed candidate nodes which are in one-hop reach from that component node in the netlist on the same sheet of the schematic (S). An assignment prediction module (GNN-AP) containing a graph neural network checks if the assigned set of seed candidate nodes contains a single seed candidate node, and then assigns it as a seed to the component node. If the assigned set of seed candidate nodes is empty, the graph neural network predicts a seed candidate node for the component node. The predicted seed candidate node is assigned as a seed to the component node, if the prediction passes a confidence threshold. If the respective set of seed candidate nodes contains multiple seed candidate nodes, then the graph neural network predicts the best seed candidate node among the multiple seed candidate nodes. The predicted seed candidate node is assigned as a seed to the component node, if the prediction passes the confidence threshold. Component nodes assigned to the same seed form a group. Efficiency of the workflows of electronic design automation is increased due to a combination of machine learning and heuristics: The assignment prediction module only needs to compute predictions for a set of seed candidate nodes which is already filtered by a generic graph heuristic.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
5.
SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED MULTI-MODALITY COMPUTER-AIDED MANUFACTURING CO-PILOT
The present disclosure provides a computer-implemented method for integrated multi- modality computer-aided manufacturing co-pilot. The method includes receiving multi- modality input data related to a computer-aided manufacturing (CAM) task, where the multi-modality input data includes a point cloud representation, a graphical representation of a 3D CAD model, a textual representation in STEP format, a 2D drawing with machining annotations, or any combination thereof. Each modality of the input data is processed using a respective encoder (PEC, TEC, GNE, IMB) to generate encoded data. The encoded data from each modality is projected into a shared embedding space using a projection module (PPJ, TPJ, GPJ, IME). A snapshot of a current state of a CAM program is received. The projected data and the snapshot are processed using a large language model (ELM). Based on the processing, both natural language explanations and actionable commands within the CAM software are generated in response to queries related to the CAM task. Further, a corresponding system and a corresponding computer program product are provided.
G05B 19/4097 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par l'utilisation de données de conception pour commander des machines à commande numérique [CN], p. ex. conception et fabrication assistées par ordinateur CFAO
G05B 19/4093 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par la programmation de pièce, p. ex. introduction d'une information géométrique dérivée d'un dessin technique, combinaison de cette information avec l'information d'usinage et de matériau pour obtenir une information de commande, appelée programme de pièce, pour la machine à commande numérique [CN]
B29C 64/20 - Appareil pour la fabrication additiveDétails ou accessoires à cet effet
B33Y 50/02 - Acquisition ou traitement de données pour la fabrication additive pour la commande ou la régulation de procédés de fabrication additive
6.
CONTOUR EXTRACTION EDGE-BASED WAFER IMAGE CHARACTERIZATION FOR MANUFACTURING PROCESS CALIBRATION
A computing system can aggregate a plurality of wafer images depicting a portion of an electronic device into a reference image. The electronic device has physical structures manufactured using one or more lithographic process. The computing system can determine which windows in the reference image and in the wafer images include image data corresponding to the physical structures of the electronic device and which of the windows in the reference image and in the wafer images include image data corresponding background image data. The computing system can compare the windows of the reference image that including image data corresponding to the physical structures of the electronic device to the windows of the wafer images include image data corresponding to the physical structures of the electronic device, and generate a gauge file to include a set of the wafer images that are selected based on the comparison.
A computer-implemented method is provided for determining a plurality of analysis windows of an integrated circuit (IC) design for analyzing the IC design, wherein the IC design may include a plurality of patterns. The method may include providing the IC design; determining a plurality of clusters in the IC design, wherein the respective cluster includes similar patterns; and determining the respective analysis window including a configurable number or type of different clusters.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
G06F 119/18 - Analyse de fabricabilité ou optimisation de fabricabilité
G06F 119/22 - Analyse de rendement ou optimisation de rendement
8.
GENERATING A LAYOUT PATTERN OF AN INTEGRATED CIRCUIT DESIGN WITH AN ARTIFICIAL INTELLIGENCE PATTERN GENERATOR
A computer-implemented method for generating a layout pattern of an integrated circuit (IC) design including: adding a random pattern structure to an input layout pattern: compressing an image of the input layout pattern to a latent space image of the input layout pattern: determining a new image by applying an inpainting technique and a denoising technique on the latent space image of the input layout pattern; and decompressing the new image from the latent space into a real space image of the generated layout pattern.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
A method and a system for translating a natural language input to a domain-specific structured query are disclosed. The method includes: receiving a user query in natural language; extracting command(s) and elements from the user query using a language model triggered by a domain-specific prompt; and generating a preliminary query that includes the extracted command(s) and elements. Significant elements are identified from a domain-specific ontology by comparing extracted elements in the preliminary with predefined elements in the ontology. Valid combinations of significant elements are mapped to the preliminary query by referencing the ontology's defined relationships to obtain applicable element combinations. The domain-specific structured query is then generated by executing the language model on the extracted commands and applicable element combinations, which enables performing actions intended by the user as expressed through the natural language input.
Methods and systems for synchronizing interactions in an immersive environment and a non-immersive environment of a software application are described. A pairing is formed between an interactive element in the immersive environment and an interactive element in the non-immersive environment. In response to an interaction with a first interactive element of the paired interactive elements, a message is communicated from the environment of the first interactive element to the environment of the second interactive element of the pairing, comprising a pairing identifier and state data associated with the first interactive element. When the message is received in the environment of the second interactive element, the second interactive element is identified based on the pairing identifier, and the state of the second interactive element is modified dynamically based on the state data.
A computer-implemented method of determining a mass property of a face bounding a region of a computer aided design (CAD) model is disclosed. The region of the CAD model includes an embedding of an implicitly defined geometric structure. The method includes generating an initial mesh representation of the face, evaluating each vertex to identify points on edges of facets of the mesh representation that lie on an iso-surface of the embedded geometric structure, refining the initial mesh representation based on the identified points, and determining a mass property based on the refined mesh representation
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06T 17/20 - Description filaire, p. ex. polygonalisation ou tessellation
G06T 17/30 - Description de surfaces, p. ex. description de surfaces polynomiales
G06F 30/00 - Conception assistée par ordinateur [CAO]
12.
METHOD AND SAMPLING SYSTEM FOR SAMPLING TRAINING DATA FOR TRAINING A GRAPH NEURAL NETWORK FOR ELECTRONIC DESIGN AUTOMATION
The invention relates to sampling training data for training a graph neural network for electronic design automation. A graph database stores (1) a plurality of graphs each representing a finished electronic design, with each graph containing components nodes with component features, and edges, wherein each component node represents a physical component. A graph clustering module assigns (3) a cluster from a set of clusters to each component node, wherein each cluster represents component nodes with common characteristics in topology and/or common component features. A cluster-based link sampling module samples (4) an edge from a sample space, wherein the sample space consists of all edges connecting clusters of component nodes in a selected graph currently selected among the graphs, and wherein a component node connected to the sampled edge is taken as a source component node, and wherein a subgraph is taken from the selected graph based on a receptive field around the source component node. Finally, a cluster-based receptive field sampling module picks (5) a cluster of component nodes that is connected to the source component node within the subgraph, reduces (6) the subgraph by dropping the picked cluster of component nodes, creates a corresponding reduced subgraph, and adds (7) the reduced subgraph along with the source component node and a target to a training set, wherein the target is a label of the picked cluster. These operations can be repeated iteratively (8), until every cluster has been picked, and/or recursively (9) within the reduced subgraphs, until only one cluster remains. Further embodiments provide a novel end-to-end training procedure for GNN-based recommender systems based on the efficient link sampling, which results in faster convergence during training, thus saving both compute resource costs and expert's time while waiting for new models. As a consequence, this enables the possibility to explore a wider range of models (e.g., a larger hyperparameter range) within given constraints.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06N 3/082 - Méthodes d'apprentissage modifiant l’architecture, p. ex. par ajout, suppression ou mise sous silence de nœuds ou de connexions
13.
GEOMETRIC TOKENS IN FOUNDATION MODEL FOR MECHANICAL DESIGN
This patent application discloses a computing system to analyze a geometric representation of the mechanical part to identify a topological connectivity for faces and edges of the mechanical part, sample the faces and the edges of the mechanical part described in the geometric representation of the mechanical part, separately encode the samples of the faces and the edges of the mechanical part into geometric tokens, and combine the geometric tokens according to the topological connectivity for the faces and the edges in the mechanical part. The computing system can implement a machine-learning algorithm that can utilize the combined geometric tokens to generate output tokens that, when decoded, correspond to one or more tasks configured for implementation by a mechanical design tool developing a mechanical design including the mechanical part.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
A method and Product Data Management (PDM) system for configuring a product are disclosed. The PDM system is configured for obtaining a plurality of original constraints from a source. Further, a plurality of sequence groups is identified from the plurality of original constraints, wherein constraints within each sequence group of the plurality of sequence groups have relative sequential effects on each other. Further, each constraint within each sequence group is remodeled to a modified expression suitable for processing using a declarative solver. The modified expression is indicative of a sequential processing priority for the constraint within the sequence group. The sequence groups are processed simultaneously, using the declarative solver, to determine one or more valid product configurations. Each constraint is processed based on the respective sequential processing priority within the corresponding sequence group. The one or more valid product configurations are outputted on an output unit.
A method and system for updating a computer-aided design (CAD) model in a CAD system are disclosed. The method comprises: displaying a model in a CAD interface; identifying a selection of geometric entities in the model; providing an interactive element in the user interface, determining a mode of operation of the interactive element; detecting a user interaction with the interactive element; and dynamically updating the model based on the selected mode of operation, the selected geometric entities, and the user interaction. A first mode of operation modifies the selected geometric entities, and a second mode of operation generates further geometric entities from the selected geometric entities.
This patent application discloses a computing system to identify multi-modal input data that describes features of a mechanical design for a product, and to separately encode the input data on a per-modality basis into modality-specific tokens configured for consumption by a machine-learning algorithm implemented by the computing system. The computing system implementing the machine-learning algorithm can analyze the modality-specific tokens together to generate output tokens embedded with a set of domain-specific operations. The computing system can decode the domain-specific operations embedded in the output tokens to determine one or more tasks with corresponding instructions configured for implementation by a mechanical design tool developing the mechanical design for the product. The mechanical design tool can utilize the tasks having the corresponding instructions to predict a domain-specific feature for the mechanical design.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
A data generation computing system can overcome the manual annotation bottleneck in training multi-modal foundation models that can effectively function as intelligent design assistants. The system can automatically creating diverse, linked, and high-quality multi- modal synthetic data from existing computer-aided design (CAD) assets, thereby enabling the scalable training of advanced mechanical design foundation models.
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
A circuit comprises scan chains. The scan chains comprise a plurality of scan cells configured to operate in one of a plurality of test-related modes based on a scan enable signal for the plurality of scan cells and a diagnosis clock control signal provided by a storage device while the circuit is being tested. The plurality of test-related modes comprises a clock-inactive capture mode and a clock-active capture mode. In the clock-inactive capture mode, the scan enable signal is inactive, the diagnosis clock control signal is inactive, and the plurality of scan cells receive no clock signals. In the clock-active capture mode, the scan enable signal is inactive, the diagnosis clock control signal is active, and the plurality of scan cells receive a clock signal. The storage device may be a scan cell in the scan chains or a shadow register of a scan cell in the scan chains.
A computer-implemented method for topology optimization of a design for manufacturing is disclosed. A method comprises: obtaining design variables associated with elements of the mesh and an overhang constraint for manufacturing the design; computing physical field variables for the elements of the mesh based on the design variables; computing build vectors describing build directions in the design space; and executing based on the physical field variables, the overhang constraint, and the build vectors, an optimization of the design that concurrently optimizes a topology of the design, constrains overhangs in the design, and optimizes a build direction for manufacturing the design, and generating updated design variables based on the optimization.
G06F 111/06 - Optimisation multi-objectif, p. ex. optimisation de Pareto utilisant le recuit simulé, les algorithmes de colonies de fourmis ou les algorithmes génétiques
G06F 113/10 - Fabrication additive, p. ex. impression en 3D
G06F 119/18 - Analyse de fabricabilité ou optimisation de fabricabilité
20.
DIAGNOSABLE LIBRARY SCAN CELLS WITH CONTROLLABLE INVERTER
A library scan cell comprises: one or more state elements configured to serve as a single bit or multiple bits of the library scan cell; and a controllable inverting device placed in a shift path of the library scan cell and between an input of one of the one or more state elements and a serial input of the library scan cell or an output of another one of the one or more state elements. The controllable inverting device is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal. The one of the one or more state elements is configured to operate in a plurality of test-related modes which comprises a diagnosis capture mode.
Automatic Switching Between Two Types of Interface Devices on Parallel Data Buses Various aspects of the disclosed technology relate to automatic switching between two types of interface devices on a data streaming network. The first type of interface devices can enter a sleep mode in response to a unique command data packet and sleep for a number of clock cycles specified in the unique command data packet (1230). The second type of interfaces devices can be activated by a sentinel signal and then process data transmitted in the data streaming network while the first type of interfaces is in the sleep mode (1240, 1250). After completing processing the data, the second type of interfaces devices become deactivated, and the first type of interfaces exits the sleep mode to process data transmitted in the data streaming network (1260). The process can be repeated.
H04L 41/0816 - Réglages de configuration caractérisés par les conditions déclenchant un changement de paramètres la condition étant une adaptation, p. ex. en réponse aux événements dans le réseau
A computer implemented method for training a generative model is provided. The method includes steps of accessing a training dataset comprising labelled and unlabelled point cloud representations of objects. In a first training phase a variational autoencoder comprising a first and second encoder and a decoder is trained on the training dataset. In a second training phase first and second denoising diffusion models are trained based on data output from the first and second encoders.
A system and method for power estimation for an electronic circuit design is disclosed. The method comprises receiving a request for performing power estimation for a first electronic circuit design of a first electronic device, wherein the request is indicative of one or more first nets in the first electronic circuit design. Further, one or more first attributes associated with at least one of the first nets in the first electronic circuit design are determined from the request based on the one or more first attributes of the first net, a capacitance model corresponding to the first net is identified, from a plurality of capacitance models stored in a database. The capacitance model of the first net is further used to perform the power estimation for the first electronic circuit design, and a power report file is generated based on the power estimation on an output device.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 119/06 - Analyse de puissance ou optimisation de puissance
24.
CONSTANT RADIUS ROLLING-BALL BLEND ON GRAPHICS PROCESSING UNIT (GPU)
Current approaches to generating rolling-ball bend faces are computationally inefficient, or result in defects, among other technical issues. A computing system can be configured to generate rolling-ball blend faces on a graphics processing unit (GPU) via multiple passes.
SIEMENS INDUSTRY SOFTWARE (A LIMITED LIABILITY COMPANY UNDER THE PRIVATE FREE ZONES REGIME) (Égypte)
Inventeur(s)
Maddukuri, Vikas
Yvon, Jean-Marc
Woods, Robert
Hemmersbach, Frank
Sherif, Salma
Elsharnoby, Mostafa
Abrégé
A method and data processing system for automatically determining positions of shield termination splices in a wire harness are provided. The method comprises the steps of accessing a digital representation of the wire harness, accessing a predefined set of constraints where each constrain defines a repositioning rule for repositioning the one or more splices and simulating the positioning of the one or more splices at different positions in the wire harness, to identify positions for each splice that are compatible with the set of constraints.
G06F 30/00 - Conception assistée par ordinateur [CAO]
H01R 43/28 - Appareils ou procédés spécialement adaptés à la fabrication, l'assemblage, l'entretien ou la réparation de connecteurs de lignes ou de collecteurs de courant ou pour relier les conducteurs électriques pour traiter le fil avant sa connexion aux pièces de contact, non prévus dans les groupes
H01B 7/00 - Conducteurs ou câbles isolés caractérisés par la forme
26.
A METHOD FOR TESTBENCH REPLICATION OF AN ASSERTION COUNTEREXAMPLE IN HIERARCHICAL C++ HIGH LEVEL SYNTHESIS DESIGNS
The present invention discloses a method and a system for testbench replication of an assertion counterexample in hierarchical C++ high level synthesis designs, comprising: - defining a high level synthesis (HLS) design for an integrated chip wherein the design of the integrated chip is programmed as a C++ hierarchical design; - verifying the HLS design and reporting inline assertions that are added via calls to an assert function of the high level synthesis design; - using a high level verification engine to debug a falsified assertion thereby providing an executable of the C++ hierarchical design that is built with a gcc compiler along with a gdb based debugger and that is used for the replication of a counterexample to remedy the falsified assertation which is referred to as testbench; - using the counterexample of the high level verification engine to drive the debugging of the falsified assertion with input values of the counterexample that will address the debugging at ac_channel operation level; - creating a database within the testbench being pre-populated with every ac_channel's read/nb_read operations data value being calculated in the counterexample that exist in cone of the falsified property where a falsified assertion has been generated for; - during the execution of the testbench when a read/nb_read operation of an internal ac_channel is performed using the pre-populated ac_channel's read/nb_read operations data value as input value for performing a read/nb_read operation during the debugging of the falsified assertion.
G06F 30/327 - Synthèse logiqueSynthèse de comportement, p. ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/3323 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p. ex. vérification de l’équivalence ou vérification des propriétés
A method of transmitting one or more radio data packets (40) by a first test device (11, 12, 13), the method comprising the steps of: obtaining, preferably repeatedly, by the first test device (11, 12, 13), a reference timestamp from a reference clock (RT), wherein the reference clock (RT) provides a reference time in a test system (1) comprising the first test device (11, 12, 13), wherein the reference timestamp indicates the reference time, transmitting, by the first test device (1), the one or more radio data packets, preferably sequentially, in accordance with a predetermined start time in the test system (1) on a communication interface (QSFP) for coupling the first test device (11, 12, 13) with a device under test, DUT (10).
A computer-implemented method for automatic selection of a tool of a CNC-machine-tool toolset. The method includes (a) a training phase that includes: (i) collecting a number of CAM-codes, each of which has at least one tool-object corresponding to a tool assigned to an operation-object corresponding to a machining process; (ii) extracting tool-objects and operation-objects and their respective association to each other from the CAM-codes such that a training dataset to train a machine learning model is obtained; and (iii) training the machine learning model using the training dataset, wherein the machine learning model learns the relationship between the operation-objects and tool-objects. The method further includes (b) an operational phase that includes: (i) providing an operation-object; and (ii) applying the trained machine learning model to the provided operation-object to select a tool-object for the operation-object, wherein the tool-object corresponds to a tool selected.
G05B 19/4093 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par la programmation de pièce, p. ex. introduction d'une information géométrique dérivée d'un dessin technique, combinaison de cette information avec l'information d'usinage et de matériau pour obtenir une information de commande, appelée programme de pièce, pour la machine à commande numérique [CN]
G05B 19/4097 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par l'utilisation de données de conception pour commander des machines à commande numérique [CN], p. ex. conception et fabrication assistées par ordinateur CFAO
29.
METHOD AND SYSTEM FOR NAVIGATION IN AN IMMERSIVE ENVIRONMENT
Methods and systems for controlling locomotion in an immersive environment using a hardware controller are provided. The hardware controller includes an inertial sensor and an input feature operable to transition between an inactive condition and a selected one of a first active condition and a second active condition, in response to a user interaction with the input feature. The method comprises receiving inertial data and detecting an active condition. While the detected active condition is maintained, the change in inertial data is mapped to a change in a spatial state in the immersive environment. The spatial state is updated in real time based on the output of the mapping.
G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur
G06F 3/0346 - Dispositifs de pointage déplacés ou positionnés par l'utilisateurLeurs accessoires avec détection de l’orientation ou du mouvement libre du dispositif dans un espace en trois dimensions [3D], p. ex. souris 3D, dispositifs de pointage à six degrés de liberté [6-DOF] utilisant des capteurs gyroscopiques, accéléromètres ou d’inclinaison
G06F 3/0354 - Dispositifs de pointage déplacés ou positionnés par l'utilisateurLeurs accessoires avec détection des mouvements relatifs en deux dimensions [2D] entre le dispositif de pointage ou une partie agissante dudit dispositif, et un plan ou une surface, p. ex. souris 2D, boules traçantes, crayons ou palets
A computer-implemented method and data processing system for identifying geometric features in a computer aided design (CAD) model are provided. Identification of features is based on a set of predefined conditions. Each condition is associated with a type of geometric feature and specifies a predefined threshold range of values for at least one quantity associated with the type of geometric feature. Model data for a CAD model is accessed in a CAD system. The model data is automatically evaluated in real-time to determine geometric features in the CAD model that satisfy at least one condition in the set. The geometric features that satisfy at least one condition in the set are identified in a user interface of the CAD system.
Methods for automated design search and corresponding systems and computer-readable mediums. A method (600) includes receiving (602) an automated design search (ADS) specification (154). The method includes receiving (604) design search data (166). The method includes receiving (606) a plurality of constraints (156), each constraint (156) having an associated constraint threshold (156) and computing and displaying (608) an initial output (400) of potential ADS solutions (158) according to the ADS specification (154), the design search data (166), and the constraints (156). The method includes receiving (610) a constraint relaxation input (162) from a user and, in response to receiving (610) the constraint relaxation input (162), computing and displaying (612) an updated output (500) of potential ADS solutions (158), according to the ADS specification (154), the constraints (156), the design search data (166), and the constraint relaxation input (162). The method can include dynamically and repeatedly updating (612) the updated output (500) when the constraint relaxation input (162) continues to be received (610).
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
G06F 111/06 - Optimisation multi-objectif, p. ex. optimisation de Pareto utilisant le recuit simulé, les algorithmes de colonies de fourmis ou les algorithmes génétiques
This patent application discloses a computing system to perform an unbalanced partitioning of a circuit design describing an electronic device and to simulate the unbalanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system. The computing system can merge performance data extracted from the parallel simulation of unbalanced partitions of the circuit design into a representation corresponding to a single core simulation, perform a balanced partitioning of the circuit design based, at least in part, on the merged performance data, and simulate the balanced partitions of the circuit design at least partially in parallel with the multiple processing cores of the computing system. The computing system also can iteratively merge newly extracted parallel simulation performance data, and repartition the circuit design.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
33.
VERIFICATION PERFORMANCE PROFILING WITH REGRESSION TEST
This application discloses a computing system to simulate a circuit design describing an electronic device with a plurality of functional verification tests, separately collect samples of performance data during simulation of the circuit design for each of the functional verification tests, and generate test databases for each of the functional verification tests. Each of the test databases include samples for a corresponding functional verification test. The computing system can merge the samples of performance data in the test databases for the functional verification tests. The computing system can filter the merged samples of performance data into a subset of the merged samples of performance data based, at least in part, on profile filtering commands, and generate a profile presentation including the subset of the merged samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot.
G06F 30/3308 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
34.
FAILURE RATE-AWARE PREDICTION MODELS FOR HOTSPOT PREDICTION IN CIRCUIT DESIGNS
A method for hotspot prediction for circuit designs through failure rate-aware prediction models may include training a failure rate-aware prediction model. Training the failure rate-aware prediction model may include correlating confirmed hotspot locations and confirmed non-hotspot locations to circuit elements of a training circuit design, extracting hotspot feature vectors and non-hotspot feature vectors from the correlated circuit elements, clustering the hotspot feature vectors and the non-hotspot feature vectors into feature vector clusters in a partitioned feature space. Training may also include determining a failure rate value for the given feature space partition that the given feature vector cluster is located within, the failure rate value computed based at least on the number of hotspot feature vectors included in the given feature vector cluster. The method may further include analyzing an input circuit design through the trained failure rate-aware prediction model to predict hotspot locations the input circuit design.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
35.
STATIC TIMING ANALYSIS WITH NON-RE CURSIVE CONVOLUTION-BASED DELAY CALCULATION
This application discloses a computing system to identify a path within a physical layout design of an integrated circuit. The path can have a cell configured to drive a current through a plurality of stages to a sink pins in the integrated circuit. The computing system can generate a timing for the path using non-recursive convolution to determine responses at each of the stages based on the current and loads associated with the stages, and determine a delay for signal propagation on the path based on the timing associated with stages of the path. The computing system can identify at least one timing violation for the path based on the delay for signal propagation on the path, generate a timing report including the path, the delay for signal propagation on the path, and the timing violation for the path, and modify the physical layout design based on the timing violation.
A system and a method for circuit design verification. The system and a method may reuse data generated in a verification iteration of a previous IC layout, thereby skipping one or more respective steps and/or reducing computation in the verification iteration for the current IC layout, thereby reducing the runtime for verifying the current IC layout. The method includes storing first IC layout data for a first IC layout; identifying one or more modifications between the first IC layout and a second IC layout; analyzing the one or more modifications; and based on the analysis of the one or more modifications, performing one or more of skipping a respective step of the plurality of steps, performing less computation for the respective step, or re-performing the respective step.
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 30/327 - Synthèse logiqueSynthèse de comportement, p. ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
A computing system for glitch power estimation receives a circuit design describing an electronic device and waveform data. One or more waveforms corresponding to one or more critical points in the circuit design are extracted from the waveform data. For each connected component, a zero-delay simulation is performed to generate a zero-delay output waveform associated with at least one internal node of the connected component, and a delay aware output waveform reconstruction to generate a delayed output waveform associated with at least one internal node of the connected component. One or more glitch toggles in the delayed output waveform are identified based on a comparison between the zero-delay output waveform and the delayed output waveform. A glitch power associated with the connected component based on toggles identified as glitch in the delayed output waveform is computed, and a glitch power report file is generated based on the glitch power.
Systems and methods are presented for optical proximity correction (OPC)-based generation of test patterns. A method may include accessing an input test pattern and generating an intermediate OPC test pattern set for the input test pattern, which may include performing an OPC process on the input test pattern. The OPC process may include multiple iterations, the generated intermediate OPC test pattern set may include multiple intermediate OPC test patterns, and each given intermediate OPC test pattern in the intermediate OPC test pattern set may be an output of performance of a given iteration of the OPC process. The method may also include determining one or more selected intermediate OPC test patterns from the intermediate OPC test pattern set to include in a test mask to fabricate a test circuit and obtain measurement values through which to calibrate an OPC resist model.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G03F 1/44 - Aspects liés au test ou à la mesure, p. ex. motifs de grille, contrôleurs de focus, échelles en dents de scie ou échelles à encoches
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
39.
METHOD AND SYSTEM FOR ESTIMATING INTEGRATED CIRCUIT YIELD
A method, system, and apparatus for determining a yield estimate for an integrated circuit are provided. The method includes the acts of generating a set of vectors of scaled parameter values, simulating an output of the circuit to identify a subset of the set of vectors, identifying a set of points on boundaries of failure regions in the parameter space, generating a set of sample points for each failure region. and determining a yield estimate based on the sets of sample points
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
A method for determining a process deficiency relating to an antenna effect of a three-dimensional integrated circuit (3DIC) design is provided. The 3DIC design includes at least two electrically connected circuit components. A first circuit component of the circuit components includes at least one first sub-circuit. A second circuit component of the circuit components includes at least one interposer and/or at least one second sub-circuit. The respective sub-circuit includes one or more metal layers and at least one gate. The respective interposer includes at least one metal layer. The method includes providing the 3DIC design and determining at least one geometric property of at least one representative metal layer of the respective circuit component using the 3DIC design. The respective geometric property of the at least one representative metal layer is representative of the respective circuit component with respect to an antenna effect of the respective circuit component. The method includes determining a stacked arrangement of the representative metal layers representing the respective circuit components, determining a stacked antenna effect value of the stacked arrangement using the geometric properties of the representative metal layers, and outputting that the integrated circuit design has a process deficiency if the stacked antenna effect value exceeds a preconfigurable threshold
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/39 - Conception de circuits au niveau physique
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
41.
ELECTROSTATIC DISCHARGE CELL CHARACTERIZATION FOR ELECTROSTATIC DISCHARGE RULE CHECKING
This application discloses a computing system to identify a first portion of an electrostatic discharge path in a physical design layout describing an electronic device is within at least one electrostatic discharge cell of the electronic device, and to access a library including the at least one electrostatic discharge cells to identify a first resistance corresponding to the first portion of the electrostatic discharge cell. The computing system also can determine a second resistance of a second portion of the electrostatic discharge path, generate a path resistance for the electrostatic discharge path by aggregating the first resistance and the second resistance, and perform an electrostatic discharge design rule check using the path resistance of the electrostatic discharge path and electrostatic discharge design rules.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 119/06 - Analyse de puissance ou optimisation de puissance
42.
MACHINE LEARNING-BASED EVALUATION OF BUMP CONFIGURATIONS FOR CIRCUIT DESIGNS
Systems and methods are presented for machine learning (ML)-based evaluation of bump configurations. A method may include steps of accessing an input circuit design and evaluating a bump configuration of the input circuit design that specifies a link between a source bump and sink bumps in the input circuit design. Evaluating the bump configuration can include generating an evaluation matrix based on locations of the source bump and the sink bumps in the input circuit design, constructing an evaluation image from the evaluation matrix based on matrix values in the evaluation matrix, and generating an evaluation value for the evaluation image using an evaluation ML model trained to generate evaluation values for bump configurations in circuit designs. The method may also include adjusting the bump configuration between the source bump and the sink bumps in the input circuit design based on the evaluation value.
A method for testing a first circuit design on an FPGA system, the first circuit design being compartmentalized into a plurality of interacting sub-designs. The method comprises a step in which a first sub-design of the first circuit design is mapped onto a first FPGA unit. Furthermore, a second sub-design of the first circuit design is mapped onto a second FPGA unit. In another step, a status variable for the first and second sub-design of the first circuit design are generated. The status variables are configured to indicate a readiness status of the corresponding sub-design for testing. In yet another step of the disclosed method, the status-variables of the first and second sub-design of the first circuit design are connected to a first superordinate FPGA unit each through a separate data channel.
G01R 31/3185 - Reconfiguration pour les essais, p. ex. LSSD, découpage
G06F 30/331 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation avec accélération matérielle, p. ex. en utilisant les réseaux de portes programmables [FPGA] ou une émulation
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p. ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
44.
CREATING A LAYOUT OF AN ELECTRIC CIRCUIT INCLUDING ELECTRICAL COMPONENTS USING MODELLED INTERACTION FORCES BETWEEN THE COMPONENTS
The invention relates to a method for creating a layout of an electric circuit including electrical components, wherein the components include fixed components with a fixed position in the layout and flexible components with a selectable position in the layout. To facilitate creating the layout of the electric circuit, the following steps are suggested: · assigning a first plurality of electrically connected components to a first set, wherein the first set includes at least two fixed components and at least two flexible components; · determining the selectable position of the respective flexible component by determining an equilibrium in the distribution of the components of the first set when the components of the first set exert a modelled interaction force on each other; · determining the layout including the fixed components on the respective fixed position and the flexible components on the determined respective selectable position, and · outputting the determined layout.
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
H05K 3/00 - Appareils ou procédés pour la fabrication de circuits imprimés
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
G06F 17/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des fonctions spécifiques
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
H05K 7/00 - Détails de construction communs à différents types d'appareils électriques
45.
ADDITIVE GRID-BASED FEATURE SELECTIONS FOR TRAINING OF MACHINE LEARNING (ML) MODELS FOR ELECTORNIC DESIGN AUTOMATION (EDA) DESIGN FLOWS
Various systems and method are presented in support of additive grid-based feature selection for training of machine learning (ML) models for electronic design automation (EDA) design flows. The technical aspects presented herein may include determining candidate features for the ML model from an input dataset and scanning the candidate features for different data partition sizes to evaluate training of the ML model through various feature sets and data partitioning parameters. An additive feature grid may generated by adding dimensions through performance of dimension iterations. A selected feature set may be determined based on dimensions of the additive feature grid and used to train the ML model for the EDA design flow.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 30/333 - Conception en vue de la testabilité [DFT], p. ex. chaîne de balayage ou autotest intégré [BIST]
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
46.
MODEL FORM DETERMINATIONS FOR OPTICAL PROXIMITY CORRECITON (OPC) MODELS FOR ELECTRONIC DESIGN AUTOMATION (EDA) DESIGN FLOWS
A method may be performed by a computing system for model form determination for optical proximity correction (OPC) models. The method may include a step of determining a model form for an OPC model for an electronic design automation (EDA) design flow, including by accessing a generic kernel library comprised of a multiple kernels applicable to the OPC model and wherein the multiple kernels have varying kernel parameters, accessing a set of circuit locations and measured values for the circuit locations, performing a feature selection process for multiple kernels of the generic kernel library as applied to the circuit locations to determine selected kernels from the generic kernel library, and determining the model form based on the selected kernels. The method may also include a step of training the OPC model with the determined model form.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 30/333 - Conception en vue de la testabilité [DFT], p. ex. chaîne de balayage ou autotest intégré [BIST]
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
47.
MULTI-STAGE FEATURE SELECTION FOR TRAINING OF MACHINE LEARNING (ML) MODELS FOR ELECTRONIC DESIGN AUTOMATION (EDA) DESIGN FLOWS
A method may be performed by a computing system, including steps of accessing an input dataset for an electronic design automation (EDA) design flow and performing a multi-stage feature selection process for the input dataset to determine a feature set to train a machine learning (ML) model for the EDA design flow. Performing the multi-stage feature selection process may include performing a single feature ranking process on the input dataset to obtain a ranked list of the candidate features for the input dataset, performing a multi-feature selection process that sequentially considers the candidate features in an order specified by the ranked list, and determining the feature set to train the ML model for the EDA flow through the multi-feature selection process. The method may also include a step of training the ML model for the EDA design flow through the determined feature set.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 30/333 - Conception en vue de la testabilité [DFT], p. ex. chaîne de balayage ou autotest intégré [BIST]
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
48.
METHOD OF GENERATING A CONTROL SEQUENCE FOR A COMPUTER-AIDED MANUFACTURING FACILITY
A method of generating a control sequence for a computer-aided manufacturing facility includes: providing geometry specifications of previous parts for which previously computer-aided manufacturing-code has been produced; providing a new part geometry specification; generating graph-structured data suitable as input graph-structured data from the geometry specification of the previous parts; generating graph-structured data from the geometry specification of the new part; identifying geometrical features of the new part and the previous parts by performing a sub-graph search in the graph-structured data generated; for every geometrical feature of the new part, analyzing similarity to geometrical features of the previous part and assigning a similarity score for pairs of previous part features and new part features; selecting for each new part feature a previous part feature based on the similarity score; and extracting computer-aided manufacturing-code from the computer-aided manufacturing-codes of the previous parts corresponding to the previous part features selected.
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
B33Y 50/02 - Acquisition ou traitement de données pour la fabrication additive pour la commande ou la régulation de procédés de fabrication additive
G06F 30/00 - Conception assistée par ordinateur [CAO]
G06Q 10/06 - Ressources, gestion de tâches, des ressources humaines ou de projetsPlanification d’entreprise ou d’organisationModélisation d’entreprise ou d’organisation
G06Q 10/0875 - Énumération ou classification des pièces, des fournitures ou des services, p. ex. nomenclatures
B29C 64/129 - Procédés de fabrication additive n’utilisant que des matériaux liquides ou visqueux, p. ex. dépôt d’un cordon continu de matériau visqueux utilisant des couches de liquide à solidification sélective caractérisés par la source d'énergie à cet effet, p. ex. par irradiation globale combinée avec un masque
49.
AUTOMATED PLACEMENT OF COMPONENTS IN AN INTEGRATED CIRCUIT LAYOUT DESIGN USING ARTIFICIAL INTELLIGENCE
Methods for automatically creating a layout design for manufacture of an integrated circuit and corresponding systems and computer-readable mediums. A method includes receiving (402) layout requirements (314). The layout requirements (314) describe components and connections for an integrated circuit to be manufactured. The method includes receiving (404) an artificial intelligence (AI) model, where the AI model (306) has been trained on multiple known-good layout designs (320). The method includes creating (406) component groups (500) according to the layout requirements (314), using the AI model. The method includes placing (408) planning groups (602), corresponding to the component groups (500), into a layout design (312) using the AI model (306). The method includes placing (412) the components in each planning group (602) in the layout design (312), using the AI model (306). The method includes storing (418) the layout design (312).
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
50.
AUTOMATED ROUTING IN AN INTEGRATED CIRCUIT LAYOUT DESIGN USING ARTIFICIAL INTELLIGENCE
Methods for automated routing in an an integrated circuit layout design (322) using artificial intelligence (AI) and corresponding systems and computer-readable mediums. A method includes receiving (402) routing requirements (324), receiving (404) an unrouted layout design (322), and receiving (406) an AI model (306). The method includes creating (408) a routing strategy for the unrouted layout design (322) using the AI model (306) and the routing requirements (324). The method includes creating (410) a physical routing plan based on the routing strategy to produce a routed layout design (312). The method includes storing (412) the routed layout design, wherein a physical part can thereafter be manufactured (414) according to the routed layout design.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
A method may be performed by a computing system to control a semiconductor fabrication process for circuit designs, including by accessing an ensemble of machine-learning (ML) models for the semiconductor process. The ensemble of ML models may include a given forecast ML model configured to predict a wafer value and process parameters for a given step of the semiconductor fabrication process at a given future time point for a given circuit design. Controlling the semiconductor fabrication process may also include performing a control operation for the semiconductor fabrication process responsive to a determination that the predicted wafer value or the predicted process parameters for the given step of the semiconductor fabrication process at the given future time point fail to satisfy an acceptable threshold.
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
52.
PERSISTENT EXPERT AVATAR SYSTEM WITH SYNTHESIS OF MULTIPLE DOMAINS
Methods for providing persistent, continuous, and/or customized expert interactions with a user, the method performed by a computer system (100) implementing a dedicated expert avatar (DEA), and corresponding systems and computer-readable mediums. A method includes receiving (702) a prompt (330) from a user and receiving (704) user history (306) and user preferences (308) corresponding to the user. The method includes applying (706) the user history (306) and the user preferences (308) to the prompt (330) to produce a plurality of queries (334), where each of the plurality of queries (334) corresponds to a respective expert avatar (XAv) system (320). The method includes transmitting (708) the plurality of queries (334) to the corresponding XAv systems (320) and receiving (710) an avatar response (336) from each of the XAv systems (320). The method includes validating and customizing (712) the avatar responses (336) by applying the user history (306) and the user preferences (308) to the avatar responses (336) to produce a user-customized response (332), and transmitting (714) the user-customized response (332) to the user as a response to the prompt (330).
G06N 3/006 - Vie artificielle, c.-à-d. agencements informatiques simulant la vie fondés sur des formes de vie individuelles ou collectives simulées et virtuelles, p. ex. simulations sociales ou optimisation par essaims particulaires [PSO]
A hardware model of a circuit design in a reconfigurable hardware modeling device comprises a stall signal generation device configured to generate a stall signal based on detection of activities of one or more clock-related signals of the hardware model of the circuit design and state element models for some or all of state elements in the circuit design. The one or more clock-related signals comprise one or more clock signals, one or more enable signals, or any combination thereof. The one or more clock-related signals are associated with a design path in the hardware model of a circuit design, The stall signal, when activated, is used to suppress a next state updating for the state element models. The design path may be selected based at least in part on how long the design path is and how frequent the one or more clock-related signals become active.
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 30/331 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation avec accélération matérielle, p. ex. en utilisant les réseaux de portes programmables [FPGA] ou une émulation
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
A computer-implemented method for computing a surface of a multiple-layer object is disclosed. The method includes obtaining reference data describing a reference surface, obtaining layer data describing a respective thickness and a respective boundary of each layer of the multiple layers defined on the reference surface, and computing, for each layer of the multiple layers, based on the reference data and the layer data, a respective surface signed distance field. Each surface signed distance field describes, for each of its constituent field points, a distance of the respective field point to the boundary of the respective layer. The computer-implemented method includes computing, based on the reference data, the layer data, and the surface signed distance fields for the multiple layers, a spatial field that encloses a spatial region located between the reference surface and a region corresponding to a sum of the thicknesses of the multiple layers stacked on the reference surface. The spatial field describes, for each of its constituent field points, a distance of the respective field point to the reference surface and to the boundary of the respective layer. The computer-implemented method includes computing the surface based on the spatial field
A computer-implemented method for computing a surface of a multiple-layer object is disclosed. The method includes obtaining reference data describing a reference surface, obtaining layer data describing a respective thickness and a respective boundary of each layer of the multiple layers defined on the reference surface, and computing, based on the reference data and the layer data, a spatial field that encloses a spatial region located between the reference surface and a region corresponding to a sum of the thicknesses of the multiple layers stacked on the reference surface. The spatial field describes, for each of its constituent field points, a distance of the respective field point to the boundary of the respective layer and to the reference surface. The computing of the spatial field includes computing the spatial field to describe the field to a precision that is based on a distance to the boundary of the respective layer. The computer-implemented method includes computing the surface based on the spatial field.
A method for generating a mesh representation of a planar face in a computer-aided design (CAD) model is provided. One or more isolated clusters of vertices on a boundary of the planar face are identified. An initial mesh representation of the planar face is evaluated to identify a subset of facets that fail to meet a predefined condition. Different mesh refinement methods are used to refine the initial mesh representation in neighborhoods of facets in the subset. Selection of a mesh refinement method of the different mesh refinement methods depends, at least partly, on whether an edge of a facet of the subset of facets lies within an isolated cluster of the one or more isolated clusters
A computer-implemented method for generating a mesh representation of a closed surface is provided. An initial set of tetrahedra is obtained from a triangulation of a set of covering spheres that enclose the surface. An initial mesh representation of the surface is generated based on the set of tetrahedra and an implicit function definition of the surface. The initial mesh representation is evaluated, and facets are regenerated in regions of the initial mesh representation that fail to meet predefined tolerance conditions using a modified set of tetrahedra.
G06T 17/20 - Description filaire, p. ex. polygonalisation ou tessellation
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06T 17/10 - Description de volumes, p. ex. de cylindres, de cubes ou utilisant la GSC [géométrie solide constructive]
58.
METHOD AND SYSTEM FOR AUTOMATICALLY DETERMINING A STRUCTURE OF A BILL OF PROCESS
Systems and a method for determining a BOP structure. Input data on a workpackage and input data on a schema are received; wherein the workpackage comprises BOM data. The system provides access to a LLM module pre-trained with manufacturing data. The received input data is processed into a format comprising chunks of text understandable by the LLM module. The LLM module is fed with the processed input data to obtain, as output data, a set of determined BOP structures.
G05B 19/418 - Commande totale d'usine, c.-à-d. commande centralisée de plusieurs machines, p. ex. commande numérique directe ou distribuée [DNC], systèmes d'ateliers flexibles [FMS], systèmes de fabrication intégrés [IMS], productique [CIM]
G05B 13/02 - Systèmes de commande adaptatifs, c.-à-d. systèmes se réglant eux-mêmes automatiquement pour obtenir un rendement optimal suivant un critère prédéterminé électriques
G06Q 10/0631 - Planification, affectation, distribution ou ordonnancement de ressources d’entreprises ou d’organisations
A computer implemented method for filtering a spatial index is provided. When implemented in a rendering loop, the computer implemented method reduces a number of client server calls by removing item paths that are not visible in the configured product early in the rendering loop. The method includes identifying a subset of spatial bounding boxes that are visible from a given viewpoint of a scene displayed on a client device, communicating a request to a product management server to obtain model data for each of the spatial bounding boxes in the subset, receiving a message from the product management server in response to the request, and filtering the subset based on the message
A computer-implemented method in a manufacturing process to manufacture an object using at least one manufacturing machine is disclosed. The method comprises, obtaining model data representing the object, determining one or more features of the object represented by the model data by generating for each feature a respective feature descriptor in the form of a vector of numbers describing characteristics of the respective feature and performing a machine-learning model on each feature descriptor to classify the respective feature and determining the one or more features based on the classifications, determining machine operations to manufacture the determined features, and determining an order of performance of the determined machine operations to manufacture the determined features.
A system and method for managing queries pertaining to a product are provided. The method includes receiving, by a processing unit, a user query from a user device. Further, one or more contexts are identified from a plurality of contexts by comparing the user query with each context among the plurality of contexts. Each of the contexts includes values of one or more attributes characteristic to at least a part of the product. Further, a prompt is generated by updating the user query based on the one or more contexts identified. The prompt is provided as input to a Large Language Model to generate a natural language output, on an output device.
Embodiments of the present disclosure provide a method and apparatus for designing a cooling channel, an electronic device and a computer storage medium. The method includes: acquiring a product molding line contained in a mold; receiving cooling channel quantity information, the cooling channel quantity information representing a quantity of cooling channels; generating a target polygon in the mold for an enclosed area formed by the product molding line, the target polygon being located inside the enclosed area, or, the target polygon containing the enclosed area, the target polygon having the quantity of sides matching the quantity of the cooling channels; and determining positions of the cooling channels in the mold based on positions of sides of the target polygon, to generate the cooling channels based on the positions of the cooling channels in the mold. The solution provided by the embodiments of the present disclosure may improve a design efficiency and a cooling effect.
Methods for use in integrated circuit design and corresponding systems and computer- readable mediums. A method includes receiving (902) a mask pattern for a semiconductor layer. The method includes creating (904) edge grids (322, 324, 326, 328, 330) corresponding to the mask pattern and creating (906) proximity grids (1002) corresponding to the mask pattern. The method includes convolving (908) each edge grid (322, 324, 326, 328, 330) and each proximity grid (1002) with a corresponding kernel (700) and summing (910) the convolutions and a rastered mask grid to produce a final mask pattern. The method includes performing (912) a simulation of a manufacturing process using the final mask pattern.
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p. ex. correction par deuxième itération d'un motif de masque pour l'imagerie
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
64.
ANALOG SIMULATION OF CIRCUIT DESIGNS WITH TEMPORAL PARALLELISM AND TIME-VARIANT REDUCTION
A computing system (101) implementing a design verification system (300) to alter (401) a circuit design (301) describing an electronic system into a simplified representation of the circuit design (313), and also implement an analog simulator (340) to perform (402) a simulation of the simplified representation of the circuit design. The design verification system can identify (403) circuit activity (317) corresponding to the electronic system in different temporal windows during the simulation of the simplified representation of the circuit design, perform (404) a topological analysis of the circuit design based, at least in part, on the identified circuit activity in the different temporal windows. The design verification system can modify (405) the circuit design into a plurality of circuit design subsets corresponding to the different temporal windows based, at least in part, on the topological analysis.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
65.
DETERMINING PARASITIC ELEMENTS OF AN INTERCONNECT OF AN ELECTRONIC CIRCUIT LAYOUT
The invention relates to a method for determining parasitic elements of an interconnect of an electronic circuit layout. To facilitate determining the parasitic elements, the method includes determining an interconnect parasitic model from a plurality of interconnect parasitic models of the interconnect based on a comparison between at least one performance indicator associated with each one of the interconnect parasitic models, and determining the parasitic elements of the interconnect based on the determined interconnect parasitic model.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 30/333 - Conception en vue de la testabilité [DFT], p. ex. chaîne de balayage ou autotest intégré [BIST]
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
A circuit configured to monitor functional signals comprises a signal selection unit configured to select signals for monitoring from one or more signal sources and a signature generation unit configured to generate signatures for the selected signals. The signature generation unit comprises one or more multiple-input signature registers. Each of the one or more multiple-input signature registers being constructed based on an n-bit hybrid ring generator.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
67.
REGION-BASED FILTERING OF PARASITIC NETWORKS FOR CIRCUIT TEST SIMULATIONS
Systems and methods are presented for region-specific filtering of parasitic networks for circuit test simulations. A method may include performing a circuit test through a parasitic network extracted for a circuit design, including by defining a region of the circuit design based on test locations specified for the circuit test and performing a tile filtering to remove any tiles for the specific nets that do not intersect with the region. Performing the circuit test may also include, for remaining tiles after the tile filtering, performing a resistor-filtering to remove any parasitic resistors in the remaining tiles that do not intersect with the region, obtaining a filtered parasitic network by performing a network-filtering on the parasitic network to remove network portions that do correspond to remaining parasitic resistors in the remaining tiles after the resistor-filtering, and performing a simulation for the circuit test through the filtered parasitic network.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 115/12 - Cartes de circuits imprimés [PCB] ou modules multi-puces [MCM]
68.
PROPAGATION DETERMINATIONS OF UNKNOWN VALUES IN LOGIC SIMULATIONS OF DIGITAL CIRCUIT DESIGNS
Systems and methods are provided for propagation determinations of unknown values in logic simulations of digital circuit designs. A method may include accessing (402) a digital circuit design (210) and parsing (404) the digital circuit design (210) to detect state elements. The method may also include performing (406) a logic simulation on the digital circuit design (210) that includes tracking propagation of x-values in the digital circuit, wherein the x-values represent an unknown value for an output of a digital circuit design element. During the logic simulation, method steps can include tracking (408) the state elements of the digital circuit design (210) to determine when any output of the state elements is the x-value during the logic simulation and triggering (410) an x-propagation response when an x-propagation criterion is satisfied based on detected x-value outputs for the state elements of the digital circuit design (210).
Fault Partition Node Systems for Circuit Design, Test and Diagnosis Techniques for generating a fault partition node system (also referred to as asymmetric partition tree (APT)) for a circuit design (330). The fault partition node system comprise equivalent fault group information extracted from a huge amount of fault simulation data for the circuit design. The related equivalent fault group information allows the fault partition node system to shrink or expand under certain conditions. Based on the fault partition node system, diagnosis coverage values can be predicted for various constraints, which can be employed to make circuit designs diagnosis friendly (350). The fault partition node system can also comprise diagnose-care bit information. Dictionary-like diagnosis can be performed more efficiently using the fault partition node system (360).
A scan chain comprises two neighboring scan cells (K + 1) and K and a controllable inverting device inserted between a serial output of the scan cell (K + 1) and a serial input of the scan cell K. The selection of the scan cell K for the insertion of the controllable inverting device (diagnosis point insertion) is determined based on a diagnosis coverage analysis process. The scan cell K is configured to operate in one of a plurality of test-related modes based on a regular scan enable signal and a diagnosis mode signal. The plurality of test-related modes comprises a diagnosis capture mode in which the scan cell K is configured to capture the inverted version of a bit received at the data input of the controllable inverting device. The diagnosis mode signal may be provided by a storage device.
A fault partition node system is created for a circuit design based on fault simulation for each of a plurality of test patterns. Based on the fault partition node system, a diagnosis coverage contribution value for each of the plurality of test patterns is determined. Test patterns in the plurality of test patterns are then reordered based on the diagnosis coverage contribution value. The above operations of creating, determining, and reordering can be repeated. The fault partition node system can also be used for selective chain diagnosis for performance improvement.
Various aspects of the present disclosed technology relate to techniques for test pattern generation for diagnosis. A fault partition node system or a failing bit node system is created for a circuit design based on fault simulation for each of a plurality of test patterns. Based on the fault partition node system or the failing bit node system, a plurality of faults are updated by removing, from the plurality of faults, faults of which each becomes a fault in an equivalent fault group alone. One or more test patterns are then generated targeting some of equivalent faults in the updated plurality of faults to increase diagnosis coverage. The fault partition node system or the failing bit node system is expanded based on fault simulation for each of the one or more test patterns. The above operations of updating, generating, and expanding are repeated.
CREATING A LAYOUT OF A PRINTED CIRCUIT BOARD (PCB) INCLUDING ELECTRICAL COMPONENTS USING A MODEL FOR ASSIGNING THE ELECTRICAL COMPONENTS ONTO POSITIONS OF A PCB ARRAY
The invention relates to a method for creating a layout of a PCB including a plurality of electrically connected, electrical components. To facilitate creating the PCB layout, the method includes: providing an array of a board canvas of the PCB; providing a list of components and electrical connections of the components; providing feature information of the respective component and of the respective connection; providing a model incorporating the array, the list, and the feature information, where the model describes a sequence of consecutive actions of assigning one of the components of the list onto a respective position of the array; determining a respective probability distribution for assigning one of the components onto a respective position of the array using the model; composing the layout of the components on the array using the respective assigning action with the highest respective probability in the respective probability distribution; and outputting the composed layout.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
Techniques for generating a failing bit node system for a circuit design (330). The failing bit node system comprise equivalent fault group information extracted from a huge amount of fault simulation data for the circuit design. The related equivalent fault group information allows the failing bit node system to shrink or expand under certain conditions. Based on the failing bit node system, diagnosis coverage values are be predicted for various constraints, which can be employed to make circuit designs diagnosis friendly (350). The failing bit node system can be converted into a fault partition node system. Dictionary-like diagnosis are performed based on the failing bit node system (360).
Systems and methods are presented in support of cross-mask error enhancement factor (MEEF)-based optical proximity correction (OPC) for curvilinear masks. In some examples, a method may include the steps of accessing a curvilinear mask and a cross- MEEF matrix for the curvilinear mask. The curvilinear mask may be represented through a set of vertices and the cross-MEEF matrix may specify edge placement error (EPE) changes to the set of vertices of the curvilinear mask when a given vertex of the set of vertices of the curvilinear mask is moved by a distance unit. The method may also include a step of performing an OPC operation using the cross-MEEF matrix.
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p. ex. correction par deuxième itération d'un motif de masque pour l'imagerie
G03F 1/78 - Création des motifs d'un masque par imagerie par un faisceau de particules chargées [CPB charged particle beam], p. ex. création des motifs d'un masque par un faisceau d'électrons
G03F 1/86 - Inspection au moyen d'un faisceau de particules chargées [CPB charged particle beam]
A, preferably computer-implemented, method comprising the step of determining one or more latent defects in an integrated circuit based on a stress target, the integrated circuit comprising at least one instance of a library cell, preferably from a plurality of library cells, wherein the library cell comprises or is associated with the stress target, wherein the stress target of the library cell is indicative of one or more stress states of at least one transistor of the library cell.
The present invention discloses a method and a system for an automatic classification of the solder printer tooling in the preparation of a printed circuit board, the method comprising: - providing the printed circuit board and placing a stencil layer on the printed circuit board thereby covering the printed circuit board with a stencil layer; said stencil layer comprising a variety of openings that fit to positions of the printed circuit board where a solder past pad has to be deposited; - bringing the solder past onto the stencil layer and wiping the squeegee over the stencil layer wherein the squeegee is used to bring the solder past into the openings of the stencil layer by exposing a predetermined pressure to the solder past and the stencil layer in a direction substantially perpendicular to the plane of the printed circuit board; - positioning in alignment with the squeegee an array of distance sensors in proximity to the squeegee and measuring the distance between the distance sensors and the stencil layer while wiping with the squeegee over the stencil layer; and - evaluating the measured distances with respect to a predetermined threshold for the distance between the stencil layer and the distance sensors.
H05K 3/12 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché utilisant la technique de l'impression pour appliquer le matériau conducteur
A method for computer-based simulating a system (SYS) by co-simulation of subunits (SSY) of the system (SYS) includes (a) generating dedicated models (MDL) for the simulation of the subunits (SSY) using at least partially different simulation tools (SMT). The method also includes (b) exchanging simulation data (SMD) between the dedicated models (MDL) according to a communication format standard (FMI) during co-simulation in the form of a standard simulation communication (SSC). At least one dedicated model (MDL) is a foreign model (FMD), so it was generated using a non-preparing tool (NPT), which is a simulation tool (SMT) that does not prepare models for communication according to the communication format standard (FMI). The method also includes (c) representing the foreign model (FMD) using a substitution module (SBM) in the simulation data (SMD) exchange, (d) providing an interface service (IFS) to the non-preparing tool (NPT), which converts the standard simulation communication (SSC) into communication according to the non-preparing tool's (NPT) application programming interface (1), and vice versa, and (e) operating the foreign model (FMD) in an environment of the non-preparing tool (NPT) according to the converted communication input (CVC) received from the interface service (IFS) and (f) the foreign model (FMD) sending simulation data (SMD) via the conversion of the interface service (IFS) and via the substitution module into (FMU) the standard simulation communication (SSC).
G05B 17/02 - Systèmes impliquant l'usage de modèles ou de simulateurs desdits systèmes électriques
G05B 19/418 - Commande totale d'usine, c.-à-d. commande centralisée de plusieurs machines, p. ex. commande numérique directe ou distribuée [DNC], systèmes d'ateliers flexibles [FMS], systèmes de fabrication intégrés [IMS], productique [CIM]
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06G 7/66 - Calculateurs analogiques pour des procédés, des systèmes ou des dispositifs spécifiques, p. ex. simulateurs de systèmes de commande
79.
GENERATING AN AUTOMATIC BLEND BETWEEN TWO COMPONENTS IN A COMPUTER MODEL
A computer-implemented method for generating a computer model representation of an object includes obtaining a density grid representation of at least part of the object, generating a computer model representation based on the density grid, and determining a portion of the computer model representation. The computer-implemented method also includes interpolating values in the density grid, determining a portion of the interpolation of the density grid corresponding to the portion of the computer model representation, and modifying the computer model representation based on the portion of the interpolation of the density grid
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06T 17/20 - Description filaire, p. ex. polygonalisation ou tessellation
G06F 111/06 - Optimisation multi-objectif, p. ex. optimisation de Pareto utilisant le recuit simulé, les algorithmes de colonies de fourmis ou les algorithmes génétiques
G06F 119/18 - Analyse de fabricabilité ou optimisation de fabricabilité
80.
LIGHTWEIGHT STREAM CIPHER FOR HARDWARE ROOT OF TRUST
A circuit comprises a first device comprising a nonlinear feedback shift register, a second device comprising a nonlinear feedback shift register, a third device comprising a ring generator, selection-combination devices, and an encryption device. Each of the selection-combination devices is configured to output one of bits of a keystream which is derived from a combination of first one or more bits and second one or more bits. The first one or more bits are generated based on a first group of bits outputted from the first device and a third group of bits outputted from the third device. The second one or more bits are generated based on a second group of bits outputted from the second device and a fourth group of bits outputted from the third device. The encryption device is configured to combine bits for encryption with bits of the keystream to generate encrypted bits.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
H04L 9/12 - Dispositifs de chiffrement d'émission et de réception synchronisés ou initialisés d'une manière particulière
81.
METHOD AND SYSTEM FOR MODELLING AND MANUFACTURING COMPOSITE PARTS
A method for modelling a composite part is provided. The method includes accessing a model in a modelling system where the model includes a representation of a selected layer forming the composite part and the selected layer includes one or more plies of composite fabric material. The method includes simulating a manufacturing process for the selected layer based on the model. The method also includes, for each ply in the selected layer, evaluating simulation data from simulating the manufacturing process to quantitatively determine a deviation of the ply in the manufactured selected layer from the model, identifying a set of regions of the ply in the model, based on the deviation, and automatically modifying the model based on the identified set of regions, before manufacturing the composite part.
A computer-implemented method in a computer aided design (CAD) system is provided. The method includes accessing a first facetted model representing a shape element, connecting instances of the facetted model to obtain a second facetted model, applying a nonlinear transformation to the second facetted model to obtain a third facetted model, and determining a distortion of a pair of facets between the second facetted model and the third facetted model. A topology of the third facetted model is modified based on the distortion
A method for generating a mesh for a blended rod and ball lattice is provided. The method includes obtaining, from a first lattice, a second lattice by offsetting the first lattice by a predetermined distance. The method includes marking portions of rods in the second lattice with a first identifier or a second identifier based on intersections with other lattice topologies, marking balls in the second lattice with the first identifier or the second identifier or leaving the balls unmarked, and identifying regions of the first lattice corresponding to marked regions of the second lattice. The method includes applying a blend to the first lattice to obtain a third lattice and incarnating the third lattice as a mesh. Different mesh incarnation methods are applied in the marked regions, based on whether the regions are marked with the first identifier or the second identifier.
A method for modifying a model of a shape element in a computer-aided design (CAD) system. The method comprises accessing the model in the CAD system and generating an arrangement comprising a plurality of instances of the model. A set of modifications to the model are identified to enable the plurality of instances to connect seamlessly. The modifications are implemented on the model to obtain a modified model which can be used to form a patterned CAD object.
RR as a plurality of polylines based on a pre-determined threshold. The method includes generating a set of line segments, each line segment in the set of line segments extending radially from a surface of an unblended rod and ball lattice and terminating on a bounding sphere that contains the identified constraint curves. The method includes intersecting each line segment in the set of line segments with the blended lattice surface to obtain a set of points lying on the blended lattice surface and triangulating the set of points to obtain a mesh representation of a region of the hub.
A system and method for managing real-time multi-user collaboration in a file based CAX application is disclosed herein. The method comprises receiving, by a processing unit, a plurality of inputs indicative of a plurality of operations to be performed on one or more objects in a CAX file. Each of the inputs is received from one of a plurality of user sessions as-sociated with the file based CAX application, in real time. Further, a chronological sequence of execution of each of the operations is determined, based on an order of receipt of each of the inputs. based on the chronological sequence of execution determined, each of the operations is executed on the CAX file. Furthermore, an output is generated on each of the user sessions, based on execution of each of the operations on the CAX file in the chronological sequence.
A computer-implemented method for generating a finite element mesh of a component for the numerical solution of partial differential equations for the description of technical-physical circumstances to which the component is subjected in its intended operation. The invention further relates to a method for improving the components design and generating the component. Furthermore, the invention relates to a system for performing such method. Furthermore, the invention relates to a computer-readable medium encoded with executable instructions, that when executed, cause the computer system to carry out a method according to the invention.
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06F 17/13 - Opérations mathématiques complexes pour la résolution d'équations d'équations différentielles
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06T 19/00 - Transformation de modèles ou d'images tridimensionnels [3D] pour infographie
G06F 30/00 - Conception assistée par ordinateur [CAO]
A method and system for configuring a product is disclosed. The method comprises obtaining, by a processor (102) of the PDM system (100), a plurality of options and one or more constraints defined for the product from a product database (116), wherein each of the options has one or more variants. Further, ordered logical groups are generated from the plurality of options obtained, based on a weight associated with each of the options. Furthermore, a branch and bound algorithm is used to determine one or more buildable product configurations based on the ordered logical groups and one or more of the constraints applicable to the options, wherein applicability of the one or more constraints is determined using a Satisfiability Modulo Theory-based solver. The one or more buildable product configurations are further outputted on an output device (110).
Method of machining a workpiece (WPC) by means of a B-axis lathe machine (MCH), where the method, involves the continuous change of the angular position (AGP) of a turning tool (TTL), the method comprising the following steps: (a) Providing a workpiece (WPC) raw contour geometry (RCG), (b) Providing a. workpiece (WPC) target contour geometry (TCG), (c) Providing a predetermined chip thickness (CPT) as target chip thickness (CPT) during machining, (d) Providing a tool path (TPT) of the turning tool (TTL), (e) Providing preset angular positions (PAP) of the turning tool (TTL), characterized, by the method including the additional steps: (f) Providing a. feed, map (FMP) that provides a. feed. rate (FDR), (g) Splitting the tool path (TPT) segments (SGT) into tool path (TPT) subsegments (SSG) with a predefined, segment length (SGL), (n) Determining angular positions (AGP) at the segment (SGT) end positions (EPT) by interpolating (ITP) between the positions of specified tool angle (TAP), Determination of the feed rate (FDR) at the segment end. positions (SGT) by specifying the respective preset local angular positions (PAP) to the feed map (FMP), (j) Determining of a dynamic feed rate (DFR) and a. dynamic angular position change (DAP) from an interpolation (TTP) along the segment (SGT) tool path (TPT) between the respective segment (SGT) end position (EPT) parameters, and machining the workpiece (WPC) in such a way that the tool position is continuously changed between the preset angle positions, while the tool is moved along a tool path (TPT) according to a feed calculation based, on. the specified chip thickness (CPT).
G05B 19/416 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par la commande de vitesse, d'accélération ou de décélération
G05B 19/41 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par l'interpolation, p. ex. par le calcul de points intermédiaires entre les points extrêmes programmés pour définir le parcours à suivre et la vitesse du déplacement le long de ce parcours
90.
DETERMINING A SURFACE OF AN OBJECT IN A COMPUTER MODEL
A computer-implemented method for determining a surface of an object in a computer model of the object is disclosed. The method comprises: determining a position on a surface of the computer model of the object; determining a reference point that is intersected by an axis projecting from the surface near to the position on the surface; determining one or more portions of the surface near to the position on the surface or near to another of the one or more portions of the surface; determining whether an uninterrupted line-of-sight exists between the one or more portions and the reference point; and determining that the one or more portions constitute the surface in response to determining that the uninterrupted line-of-sight exists between the one or more portions and the reference point.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
A computer-implemented method for evaluating power dissipation of an electronic circuit design including at least one logic gate is disclosed. The method includes receiving one or more data files descriptive of the electronic circuit design, descriptive of waveform data descriptive of signal activity for logic gates used in the electronic circuit design, and descriptive of power dissipation values for internal cells of the logic gates of the electronic circuit design (701). Waveform data is extracted from the one or more data files descriptive of signal activity at primary inputs of the electronic circuit design and descriptive of outputs of registers and memories of the electronic circuit design (702). Simulation of the logic gates is performed using the extracted waveform data to generate simulated waveform data descriptive of simulated logic transitions for the internal cells of the logic gates (703), and event-based evaluation of the power dissipation of the electronic circuit design is performed based on the extracted waveform data, the simulated waveform data, and the power dissipation values (704).
A monitor device for monitoring a propagation delay of a signal along a path through an integrated circuit is disclosed. The monitor device comprises a delay device configured to receive the signal and generate a delayed signal being a version of the received signal that is time-delayed relative to the received signal, a detection window device configured to generate a detection window signal based on a clock signal of the integrated circuit, and a determination device configured to determine whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal, and to generate a determination signal based on the determination.
Systems and methods are presented for determination of layout-based systematic defect candidates based on design uniqueness and repeater overlap. A method may include accessing diagnosis reports (220) generated for physical circuits and identifying multiple repeater sets (230) from the diagnosis reports (220). The method may also include extracting layout patterns (250) from the diagnosis reports (220) and determining (608) a layout-based systematic defect candidate (510) from among the layout patterns (250) based on a design uniqueness factor and a repeater overlap factor. The design uniqueness factor may be based on a degree to which other layout patterns similar to a given layout pattern do not otherwise occur among layout patterns (320) for the circuit design (310). The repeater overlap factor may be based on a degree to which other layout patterns similar to the given layout pattern occur among layout patterns for other repeater sets of the multiple repeater sets (230).
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 119/02 - Analyse de fiabilité ou optimisation de fiabilitéAnalyse de défaillance, p. ex. performance dans le pire scénario, analyse du mode de défaillance et de ses effets [FMEA]
A computer-implemented method for determining placement of monitors for monitoring propagation delays in paths through an integrated circuit is disclosed. The method comprises: determining one or more paths through an integrated circuit which terminate at a same flip flop of the integrated circuit (706 a ii); determining logical cells in the one or more paths terminating at that flip flop (706 a ii); determining a measure of the number of those logical cells that are also in one or more alternative paths terminating at one or more alternative flip flops monitored by one or more monitors (706 a iii); determining whether the measure of the number of those logical cells that are also in the alternative paths satisfies a threshold condition (706 a iii); and determining, based on a determination that the number of logical cells that are also in the alternative paths does satisfy the threshold condition, placement of a monitor to monitor the flip flop.
A monitor device for monitoring a propagation delay of a signal along a path through an integrated circuit is disclosed. The monitor device comprises a delay device configured to receive the signal and generate a delayed signal being a version of the received signal that is time-delayed relative to the received signal, a detection window device configured to generate a detection window signal based on a clock signal of the integrated circuit, and a determination device configured to determine whether a value of the received signal is different to a value of the delayed signal during a time defined by the detection window signal, and to generate a determination signal based on the determination.
A, preferably computer-implemented, method of test case prioritization, the method comprising: obtaining a test case coverage for each one of a plurality of the test cases, wherein the test cases serve for testing an integrated circuit, e.g., in a hardware description language, preferably on the register transfer level, determining a priority of each test case based on the respective test case coverage, wherein the priority indicates an execution sequence of the test cases.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06N 3/00 - Agencements informatiques fondés sur des modèles biologiques
Systems and methods are presented for stepover-based generation toolpaths for additive manufacturing processes. A method may include automatically generating a toolpath (130) for a slice region (120) based on an allowable stepover range specified for an additive manufacturing process, including by determining a medial axis (210) of the slice region (120), partitioning the slice region (120) into multiple subsections (231, 232, 233, 234) based on the medial axis (210), modifying a given subsection responsive to a determination that a sub-toolpath for the given subsection would violate the allowable stepover rang, generating sub-toolpaths for each of the multiple subsections of the partitioned slice region, including any modified subsections, and generating the toolpath (130) for the slice region (120) as a combination of the sub-toolpaths generated for each of the multiple subsections of the partitioned slice region.
A computer-implemented method and system extract surface feature information from point cloud data. A 3D topology reconstruction engine receives point cloud data comprising one or more point cloud representations of an object and generates a curvature-based segmentation and region growing segmentation of the point cloud data. A feature removal module identifies and removes isolated clusters to correct over- segmentation.
G06T 7/187 - DécoupageDétection de bords impliquant des croissances de zonesDécoupageDétection de bords impliquant des fusions de zonesDécoupageDétection de bords impliquant un étiquetage de composantes connexes
99.
SELECTIVE REUSE IN ANALOG SIMULATION OF AN INTEGRATED CIRCUIT
A computing system can identify result data corresponding to a simulation of a first circuit design (301) utilizing a set of samples from a distribution describing manufacturing variation for integrated circuitry (302), determine a second circuit design describing an integrated circuit is compatible with the first circuit design based on a comparison of variables for manufacturing variation in the first circuit design to variables for manufacturing variation in the second circuit design (342), and reuse at least a portion of the result data when simulating the second circuit design utilizing values from the distribution describing the manufacturing variation identified based, at least in part, the result data corresponding to the simulation of the first circuit design. The computing system can estimate a yield for an output of the integrated circuit described by the second circuit design based on a response of the second circuit design to the simulation (306).
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
11,...,BM}, wherein the module A (110) is configured for operating in synchronicity with a clock signal CK_A (210) of period T and the module Bj (120) is configured for operating in synchronicity with a clock signal CK Bj of said period T, the method comprising: - adjusting or controlling, by a phase adjustment circuit, for each couple of modules formed by the module A (110) and one of said modules Bj (120) and in function of a total adjustment time TT_ Dj calculated for each couple, a relative time between an arrival time of signal S_Aj data at the sampling location of the sampling component of the module Bj (120) and a sampling time of said data by the sampling component of module Bj, wherein said sampling time is temporally directly adjacent to the arrival time; wherein said total adjustment time TT_Dj is configured for increasing, for both a sampling by a sampling component of module A (110) of data values of a signal S_Bj sent by the module Bj (120) to the module A and the sampling by the sampling component of module Bj (120) of data values of the signal S_Aj, a time separation between data arrival at a sampling location of the concerned sampling component and data sampling by said concerned sampling component, wherein the time at which said data sampling takes place is temporally directly adjacent to the time at which the data arrive at said sampling location of the concerned sampling component.
brevets
