A method for determining timing accuracy of one or more radio data packets includes: generating stimulus data, wherein the stimulus data includes the radio data packets and a reference time for transmission of the radio data packets over the air; storing the stimulus data on a test device; and replaying the stimulus data, by the test device, in order to determine the timing accuracy of the transmission of the one or more radio data packets by a device under test.
Methods for circuit design verification and corresponding systems and computer-readable mediums. A method includes receiving a plasma induced damage (PID) group defining a plurality of metal layers and having at least one risk connection comprising a plurality of risk links, and at least one corresponding protection connection comprising a plurality of protection links. The method includes identifying a lowest risk protection layer as a lowest of plurality of metal layers at which any of the risk links is established. The method includes determining whether a connection is established for all of the protection links at the lowest risk protection layer. The method includes, when it is determined that a connection is established for all of the protection links at the lowest risk protection layer, then returning a PASS result.
G06F 21/88 - Détection ou prévention de vol ou de perte
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
Methods for performing calculations on an integrated circuit (IC) layout design and corresponding systems and computer-readable mediums. A method includes receiving an IC layout design that includes a plurality of circuit elements. The method includes assigning a connection in a same IC net between at least two circuit elements of the plurality of circuit elements and assigning a property value to the at least two circuit elements based on the assigned connection. The method includes performing a calculation, such as a net area ratio calculation, on the IC layout design according to the assigned connections and the assigned property values.
Systems and methods are presented for improved determination of cell correspondences between circuit designs. A method may include steps of accessing a source circuit design and a layout circuit design, accessing previously-determined corresponding hierarchical cells between the source circuit design and the layout circuit design, and determining additional corresponding hierarchical cells between the source circuit design and the layout circuit design, including by constructing a class-correspondence graph for the source circuit design and the layout circuit design, determining components from the class-correspondence graph, constructing a component-containment graph for the components of the class-correspondence, topologically sorting the component-containment graph, processing the components in a top-down topological order to determine the additional corresponding hierarchical cells between the source circuit design and the layout circuit design.
G06F 30/3323 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p. ex. vérification de l’équivalence ou vérification des propriétés
5.
INTELLIGENT EJECT DIRECTION DETERMINATIONS FOR INJECTION MOLD DESIGNS
A computing system may include an eject direction determination engine configured to determine an eject direction for an injection mold design, including by determining a set of candidate eject directions for the injection mold design, including a bounding box candidate eject direction determined based on a minimum bounding box of an object representative of a product to be manufactured through the injection mold design and selecting the eject direction for the injection mold design from the set of candidate eject directions based on eject direction determination criteria. The computing system may also include an eject direction application engine configured to set the determined eject direction for the injection mold design so that physical mold pieces constructed from the injection mold design are configured to separate from one another in the determined eject direction during an injection mold production process to manufacture the product.
A computer-implemented method and system for interacting with a computer-aided design (CAD) model are described. A user selects one or more geometric entities in the CAD model. In response, the system identifies a first point associated with the one or more geometric entities and displays a repositionable graphical element in the user interface. In response to a second user input, the graphical element is displayed at a second point different from the first point, and the system dynamically displays a graphical representation of a relative position of the first point in relation to the second point in a predefined coordinate system.
A computing system may include an image access engine configured to access a panoramic point cloud image of a physical environment. The computing system may also include an environment location-aware text engine configured to transform the panoramic point cloud image into an alternate representation that reduces distortion in the panoramic point cloud image and perform an optical character recognition (OCR) process on the alternate representation to determine text in the panoramic point cloud image. The environment location-aware text engine may further be configured to construct text labels to track the text determined in the panoramic point cloud image and support text searches for the physical environment through the text labels.
For an improved management of machining information, esp. for a facilitated determination of step features from a sample machining process, a computer-implemented method is suggested comprising: providing a sample machining process for machining a sample workpiece from a sample blank, the sample machining process comprising at least two consecutive sample machining steps performed by the respective tool starting with a respective sample start part and ending with a respective sample end part, wherein the respective sample end part of the respective sample machining step is the respective sample start part of the respective subsequent sample machining step; determining a respective step tool volume corresponding to a movement of the respective tool during the respective sample machining step; determining a respective step volume corresponding to the respective sample start part of the respective sample machining step changed by the respective step tool volume; determining at least one respective step feature corresponding to the respective step volume; and storing the respective step feature in a machining information database.
A memory-testing circuit in a circuit comprises: a test controller; a memory data source selection device configured to select input data for a write port of the memory from test data outputted from the test controller and data from an output of the memory; and a memory address source selection device configured to select an address for an address port of the memory from an address outputted from the test controller and one of one or more preset addresses of the memory. The one or more preset addresses correspond to one or more preserved locations of the memory configured to temporarily store data for one or more locations of the memory to be tested.
A computer-implemented method of modelling engineering design components in a Computer-Aided Design (CAD) system is disclosed, wherein an engineering design component includes a feature having at least three occurrences of a shape element arranged in a regular pattern. The method is split into three stages: definition of a core set of behavioral characteristics; definition of an optional set of behavioral characteristics; and a hierarchical implementation of the optional characteristics by solving optional constraints after constraints corresponding to the core behavioral characteristics have been solved.
A computer-implemented method includes editing, at a local client device, an engineering design (e.g., computer aided design (CAD) model), hosted on a remote server. The local client device and the remote server communicate over a communications network and are remote from each other. The remote server configures an operation within a CAD model based on user input during an edit of the CAD model involving a drag. This results in a subset of the CAD model and the solving instructions required to perform the user update being generated and sent as a data package including the subset of the CAD model and the solving instructions to the local client device. The CAD model and any associated algorithms stored on the remote server are not communicated to the local client device.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
G06F 111/02 - CAO dans un environnement de réseau, p. ex. CAO coopérative ou simulation distribuée
This application discloses a computing system implementing a reliability verification tool to identify a portion of a layout design describing an integrated circuit includes a victim transistor having a gate connected to an aggressor transistor. The reliability verification tool can extract a resistance network for connections between the victim transistor and the aggressor transistor, and simulate the resistive network to determine connectivity between the wells of the victim transistor and the aggressor transistor occurs prior to the victim transistor having a gate connected to an aggressor transistor.
G06F 21/71 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 119/10 - Analyse du bruit ou optimisation du bruit
13.
MEMORY BUILT-IN SELF-TEST WITH ADDRESS SKIPPING TRIM SEARCH
An address-skipping trim search performed by a memory built-in self-test system comprises: perform memory read operations on one memory bank to determine whether it fails to correctly sense values of stored data based on a reference trim value for a previous memory bank; if the present memory bank fails, perform memory read operations to search for a new reference trim value for the present memory bank; or otherwise, treat the present reference trim value as the one for the present memory bank and proceed to testing a next memory bank. The range for searching for the new reference trim value can be limited by the present reference trim value.
A computing system can obtain wafer images of integrated circuitry having physical structures and classify each of the wafer images based on image characteristics of the wafer images. The computing system can partition each of the wafer images into a plurality of blocks, analyze each of the blocks to determine which of the blocks correspond to a background portion or a contour portion of the wafer images, assign an image score to each wafer image based on the analysis of each of the blocks, and classify the wafer images based on the image scores assigned to the wafer images. The computing system can set parameters for contour extraction using at least one of the wafer images selected from each of the classifications of the wafer images, and extract contours corresponding to the physical structures of the integrated circuitry from the wafer images based, at least in part, on the parameters.
G06T 7/194 - DécoupageDétection de bords impliquant une segmentation premier plan-arrière-plan
G06V 10/46 - Descripteurs pour la forme, descripteurs liés au contour ou aux points, p. ex. transformation de caractéristiques visuelles invariante à l’échelle [SIFT] ou sacs de mots [BoW]Caractéristiques régionales saillantes
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
15.
ADAPTIVE TARGET CONTROL FOR CURVILINEAR OPTICAL PROXIMITY CORRECTION (OPC)
Aspects of the disclosed technology relate to techniques for achieving optical proximity correction. Anchor points in a layout design may be designated as more important or less important. Optical proximity correction iterations are performed on each of the plurality of regions to generate a modified layout design by processing the more important anchor points differently than the less important anchor points, such as by different weighting or by dynamically changing the target for the less important anchor points. In this way, the edge placement error may be reduced or eliminated for the more important anchor points.
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
A computing system may include a voxel access engine configured to access voxel data and a voxel processing engine. The voxel processing engine may identify and label thin features in the voxel data, smooth the voxel data to preserve the thin features, and convert the voxel data to form a faceted representation. The voxel processing engine may also adaptively perform a pressing process on the faceted representation. Responsive to a determination that a pressing reapplication criterion is satisfied, the voxel processing engine may modify the voxel data, convert the modified voxel data to form the faceted representation of the object, and perform the pressing process on the faceted representation of the object formed through the modified voxel data.
A circuit comprises: a plurality of identical circuit blocks, each of the plurality of identical circuit blocks comprising one or more test output ports; a first bit-combining device and a second bit-combining device for each of the one or more test output ports; a delay device for each of the one or more test output ports; and a network coupled to each of the plurality of identical circuit blocks and configured to transport a first bit stream and a second bit stream during a test, wherein the first bit-combining device and the second bit-combining device are configured to combine bits outputted from the each of the one or more test output ports with bits of the first bit stream and bits of the second bit stream that are delayed by the delay device, respectively.
A computer-implemented method of enabling a user to select at least one component from a group including identical and/or non-identical components forming part of a computer-aided design (CAD) model is provided. The method includes: a) receiving a seed component selection from a user via a user input device, where the seed component represents component criteria desired by the user; and b) based on the seed component, generating a selection including at least one component sharing common shape elements with the seed component. The HDBSCAN algorithm is used to cluster together components within a CAD application. The clustered components are then displayed to a user based on the seed component. This enables a user to select similar components quickly and simply.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
19.
DETERMINING AN ASSEMBLING RISK FOR AN ELECTRONIC COMPONENT TO BE MOUNTED TO A PRINTED CIRCUIT BOARD
A method and a system for determining an assembling risk for an electronic component to be mounted to a printed circuit board. The method includes the following steps: providing a component library with a number of electronic components and its specific component identifier; wherein the component identifier includes an identifier string of letters and numbers providing information on a number of physical attributes of the electronic component; providing an evaluation scheme for each of the number of physical attributes; selecting an electronic component from the component library and evaluating each of the physical attributes; determining for each of the physical attributes the intermediate risk value and calculating from the intermediate risk values a final risk score; and determining the assembling risk associated with the final risk score by comparing the final risk score with a pre-defined risk scale.
H05K 13/08 - Contrôle de la fabrication des ensembles
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 111/20 - CAO de configuration, p. ex. conception par assemblage ou positionnement de modules sélectionnés à partir de bibliothèques de modules préconçus
G06F 115/12 - Cartes de circuits imprimés [PCB] ou modules multi-puces [MCM]
20.
REALISTIC TEST CIRCUIT GENERATION THROUGH RANDOM CIRCUIT LAYER BLOCKS
A method may support realistic test circuit generation through random circuit layer blocks. The method may include accessing a set of circuit layer blocks, performing a block-level design rule check (DRC) process on the set of circuit layer blocks, wherein the block-level DRC process applies selected design rules that are a subset of a design rule set for a circuit manufacturing process, and obtaining a set of clean circuit layer blocks by discarding circuit layer blocks in the accessed set of circuit layer blocks that fail the block-level DRC process and keeping circuit layer blocks in the accessed set of circuit layer blocks that pass the block-level DRC process. The method may also include generating a test circuit layer formed through randomly selected circuit blocks from the set of clean circuit layer blocks and utilizing the test circuit layer in support of testing the circuit manufacturing process.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
21.
AUTOMATED CELL BLACK BOXING FOR LAYOUT VERSUS SCHEMATIC
Text containers comprising information of cell ports are determined based on statements for cell ports in a rule file. Drawn layers comprising cell ports are determined based on the determined text containers or based on statements for attaching each of the test containers to a layout design layer in the rule file. Layout design layers connected to the drawn layers comprising cell ports are determined based on statements for connecting layout design layers in the rule file. A file for cell port detection is generated which associates each of the text containers comprising information of cell ports with one or more of the drawn layers comprising cell ports and one or more of the layout design layers connected to the one or more of the drawn layers comprising cell ports. The file for cell port detection can be used for extracting ports for cells to be black boxed.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
22.
MULTI-LEVEL PREDICTIONS IN WORKFLOW LOGIC OF COMPUTER-AIDED DESIGN (CAD) APPLICATIONS
A computing system may include a logic construction engine configured to construct, via multi-level prediction, workflow logic to process a computer-aided design (CAD) model. The logic construction engine may do so by identifying a multi-node sequence inserted into the workflow logic, aggregating past workflow data specific to the multi-node sequence, determining a node prediction in the workflow logic for the multi-node sequence based on the aggregated past workflow data, and providing the node prediction as a suggested insertion for the workflow logic.
A computer-implemented method is provided for rendering, to a designer, a two-dimensional image of an assembly of part instances in a three-dimensional assembly space within a computer-aided design (CAD) system utilizing double precision to describe part assemblies. Such assemblies are considered to be distant from a nominal observer. A viewport on a two-dimensional image plane is defined, and a combined transform is defined in quadruple precision to enable the generation of clipping lines and/or clipping points. The clipping lines and clipping points clipping the faces and edges of the part instance in the assembly to the portion of the assembly that lies within the viewport.
A computing system may include a computer-aided design (CAD) face access engine configured to access a CAD object and an imprint-based meshing engine configured to define an imprint region for a face of the CAD object and determine that the imprint region meets constraint criteria. Responsive to a determination that the imprint region meets the constraint criteria, the imprint-based meshing engine may modify the imprint region into an adapted imprint region and generate an output mesh using the adapted imprint region.
A computer-implemented method of providing a view of a filtered hierarchical data structure is described. A user views an initial view of a hierarchical data structure showing at least one branch value at an nth level expansion and provides a filter. A pre-constructed query index corresponding to the filter is queried against the hierarchical data structure to identify unconfigured paths to descendant values of a first child of nth level branch value. The descendant value and branch values between the descendant value and the branch value shown in the nth level expansion are marked as displayable when the filter is met. The process is repeated for all other branch values shown in the initial view. A revised view showing only those values from the initial view in which the branch value, a child value, or a descendant value were marked as displayable is then displayed to the user.
Layout features in a layout design are classified into groups of layout features. A machine learning-based SRAF generation process is then performed to generate sub-resolution assist features for layout features in each of the groups of layout features. Each of the groups of layout features has a specific machine learning model. The machine learning-based SRAF generation process comprising: dividing regions where sub-resolution assist features are likely to be placed into areas of interest, extracting a feature vector for each of the areas of interest based on a layout area centered at the each of the areas of interest, determining whether the each of the areas of interest should be part of a sub-resolution assist feature by using the feature vector as an input of the specific machine learning model, and generating the sub-resolution assist features based on results of the determining.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
27.
SYSTEM AND METHOD FOR MANAGING UPDATING OF ARTIFACTS ASSOCIATED WITH AN APPLICATION
A system and method for updating of artifacts in a live production environment of an application are provided. The system includes a database server, and an application server wherein the application is hosted, configured to provide a code editor interface, on a user device for enabling a user to update at least one artifact definition associated with at least one artifact associated with the application, wherein the updated artifact definition is stored on the database server. The application server retrieves the updated artifact definition from the database server upon being notified of the user updates to the artifact definition, by the user device. The application server furthers renders an updated artifact based on the updated artifact definition within the live production environment of the application in real-time, on the user device.
A computer implemented method for providing a recommender system for a design process of a complex system is provided, wherein the recommender system is shared by a plurality of users, wherein the complex system includes a plurality of connectable components and is designed in a design process by a sequence of design steps wherein in each design step a partial design is created until a completed design is obtained, wherein a partial design of one step and a partial design of a subsequent step differ in a design difference reflecting a difference in at least one element including a component or/and connection of the components, and wherein the shared recommender system provides at each design step a prediction of the subsequent design difference.
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
G06F 111/20 - CAO de configuration, p. ex. conception par assemblage ou positionnement de modules sélectionnés à partir de bibliothèques de modules préconçus
29.
CIRCUIT DESIGN AND MANUFACTURING HOTSPOT ROOT CAUSE EXTRACTION
Various aspects of the present disclosed technology relate to techniques for hotspot root cause determination. Feature values for a plurality of design/process-related features for each of the layout regions of interest on a layout design are determined. Population ratios for feature value ranges for each of the plurality of design/process-related features are determined based on a number of layout regions of interest having feature values within each of the feature value ranges. Hotspot feature repeater values are determined. Based on the population ratios and the hotspot feature repeater values, a root cause analysis can be performed to determine one or more design/process-related features that are most likely causes for each of a plurality of hotspot layout regions. The information of the one or more design/process-related features can be used to identity other hotspot regions and adjust the layout design or to adjust a manufacturing process.
A method of verifying integrity of data from a device under test includes obtaining network data from the device under test, wherein the network data is generated by the device under test based on a test data from a source device by transforming the test data from a first domain to a second domain and framing the transformed test data in a first protocol. The method further includes: deframing the received network data from the first protocol to a second protocol for extracting the transformed test data; obtaining the test data from the source device for verifying the transformed test data; and verifying the integrity of the transformed test data based on the test data using a block error rate or a bit error rate.
A computing system to parse a schematic design illustrating a circuit design for an electronic system to identify text and enclosures representing circuit devices of the electronic system, The computing system can classify the text based on a proximity of the text to the enclosures in the schematic diagram, and match the text to the enclosures in the schematic diagram based on the classifications, which correlates the circuit devices represented by the enclosures to the text matched to the enclosures. The computing system can identify one of the circuit devices includes a connector having one or more pins, and correlate the text matched to the enclosure to at least one of the pins based on a relative alignment of the pins with the text. The computing system can generate an interactive technical file that includes the correlations of the circuit devices and pins to the text matched to the enclosures.
This application discloses a computing system (400) to generate a product model (409) that describes attributes of a product including an electronic system (401). The computing system (400) can implement a machine-learning algorithm having been trained with metadata populated in previously generated product models for different electronic systems, which can determine one or more sets of metadata capable of being correlated to the electronic system included in the product model based on the attributes of the electronic system described in the product model. The sets of metadata can correspond to different design constraints in the product model associated with electrical connectivity for the electronic system and their corresponding parameter values. The computing system can populate at least one of the sets of metadata into the product model to correlate with the electronic system.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
A method of generating a simulated multipath fading channel data includes obtaining IQ sample data and selecting one or more radio samples from the IQ sample data for appending to the IQ sample data. The method also includes generating additional IQ sample data by appending the selected one or more radio samples prior to a start radio sample of the IQ sample data, and generating the simulated multipath fading channel using the additional IQ sample data, a predefined set of propagation delay, and attenuation coefficients associated with a channel model.
A method of monitoring messages from a sensor using an integrated circuit is provided, wherein the messages include data measured by that sensor. The method includes reading a first message from interconnect circuitry of the integrated circuit, the interconnect circuitry connecting the sensor to one or more core devices configured to process the message. The method further includes calculating a first hash value for the first message and comparing the first hash value to one or more prior hash values stored in a hash store, wherein each prior hash value corresponds to a message that was read from the interconnect circuitry prior to the first message. The method further includes performing a corrective action when the difference between the first hash value and at least one of the prior hash values stored in the hash store is above a predetermined threshold.
A computing system may include a quantifier determination engine configured to determine a defectivity quantifier for a lithographical circuit fabrication process performed with a target value for a process parameter, including by modifying the target value to obtain an off-target value for the process parameter, determining a defectivity quantifier for the lithographical circuit fabrication process performed with the off-target value, and extrapolating the defectivity quantifier for the lithographical circuit fabrication process performed with the target value from the determined defectivity quantifier for the lithographical circuit fabrication process performed with the off-target value. The computing system may also include a quantifier provision engine configured to provide the determined defectivity quantifier for assessment of the lithographical circuit fabrication process.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
A circuit comprises: scan chains comprising scan cells, the scan chains configured to shift in test patterns, apply the test patterns to the circuit, capture test responses of the circuit, and shift out the test responses; a decompressor configured to decompress compressed test patterns into the test patterns; and a test response compactor configured to compact the test responses, the test response compactor comprising: first X-masking circuitry configured to mask, based on first masking information, some of X bits in the test responses, the first masking information remaining the same while a test response for each of the test patterns is being shifted out, the first masking information being different for at least two of the test patterns; and second masking circuitry configured to mask, based on second masking information, rest of the X bits in the test responses.
A computing system implementing a design characterization tool can sample a distribution of values for manufacturing variation of an integrated circuit described by a circuit design. The design characterization tool can order the samples based on predicted output values of the circuit design set with characteristics in the samples of the values for manufacturing variation. The computing system can implement an analog simulator to simulate the circuit design utilizing a subset of the samples of values for manufacturing variation to identify simulated output values for an output distribution model. The design characterization tool can estimate an error in the order of the samples associated with the predicted outputs of the circuit design based on the simulated output values in the output distribution model. The design characterization tool can modify the output distribution model to correct a bias based on the estimated error in the order of the samples.
A preliminary netlist comprising the photonic devices and location and rotation information for each of the photonic devices is extracted from the original layout design. In the extraction, each of the photonic devices is treated as a black box. A geometric pattern for the each of the photonic devices is then identified in a group of geometric patterns for each of the photonic devices based on physical properties of the each of the photonic devices specified in the circuit design. A new layout design is generated based on the identified geometric pattern for each of the photonic devices, the location and rotation information for each of the photonic devices, and the preliminary netlist. Geometric elements in each of the photonic devices in the new layout design are compared with corresponding geometric elements in the original layout design.
G06F 30/327 - Synthèse logiqueSynthèse de comportement, p. ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
40.
DISTRIBUTED HANDLING OF FORWARD ERROR CORRECTION IN HARDWARE ASSISTED VERIFICATION PLATFORMS
This application discloses distributed forward error correction in hardware assisted verification platforms (300) including a hardware-assisted verification system (320) to emulate an electronic system (322) described by a circuit design (301). The hardware-assisted verification system (320) can implement forward error correction circuitry (324) to analyse a data packet (311) for use by the emulated electronic system (322) during functional verification operations of the circuit design (301), which can identify that the data packet includes one or more corrupted bits (321). The forward error correction circuitry (324) can transmit the corrupted data packet (321) to a computing system (330) implementing an error correction algorithm configured to perform error correction operations (332) on the corrupted data packet (321). The computing system implementing the error correction algorithm (330) can generate a corrected data packet (331) during the error correction operations and transmit the corrected data packet to the hardware-assisted verification system (320) for use by the emulated electronic system (322) during functional verification operations of the circuit design (301).
A computer-implemented method of handling large transforms in a computer-aided design (CAD) solid model utilizing double precision to describe a physical assembly of parts is described. If the unit size of a transform of interest exceeds a pre-determined threshold, the double precision of the transform is converted to quadruple precision whilst maintaining the double precision of the assembly. The results of any operation are output in double precision. A computer program and method of adapting an existing CAD model are also described.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
42.
METHOD OF MODIFYING A SPACE-FILLING LATTICE USING A BOUNDARY-REPRESENTATION MODEL
A computer-implemented method of determining the dimensions of a space-filling lattice in a solid model is disclosed, wherein information including a lattice, a set of faces, and data indicating a spatial relationship between the lattice and each face in the set is received. A set of points indicating the intersection positions where each rod intersects a face is identified, and each intersecting rod is classified based upon whether or not each subset of mutually tolerantly coincident points within the set indicates that a rod is divided by a face. If a rod is divided, the lattice is modified by adding a new ball where the rod is divided and classifying the new rods either side of it. These classifications are spread to adjacent rods without crossing any new ball to establish the complete set of surviving rods. Each connected set of surviving rods is used to instantiate a new lattice.
A method of measuring the junction temperature, Tj, of a semiconductor switching element in real-time, and a device for carrying out such a measurement are described. A plurality of measurements of a first and a second, different, temperature-sensitive parameter (TSP) of the semiconductor switching element while recording other quantities determining the semiconductor switching element operating point is taken. The junction temperature value based on the measured values of the first temperature-sensitive parameter and the at least one second temperature-sensitive parameter are calculated and compared to determine the actual junction temperature Tj. Each of the plurality of measurements of the first temperature-sensitive parameter and the at least one second temperature-sensitive parameter is synchronized with a switching event of the semiconductor switching element.
G01K 7/01 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments semi-conducteurs à jonctions PN
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A computing system may include a linear mesh access engine configured to access a linear mesh and a target geometry as well as curved mesh generation engine configured to construct a curved mesh. Construction of the curved mesh may include projecting the linear mesh on to the target geometry to form a projected mesh, determining deformation patches included in the projected mesh, selecting a cost function to apply to the deformation patches from a set of available cost functions, iteratively adapting the deformation patches based on the selected cost function to obtain adjusted mesh elements, and forming the curved mesh as a combination of the adjusted mesh elements and portions of the projected mesh not determined as part of the deformation patches.
G06T 19/20 - Édition d'images tridimensionnelles [3D], p. ex. modification de formes ou de couleurs, alignement d'objets ou positionnements de parties
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
A computer-implemented method of bounding spatial data in a hierarchical product structure with hierarchical transforms is described. Initially, the part or part assembly at the lowest level of a hierarchical assembly path is selected. Then, a hierarchical merge of the spatial bounds of one or more bounding boxes of the part or part assembly is performed to generate a set of intermediate spatial bounds. Following this, a merge of the set of oriented bounds of the one or more bounding boxes of the part or part assembly is performed to generate a reduced set of oriented bounds. Finally, the intermediate bounds and the reduced set of oriented bounds are stored for use in configuring the assembly path when building a product from the hierarchical product structure.
A computing system may include a computer-aided design face access engine configured to access a CAD object and an imprint-based meshing engine configured to define an imprint region for a face of the CAD object and decompose the face into virtual faces, including an imprinted virtual face and a remainder virtual face. The imprint-based meshing engine may also be configured to mesh the imprinted virtual face, mesh the remainder virtual face, and merge the imprint region mesh and the remainder region mesh together to form an output mesh, including by extending a portion of the imprint region mesh into the remainder portion of the face or extending a portion of the remainder region mesh into the imprint region.
G06F 30/23 - Optimisation, vérification ou simulation de l’objet conçu utilisant les méthodes des éléments finis [MEF] ou les méthodes à différences finies [MDF]
G06T 17/20 - Description filaire, p. ex. polygonalisation ou tessellation
47.
Construction of conformal cooling channels for injection mold designs
A computing system may include a design access engine configured to access an injection mold design and a channel construction engine configured to construct conformal cooling channels for the injection mold design. The channel construction engine may do so by extracting a cooling surface of the injection mold design, generating a central offset surface with a same shape as the cooling surface, projecting cooling lines on to the central offset surface, detecting sharp portions of the projected cooling lines, smoothing the detected sharp portions of the projected cooling lines, and generating the conformal cooling channels using the smoothed cooling lines along the central offset surface as a center line for the conformal cooling channels.
G06F 30/13 - Conception architecturale, p. ex. conception architecturale assistée par ordinateur [CAAO] relative à la conception de bâtiments, de ponts, de paysages, d’usines ou de routes
B29C 33/38 - Moules ou noyauxLeurs détails ou accessoires caractérisés par la matière ou le procédé de fabrication
B29C 45/73 - Chauffage ou refroidissement du moule
B29C 64/386 - Acquisition ou traitement de données pour la fabrication additive
B33Y 50/00 - Acquisition ou traitement de données pour la fabrication additive
B33Y 80/00 - Produits obtenus par fabrication additive
48.
SPATIAL DECOMPOSITION-BASED INFILLS OF UNIT CELL DESIGNS FOR COMPUTER-AIDED DESIGN (CAD) OBJECTS
A computing system may include a decomposition engine configured to access a unit cell design and a fill region of a computer-aided design object to infill with instances of the unit cell design and spatially decompose the fill region into power-of-two boxes. The power-of-two boxes may have dimensions equal to dimensions of the unit cell design multiplied by a power of two. The computing system may also include an infill engine configured to infill the fill region by performing a joining operation of aggregated bodies based on the spatial decomposition of the fill region. Each given aggregated body may comprise a number of unit cell designs equal to a power of two that are joined together to form the given aggregated body.
A modeling method for a tubular structure includes: acquiring a structural wire-frame; generating, at each non-manifold node of non-manifold nodes of the structural wire-frame, a polyhedral structure formed by faces of a polyhedron; generating, at each manifold node of manifold nodes of the structural wire-frame, a connecting face; generating, at each end node of end nodes of the structural wire-frame, an end face; connecting vertices of the connecting wire-frame, vertices of the connecting face, and vertices of the end face; and carrying out curved-surface subdivision.
Embodiments of the present disclosure provide a method and system for digital plant system model creation and simulation and a storage medium. The method includes: receiving a digital model created by a user based on a modeling library: in the modeling library, a digital plant system is divided into multiple subsystems, and motion joints in each subsystem are set with at least one option of at least one solution parameter of dynamics, kinematics and articulation; for each motion joint in the digital model, associating a corresponding algorithm engine in a simulation engine with the motion joint according to a solution parameter of the motion joint: the simulation engine comprises a kinematics algorithm engine, a dynamics algorithm engine and an articulation algorithm engine: using the corresponding algorithm engine to solve the motion joint associated with the algorithm engine. The technical scheme in embodiments of the present disclosure can improve the performance, stability and accuracy of the virtual digital plant.
A computing system may include a transition generation engine configured to access a computer-aided design (CAD) object comprising an external surface and an internal lattice structure represented through repeating unit cells of a lattice design, the internal lattice structure represented as a signed distance field (SDF). The transition generation engine may generate a transition structure for the CAD object within a transition distance from the external surface, including by applying a secondary SDF to modify a portion of the internal lattice structure within the transition distance from the external surface. The computing system may also include an object processing engine may be configured to process the CAD object comprising the transition structure (230) in support of physical manufacture of the CAD object.
A method may include the steps of accessing an input data set of hotspot locations on manufactured circuits of a circuit design. The hotspot locations may be confirmed through a high precision imaging process from a set of candidate locations of the circuit design determined by a low precision imaging process. The method may further include correlating the hotspot locations to layout data for the circuit design, extracting fragment feature vectors for the hotspot locations from optical proximity correction (OPC) fragments of the layout data, processing the fragment feature vectors, providing the processed fragment feature vectors as a training set for training a machine-learning model, and applying the machine-learning model to down select a different set of candidate locations determined by the low precision imaging process.
A computing system may include a database system and an application server. The application server may include a logic packaging engine configured to identify a product at a particular stage of a manufacturing process, extract parameter values for the product, and determine processing logic applicable to the product. The processing logic may be designed to query the product database for the product. The logic packaging engine may also be configured to generate an execution package for the database system to perform the query on the product database, and the execution package can include the parameter values for the product at the particular stage in the manufacturing process and metadata references to corresponding query templates stored on the database system.
A PCB analysis utilizes manufacturing capability data shared in a multi-tenant collaborative network in a mixed cloud and on-premise environment. Access to a tenant's account of a DFM application deployed on the tenant's premises is provided. The DFM application is enabled to activate the PCB analysis on a DFM profile with manufacturing capability data. The tenant's account requests a utilization authorization of a given DFM profile stored in a cloud data layer. When the utilization is authorized, the given DFM profile is downloaded embedded in a locked DFM envelope, which locks together the given DFM profile with an injected identifier of the authorized tenant's account. Via the DFM application, when logged into the tenant's account, the PCB analysis is activated by permitting the unlocking of the DFM profile from the DFM envelope only when the identifier of the tenant's account is the same as the injected identifier.
A method of modifying instances of at least one part P including at least one entity e in a mechanical component design, is disclosed. A first part P1 has a local co-ordinate frame F and includes at least one entity ei. A transform T1 applied to the part P1 obtains a part instance P1T1 having an instance co-ordinate frame F1 in a common global space. At least one entity e1 in the part instance P1T1 is then marked as a positioning entity pe1 and grouped rigidly with the instance co-ordinate frame F1. Causing a positioning entity pe1 to move in the instance co-ordinate frame F1 causes all positioning entities pe1 in the instance co-ordinate frame F1 to move rigidly with the instance co-ordinate frame F1 and any unmarked entities e1 to move independently of the rigid grouping of positioning entities pe1.
This application discloses a hotspot identification system to generate process variability bands for structures of an integrated circuit capable of being fabricated utilizing at least one lithographic mask based, at least in part, on a mask layout data describing the lithographic mask and a distribution of manufacturing parameters during fabrication. The hotspot identification system can utilize the process variability bands to identify a subset of the structures that correspond to hotspots in the integrated circuit and identify corresponding values for the manufacturing parameters associated with the identified hotspots. A wafer testing system can implement a real-time wafer assessment process by comparing measured manufacturing parameters associated with a fabricated integrated circuit to the values for the manufacturing parameters associated with the identified hotspots, and dynamically identifying a disposition for the fabricated integrated circuit corresponding to one or more structures associated with the identified hotspot based on the comparison.
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
A computer-implemented method of extending a mixed sheet within a B-rep model is described. The mixed sheet includes surfaces having different geometries, such as a mesh positioned between first and second classical geometry surfaces. A first guide curve is defined, located at the boundary of a first surface for a length corresponding to the desired mixed sheet extension adjacent the first surface. A second guide curve may also be defined, located at the boundary of a second surface for a length corresponding to the desired mixed sheet extension adjacent the second surface. At least one extension mesh rung is created by generating facets between the two external mesh vertices using first and second extension vectors, wherein the first extension vector has a pre-determined spatial relationship to the first guide curve. If included, the second extension vector has a pre-determined spatial relationship to the second guide curve.
A method of verifying a model-based system engineering (MBSE) artifact includes translating, by a translator implemented in software, the MBSE artifact into formulas of a first-order logic. The method further includes checking, by a solver executing a decision procedure implemented in software and operating on the formulas of the first order logic, whether or not a conjunction of the formulas is satisfiable.
A computing system may include physical devices of a manufacturing facility and a message processing engine. The message processing engine may be configured to receive, from the physical devices of the manufacturing facility, update messages for product manufacture processes performed by the manufacturing facility and parse the update messages to determine a value of a promoted attribute for each of the update messages. The message processing engine may also be configured to group the update messages into different message groups according to the determined value of the promoted attribute and sequentially process update messages grouped into a particular message group for a particular value of the promoted attribute.
A method of determining a bit length of an IQ sample associated with a first data frame is provided. The method includes determining a first parameter associated with a payload length of the first data frame, and determining a second parameter indicative of a number of physical resource blocks in the first data frame. A presence of a compression header is detected based on the first parameter and the second parameter, and the bit length of the IQ sample is determined from one of the detected compression header and the first parameter and the second parameter. The bit length of the IQ sample may be determined automatically from information available in the data frame. This eliminates the need for manual entry of parameters into the packet analyzer and eliminates the likelihood of errors to due incorrect entry.
Various aspects of the present disclosed technology relate to techniques for retargeting free-form layout features. In a retargeting process, anchor points are selected on boundary lines of layout features based on one or more predetermined conditions. Property values comprising spacing values and linewidth values for each of the anchor points are then determined. Based on the determined property values, positions of the anchor points are adjusted to derive new anchor points. Retargeted layout features are derived by using splines as interpolating curves passing through the new anchor points or as approximating curves passing near to but not necessarily through the new anchor points.
This application discloses a computing system implementing a shared management system (340) to distribute virtual product models (343), each corresponding to a shared product model (341) describing a product having an electronic device with multiple printed circuit boards, to multiple printed circuit board layout tools (320-1 to 320-N). The printed circuit board layout tools (320-1 to 320-N) separately modify the corresponding virtual product models (343) to generate layout designs for the multiple print circuit boards and generate at least one system-level design rule describing a physical limitation for the electronic device. The shared management system (340) can update the shared product model (341) based on the modifications to at least one of the virtual product models by the printed circuit board layout tools (320-1 to 320-N), and transmit a notification (347) to at least one of the printed circuit board layout tools when the updated shared product model (341) conflicts with the physical limitation for the electronic device described in the at least one system-level design rule.
A first circuit design and a second circuit design are analyzed to determine part of the second circuit design structurally similar to part of the first circuit design. A first set of test patterns for the first circuit design is modified to generate a second set of test patterns for the second circuit design by reusing values of bits in the first set of test patterns associated with the part of the first circuit design as values of bits in the second set of test patterns associated with the part of the second circuit design. Fault simulation is performed on the second circuit design using the second set of test patterns to determine a subset of faults undetectable by the second set of test patterns. Test pattern generation is performed for the subset of faults to generate a third set of test patterns for the second circuit design.
G06F 30/333 - Conception en vue de la testabilité [DFT], p. ex. chaîne de balayage ou autotest intégré [BIST]
G06F 119/02 - Analyse de fiabilité ou optimisation de fiabilitéAnalyse de défaillance, p. ex. performance dans le pire scénario, analyse du mode de défaillance et de ses effets [FMEA]
A method of modifying a CAD system model performed on a data processing system includes receiving a dataset of co-ordinates representing an article in 2d, or in 3d and receiving 2d or 3d constraints respectively, to be applied to any changes to the dataset of co-ordinates for the article. A modification to be applied to the dataset is received and combined with the relevant 2d and 3d constraints to produce a constrained modification for each of the article and associated article. The constrained modification is solved in 2d and in 3d to determine whether a solution exists in which all constraints are met. If the solve is successful, the constrained modification is applied to each dataset simultaneously and, updated datasets are stored. If the solve fails, the constraints may be reduced and the solve step repeated, or the process is terminated.
A computing system implementing a design characterization tool can sample a distribution of values describing manufacturing variation for an integrated circuit described by a circuit design. The design characterization tool can utilize a set of the samples to generate a surrogate model of the circuit design, and can order another set of the samples based on predicted outputs of the surrogate model. The design characterization tool can simulate the surrogate model or the circuit design utilizing the ordered samples, and stop the simulations prior to all of the samples from the distribution having been utilized in the simulations. The design characterization tool can utilize a confidence interval stopping condition or a drought stopping condition to determine when to stop the simulations. The design characterization tool can utilize results of the simulations to characterize operational variation of the circuit design to the manufacturing variation described in the distribution of the values.
G06F 30/3308 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation
G06F 30/3315 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant une analyse temporelle statique [STA]
A testing circuit configured to test and diagnose a read-only memory comprises two multiple-input signature registers configured to generate two sets of signatures for multiple iterations of reading some or all of words stored in the read-only memory, control circuitry configured to control, according to a test algorithm, from which of the outputs of the read-only memory each of the two multiple-input signature registers receives test response signal bits for each of the reading operations during each of the iterations, and a faulty element location determination device configured to generate a faulty element location signal for the read-only memory based on results of comparing the two sets of signatures with reference signatures.
This application discloses a computing system to identify suspected defects in a manufactured integrated circuit, which correspond to electrical failures detected by a test applied to the manufactured integrated circuit. The computing system can utilize the suspected defects in the manufactured integrated circuit to cluster features in a physical layout design describing the manufactured integrated circuit. Each cluster of the features corresponds to a candidate for a physical root cause of the suspected defects in the manufactured integrated circuit. The computing system can detect a physical root cause of the electrical failures in the manufactured integrated circuit based on the clusters of the features. A physical failure analysis process includes an inspection of the manufactured integrated circuit to confirm the physical root cause of the electrical failures in the manufactured integrated circuit corresponds to a systemic manufacturing fault in the manufactured integrated circuit.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
68.
GENERATION OF CFD-BASED STRUCTURALLY INDEPENDENT AERODYNAMIC INFLUENCE COEFFICIENT MATRIX
This invention is a methodology, called CFD-based AIC generator, that can generate CFD-based structurally-independent Aerodynamic Influence Coefficient (AIC) matrices. Because the AIC matrices are independent of structure, they can be repeatedly used during the flight vehicle's structural design cycle for a fixed aerodynamic configuration to rapidly generate flutter, aeroservoelastic (ASE), and dynamic loads solutions. Inputs to processing include a CFD surface mesh, a coarsening ratio criterion, and a mid-layer panel model. The coarsening ratio criterion is computed from the CFD mesh. The mid-layer panel model is comprised of coarsened grid points derived from the CFD mesh and the coarsening ratio criterion.
G06F 30/15 - Conception de véhicules, d’aéronefs ou d’embarcations
G06F 30/28 - Optimisation, vérification ou simulation de l’objet conçu utilisant la dynamique des fluides, p. ex. les équations de Navier-Stokes ou la dynamique des fluides numérique [DFN]
69.
WAFER IMAGE DEFECT DETECTION AND CHARACTERIZATION FOR MANUFACTURING PROCESS CALIBRATION
A computing system implementing a raw data filtering tool can aggregate multiple wafer images depicting a portion of an electronic device into a reference image, detect one or more of the wafer images have defects based on a comparison of the reference image to the wafer images, and generate a gauge file to include a set of the wafer images selected based on the detection of defects in the wafer images. The raw data filtering tool also can iteratively build defect maps that include differences between the reference image and the wafer images, and characterize the detected defect in the wafer images with a size and a location based on the defect maps. The raw data filtering tool can provide feedback to a foundry about wafer images were excluded from the set of the wafer images based on the detection of defects in the wafer images.
A computing system implementing a physical verification tool can identify edges of a geometric pattern located within a search area surrounding a point of interest in a semiconductor layout design, characterize the edges of the geometric pattern based on locations of center points of the edges from the point of interest within the search area, and generate geometrical feature vectors for the point of interest in the semiconductor layout design based on the characterization of the edges of the geometric pattern. The computing system can reconstruct the semiconductor layout design corresponding to the search area surrounding the point of interest using the geometrical feature vectors for the point of interest in the semiconductor layout design.
G06V 10/44 - Extraction de caractéristiques locales par analyse des parties du motif, p. ex. par détection d’arêtes, de contours, de boucles, d’angles, de barres ou d’intersectionsAnalyse de connectivité, p. ex. de composantes connectées
G06T 7/70 - Détermination de la position ou de l'orientation des objets ou des caméras
71.
METHOD AND SYSTEM FOR REGULATING A MULTI-PART 3D PRINTING ORDER TRANSFER
Systems and a method for regulating a multi-part 3D printing order transfer between at least one requesting unit and a plurality of supplying units. Access to a nesting module is received. A quote module is defined for providing a price quote for a printing order based on material cost and on production cost. At least a portion of the production cost is calculated based on required build portion and on selected printing job type. For each supplying unit, it is received data on supplier auto-quote profile. Aata on a multi-part order of N parts requested by the requesting unit. For each relevant supplying unit and by using said two modules customized in via the auto-quote profiles, it is calculated a supplier quote to the nestable part subset, by applying the customized quote module—with the identified build portion size and with the type of the identified jobs as module input parameters. Supplying units are identified and the 3D printing order transfer is regulated by matching a selected set of supplying units to the requesting unit.
A computing system can perform static verification operations on a circuit design with a first set of design constraints characterizing portions of an electronic device described by the circuit design and identify one or more violations associated with clock domain crossings in the circuit design. The computing system can analyze the circuit design and the first set of the design constraints to determine at least one of the violations associated with the clock domain crossings in the circuit design corresponds to the first set of the design constraints, and generate one or more additional design constraints to integrate into the first set of the design constraints based on the analysis of the circuit design and the first set of the design constraints. The computing system can re-perform the static verification operations on the circuit design based on a second set of the design constraints that includes the additional design constraints.
Systems and a method for detecting a false error in a set of errors detected on components of a board that is inspected by an automated optical inspection (AOI) machine. Input data are received. The input data include data originating from AOI machine's inspection results of a given inspected board marked as failed. A false error detector is applied to the input data. The detector is modeled with a trained function and the detector generates output data. The output data determines whether or not at least one of the component errors that are reported by the AOI machine for the given board is a false error.
The described method as a key enabler for Optical Inspection dynamically uses individual marks like fiducials, barcodes, data matrix codes (“markers”) in the scenes, beyond their basic presence, meaning the change of situation between a first processing status and a subsequent processing status in the processing station. The same markers are simultaneously used for: the identification of components (“comp”); the identification of locations (“loc”); the definition of dependencies between identity and location (valid, invalid); and the automated detection and evaluation of the dependencies.
A method and system for performing clearance analysis of a product assembly in a computer-aided design (CAD) environment is disclosed. A method includes receiving a request for evaluating clearance between components of a product assembly in a CAD environment from a user device. The request includes a unique identifier of the product assembly. The method includes obtaining product data associated with the product assembly from a PDM database based on the unique identifier of the product assembly, and iteratively decomposing a product space including the product assembly in the CAD environment into a plurality of variable-sized partitions based on the product data. The method also includes selecting one or more variable-sized partitions for evaluating clearance between the components in the product assembly from the plurality of the variable-sized partitions, and evaluating clearance between the components in the selected variable-sized partitions.
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
76.
Method of programming a software module associated with a firmware unit of a device
A method of programming a software module associated with a firmware unit of a device is provided. The method includes obtaining a register transfer level program associated with the firmware unit. The register transfer level program includes a plurality of register variables indicative of a plurality of registers in the firmware unit, defined within a first namespace of the register transfer level program. The method includes linking the first namespace associated with the register transfer level program with a namespace associated with a software module for referencing at least one register variable from the plurality of register variables. The register transfer level program includes design level description of one or more operations associated with the firmware unit in a high-level programming language.
This application discloses a memory built-in self-test system to prompt a memory device to sense values of stored data using a reference trim during memory read operations. The memory built-in self-test system can automatically set the reference trim for the memory device. The memory built-in self-test system includes a memory built-in self-test controller to prompt the memory device to perform the memory read operations with different test values for the reference trim. The memory built-in self-test system also includes a trim feedback circuit to determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim, and set the reference trim for the memory device based, at least in part, on the failures of the memory device to correctly sense the stored data.
A method and system for providing a three-dimensional Computer-Aided Design (CAD) model of an object in a CAD environment are provided. A method includes receiving a request for a three-dimensional CAD model of a physical object, where the request includes a two-dimensional image of the object. An image vector is generated from the two-dimensional image using a first trained machine learning algorithm. The method includes generating a three-dimensional point cloud model of the object based on the generated image vector using a second trained machine learning algorithm, and generating a three-dimensional CAD model of the object using the three-dimensional point cloud model of the object. The method includes outputting the three-dimensional CAD model of the object on a graphical user interface.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
79.
BOUNDING BOX-BASED VISUALIZATION OF COMPUTER-AIDED DESIGN (CAD) MODELS VIA PIXEL COLOR ANALYSES
A client computing system may include a model visualization engine configured to visualize a view of a computer-aided design (CAD) model in an application window, including by accessing bounding box data for non-visualized CAD parts of the CAD model, assigning a color value to each of the bounding boxes of the non-visualized CAD parts, capturing a 2D image of the view of the CAD model rendered using the bounding boxes for the non-visualized CAD parts, and analyzing the 2D image to identify pixel colors present in the 2D image to determine visible CAD parts in the view of the CAD model. The model visualization engine may further visualize the view of the CAD model by retrieving visualization data for the visible CAD parts and visualizing, in the application window, the visible CAD parts in the view of the CAD model via the retrieved visualization data.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
A computing system may include a model access engine configured to access a CAD model comprised of multiple CAD parts. The computing system may also include a model explosion engine configured to construct a blocking data structure for the CAD model that stores a blocking state for each pair of CAD parts of the CAD model (210) as well as an explosion graph for the CAD model. Iterative generation of the explosion graph by the model explosion engine may include querying the blocking data structure to determine unblocked CAD parts for which to insert a node into the explosion graph. The model explosion engine may also be configured to generate an exploded view representation of the CAD model using the constructed explosion graph.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
81.
METHOD AND SYSTEM FOR DYNAMICALLY RECOMMENDING COMMANDS FOR PERFORMING A PRODUCT DATA MANAGEMENT OPERATION
A method and system for dynamically recommending commands for performing a PDM operation on product data objects in a product data management environment is disclosed. In one embodiment, a method includes determining a context in which a user is operating within a product data management environment. The method includes dynamically determining a set of commands suitable for performing a candidate PDM operation on the product data objects based on the determined context. Furthermore, the method includes computing a score for each of the commands suitable for performing the candidate PDM operation on the product data objects. Moreover, the method includes assigning a rank to each command suitable for performing the candidate PDM operation based on the score associated with each command, and outputting one or more commands from the set of commands on a graphical user interface based on the rank assigned to each command.
G06Q 10/0631 - Planification, affectation, distribution ou ordonnancement de ressources d’entreprises ou d’organisations
G06Q 10/04 - Prévision ou optimisation spécialement adaptées à des fins administratives ou de gestion, p. ex. programmation linéaire ou "problème d’optimisation des stocks"
Aspects of the disclosed technology relate to techniques for applying optical proximity correction to free form shapes. Each optical proximity correction iteration comprises: computing edge adjustment values for the straight ty correction iteration immediately preceding the each of the plurality of optical proximity correction iterations, adjusting locations of the straight line fragments based on the determined edge adjustment values, determining smooth boundary lines for the layout features based on the straight line fragments on the adjusted locations, performing a simulation process on the layout features having the smooth boundary lines to determine a simulated image of the layout features, and deriving the edge adjustment errors for the straight line fragments based on comparing the simulated image with a target image of the layout features.
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
83.
METHOD AND SYSTEM FOR VALIDATING PRODUCT AND MANUFACTURING INFORMATION OF A GEOMETRIC MODEL
A method and a system for validating product and manufacturing information associated with a geometric model in a computer-aided design environment are provided. The method includes generating a geometric model of a physical object in the computer-aided design environment. The geometric model of the physical object includes product and manufacturing information. The method includes extracting the product and manufacturing information from the geometric model, and validating the extracted product and manufacturing information using at least one checker. The at least one checker includes one or more logical elements capable of validating the product and manufacturing information. The method includes outputting results of the validating of the product and manufacturing information on a graphical user interface.
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
84.
METHOD AND SYSTEM FOR SCATTERING GEOMETRIC COMPONENTS IN A THREE-DIMENSIONAL SPACE
A method and system for scattering geometric components in a three-dimensional space are disclosed. A method includes determining geometric components needed for assembling a CAD model of a product, and determining a scatter plane for scattering the geometric components in the three-dimensional space in the CAD environment. The method includes computing a two-dimensional projection of the geometric components. The method also includes determining a position of each of the geometric components based on the two-dimensional projection of the geometric components. The method includes placing each of the geometric components in the scatter plane based on the position of said each geometric component.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
85.
LAYOUT-BASED WAFER DEFECT IDENTIFICATION AND CLASSIFICATION
This application discloses a scanning electron microscope system to capture an image of an electronic device manufactured according to a layout design describing the electronic device, and a computing system to generate a predicted image of the electronic device using the layout design. The predicted image corresponds to an expected image of the electronic design system captured by the scanning electron microscope system. The computing system identifies manufacturing defects present in the electronic device based on differences between the predicted image of the electronic device and the captured image of the electronic device, and utilizes the captured image of the electronic device to classify the manufacturing defects identified based on the predicted image of the electronic device from the layout design. The computing system can generate a manufacturing defect report identifying the manufacturing defects used to perform repair of the electronic device or modification of the layout design.
A computer implemented method of bounding spatial data associated with the geometric bounds of an item mapped into one or more 3-D axis-aligned bounding boxes is disclosed. The geometric bounds bound each permutation of all possible positions of the item geometrically. The method includes: partitioning a set of bounding boxes using a first group of intervals along the x axis direction and allocating a partition identification xpar; partitioning the set of bounding boxes using a second group of intervals along the y axis direction and allocating a partition identification ypar; partitioning the set of bounding boxes using a third group of intervals along the z axis direction and allocating a partition identification zpar; and partitioning the set of bounding boxes by partition identification tuples (xpar, ypar, zpar). The method further includes merging bounding boxes with the same partition identification tuple.
A computing system may include a design space access engine configured to access a design space of a physical structure. The computing system may also include a structural design engine configured to encode the design space into a set of 3-dimensional (3D) rectangles. Each 3D rectangle may define candidate beam locations in the physical structure and candidate beam locations of the 3D rectangles may be defined by lines between vertex pairs of each 3D rectangle. The structural design engine may also provide the encoded design space as an input to a machine-learning (ML) model, generate, through the ML model, a design of the physical structure based on the encoded design space, and provide the design of the physical structure in support of manufacture of the physical structure.
G06F 30/13 - Conception architecturale, p. ex. conception architecturale assistée par ordinateur [CAAO] relative à la conception de bâtiments, de ponts, de paysages, d’usines ou de routes
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
A computer implemented method of remeshing patches in a triangular meshed surface that employs an advancing front process is disclosed. An initial surface includes a triangular surface mesh, and a target size field that specifies an optimal triangle edge length at each position on the triangular surface mesh is defined over every point in. The triangular surface mesh is partitioned into patches, where each patch includes a contiguous set of adjacent faces delimited by closed loops of boundary or feature edges and has principal surface curvatures. The method employs an asterisk field generated from a cross field calculated for the patch in order to generate a remeshed surface.
A method and system for generating a three-dimensional model of a multi-thickness object in a formed state in a computer-aided design (CAD) environment is disclosed. In one embodiment, a method includes receiving a request to generate a feature of a three-dimensional model. The method includes creating a virtual datum plane, and dynamically computing an offset value for the feature with reference to the virtual datum plane based on a thickness value. The offset value determines an offset between the virtual datum plane and one of the surfaces of the feature. The method includes generating the feature of the three-dimensional model in the formed state with reference to the virtual datum plane based on the thickness value, a location of the feature and the offset value. Moreover, the method includes outputting the three-dimensional model of the multi-thickness object having the generated feature in the formed state.
A computing system implementing a design verification system can classify a mixed-signal circuit design describing an electronic device based on a design topology of the mixed-signal circuit design. This classification can be performed by identifying a top-level design block in the mixed-signal circuit design, traversing a connectivity of a design hierarchy to identify lower-level design blocks in the mixed-signal circuit design, and classifying the mixed-signal circuit design based on at least one of a design type of the top-level design block, design types of the lower-level design blocks, or a connectivity of design blocks in the mixed-signal circuit design. The design verification system can selectively partition the mixed-signal circuit design into an analog partition and a digital partition based on the classification, and simulate the analog partition of the mixed-signal circuit design with an analog simulator and the digital partition of the mixed-signal circuit design with a digital simulator.
G06F 30/38 - Conception de circuits au niveau mixte des signaux analogiques et numériques
G06F 30/3308 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
A computer implemented method of dynamically verifying clock domain crossing (CDC) paths in a register-transfer level (RTL) design is provided. In addition to static analysis, formal analysis, and simulation steps, each CDC path is allocated a persistent unique identifier. This enables the updating of a centralized results database using the persistent unique identifier to label the associated CDC protocol assertions, functional coverage, and results of the formal analysis and simulation. In addition, prior to simulation analysis, CDC protocol assertions that have been proven during formal analysis are turned off, resulting in the simulation run only being carried out for non-proven CDC protocol assertions.
Various aspects of the present disclosed technology relate to hybrid static and dynamic switching in a reconfigurable hardware modeling circuit for flexible and low latency communications. The reconfigurable hardware modeling circuit comprises serializer circuitry and deserializer circuitry for one or more communication ports, wherein the serializer circuitry has first sub-channels for receiving data to be sent out from the reconfigurable hardware modeling circuit, and the deserializer circuitry has second sub-channels for outputting data received by the reconfigurable hardware modeling circuit. The reconfigurable hardware modeling circuit also comprises static switching circuitry configurable to couple each of first zero or one or more sub-channels in the first sub-channels with one of signal sources comprising the second sub-channels and dynamic switching circuitry configurable to couple, in a time-division multiplexing mode, each of second zero or one or more sub-channels in the first sub-channels with more than one of the signal sources.
G06F 30/327 - Synthèse logiqueSynthèse de comportement, p. ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/331 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation avec accélération matérielle, p. ex. en utilisant les réseaux de portes programmables [FPGA] ou une émulation
93.
Managing a postprocessor for machining with a machine tool method, computer system, and machine tool
For an improved management of a postprocessor, for machining with a machine tool, a computer-implemented method includes providing toolpath data for machining a workpiece with a tool along a corresponding toolpath. The tool is comprised by a machine tool that is numerically controlled by a control device. Sample machine code is provided. Atrial postprocessor software component for determining machine code using toolpath data is provided. Trial machine code is determined using the trial postprocessor software component and the toolpath data. A sample code architecture of the sample machine code and a trial code architecture of the trial machine code are determined. Characteristics of the sample machine code are determined by comparing the sample code architecture with the trial code architecture, and a new postprocessor software component is determined by incorporating the characteristics into the trial postprocessor software component.
G05B 19/29 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par systèmes de commande de positionnement ou de commande de contournage, p. ex. pour commander la position à partir d'un point programmé vers un autre point ou pour commander un mouvement le long d'un parcours continu programmé utilisant un dispositif de mesure numérique absolue pour commande point par point
G05B 19/4093 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique caractérisée par la programmation de pièce, p. ex. introduction d'une information géométrique dérivée d'un dessin technique, combinaison de cette information avec l'information d'usinage et de matériau pour obtenir une information de commande, appelée programme de pièce, pour la machine à commande numérique [CN]
Surface editing is performed in typical computer-aided design (CAD) software products by using special tools to edit special surfaces, such as b-splines or subdivision surfaces. It is recognized herein that current approaches to editing surfaces are not generally applicable. For example, common CAD and surface modeling software products are tailored to a specific surface type or vendor specific format, or otherwise are not generally applicable to given analytical and non-analytical surfaces. In various embodiments described herein, subdivision surfaces can be generated to represent any surface. Further, surfaces can be manipulated using a control cage associated with the subdivision surface.
High Bandwidth IJTAG Through High Speed Parallel Bus A system in a circuit comprises: a first network (710) configurable to transmit data in parallel in the circuit, the first network (710) comprising circuit block interface devices, each of the circuit block interface devices being coupled to ports of one of circuit blocks in the circuit; a plurality of second networks (720, 725, 727), each of the plurality of second networks (720, 725, 727) configurable to transmit data in serial in one of the circuit blocks in the circuit; a third network (730) configurable to transmit data in serial in the circuit when being coupled to the plurality of second networks (720, 725, 727); and a plurality of network switching interface devices (740, 745, 747), each of the plurality of network switching interface devices (740, 745, 747) configurable to couple either the first network (710) or the third network (730) to one of the plurality of second networks (720, 725, 727) based on a control signal stored in the each of the plurality of interface devices (740, 745, 747).
Various aspects of the present disclosed technology relate to techniques for classifying layout patterns. First, a set of density feature vectors for a set of layout regions in the layout design are extracted using a set of rings. Each component of a density feature vector in the set of density feature vectors corresponds to a ring in the set of rings. The set of rings do not overlap with each other and cover a whole area of a circle when being placed together. Next, a machine learning-based clustering process is performed to separate layout features in the set of layout regions into clusters of layout features based on the set of density feature vectors. Each of the clusters of layout features may be further divided into subclusters based on one or more properties.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
97.
HEAT-AWARE TOOLPATH GENERATION FOR 3D
PRINTING OF PHYSICAL PARTS
A computing system may include an access engine and a heat-aware toolpath engine. The access engine may be configured to access a slice of a 3-dimensional (3D) computer-aided design (CAD) object, wherein the 3D CAD object represents a physical part and wherein the slice represents a physical layer for 3D printing of the physical part. The heat-aware toolpath engine may be configured to generate a layer toolpath to control the 3D printing of the physical layer, including by partitioning the slice into zones and determining a zone order, based on a heat-aware criterion, for the layer toolpath to traverse for the 3D printing of the physical layer. The heat-aware toolpath engine may also be configured to provide the layer toolpath to support the 3D printing of the physical part.
A method of protocol processing including a main program code that has one or more code segments and instructions for processing different protocol elements of a data packet stream of a transport protocol is disclosed herein. The method includes assigning a latency requirement and/or bandwidth requirement to one or more of the code segments of the main program code; and compiling each of the code segments according to the assigned latency and/or bandwidth requirement into a respective target code for executing each of the target codes by different processors.
A computing system may include a constraint learning engine and a constraint generation engine. The constraint learning engine may be configured to access a computer-aided design (CAD) assembly comprising multiple CAD parts and generate a representation graph of the CAD assembly, determine constraints in the CAD assembly, wherein the constraints limit a degree of movement between geometric faces of different CAD parts in the CAD assembly, insert constraint edges into the representation graph that represent the determined constraints; and provide the representation graph as training data to train a machine-learning model. The constraint generation engine may be configured to generate constraints for a different CAD assembly by applying the machine-learning model for the different CAD assembly.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
Systems and methods for simulation and testing of multiple virtual electronic control units (VECUs). A method (1000) includes executing, by one or more computer systems (101), a first VECU (502). The method includes executing a virtual bus (510), the virtual bus (510) associated with the first VECU (502). The method includes executing at least one second VECU. The method includes simulating a multiple-VECU system by managing communications, using the virtual bus (510), between the first VECU (502) and the at least one second VECU.
H04L 43/20 - Dispositions pour la surveillance ou le test de réseaux de commutation de données le système de surveillance ou les éléments surveillés étant des entités virtualisées, abstraites ou définies par logiciel, p. ex. SDN ou NFV
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