The present disclosure provides a semiconductor device and a manufacturing method therefor. The manufacturing method comprises: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a plurality of active regions which are located in the substrate and are arranged separately, a plurality of openings exposing parts of the active regions, and a protective layer covering the surface of the substrate among the openings; forming a semiconductor layer in the openings, wherein the surface of the semiconductor layer is not lower than the surface of the protective layer; forming a first dielectric layer, wherein the first dielectric layer covers the semiconductor layer; and sequentially etching the first dielectric layer and the semiconductor layer to form a plurality of initial bit line structures extending in a direction parallel to the substrate, wherein the initial bit line structures comprise the semiconductor layer and the first dielectric layer located on the semiconductor layer.
Provided in the present disclosure are a control circuit and a memory. The control circuit comprises: an enable circuit, a decoding circuit and a signal generation circuit, wherein the enable circuit generates an enable signal, an active level of which starts from an active edge of an activation command signal and terminates at an active edge of a precharge command signal; when the enable signal is at the active level, the decoding circuit outputs a decoded signal, which is obtained by means of decoding an instruction signal; and the signal generation circuit generates, on the basis of the decoded signal, a control signal for a read or write operation of a memory.
The present embodiments provide a test mode control circuit, a control method, and a memory. In the circuit: an address processing circuit is used to obtain a target address signal when an enable signal is in an enabling state; a delay circuit is used to obtain a shifted mode register write signal; a sampling latch circuit is used to obtain a target operation code signal when the enable signal is in the enabling state; and a test circuit is used to generate and output a corresponding test signal.
The present disclosure relates to the technical field of storage, and relates to a storage unit, and a memory and a preparation method therefor. In the storage unit, a semiconductor layer is in a closed ring shape; and an inner area of the ring of the semiconductor layer comprises a first area and a second area, which are insulated and isolated from each other in a first direction. The semiconductor layer comprises: a first semiconductor portion, which surrounds part of the boundary of the first area, and a second semiconductor portion, which surrounds part of the boundary of the second area. A first gate electrode is located in the first area. Two second gate electrodes are respectively located on two sides of the first semiconductor portion that are away from the first gate electrode and opposite each other in a second direction, the second direction intersecting with the first direction. A contact electrode conformally covers an inner side wall of the second semiconductor portion. A first electrode is located in the second area and is insulated from the contact electrode. A second electrode is located on the outer side of the second semiconductor portion that is away from the first electrode in the first direction and the second direction, and the second electrode is insulated from the second semiconductor portion.
A semiconductor package structure, comprising: a first substrate, a second substrate, a processor module, a chip stacking structure and a signal adapter board. The processor module is arranged on a first plane of the first substrate and is connected to the first substrate; the chip stacking structure is arranged on the first plane of the first substrate and is connected to the first substrate, and the first substrate is used for transmitting a first-type signal between the processor module and the chip stacking structure; the signal adapter board is connected to the processor module and the chip stacking structure and is used for transmitting a second-type signal between the processor module and the chip stacking structure; and the second substrate is parallel to the first substrate and is connected to a second plane of the first substrate, and the second plane of the first substrate is parallel to and opposite to the first plane of the first substrate. According to embodiments of the present disclosure, the semiconductor packaging cost can be reduced.
The present disclosure provides a signal processing circuit and a memory. The signal processing circuit comprises: a pulse stretching circuit which is used for stretching the pulse width of an address signal by means of a command signal to generate an address stretched signal; and an address decoding circuit which has an input end coupled to an output end of the pulse stretching circuit, and is used for decoding the address stretched signal to generate an address decoded signal.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/12 - Circuits de commande de lignes de bits, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
Provided in the present disclosure are a refresh control circuit and a memory. The refresh control circuit comprises a self-refresh control signal generation module and a self-refresh signal generation module, wherein the self-refresh control signal generation module is configured to receive a self-refresh mode signal, output a self-refresh control signal of a first level when the self-refresh mode signal indicates that a memory enters a self-refresh mode, and output a self-refresh control signal of a second level when the self-refresh mode signal indicates that the memory exits the self-refresh mode; and the self-refresh signal generation module is configured to receive the self-refresh control signal, output a self-refresh signal, generate a shielding signal on the basis of the self-refresh control signal, and shield the self-refresh control signal for a preset duration on the basis of the shielding signal and then output the self-refresh control signal.
Embodiments of the present disclosure disclose a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate; a first conductive layer, located on the substrate and comprising a first sub-conductive structure, a second sub-conductive structure, and a second conductive structure which are arranged at intervals; a second conductive layer, located on the first conductive layer; an isolation structure, located between the first sub-conductive structure and the second sub-conductive structure, connected to the second conductive layer and used for electrically isolating the first sub-conductive structure from the second sub-conductive structure; and a contact plug, located between the second conductive structure and the second conductive layer, and used for electrically connecting the second conductive structure to the second conductive layer.
The present disclosure relates to the technical field of storage, and relates to a storage unit, a memory and a manufacturing method therefor. The storage unit comprises: a transistor and a capacitor. The transistor comprises: a semiconductor layer, a first gate, and a second gate. The semiconductor layer comprises a first portion extending in a first direction, and a second portion and a third portion respectively connected to the two ends of the first portion and extending in a second direction; the second direction intersects the first direction; and the side of the second portion facing away from the third portion is electrically connected to a bit line. The first gate and the second gate are respectively located on the two opposite sides of the first portion in the second direction. The capacitor is located on the side of the third portion facing away from the second portion and is electrically connected to the third portion.
Provided in the present disclosure are a semiconductor device and a manufacturing method therefor. The manufacturing method comprises: providing a substrate, wherein a device region of the substrate comprises a first sub-region and a second sub-region, a first isolation sub-structure located in the first sub-region comprises a first dielectric layer that fills up a first sub-trench, and a second isolation sub-structure located in the second sub-region comprises a first dielectric layer and a first isolation layer that sequentially cover the side wall and the bottom of a second sub-trench, and a second dielectric layer that fills up the second sub-trench; removing part of the first dielectric layer and part of the second dielectric layer from the second sub-trench, so as to expose at least part of the side wall of the first isolation layer; and removing from the second sub-trench part of the first isolation layer that is exposed.
An information processing apparatus, comprising: a mainboard (101), which has a first surface, wherein the first surface is provided with a central processing unit (102) electrically connected to the mainboard (101); a compressed additional memory module (103), which is located on one side of the first surface, wherein at least one surface of the compressed additional memory module (103) is provided with a plurality of chips (104); and an external connection structure (105), which is located on one side of the first surface, and is configured to electrically connect to the compressed additional memory module (103) and the central processing unit (102), wherein the central processing unit (102) is configured to read data from each chip (104) and write data into each chip (104) at least via the external connection structure (105).
An exposure compensation amount determination method, comprising: forming a first photoresist pattern (310) by means of executing a first photolithography process, and transferring the first photoresist pattern (310) to the current layer to form a first pattern; and then executing a second photolithography process to form a second photoresist pattern (320) on the first pattern, transferring the second photoresist pattern (320) to the current layer to obtain a second pattern, and on the basis of the first pattern and the second pattern, obtaining a target pattern. An exposure compensation amount can be determined by means of combining an alignment offset obtained when the first pattern is formed, an alignment offset with respect to the first pattern, which is obtained when the second image is formed, and an alignment offset of the target image and a substrate alignment mark.
The present disclosure provides a command generation circuit and a memory. A first sampling circuit is used for performing sampling processing on a first command signal according to a first clock signal to obtain a first intermediate signal; a base delay circuit is used for performing sampling and shifting processing on the first intermediate signal according to a first control signal and the first clock signal to obtain a second intermediate signal; a second sampling circuit is used for performing setting processing on the second sampling circuit according to the first intermediate signal, and performing sampling processing on the second intermediate signal according to the first clock signal to obtain a third intermediate signal; and a command adjustment circuit is used for performing pulse-width adjustment processing on the first command signal according to the first intermediate signal and the third intermediate signal to obtain a second command signal.
Provided in the embodiments of the present disclosure are a memory and a controller. The memory comprises an ECS circuit. The ECS circuit comprises: an ECS module, which is used for receiving a period control signal sent by a controller, generating an ECS clock signal according to the period control signal, executing an ECS operation on the basis of the ECS clock signal, and generating and outputting error information after the present ECS operation is completed, wherein the period of the ECS clock signal is positively correlated with a period for executing the present ECS operation; and a register module, which is connected to the ECS module, and is used for receiving the error information and sending the error information to the controller, such that the controller updates the period control signal according to the error information, wherein the ECS module executes the next ECS operation according to the updated period control signal.
The present disclosure provides a memory. The memory comprises: a plurality of main storage arrays, a plurality of redundant arrays, and a plurality of write selection circuits; the redundant arrays are used for replacing faulty storage units in the main storage arrays; each write selection circuit receives M sets of data, and is adapted, according to a write selection signal, to output data to be recovered in the M sets of data to a data transmission path of the corresponding redundant array or not to output data.
Provided in the present disclosure are a fault addressing circuit and a memory. The fault addressing circuit comprises an enable circuit and an output circuit, wherein with regard to a column address corresponding to a command address signal, the enable circuit outputs a valid enable signal if a fault array identifier of the column address is not an invalid value, otherwise outputs an invalid enable signal, and the enable circuit outputs an invalid enable signal with regard to other column addresses; and the output circuit outputs, according to an enable signal of each column address, a fault array identifier of a column address with a valid enable signal.
Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate provided with a word line trench, the bottom and the side wall of the word line trench being covered with a dielectric layer; a word line that is located on the inner wall of the dielectric layer and fills part of the word line trench, the top of the word line being provided with a protruding portion that protrudes in the vertical direction; an isolation layer filling a recess on at least one side of the protruding portion; and an insulating layer that is located above the word line and the isolation layer and fully fills the word line trench, the dielectric constant of the insulating layer being less than that of the isolation layer.
Disclosed in the present application are a column control circuit and a storage apparatus. The column control circuit comprises a delay control circuit and a control signal generation circuit, wherein the delay control circuit receives a column selection start signal and performs delay processing, so as to output a column selection termination signal and a reset signal; the control signal generation circuit receives the column selection start signal, the reset signal, the column selection termination signal and a target bank group selection signal, and outputs a target column selection start signal, a target column selection termination signal and a target column selection window signal; from a start moment when the target column selection start signal is in an effective state until the reset signal is effective, the target column selection window signal is in an effective state, and an effective duration of the target column selection window signal is greater than or equal to an effective duration of the target bank group selection signal.
The present disclosure relates to a semiconductor structure, a semiconductor forming method, and a memory. The semiconductor structure comprises: a substrate having an array area and a peripheral area; a first stack structure located in the peripheral area, the first stack structure comprising a plurality of first semiconductor layers, a plurality of second semiconductor layers, and a stress release layer, wherein the first semiconductor layers and the second semiconductor layers are alternately stacked in sequence, and the stress release layer is located on the top first semiconductor layer; a storage structure located in the array area, the storage structure comprising a plurality of storage units which are sequentially stacked; a first peripheral transistor structure arranged on the top surface of the first stack structure, the first peripheral transistor structure being electrically connected to the storage units of a first portion; and a second peripheral transistor structure arranged on the top surface of the substrate, the second peripheral transistor structure being electrically connected to the storage units of a second portion.
Disclosed are a semiconductor structure and a manufacturing method therefor. The manufacturing method comprises: providing a substrate having at least one blind hole; using an epitaxial growth process to form bottom silicon at least at the bottom portions of the blind holes; forming an initial silicon material layer fully filling the rest of the blind holes, the melting point of the initial silicon material layer being lower than the melting point of the bottom silicon; using laser to process the initial silicon material layer, such that the initial silicon material layer is molten; and performing cooling processing on the laser-treated initial silicon material layer, such that the initial silicon material layer recrystallizes to form a silicon material layer.
Provided in the embodiments of the present disclosure are a manufacturing method for a semiconductor structure and a structure thereof. The manufacturing method for a semiconductor structure comprises: providing a substrate, forming a plurality of lower electrode layers, forming a capacitive dielectric layer, forming an upper electrode layer, forming a seed crystal layer, and growing and forming a semiconductor conductive layer along the surface of the seed crystal layer, wherein each lower electrode layer is located on the surface of the substrate, the capacitive dielectric layer covers the surface of each lower electrode layer, the upper electrode layer covers the surface of the capacitive dielectric layer, a groove is defined by means of the upper electrode layer between adjacent lower electrode layers, the seed crystal layer covers the surface of the upper electrode layer, the groove is not filled with the seed crystal layer, the seed crystal layer contains a fourth main group element, and the semiconductor conductive layer covers the surface of the seed crystal layer and fills the groove.
The embodiments of the present disclosure provide a memory and a control method therefor, and a memory system. The memory comprises: M storage groups, wherein each storage group comprises at least two storage blocks; a compression module, which is configured to perform in a compression test mode compression processing on first data outputted by each storage block, so as to obtain first compressed data; and a data transmission module, which is connected to the compression module and comprises a plurality of bus transmission modules and a plurality of data terminal areas, wherein the bus transmission modules and the data terminal areas are connected by means of a transmission line group, each bus transmission module is connected to N storage groups, and the bus transmission modules are configured to output one piece of first data in a normal mode, or, perform parallel-serial conversion processing on a plurality of pieces of first compressed data and output a second compression signal in the compression test mode.
Provided in the embodiments of the present disclosure are a memory, a control circuit thereof and an operating method therefor. The control circuit comprises: an address decoding logic circuit, configured to output address signals of designated banks to a bank group, and comprising a first input end configured to receive a first address signal and a second input end configured to receive a second address signal; and an address selection circuit, connected to the second input end or the first input end, and the address selection circuit being configured to output the corresponding second address signal according to the first address signal or configured to output to the address decoding logic circuit a predetermined third address signal as the second address signal.
Embodiments of the present disclosure relate to a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a first chip, the first chip being provided with a first pad; a second chip, the second chip being provided with a second pad and a metal bump, and the metal bump being located on the surface of the second pad away from the second chip and bonded to the first pad; and an insulating layer, located between the first chip and the second chip, a first cavity and a second cavity being formed in the insulating layer, the first cavity being located on the periphery of the first pad, the second cavity being located on the periphery of the metal bump, and the first cavity being communicated with the second cavity to form a cavity, wherein the cavity is filled with the metal bump.
H01L 23/488 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de structures soudées
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
Embodiments of the present invention provide a command processing circuit and a memory. The command processing circuit comprises a counting circuit and a command generation circuit; there are a plurality of cascaded counting groups in the counting circuit; an initial command can be sent to a clock end of a selected counting group, and a counting result of the final counting group is output as a command count value; when the command count value reaches a target value, the command generation circuit generates a first operation command on the basis of the current initial command or the next initial command.
G11C 11/413 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
The present disclosure relates to the field of semiconductor circuit design, and in particular to a sense amplifier circuit structure and a memory. The sense amplifier circuit structure comprises: a first N-type transistor, connected to a bit line, a first power supply node and a complementary amplification bit line; a second N-type transistor, connected to a complementary bit line, the first power supply node and an amplification bit line; a first P-type transistor, connected to the amplification bit line, a second power supply node and the complementary amplification bit line; a second P-type transistor, connected to the complementary amplification bit line, the second power supply node and the amplification bit line; a first isolation transistor, connected to the bit line and the amplification bit line; and a second isolation transistor, connected to the complementary bit line and the complementary amplification bit line, the thicknesses of gate oxide layers of the first isolation transistor and the second isolation transistor being greater than the thicknesses of gate oxide layers of the first N-type transistor and the second N-type transistor.
Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, embedded word line structures, a bit line contact structure, and an embedded bit line structure; the substrate comprises active regions which are spaced apart from each other; the embedded word line structures are located in the substrate, and the embedded word line structures each comprise a word line conductive layer; the bottom surface of at least part of the bit line contact structure is flush with the top surface of the word line conductive layer, or the bottom surface of at least part of the bit line contact structure is lower than the top surface of the word line conductive layer; the embedded bit line structure is located in the substrate, the embedded bit line structure extends in a second direction, and the embedded bit line structure is located on the top surface of the bit line contact structure.
A semiconductor structure and a preparation method therefor. The method comprises: providing a grinding fluid, wherein the grinding fluid comprises grinding particles (101), deionized water and a surfactant (105), and has a pH value of no greater than 3.5; and subjecting an initial semiconductor structure (106) to chemo-mechanical grinding treatment with the grinding fluid, so as to obtain a semiconductor structure (107). The preparation method for a semiconductor structure can realize a surface treatment on various materials, and as for different polishing objects, initial semiconductor structures made of various materials can share one grinding fluid; therefore, chemo-mechanical grinding (CMP) of initial semiconductor structures made of different materials can be achieved by means of only one set of a chemical grinding fluid supply system, such that a CMP process is simplified, and the cost is reduced.
H01L 21/306 - Traitement chimique ou électrique, p.ex. gravure électrolytique
H01L 21/302 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour changer leurs caractéristiques physiques de surface ou leur forme, p.ex. gravure, polissage, découpage
H01L 21/304 - Traitement mécanique, p.ex. meulage, polissage, coupe
H01L 21/461 - Traitement de corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour changer les caractéristiques physiques ou la forme de leur surface, p.ex. gravure, polissage, découpage
H01L 21/463 - Traitement mécanique, p.ex. meulage, traitement par ultrasons
B24B 57/02 - Dispositifs pour l'alimentation, l'application, le triage ou la récupération de produits de meulage, polissage ou rodage pour l'alimentation en produits de meulage, polissage ou rodage à l'état fluide, vaporisés, pulvérisés ou liquéfiés
Provided in the embodiments of the present disclosure are a signal driving circuit and a memory. The signal driving circuit comprises a driving module and a control module; the driving module is configured to receive an input signal, output a first output signal in a second level state when the input signal is in a first level state, and output a first output signal in the first level state when the input signal is in the second level state; the control module is configured to cause the driving module to output a second output signal in the second level state when the input signal is in the first level state, the time when the second output signal jumps from the first level state to the second level state being less than the time when the first output signal jumps from the first level state to the second level state.
Provided in the embodiments of the present disclosure are a sense amplifier and a control method therefor, and a memory. The sense amplifier comprises a sense amplifier circuit, and an offset cancellation circuit and an isolation circuit, which are connected to the sense amplifier circuit, wherein the sense amplifier circuit comprises a first NMOS transistor and a second NMOS transistor; the offset cancellation circuit is used for charging a gate capacitor of the first NMOS transistor and a gate capacitor of the second NMOS transistor; and the isolation circuit is further electrically connected to a first bit line and a second bit line, and the isolation circuit is used for connecting the gate capacitor of the first NMOS transistor to the second bit line and connecting the gate capacitor of the second NMOS transistor to the first bit line, so as to realize charge sharing.
G11C 7/12 - Circuits de commande de lignes de bits, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
G11C 11/4063 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation
A control circuit (200) and a memory (300). The control circuit (200) comprises a reset signal generation circuit (220) and a test mode circuit (230). The reset signal generation circuit (220) is used for receiving a control signal and a test mode entry signal, and generating and outputting a test mode reset signal according to the control signal and the test mode entry signal. The test mode circuit (230) is used for resetting and outputting a test mode signal according to the test mode reset signal, wherein the test mode signal indicates duty cycle adjustment of a clock signal.
A memory, comprising a compression circuit and a data input/output selector. An input end of the compression circuit receives read data transmitted by means of transmission paths of a plurality of data input/output pins, and respectively compresses the read data transmitted by means of the transmission paths of the data input/output pins to obtain a plurality of pieces of compressed data. A first input end of the data input/output selector is connected to an output end of the compression circuit to receive the plurality of pieces of compressed data, and the data input/output selector is used for transmitting the plurality of pieces of compressed data to a target data input/output pin in a test mode, wherein the target data input/output pin is any one of the plurality of data input/output pins.
Disclosed is a memory, comprising: a first input end of a data input/output selector receiving serial data received by means of a target data input/output pin, wherein the data input/output selector is used for respectively transmitting, in a test mode and to a transmission path corresponding to each data input/output pin in the memory, each bit of data in the serial data, which is received by means of the target data input/output pin, and the target data input/output pin is any one of a plurality of data input/output pins in the memory.
The present disclosure relates to a memory structure and a preparation method therefor. The preparation method for the memory structure comprises: providing a substrate, wherein the substrate comprises a base substrate, a first dielectric layer and a first substrate layer, and the first dielectric layer is located between the base substrate and the first substrate layer; forming a first circuit structure on the basis of the first substrate layer; flipping over the substrate, so that the first dielectric layer is located above the first circuit structure; and forming a second circuit structure above the first dielectric layer, and forming a conductive structure connecting the first circuit structure and the second circuit structure.
The present disclosure relates to a semiconductor structure and a forming method therefor. The semiconductor structure comprises: an active pillar group, a word line group, and a bit line. The active pillar group comprises a first active pillar and a second active pillar; the first active pillar comprises a first inner surface and a first outer surface; and the second active pillar comprises a second inner surface and a second outer surface. The word line group comprises a first word line and a second word line; the first word line is distributed around the first outer surface of the first active pillar; and the second word line is distributed around the second outer surface of the second active pillar. The bit line is electrically connected to the first active pillar and the second active pillar in the active pillar group.
A timing signal generator (10), a method, and a memory. The timing signal generator (10) comprises: a delay chain module (11) configured to delay a first command signal to generate a first edge timestamp signal, and delay a second command signal to generate a second edge timestamp signal; and a signal generator (12) configured to generate and output a target pulse signal by means of the first edge timestamp signal and the second edge timestamp signal.
The present disclosure relates to a semiconductor structure and a manufacturing method therefor. The manufacturing method comprises: providing a temporary substrate (1), wherein the temporary substrate (1) has an array region (1A); in the array region (1A) of the temporary substrate (1), forming a plurality of first semiconductor pillars (21) arranged in rows in a first direction, wherein a first spacing (d1) is provided between adjacent first semiconductor pillars (21) in the first direction; forming a plurality of word lines (4) extending in the first direction and arranged at intervals, wherein the word lines (4) are formed on side walls of the corresponding first semiconductor pillars (21); forming a plurality of bit lines (7) extending in a second direction and arranged at intervals, wherein the bit lines (7) are formed on top faces of the corresponding first semiconductor pillars (21), and the first direction intersects the second direction; bonding the temporary substrate (1) to a bearing substrate (8); and grinding a back side of the temporary substrate (1) until the first semiconductor pillars (21) are exposed.
The present application relates to a fuse array circuit and a memory. The fuse array circuit comprises: column selection signal lines (10), programming voltage line groups (20), at least one first fuse unit (30), and at least one second fuse unit (40), wherein each programming voltage line group (20) comprises an even programming voltage line (21) and an odd programming voltage line (22); a first end of each first fuse unit (30) is connected to a column selection signal line (10), and a second end of the first fuse unit (30) is connected to an even programming voltage line (21); a first end of each second fuse unit (40) is connected to a column selection signal line (10), and a second end of the second fuse unit (40) is connected to an odd programming voltage line (22); and the first fuse unit (30) corresponds to the second fuse unit (40) on a one-to-one basis, the first fuse unit (30) and the corresponding second fuse unit (40) share the same column selection signal line (10), and the time at which a signal transmitted by the even programming voltage line (21) is at an active level is different from the time at which a signal transmitted by the odd programming voltage line (22) is at an active level.
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
G11C 17/18 - Circuits auxiliaires, p.ex. pour l'écriture dans la mémoire
39.
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
The present disclosure relates to a semiconductor structure and a preparation method therefor. The preparation method comprises: providing a substrate; forming a vertical stacking structure on the substrate, the vertical stacking structure comprising a transistor region, a bit line region and a capacitor region, the bit line region and the capacitor region being located at two opposite sides of the transistor region along a first direction, respectively, and spaced apart from the transistor region, and the vertical stacking structure comprising a patterned sacrificial layer and a patterned active layer which are alternately stacked; forming a first trench between the transistor region and the bit line region, and between the transistor region and the capacitor region, the vertical stacked structure of the first trench exposing the transistor region being perpendicular to a sidewall in the first direction; removing at least a portion of the patterned sacrificial layer of the transistor region along the first trench; and forming a word line structure, the word line structure extending in the vertical direction and being in contact with the patterned active layer of the transistor region.
A register, comprising a state latch circuit, an output circuit and a state transition circuit. The output circuit is connected to the state latch circuit; the state latch circuit latches, at an output end, a plurality of pieces of current state data of an input end under triggering of one clock pulse signal; the state transition circuit is connected to the state latch circuit; the state transition circuit performs a logic operation on a multi-bit current state output and then outputs multi-bit next state data; and the output circuit performs a logic operation on the multi-bit current state output and then outputs multi-bit output data.
G11C 19/28 - Mémoires numériques dans lesquelles l'information est déplacée par échelons, p.ex. registres à décalage utilisant des éléments semi-conducteurs
G06F 7/58 - Générateurs de nombres aléatoires ou pseudo-aléatoires
41.
ANTI-FUSE STRUCTURE AND PREPARATION METHOD THEREFOR
The present disclosure provides an anti-fuse structure and a preparation method therefor. The anti-fuse structure (100) comprises a bit line structure (10) and a gating structure (20) electrically connected to the bit line structure (10). The gating structure (20) comprises a variable resistance structure (21), a threshold gating structure (22) and a word line structure (23) which are stacked in sequence. The variable resistance structure (21) is adjacent to the bit line structure (10). The stacking direction of the variable resistance structure (21), the threshold gating structure (22) and the word line structure (23) intersects with the thickness direction of the bit line structure (10).
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
42.
ANTIFUSE STRUCTURE, PREPARATION METHOD THEREFOR, ANTIFUSE ARRAY STRUCTURE, AND MEMORY
The present disclosure relates to an antifuse structure, a preparation method therefor, an antifuse array structure, and a memory. The anti-fuse structure (100) comprises a bit line structure (10), word line structures (40), and a variable resistance structure (20) and a threshold gating structure (30) located between the bit line structure (10) and each word line structure (40). The variable resistance structures (20) are configured to change from a high resistance state to a low resistance state at a preset programming voltage. The threshold gating structures (30) are configured to be gated at a threshold voltage.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
43.
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR
Provided in the present disclosure are a semiconductor structure and a manufacturing method therefor. The manufacturing method comprises: forming a plurality of laminated structures, which are sequentially stacked, wherein a plurality of first electrodes, which are arranged at intervals, are formed in each laminated structure, and the plurality of first electrodes in two adjacent laminated structures correspond to and are in contact with each other; exposing at least part of the peripheral surface of each first electrode in each laminated structure; at least forming a dielectric layer on at least part of the surface of each first electrode; and forming a second electrode on the dielectric layer.
Provided in the present disclosure are an anti-fuse device and a manufacturing method therefor, and an anti-fuse array and an operation method therefor. The anti-fuse device comprises a first connecting end, a second connecting end and a dielectric layer. The first connecting end comprises a first doped region and a second doped region arranged below the first doped region, wherein the conduction type of the first doped region is opposite to the conduction type of the second doped region, and the first doped region and the second doped region are connected and form a PN junction. The second connecting end at least covers the second doped region. The dielectric layer is arranged between the second connecting end and the second doped region, and the second connecting end and the second doped region are spaced apart by means of the dielectric layer.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H10B 20/20 - Dispositifs ROM programmable électriquement [PROM] comprenant des composants à effet de champ
H10B 20/25 - Dispositifs ROM programmable une seule fois, p.ex. utilisant des jonctions électriquement fusibles
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
45.
SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREFOR, AND MEMORY
A semiconductor structure and a forming method therefor, and a memory. The forming method comprises: forming a first barrier layer (21), a second barrier layer (22) and a third barrier layer (23), wherein the thickness of the first barrier layer (21) is greater than the thickness of the second barrier layer (22) and the thickness of the third barrier layer (23), the first barrier layer (21) covers a channel region (12), part of a first doped region (11) and part of a second doped region (13), the second barrier layer (22) covers the first doped region (11), and the third barrier layer (23) covers the second doped region (13); forming a first doped layer (3) on a side wall of the first barrier layer (21), the surface of the second barrier layer (22) and the surface of the third barrier layer (23); forming a second doped layer (4) on the first doped layer (3), wherein the concentration of target ions in the second doped layer (4) is greater than the concentration of target ions in the first doped layer (3); and performing thermal annealing on the first doped layer (3) and the second doped layer (4).
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
46.
SEMICONDUCTOR PACKAGING STRUCTURE AND FORMATION METHOD THEREOF
The present disclosure relates to a semiconductor packaging structure and a formation method thereof. The semiconductor packaging structure comprises: a packaging substrate; an adapter plate located on and electrically connected to the packaging substrate; a control chip, located on a first plane of the adapter plate; a chip stacking structure, located on the first plane of the adapter plate and comprising: a first semiconductor chip connected to the adapter plate; and a second semiconductor chip stacking structure located on the first semiconductor chip and comprising a plurality of second semiconductor chips successively stacked along a first direction, the first direction being parallel to the first plane of the adapter plate; and the second semiconductor chips being connected via a bonding layer.
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
The embodiments of the present disclosure provide a read/write circuit and a memory. The read/write circuit comprises: a write drive circuit used, according to a write control signal, for writing data to be written into a global data line; a read/write conversion circuit used, according to a write enable signal, for writing the data on the global data line to a local data line and to a complementary local data line, and additionally being used, according to a read enable signal, for reading, to the global data line and to a complementary global data line, the data on the local data line and on the complementary local data line; and a read drive circuit, used for amplifying the data on the global data line and on the complementary global data line, and for generating target read-out data.
Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a first insulating layer, a dummy active region and a second insulating layer which are located in the first insulating layer, a first sub-trench located in the dummy active region, a second sub-trench located in the second insulating layer, and a transistor comprising a channel material layer, a gate dielectric layer, and a gate conductive layer; the bottom surface of the first sub-trench is higher than the bottom surface of the second sub-trench; the channel material layer conformally covers the first sub-trench, the top surface of the dummy active region, and the sidewall of the dummy active region exposed by the second sub-trench; the channel material layer located on the sidewall of the dummy active region exposed by the second sub-trench is covered by the gate dielectric layer and the gate conductive layer.
Disclosed in the embodiments of the present disclosure are a refresh control circuit and a memory. The refresh control circuit comprises a flag signal generation module, an address sampling module and an execution module, wherein the flag signal generation module is configured to generate n refresh flag signals according to continuously received refresh commands; the address sampling module is configured to receive the n refresh flag signals, and sequentially select and output, in response to the n refresh flag signals, n hammer row addresses which are enabled for the maximum number of times; and the execution module is configured to sequentially receive the n hammer row addresses, and sequentially execute a refresh operation on adjacent victim row addresses of the n hammer row addresses.
Disclosed in the embodiments of the present disclosure are a refresh circuit and a memory. The refresh circuit comprises: a refresh command detection module, which is configured to receive refresh commands, count the refresh commands to generate a count value, and generate n address selection signals according to the count value, n being a positive integer; a victim row address output module, which is configured to receive the address selection signals, and sequentially select and output all or some of 2n victim row addresses associated with a hammer row address; and an execution module, which is configured to execute a refresh operation on the 2n victim row addresses during execution of the current refresh command.
The embodiments of the present disclosure provide a programmable non-volatile memory and an operation method. The memory comprises: a plurality of protection transistors and a voltage conversion circuit, each protection transistor having a first end connected to a bit line, and a second end and a gate each connected to a power supply node; the voltage conversion circuit is connected to a first node and a second node, and is configured for: receiving an input signal; during a programming operation, operating in response to the input signal so as to conduct a transmission path between the power supply node and the first node; and during a read operation, operating in response to the input signal so as to conduct a transmission path between the power supply node and the second node; wherein the input signal has a different electrical level during the programming operation and during the read operation, and a second voltage and a first voltage satisfy: 0
Provided in the embodiments of the present disclosure are a packaging substrate, and a semiconductor structure and an electronic device having same. The packaging substrate comprises a first packaging layer and a second packaging layer which are parallel in a third direction, wherein the second packaging layer is grounded. The first packaging layer comprises a plurality of pads, wherein the projection of each pad on the second packaging layer forms one coupling area, part of the coupling area being hollowed out.
Disclosed are a semiconductor structure manufacturing method, and a semiconductor structure. During the manufacture of a semiconductor structure, bit line structures are formed in multiple independently-arranged active regions, and a first groove portion and a second groove portion are formed between the bit line structures. A first width of the first groove portion is greater than a second width of the second groove portion. The second groove portion is located over the first groove portion and is connected to the first groove portion. The first groove portion and the second groove portion are filled to form a storage node contact structure.
The present disclosure provides a transistor and a fabrication method therefor. A substrate of the transistor is provided with a first recess. A first source-drain area and a second source-drain area are located on two sides of the first recess, respectively, and the distance between the first source-drain area and the first recess is smaller. A first portion of a gate is located in the first recess, and a second portion is located on the first portion. The center line of the second portion and the second source-drain area are located on the same side of the center line of the first portion. A gate dielectric layer is arranged between the gate and an active area.
Embodiments of the present disclosure provide a semiconductor structure and a forming method therefor. The method comprises: providing a substrate comprising an active region, wherein the active region comprises a first protruding portion, a main body portion and a second protruding portion; forming, on the surface of the active region, first side wall layers located on the side wall of a gate structure, wherein an opening is formed between the first side wall layers, and the opening at least exposes part of the first protruding portion and part of the second protruding portion; and performing first ion implantation on the exposed first protruding portion and the exposed second protruding portion by using first ions.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
The embodiments of the present disclosure provide a control circuit and a memory. The control circuit can comprise: a command adjustment module, used for performing pulse width adjustment on a write command signal according to a first clock signal, obtaining a first output signal; a signal sampling module, used for sampling the first output signal according to the first clock signal, obtaining a second output signal; and a delay shift module, used for performing first delay processing on the second output signal, generating a first intermediate signal, and, according to the second clock signal, performing sampling and shift processing on the first intermediate signal, obtaining a third output signal; wherein a time interval between a falling edge of the first intermediate signal and a rising edge of the second clock signal satisfies a preset margin.
A repair circuit and method, a memory and an electronic device. The repair circuit and method are applied to a memory comprising a plurality of storage blocks; each storage block has its own candidate repair code, the candidate repair code indicating that redundant rows in the storage block are all occupied, or an unoccupied redundant row having the highest priority in the storage block. The method comprises: when there is an invalid row in the memory, selecting and outputting a target repair code from amongst the multiple candidate repair codes; and using the target repair code to perform redundancy repair processing on the invalid row.
An antifuse structure (500), a forming method therefor and an antifuse array. The antifuse structure (500) comprises a substrate (1), two dielectric layers (3, 4) and two electrical connection ends (2, 5). The substrate (1) comprises a first doped region (11) and a second doped region (12) which abut on each other in a first direction (x), the second doped region (12) having a first surface (121) and a second surface (122), the first surface (121) extending in the first direction (x), and the second surface (122) abutting on the side of the first surface (121) away from the first doped region (11); a first electrical connection end (2) is connected to the first doped region (11); a first dielectric layer (3) is located on the first surface (121) of the second doped region (12); a second dielectric layer (4) is located on the second surface (122) of the second doped region (12); and a second electrical connection end (5) covers the surfaces of the first dielectric layer (3) and the second dielectric layer (4), and is insulated from the first electrical connection end (2).
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
Disclosed is a manufacturing method for a semiconductor structure. The method comprises: providing a substrate; forming in the substrate a plurality of parallel first grooves; then cleaning and drying the plurality of first grooves, and performing first filling on the first grooves by using an insulating material; then forming in the substrate a plurality of second grooves parallel to the first grooves; and cleaning and drying the plurality of second grooves, and then performing second filling on the second grooves by using the insulating material, wherein at least one second groove is located between two adjacent first grooves.
Disclosed are a semiconductor package structure and a manufacturing method. At least one vortex tube structure is arranged in the semiconductor package structure. The vortex tube structure is used for separating compressed gas into high-temperature gas and low-temperature gas, and separately releasing the high-temperature gas and the low-temperature gas to the outside of the semiconductor package structure. Part of heat of the semiconductor package structure is taken away by means of flowing of the low-temperature gas.
H01L 23/467 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de gaz, p.ex. d'air
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
61.
ADDRESS SELECTION CIRCUIT, ADDRESS SELECTION METHOD, REFRESH CONTROL CIRCUIT AND STORAGE SYSTEM
Disclosed are an address selection circuit, an address selection method, a refresh control circuit and a storage system. The address selection circuit comprises: multiple address register units, which are configured to store row addresses; a state register unit, which is configured to store and output an address state signal, each bit of the address state signal representing a valid state or an invalid state of a corresponding address register unit, the valid state indicating that a row address is stored in the address register unit, and the invalid state indicating that a row address is not stored in the address register unit; a shift signal generation circuit, which is used to generate a shift signal according to the address state signal; a shift selection circuit, which is used to select multiple address register units according to the shift signal, and make the row address stored in a selected address register unit a row hammer address.
A package structure and a manufacturing method therefor. The method comprises: providing a first wafer (1), a first chip (2) and a plurality of chip stacks (3), wherein the first wafer (1) comprises a plurality of bearing areas (13); arranging the chip stacks (3) in the bearing areas (13); arranging the first chip (2) on the plurality of chip stacks (3); bonding the first wafer (1), the first chip (2) and the chip stacks (3); forming a package layer (7) to package the first wafer (1), the first chip (2) and the chip stacks (3), which are bonded together; and forming, on the side of the first wafer (1) that is away from the chip stacks (3), an external connection end (16) which is at least electrically connected to the chip stacks (3).
H01L 21/50 - Assemblage de dispositifs à semi-conducteurs en utilisant des procédés ou des appareils non couverts par l'un uniquement des groupes
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
Disclosed is a memory layout. The memory layout comprises: a plurality of storage arrays (10), which are arranged in a preset direction; and a local amplifier (200), which is located between adjacent storage arrays (10), the local amplifier (200) being used for implementing data transmission between a local data line and a global data line, and the local amplifier (200) comprising a plurality of transistors (210), which are arranged in a direction perpendicular to the preset direction, wherein the plurality of transistors (210) have a common active region (211), the plurality of transistors (210) have respective corresponding gate structures (212), the plurality of gate structures (212) are located in the active region (211) and are arranged at intervals in the direction perpendicular to the preset direction, and the gate structures (212) extend in the preset direction. The local amplifier (200) further comprises a plurality of conductive plugs (213), which are located in the active region (211) and spaced apart from the gate structures (212), wherein the conductive plugs (213) extend in the preset direction.
Disclosed are a semiconductor structure and a memory. The semiconductor structure comprises: a conductive layer, which comprises at least two groups of word lines, wherein each group of word lines comprises first-type word lines and second-type word lines, which extend in a first direction, and the first-type word lines and the second-type word lines are alternately arranged in a second direction; and a device layer, which at least comprises two drive units, wherein each drive unit drives one first-type word line and one second-type word line, which are adjacent to each other in one group of word lines. Each drive unit comprises a first drive structure and a second drive structure, wherein the first drive structure comprises a first PMOS transistor, a first NMOS transistor and a second NMOS transistor; the second drive structure comprises a second PMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the first PMOS transistor, the first NMOS transistor and the second NMOS transistor are connected to the first-type word lines; and the second PMOS transistor, the third NMOS transistor and the fourth NMOS transistor are connected to the second-type word lines.
Disclosed are an address selection circuit, an address selection method, a refresh control circuit, and a storage system. The address selection circuit comprises: a comparison unit and a register unit; an input end of the comparison unit being connected to an output end of the register unit; and an output end of the comparison unit being connected to an input end of the register unit; the comparison unit being configured for comparing a first count value outputted by the register unit against a different first count value which has not yet been compared, and outputting the larger first count value to the register unit; and the register unit being configured for storing an initial first count value or the larger first count value outputted by the comparison unit; the first count value representing the number of times a row address has been accessed; and the register unit being further configured to output the largest count value of a plurality of first count values.
Disclosed are an address selection circuit, an address selection method, a refresh control circuit, and a storage system. The address selection circuit comprises: a comparator circuit, configured to output the maximum count value among a plurality of first count values by means of multiple rounds of comparison, wherein in each round of comparison, the comparator circuit compares one first count value stored by the comparator circuit with another first count value which is not compared, so as to replace the first count value stored by the comparator circuit with the larger first count value, and the first count value represents the number of times of access to a row address; and a row hammer address generation circuit, configured to select a row address corresponding to the larger first count value in each round of comparison to replace a row address stored by the row hammer address generation circuit, and after the last round of comparison, output the row address stored by the row hammer address generation circuit as a row hammer address.
Disclosed are an address selection circuit and method, a refresh control circuit, and a storage system. The address selection circuit comprises: a plurality of address register units; an address state signal generation circuit for outputting an address state signal, each bit of the address state signal indicating a valid or invalid state of a corresponding address register unit; and a row hammer address generation circuit for outputting a pointer, shifting the pointer according to the address state signal, and using, as a row hammer address, a row address stored in an address register unit to which the shifted pointer points. The address state signal generation circuit is further used for determining, according to the position to which the shifted pointer points, the sequence of the plurality of address register units corresponding to a plurality of bits of an address state signal outputted next time.
Disclosed are an address selection circuit, an address selection method, a refresh control circuit, and a storage system. The address selection circuit comprises: a page table, wherein each page table item comprises a row address, and a first count value for representing the number of times the row address is accessed; a second counting unit, which is configured to generate a second count value, wherein the second count value is used as an index value corresponding to one page table item; a comparison circuit, which is used for outputting the maximum count value among a plurality of first count values by means of multiple rounds of comparison; a row hammer address generation circuit, which is used for outputting, as a row hammer address, a row address corresponding to the maximum count value; and a row hammer index generation circuit, which is is used for outputting, as a row hammer index value, an index value corresponding to the maximum count value, wherein the row hammer index value is used for searching for a page table item corresponding to the maximum count value.
A semiconductor structure comprises a substrate, wherein the substrate is provided with a plurality of transistor groups (T0) which are arranged in a first direction (X), and each transistor group (T0) comprises an active region (1). The active region (1) comprises a first drain region (D1), a first channel region (C1), a source region (S), a second channel region (C2) and a second drain region (D2) which are sequentially arranged in the first direction (X), wherein the first drain region (D1) comprises a first protruding region (D11), and the second drain region (D2) comprises a second protruding region (D21); the first protruding region (D11) and the second protruding region (D21) are both arranged in a manner of protruding away from the source region (S); the first protruding region (D11) and the second protruding region (D21), which are opposite each other, of adjacent transistor groups (T0) in the first direction (X) are arranged in a staggered manner in the first direction (X); and an isolation structure (5) is further provided between adjacent active regions (1), the first direction (X) being parallel to the substrate.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
Disclosed are a memory circuit and a memory layout. The memory layout comprises an amplifier module comprising a plurality of amplifier units. Each amplifier unit comprises a first transistor, a second transistor and a third transistor. Two first transistors constitute a first transistor group. A second transistor and a third transistor connected to a first transistor constitute a second transistor group. Second transistor groups are respectively arranged on two opposite sides of the first transistor group in a second direction. In the second direction, for the two first transistors of the first transistor group, one of the first transistors is connected to the second transistor and the third transistor in the second transistor group on the adjacent side, and the other first transistor is connected to the second transistor and the third transistor in the second transistor group on the adjacent other side.
Disclosed are a storage circuit and a memory. The storage circuit comprises 2n word lines, at least one word line driver and 2n protection modules, wherein n is a positive integer. The at least one word line driver is correspondingly connected to first ends of the 2n word lines. Each protection module is correspondingly connected to a second end of one word line. Each word line driver is configured to receive and respond to a drive enable signal, so as to activate a corresponding word line. Each protection module is configured to receive a protection enable signal, and if the protection enable signal represents that the word line connected to the protection module is not activated, ground the second end of the word line.
The present disclosure relates to a semiconductor structure and a method for forming same. The semiconductor structure comprises a substrate, a strained layer and a filling layer, wherein the substrate comprises a first groove, an active region located below the first groove, and a protrusion which is connected to the active region and protrudes in a first direction from the active region, the protrusion being located in the first groove and protruding in the first direction from the bottom surface of the first groove; the strained layer covers at least the surface of the protrusion; and the filling layer fills the first groove and covers the strained layer, the filling layer is of a solid structure, and the lattice constant of the filling layer is different from that of the strained layer.
Disclosed are a semiconductor structure and a forming method therefor. The semiconductor structure comprises: a substrate, the top surface of the substrate being provided with a support structure and a capacitor hole; and a capacitor structure comprising a first electrode layer, a dielectric layer, a second electrode layer, and a filling layer, wherein the first electrode layer covers the inner wall of the capacitor hole, the filling layer covers the inner surface of the lower portion of the first electrode layer and fills the lower portion of the capacitor hole, the dielectric layer at least covers the surface of the first electrode layer, and the second electrode layer covers the surface of the dielectric layer.
Disclosed are a storage circuit and a memory. The storage circuit comprises: a plurality of sensing amplification modules and a plurality of delay adjustment modules. The delay adjustment modules are correspondingly connected to the sensing amplification modules, and each delay adjustment module is configured to adjust the delay amount of a turn-on signal in response to a delay enable signal and transmit the adjusted turn-on signal to the corresponding sensing amplification module. Each sensing amplification module is configured to be turned on for operation in response to the adjusted turn-on signal.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
The present disclosure provides a delay generation circuit and method, and a memory. The delay generation circuit comprises: a basic delay generation module, used for performing sampling and delay processing on a command signal according to a first clock signal to generate a first delay signal; an adjustable delay generation module, used for performing sampling processing on the first delay signal according to a first delay clock signal to obtain a second delay signal, and performing sampling processing on the first delay signal according to a second delay clock signal to obtain a third delay signal; and a selection module, used for performing signal selection on the second delay signal and the third delay signal according to a first mode signal and outputting a target delay signal.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p.ex. des signaux d'horloge
Disclosed are a semiconductor device and a memory. The semiconductor device comprises a switch structure, and amplification structures located on two opposite sides of the switch structure in a first direction, wherein each amplification structure comprises a sense amplification structure and an isolation unit; the switch structure comprises a pre-charge balance structure, and a first center line extending in the first direction; and in a second direction perpendicular to the first direction, the isolation unit is located between the first center line and the pre-charge balance structure.
Disclosed are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a first substrate having an array area and a peripheral area. A plurality of bit lines are provided on the first substrate of the array area. An insulating layer covers the surface of the first substrate. A second substrate is provided on the bit lines and the insulating layer. The second substrate comprises a plurality of semiconductor pillars located in the array area and a semiconductor layer located in the peripheral area. A plurality of word lines extending in a second direction are located between adjacent semiconductor pillars. The top surface of each semiconductor pillar is in electrical contact with the bottom of a capacitor structure. A part of the surface of the semiconductor layer is provided with a plurality of gate structures.
The present disclosure relates to the field of semiconductors, and relates to a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises: a substrate, a first dielectric layer and a plurality of capacitors. The substrate has an array area and a peripheral area arranged on at least one side of the array area. The first dielectric layer is arranged on the substrate, and is provided with a plurality of capacitor grooves located in the array area. The part of the first dielectric layer located in the array area forms a first isolation structure, and the part of the first dielectric layer located in the peripheral area forms a second isolation structure. The plurality of capacitors are respectively located in corresponding capacitor grooves.
Embodiments of the present disclosure relate to a semiconductor structure and a preparation method therefor. The preparation method comprises: providing a substrate; forming a vertical stacking structure on the substrate, wherein the vertical stacking structure comprises a word line area, and a first area, a second area and a third area which are sequentially connected and arranged in a first direction, the first area and the third area are each provided with a first opening, the first openings penetrate through the vertical stacking structure in the vertical direction, the word line area extends in a second direction and is connected to the adjacent second area, the vertical stacking structure comprises a patterned sacrificial layer and a patterned active layer which are alternately stacked in the vertical direction, and the second direction intersects with the first direction; removing the patterned sacrificial layer in the first area, the second area and the third area on the basis of the first openings; and removing the patterned sacrificial layer in the word line area, and forming a word line structure on the upper surface and the lower surface of the patterned active layer in the word line area. According to the preparation method, a good etching profile can be obtained, and the production yield and the product reliability are improved.
The present disclosure relates to a write-leveling system and a write-leveling method. The write-leveling system comprises: a controller and a storage chip, wherein the controller is used for providing a clock signal and a data gating signal for the storage chip; a first adjustment time is stored in the storage chip, and the first adjustment time is used for representing a path delay difference between the clock signal and the data gating signal within the storage chip; and on the basis of the first adjustment time, the controller adjusts a sending delay for sending the data gating signal to the storage chip, and continuously adjusts the sending delay until a trigger edge of the clock signal that is received by the storage chip is aligned with a trigger edge of the data gating signal.
Disclosed are a semiconductor structure and a manufacturing method therefor. The manufacturing method comprises: providing a substrate, wherein the substrate comprises semiconductor columns and first isolation columns, a plurality of semiconductor columns extend in a first direction and are arranged in an array in a second direction and a third direction, a plurality of first isolation columns extend in the third direction and are arranged in the second direction, each of the first isolation columns penetrates through a row of semiconductor columns arranged in the third direction, and the semiconductor columns encircle side faces of the first isolation columns; removing some of the first isolation columns to form first through holes, wherein the first through holes extend in the third direction, and the semiconductor columns are exposed out of two opposite sides of the first through holes; and forming a word line structure in the first through holes.
The present disclosure relates to the technical field of semiconductors, and relates to a semiconductor device and a manufacturing method therefor. The manufacturing method of the present disclosure comprises: providing a substrate with a surface containing silicon; and depositing a first material on the surface of the substrate, wherein the first material reacts with silicon on the surface of the substrate to form a cross-linked structure layer; forming a nickel nitride layer on the surface of the cross-linked structure layer; and subjecting the substrate, the cross-linked structure layer and the nickel nitride layer to rapid heat treatment, so as to form a nickel silicide thin film layer. The manufacturing method of the present disclosure can reduce the contact resistance of the nickel silicide thin film layer. (FIG. 1)
Disclosed are a memory circuit and a memory thereof. The memory circuit comprises: multiple memory blocks, wherein each memory block comprises a first memory part, a second memory part and a third memory part that are sequentially arranged in a first direction; a part of the second memory part and the first memory part jointly form a first memory sub-block, and the remaining part of the second memory part and the third memory part jointly form a second memory sub-block; the first memory sub-block is used to store either high-order bytes or low-order bytes, and the second memory sub-block is used for storing the other of the high-order bytes and the low-order bytes; and in the first direction, block selection addresses of different memory parts arranged in parallel are different.
G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
The present disclosure provides a signal generation circuit. A trigger circuit receives a target clock signal and generates a first command signal in response to an initial command signal. A selection circuit receives a coded signal of a mode register and generates a first selection signal and a second selection signal, the coded signal corresponding to different burst length modes. An output circuit receives the first command signal and generates a target command signal in response to the first selection signal and the second selection signal, the target command signal having an effective level length corresponding to the burst length mode.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p.ex. des signaux d'horloge
H03K 19/173 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
Provided in the present disclosure are a refresh control circuit and a memory thereof. The refresh control circuit comprises an address output circuit, which outputs a first target row address in response to a first refresh signal and outputs one of a second target row address or a row hammer victim address in response to a second refresh signal and a row hammer refresh enable signal, wherein a phase in which the first refresh signal is in an active state is different from a phase in which the second refresh signal is in an active state; and the first target row address corresponds to at least one word line in a storage array, and the second target row address corresponds to at least one redundant word line.
Disclosed in the embodiments of the present disclosure are a defective pixel repair circuit, and a memory. The defective pixel repair circuit comprises: an address register circuit, a detection circuit and an address search circuit, wherein the address register circuit is used for receiving two defective pixel addresses and registering same; the detection circuit is used for acquiring the two defective pixel addresses, outputting a first control signal when detecting that the two defective pixel addresses belong to the same row, and outputting a second control signal when detecting that the two defective pixel addresses do not belong to the same row; and the address search circuit is controlled by the first control signal to output a row repair address jointly corresponding to the two defective pixel addresses, or is controlled by the second control signal to output a column repair address corresponding to each defective pixel address.
The present disclosure relates to a semiconductor structure and a preparation method therefor. The preparation method for a semiconductor structure comprises: forming, within a semiconductor substrate, a plurality of first isolation trenches arranged at intervals; forming, within the semiconductor substrate, a plurality of gap trenches arranged at intervals, wherein the extension directions of the gap trenches intersect with the extension directions of the first isolation trenches; forming a first patterned mask layer which covers and partially fills in the gap trenches, wherein air gaps are formed between the first patterned mask layer and the bottoms of the gap trenches; and etching the semiconductor substrate by using the first patterned mask layer as a mask, so as to form second isolation trenches, wherein the semiconductor substrate is isolated into a plurality of active pillars by means of the second isolation trenches and the first isolation trenches.
The present disclosure relates to a semiconductor device and a preparation method therefor. The preparation method for a semiconductor device comprises: providing a substrate, wherein the substrate is provided with an array area and a peripheral area, the array area comprises a first area and a second area, and the first area is located between the peripheral area and the second area; forming a first support layer on the substrate, wherein the thickness of the first support layer in the first area is greater than the thickness of the first support layer in the second area; and manufacturing a capacitor in the array area, such that the bottom of the capacitor is formed within the first support layer.
Provided in the embodiments of the present disclosure is a test method for a memory. The memory comprises a main storage module and an ECC storage module. The method comprises: receiving first write data in a first test mode, and performing copying and expansion on the first write data to obtain first test data, or receiving second write data in a second test mode, and performing calculation on the second write data by using an ECC algorithm, so as to obtain second test data, wherein the first test data is used for determining whether a read-write function of an ECC storage module and a read-write function of a main storage module are normal, and the second test data is used for determining whether the read-write function of the main storage module is normal; in response to a test mode signal, writing the first test data or the second test data into the ECC storage module as ECC check data, wherein the test mode signal is used for indicating the execution of the first test mode or the second test mode; and reading the ECC check data stored in the ECC storage module, and performing determination on the basis of the ECC check data.
Provided in the present disclosure are a refresh circuit and method, and a memory. The refresh circuit can store a weak address signal, and also counts refresh operations to generate a first count value, wherein the first count value is used for generating a row address signal; the refresh circuit outputs a switching flag signal on the basis of a comparison result between the first count value and a first threshold value; and on the basis of the switching flag signal, the refresh circuit selects one of the row address signal and the weak address signal as an address signal to be refreshed, and outputs same.
The present disclosure relates to a semiconductor structure and a forming method therefor. The forming method comprises: providing a substrate; sequentially forming a film layer to be etched, a first mask layer and a second mask layer on the surface of the substrate, the second mask layer comprising first patterns; etching the first mask layer along the first patterns to form a plurality of mask structures; forming isolation layers on the side walls of the mask structures; forming a third mask layer between the mask structures; removing the isolation layers to form a second pattern; and transferring the second pattern into said film layer to form a target pattern, wherein the etch selectivity ratio of said film layer with respect to the first mask layer is not less than the etch selectivity ratio of said film layer with respect to the third mask layer.
Disclosed are a semiconductor structure and a manufacturing method therefor. The manufacturing method comprises: providing a substrate, the substrate being provided with multiple mutually spaced active areas, and isolation structures located between every two adjacent active areas; performing first patterning process on the substrate to form a first contact hole exposing at least some of the active areas; forming a first capacitive contact layer in the first contact hole; forming a dielectric layer on the first capacitive contact layer and the substrate; performing second patterning process at least on the dielectric layer to form a second contact hole exposing part of the surface of the first capacitive contact layer; and forming a second capacitive contact layer in the second contact hole, the second capacitive contact layer and the first capacitive contact layer together forming a capacitive contact layer.
Disclosed are a manufacturing method for a semiconductor structure, and a semiconductor structure. The manufacturing method for the semiconductor structure comprises: providing a substrate; forming a dielectric layer on the substrate; forming on the dielectric layer a mask structure arranged in a spaced mode, the mask structure comprising a first pattern structure and a spacing structure covering the side wall of the first pattern structure; by using the mask structure as a mask, performing etching to form a first trench passing through the dielectric layer and extending into the substrate; forming a first supporting structure in the first trench; removing the first pattern structure; and by using the first supporting structure and the spacing structure as masks, performing etching to form a second trench passing through the dielectric layer and extending into the substrate, the first trench and the second trench dividing the substrate into a plurality of active areas.
Provided in the embodiments of the present disclosure are a semiconductor structure and a layout method therefor, and a column gating circuit and a memory. The semiconductor structure comprises: two rows of active structures arranged in a first direction, wherein each row of active structures comprises first active structures and second active structures which are arranged in a second direction, each active structure comprises a first portion, a second portion and a third portion which are connected in sequence in the second direction, and the third portion of each first active structure and the first portion of each second active structure are arranged in a staggered manner; and connection structures, wherein each connection structure covers and connects third sub-portions of the second portions of two first active structures adjacent in the first direction and first sub-portions of the second portions of two second active structures adjacent in the first direction.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
The present disclosure relates to the field of semiconductor circuit designs, and in particular to a power-on monitoring circuit and a memory. The power-on monitoring circuit comprises a monitoring circuit and a sensing circuit, wherein the monitoring circuit is configured to monitor a power source voltage and output an indication voltage, and the sensing circuit is configured to generate a power-on flag signal on the basis of the indication voltage. The monitoring circuit comprises: a first resistor string and a second resistor string, wherein a first end of the first resistor string is coupled to the power source voltage, a second end thereof is connected to a voltage division node, a first end of the second resistor string is connected to the voltage division node, a second end thereof is coupled to a grounding end, and a temperature coefficient of the first resistor string is greater than a temperature coefficient of the second resistor string; a driving transistor, wherein a first end of the driving transistor is coupled to the grounding end, a second end thereof is coupled to an output node of the indication voltage, and a control end thereof is connected to the voltage division node; and a voltage division resistor, wherein a first end of the voltage division resistor is coupled to the power source voltage, and a second end thereof is connected to the output node of the indication voltage.
Provided in the embodiments of the present disclosure are a refresh circuit and method, and a memory. The circuit comprises: a refresh command counting module, which is configured to count refresh commands, so as to generate a first count value; a refresh address generator, which is configured to output row address signals, and update the row address signals on the basis of a refresh operation; a weak address generator, which is configured to receive a refresh address selection signal, and output a plurality of weak address signals on the basis of the refresh commands when the refresh address selection signal is at a second level; and a refresh module, which is configured to execute, when the refresh address selection signal is received and in response to received refresh command signals, the refresh operation on storage rows corresponding to the row address signals or the plurality of weak address signals.
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/402 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge propre à chaque cellule de mémoire, c. à d. rafraîchissement interne
Provided in the embodiments of the present disclosure are a word line driving circuit and a memory. The word line driving circuit comprises: driving unit groups, which are connected to a plurality of word lines and are used for driving one of the word lines; and an equalization unit, which is connected between the plurality of word lines and is used for equalizing the potential between the plurality of word lines before one of the word lines is driven.
G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
Provided in the present disclosure are an anti-fuse array and a semiconductor structure. The anti-fuse array comprises: a plurality of first anti-fuse units, which are arranged in an array, wherein each first anti-fuse unit comprises a first selection device and a first program device; and a plurality of first program wires, which extend in a first direction, wherein control ends of first program devices located in the same row are all connected to the same first program wire, and each first program wire is provided with a first auxiliary structure.
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
Provided is a memory. The memory comprises a first voltage following branch (201), a first current generation branch (202), a voltage generation branch (203), a charge pump circuit (204), and a word line driving circuit (205), wherein the first voltage following branch (201) generates a first voltage signal having a negative temperature coefficient; according to the first voltage signal having a negative temperature coefficient, the first current generation branch (202) generates a first current signal having a negative temperature coefficient; according to the first current signal having a negative temperature coefficient, the voltage generation branch (203) generates a reference power source voltage signal having a negative temperature coefficient; according to the reference power source voltage signal, the charge pump circuit (204) generates a word line turn-on power source voltage having a negative temperature coefficient; and the word line driving circuit (205) receives the word line turn-on power source voltage, and is used for providing, when driving a word line, the word line turn-on power source voltage for the driven word line.
G11C 11/402 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge propre à chaque cellule de mémoire, c. à d. rafraîchissement interne
Disclosed are a control circuit and a semiconductor memory. The control circuit comprises a data input and output module. After check of CRC data fails, the data input and output module generates a CRC warning signal; and when the number of errors of CRC data reaches a CRC automatic disable threshold, said module generates a CRC check blocking signal. The CRC check blocking signal can prevent the data input and output module from generating a CRC warning signal.
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