Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate, a capacitor structure, a transistor structure, bit lines, and word lines. The capacitor structure is arranged on the substrate, the transistor structure is arranged on a side of the capacitor structure, one of a source and a drain of the transistor structure is electrically connected to the capacitor structure, a gate of the transistor structure is electrically connected to the word lines, and other one of the source and the drain of the transistor structure is electrically connected to the bit lines. A word line isolation structure is arranged between adjacent two of the word lines, and a bit line isolation structure is arranged between adjacent two of the bit lines. A width of the word line isolation structure is not equal to a width of the bit line isolation structure.
A semiconductor structure and a fabricating method are disclosed. The method includes: providing a substrate; forming a bit line contact structure and a bit line on the substrate; the bit line contact structure is located between the bit line and the substrate; performing ion doping treatment on the sidewalls of the lower part of the bit line contact structure to forming a doped region; performing nitridation treatment on the doped region to transform the doped region into a nitride structure
The disclosed semiconductor structure includes a conductive layer, a channel in the conductive layer. The inner wall of the channel is covered with a first dielectric layer. The thickness of the first dielectric layer is greater at the orifice of the channel than the thickness on the side away from the orifice; the first dielectric layer on the side close the orifice is covered with a second dielectric layer, and the second dielectric layer blocks the orifice; an air gap is formed in the first dielectric layer and the second dielectric layer, and the size of the air gap on the side away from the orifice is larger than the size of the air gap on the side close to the orifice. The present application can effectively reduce the parasitic capacitance of the conductive connection structure, alleviate its RC delay problem, and optimize the storage performance of the memory.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
4.
A SEMICONDUCTOR STRUCTURE AND METHOD MAKING THE SAME
A semiconductor structure and a method of fabricating the semiconductor structure are disclosed. The semiconductor structure includes: a carrying layer, a barrier layer, a solder layer and an adhesive layer. The barrier layer is located on the surface of the carrying layer, and there are openings in the barrier layer. The barrier layer includes multiple sub-barrier layers in a stack. The multiple sub-barrier layers respectively form a plurality of steps in the opening, and the heights of the plurality of steps decrease sequentially in a direction from outside of the opening to inside of the opening. A solder layer and an adhesive layer are located in the opening, and the adhesive layer covers the solder layer.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A delay measuring circuit includes a control oscillation module with its input terminal connected to its output terminal, which sequentially generates a number of time delay signals with a cycle time T after receiving first enable control signal; a target oscillating module receives a second enabling signal delayed by a first preset threshold than the first enabling signal; after the first preset time T1 is disconnected from the ground terminal/power supply terminal, each stage of the target unit in the target oscillating module connects at the second preset time T2. The level of the target unit turns over at first preset time T1, and target unit maintains logic level for second preset time T2; T1+T2=T/2, and N is an odd integer. So leakage current is reduced and mutual influence of the action current between the adjacent two-level target units are avoided, thus improving ring oscillator performance and reliability.
H03K 5/14 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de lignes à retard
H03K 5/19 - Contrôle de la configuration de trains d'impulsions
H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON
6.
ANTI-FUSE CIRCUIT AND ANTI-FUSE UNIT PROGRAMMING STATE VERIFICATION METHOD
An embodiment of the present disclosure provides an anti-fuse circuit, including: an anti-fuse unit; a programming circuit connected to the anti-fuse unit, and the programming circuit performs programming of the anti-fuse unit according to the programming control signal and the programming signal; the read unit reads the anti-fuse unit to obtain a data signal; the verification control unit controls the electrical connection between the reading unit and the anti-fuse unit according to the verification enable signal and the programming signal of the anti-fuse unit, when verifying the programming state of the anti-fuse unit. When the anti-fuse circuit verifies the programming state of the anti-fuse unit, it controls the electrical connection between the read unit and the anti-fuse unit according to the verification enable signal and the programming signal of the anti-fuse unit, to realize real-time verification of programming status.
G11C 17/18 - Circuits auxiliaires, p.ex. pour l'écriture dans la mémoire
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
The present disclosure provides an electronic device and a driving method. The electronic device comprises: a sensitivity amplifier and a voltage adjustment circuit. The sensitivity amplifier includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a control circuit. The control circuit is connected to the third node, the fourth node, and a preset voltage terminal. A first control signal terminal responds to the signal of the first control signal terminal to connect the preset voltage terminal and the third node and the fourth node. The preset voltage terminal inputs a preset voltage signal. The electronic device write a preset voltage signal of a suitable size to the sensitivity amplifier through the voltage adjustment circuit, so that the sensitivity amplifier has an appropriate voltage difference between the bit line and the complementary bit line during offset elimination.
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
A semiconductor structure includes: a core device region and an anti-fuse device region, disposed on a same substrate; a first dielectric layer, disposed on the substrate of the core device region and the anti-fuse device region, wherein the first dielectric layer has a first dielectric constant; a second dielectric layer, disposed on the first dielectric layer of the core device region; and a conductive layer, disposed on the second dielectric layer of the core device region and the first dielectric layer of the anti-fuse device region; wherein the second dielectric layer has a dielectric constant larger than the first dielectric constant.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
9.
Data transmission circuit, data transmission method and memory device
A data transmission circuit, method and memory device are provided. A comparison circuit is configured to compare global data with bus data to output a comparison result on whether the number of different bits between the global data and the bus data exceeds a preset threshold; a correction circuit is configured to check and/or correct the global data to generate corrected data; a first data conversion circuit is configured to invert the corrected data and transmit the inverted corrected data to the data bus when exceeding the preset threshold, and transmit the corrected data to the data bus when not exceeding the preset threshold, and the first data conversion circuit is further configured to output a mark signal; and a recovery circuit is configured to transmit data or inverted data on the data bus to a serial-parallel conversion circuit according to a value of the mark signal.
The disclosed semiconductor structure includes a window region, a transistor region, and a step region arranged in a first direction. The transistor region includes a word line region and a window region. The method making the semiconductor structure includes: forming active layers at intervals, forming dummy word line structures in the word line region and the step region covering the active layers at the same layer; forming a first isolation layer which a main body part and an interval part connected together, wherein the main body part is located in the window region, and the interval is located in the word line region and the step region between adjacent dummy word line structures; removing the active layers from the step region, removing the dummy word line structures; and forming a dielectric layer in the step region and the word line region. The embodiments improve the semiconductor structure's performance.
BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY (Chine)
Inventeur(s)
Shao, Guangsu
Xiao, Deyuan
Qiu, Yunsong
Abrégé
Embodiments provide a semiconductor structure and a fabrication method thereof, which relate to the field of semiconductor technology. The method for fabricating a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array in the substrate; and forming a gate arranged around each of the active pillars, where a projection of the gate on the active pillar covers a channel region of the active pillar. Along a direction perpendicular to the substrate, the gate includes a first conductive layer and a second conductive layer sequentially arranged in a stack, and a work function of the first conductive layer is different from a work function of the second conductive layer.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
The embodiments of the present application provide a semiconductor structure manufacturing method for forming a semiconductor structure. The method includes: forming a plurality of discrete transistor structures (102) on a substrate (101); forming a dielectric layer (111) covering the transistor structure (102); forming a plurality of metal lines (103) on the top surface of the dielectric layer (111); forming an opening (105) in the gap between two of the plurality of metal lines (103); the insulation layer (106) fills the opening (105), the dielectric constant of the insulating layer (106) is smaller than the dielectric constant of the dielectric layer, and therefore the insulating layer (106) reduces the parasitic capacitance between the metal lines (103) as well as the parasitic capacitance between the metal lines (103) and the transistor structure (102); this method discloses how to form plurality of metal lines in the chip array area, meanwhile keeping the parasitic capacitance between the formed metal lines and other conductive structures small.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
13.
An Apparatus and Method of Generating Chip Select Signals
A method and apparatus for generating a chip select signal include: sampling an external control signal to obtain a first and a second sampling signals; inputting the first sampling signal into a first vector file to generate a power supply control signal; inputting the second sampling signal into a second vector file to generate a chip select control signal; generating a chip select signal based on the power supply control signal and the chip select control signal, which include a high potential, a low potential and a high resistance state, the high potential voltages of the power supply control signal and the chip select control signal are different, and the low potential voltages of the power supply control signal and the chip select control signal are different. The disclosure realizes four different potentials for the chip select signals by applying two vector files.
The disclosed data transmission circuit and a memory include a sense amplifier circuit, a first sub-discharge path, a second sub-discharge path, and a discharge adjustment unit. The sense amplifier circuit generate amplified signals based on two terminals. The first sub-discharge path, in the read state, discharges at the first terminal to the discharge terminal based on the first data line signal; the second sub-discharge path, in reading state, discharges at the second terminal to the discharge terminal based on the discharge adjustment signa. The discharge adjustment unit is electrically connected to the second sub-discharge path and the control signal, but is not connected to the first sub-discharge path, and is used for generating the discharge adjustment signal based on the control signal, to adjust the discharge capacity of the second sub-discharge path. The present disclosure improves the anti-interference ability and data transmission efficiency of the data transmission circuit.
A read/write switching circuit and a memory are provided. The read/write switching circuit includes: a first data line (Ldat) connected to a bit line (BL) through a column select module, a first complementary data line (Ldat#) connected to a complementary bit line through the column select module, a second data line (Gdat) and a second complementary data line (Gdat#), and further includes: a read/write switching module (101) configured to transmit data between the first data line and the second data line and transmit data between the first complementary data line (Ldat#) and the second complementary data line (Gdat#)during read and write operations in response to read and write control signals; and an amplification module (102) connected between the first data line (Ldat) and the first complementary data line (Ldat#) and configured to amplify data of the first data line (Ldat) and data of the first complementary data line (Ldat#).
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
A semiconductor die, a semiconductor device and a method for forming a semiconductor device are provided. The semiconductor die includes: a substrate including a top surface and a bottom surface; and a plurality of pairs of signal via groups independent of each other, a plurality of signal via groups being arranged in the substrate and spaced apart from each other, two signal via groups in each pair of signal via groups are distributed symmetrically with respect to an axis located on the top surface of the substrate, one of the two signal via groups being distributed in a first region arranged on one side of the axis, and another one of the two signal via groups being distributed in a second region arranged on another side of the axis, the axis being parallel to a first direction or a second direction.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
17.
Semiconductor Structure And Method of Making The Same
The disclosed method provides a solution to the gate-induced drain leakage (GIDL*) current in a semiconductor structure. The method includes forming a first trench with a first initial doped region at its bottom, oxidizing the first trench, forming a first oxide layer on the sidewalls of the first trench, and forming a second oxide layer at the bottom of the first trench. The first oxide layer's thickness is greater than the second oxide layer's thickness. The doping element of the first initial doped region prolongs the reduction rate, so that the oxidation rate of the first initial doped region is lower than the oxidation rate of the substrate, thereby forming the first oxide layer. The GIDL of the semiconductor structure can be reduced, the turn-on sensitivity of the semiconductor structure can be improved, and the yield of the semiconductor structure can be increased.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
18.
Chemical Mechanical Polishing Process Method and Device
A CMP method includes: provide a substrate with a dielectric layer and a conductive layer, using a mixture of a first polishing liquid and a second polishing liquid to do first CMP polish the substrate placed on the polishing disc to remove the conductive layer covering the upper surface of the intermediate dielectric layer; after the substrate is rinsed with a cleaning solution, the second polishing solution is applied to do second CMP polish on the substrate to remove a part of the dielectric layer, so that the upper surface of the dielectric layer is lower than the upper surface of the conductive layer filled in the groove, so as to ensure that the conductive layer in the groove can protrude from the surface of the dielectric layer. This technique improves product yield for single disc CMP process.
B24B 37/22 - Tampons de rodage pour travailler les surfaces planes caractérisés par une structure multicouche
B24B 37/005 - Moyens de commande pour machines ou dispositifs de rodage
B24B 37/16 - Plateaux de rodage pour travailler les surfaces planes caractérisés par la forme ou le profil de la surface du plateau de rodage, p.ex. rainurée
The present application provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing the semiconductor structure includes: providing a base, the base including a substrate and a first dielectric layer on the substrate; forming a through silicon via in the base, the through silicon via penetrating through the first dielectric layer, extending into the substrate, and having a depth less than a thickness of the base; forming an electrically conductive structure in the through silicon via; forming a filling hole in the first dielectric layer and the substrate, the filling hole surrounding the electrically conductive structure, exposing a sidewall of the electrically conductive structure and a part of the substrate, and having a stepwise sidewall; and forming a thermally conductive structure in the filling hole.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/26 - Bombardement par des radiations ondulatoires ou corpusculaires
H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p.ex. recuit, frittage
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
20.
Semiconductor Memory and Method of Making The Same
The present application provides a method for fabricating a semiconductor memory structure. The method includes: providing a substrate; forming a stack layer on the substrate, and arranging spacer rows in the stack layer, forming a plurality of active lines, and forming a plurality of transfer pillars in the stack layer; forming a spacer structure outside the transfer pillars, and forming an etching hole; etching the second composite mask layer and the initial semiconductor along the etching hole layer of the active lines to form a plurality of discrete active region masks; and etching the substrate along the active region masks to form a plurality of discrete active regions. The disclosed technique can effectively reduce the preparation difficulty of the active area, improve the LCDU of the active area, and improve the performance of the semiconductor structure.
A semiconductor structure and a method making it are disclosed. The method includes: providing a substrate, and sequentially forming a bitline contact structure and a bitline on the substrate; the bitline includes a connection layer connected to the bitline contact structure. The bitline contact structure and the sidewalls of the connection layer are etched back. A first silicide layer covering the sidewalls of the bitline contact structure, and a second silicide layer covering the sidewalls of the connection layer are formed. This structure can reduce the contact resistance between the bitline contact structure and the bitline, as well as the parasitic capacitance between the bitline contact structure and the adjacent conductive structures, thereby improving the electrical performance and reliability of the semiconductor structure and improving the semiconductor yield.
Embodiments of the present disclosure provide a semiconductor device, comprising a semiconductor layer, extending along the first direction; the semiconductor layer includes a capacitor area facing the capacitor structure, and the capacitor structure includes: a lower electrode layer, the capacitor dielectric layer and the upper electrode layer, sequentially surrounding the sidewalls of the capacitor area extending along the first direction, a part of the lower electrode layer surrounds the sidewalls of the capacitor region, and also surrounds the bottom of the upper electrode layer, the sidewalls extending along the first direction, and the capacitor dielectric layer is located between the upper electrode layer and the lower electrode layer. The disclosed device improves the capacitance of the capacitor structure while improving the integration density of the semiconductor structure.
A semiconductor structure and a preparation method making it are disclosed. The semiconductor structure includes: a substrate, a bit line contact structure, a first epitaxial layer, a bit line and a second epitaxial layer. The structure includes bit line contact holes. The bit line contact structure is disposed in one of the bit line contact holes. The first epitaxial layer is epitaxially grown on the sidewalls of the bit line contact structure. The bit line includes a connection layer connected to the bit line contact structure. The second epitaxial layer is epitaxially grown on the sidewalls of the connection layer. The present disclosure can reduce the contact resistance and parasitic capacitance between the bit line contact structures and the bit lines, thereby improving the electrical performance of the semiconductor structure, thereby raising the reliability and yield of the semiconductor structure.
The present disclosure relates to a semiconductor device and a method of forming the same. The semiconductor device includes: a substrate; a transistor on the substrate, which includes an active cylinder, the active cylinder includes a channel region, a source region and a drain distributed on opposite sides of the channel region, a first doped region located between the source region and the channel region, and a second doped region located between the drain region and the channel region, the first doped impurity region, the source region, the second doped impurity region and the drain region, all these regions include doped ions of the first type, and the doped concentration of the first impurity region is lower than that of the source region impurity concentration, the doped concentration of the second doped region is lower than the doped concentration of the drain region. The present disclosure reduces the band-to-band tunneling effect inside the transistor, thereby reducing the GIDL effect.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
A memory structure of an integrated circuit includes a plurality of memory arrays arranged in parallel along the first direction and extending along the second direction, a sensitivity amplifier array extending along the second direction is arranged between every two memory arrays, and the sensitivity amplifier array includes an odd-numbered sensitivity amplifier array and an even-numbered sensitivity amplifier array, the odd-numbered sensitivity amplifier array is connected to an odd-numbered global signal line, and the even-numbered sensitivity amplifier array is connected to the even-numbered global signal line; a first sensitivity amplifier array is arranged between the memory arrays at the edge, and the first sensitivity amplifier array is connected to both the odd-numbered global signal line and the even-numbered global signal line. The present disclosure can improve reliability, yield and test success rate of the memory products.
A method for manufacturing the semiconductor structure includes following operations. A base is provided. A plurality of stack structures spaced apart from each other along a first direction are formed on a surface of the base and a plurality of first isolation layers arranged between the plurality of stack structures are formed, the plurality of stack structures include a plurality of first interlayer dielectric layers, a plurality of initial active layers and a plurality of second interlayer dielectric layers. Portion of each initial active layer is etched to form a first trench in each initial active layer. A plurality of oxide semiconductor layers are formed in a plurality of first trenches. Portions of the plurality of oxide semiconductor layers and remaining portions of the plurality of initial active layers are etched to form a plurality of active structures arranged in an array along the first direction and a second direction.
Provided are a data transmission circuit, a data transmission method, and a storage device. The data transmission circuit includes a controllable delay module and a mode register data processing unit. The controllable delay module is configured to generate a delayed read command in response to a mode register read command. The mode register data processing unit is configured to read setting parameters from a mode register in response to the mode register read command, and to output the setting parameters in response to the delayed read command. Here, a time difference between a start moment of outputting of the setting parameters and a moment when the controllable delay module receives the mode register read command is a first preset threshold.
A method of manufacturing a semiconductor structure is disclosed. The semiconductor structure includes a transistor area, which includes a first source-drain area and a word line region. The method includes forming an active layer on a substrate, and the active layer of the transistor region includes a plurality of active structures. A dummy word line structure covering the active structure of the same layer is formed in the first source drain region and the word line region. The first isolation layers arranged alternately with the dummy word line structures in the third direction are formed. Then the dummy word line structure is removed. An initial dielectric layer is formed on the surface of the active structure of the first source-drain region and the word line region. An initial word line is formed on the surface of the initial dielectric layer. The initial word line and the initial dielectric layer located in the first source and drain region are removed.
A method for fabricating a semiconductor structure and the device are disclosed. The method includes: providing a first sacrificial layer and semiconductor columns on a substrate; forming an isolation structure, disposed between adjacent stacked structures along the first direction; etching the isolation structure to form a through-hole, the through-hole exposes a part of the surface of the substrate, and also exposes each side of each stacked structure; along the second direction, the width of the bottom of the through-hole is greater than the width of the top of the through-hole, and the second direction is perpendicular to the first direction; the first sacrificial layer exposed by the through-hole is laterally etched, and a part of the first sacrificial layer is removed. A sacrificial layer exposes the top surface and the bottom surface of each semiconductor column. The present disclosure improves the morphology of the semiconductor structure.
Embodiments of the present disclosure relate to an electrostatic protection structure and an electrostatic protection circuit. The electrostatic protection structure includes: a SCR structure and a trigger structure; the SCR structure includes: a well region of a second conductivity type and a first well of a first conductivity type region, a first-doped region of the first conductivity type, and a first-doped region of the second conductivity type; the trigger structure includes: a first-doped region of the second conductivity type, a second well region of the first conductivity type, a second-doped region of two conductivity types, a third-doped region of the second conductivity type, a fourth-doped region of the second conductivity type, and a first gate electrode. The electrostatic protection structure weakens the positive feedback of the parasitic transistor in the SCR device, improves the anti-latch capability of the device, realizes stronger protection capability, and enhances the reliability of the circuit.
H02H 9/02 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de courant
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
31.
Latch performance detection method, device and electronic device
The present disclosure provide latch performance detecting method and a device. The method includes: extracting circuit structure information of a latch, having a transmission gate and a latch unit, an output terminal of the transmission gate is coupled to the input terminal of the latch unit, and the input terminal is coupled to the output terminal of the drive unit corresponding to the latch; the resistance value of the equivalent resistor of the latch is determined based on the circuit structure information, The first terminal of the equivalent resistor is the output terminal of the driving unit, and the second terminal is the input terminal of the latching unit; based on the resistance value of the equivalent resistor, the latching performance is determined. The embodiments of the present disclosure can accurately detect whether the latch is in a metastable state, which helps to improve the performance of the circuit.
G11C 29/56 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne Équipements externes pour test de mémoires statiques, p.ex. équipement de test automatique [ATE]; Interfaces correspondantes
32.
Semiconductor Structure and Method of Making the Same
A semiconductor structure includes: an electrode cover layer; a first conductive structure on the electrode cover layer; a contact structure, including a first and a first contact layera. The first contact layer is in contact with the first conductive structure, the bottom of the second contact layer is in contact with the top of the first contact layer, the width of the first contact layer is greater than the width of the bottom of the second contact layer, the lower surface of the contact structure is not lower than the lower surface of the electrode cover layer, and the resistivity of the first conductive structure is not greater than that of the contact structure and is not greater than that of the electrode cover layer. The contact area between contact structure and electrode covering layer is increased, thus avoiding voids in the contact structure, reducing contact and volume resistance between the contact and the capacitance under the electrode covering layer.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
33.
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
A method for manufacturing a semiconductor structure includes: a base provided with a contact hole is provided; an initial contact structure including a first diffusion barrier layer, a conductive layer and a second diffusion barrier layer stacked onto one another is formed on the base, the first diffusion barrier layer conformably covering the contact hole and covering part of a top surface of the base, the conductive layer covering first diffusion barrier layer and being filled in unoccupied space in the contact hole, the second diffusion barrier layer covering a side of the conductive layer away from first diffusion barrier layer, the initial contact structure outside the contact hole being provided with a groove exposing side walls of conductive layer and second diffusion barrier layer; a third diffusion barrier layer is formed on a side wall of initial contact structure exposed by the groove to obtain a target contact structure.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
The present application relates to the technical field of semiconductor manufacturing equipment, and provides a dust collection device. The dust collection device includes: an air inlet channel, a dust settling channel extending along a preset path, an airflow rotation channel surrounding the settling channel, an air outlet channel and a collection chamber, where one end of the airflow rotation channel is communicated with the dust settling channel, and the other end of the airflow rotation channel is communicated with the air outlet channel; an upstream end of the dust settling channel is communicated with the air inlet channel, and a downstream end of the dust settling channel is communicated with the collection chamber; and the height of the dust settling channel gradually decreases in an extension direction of the preset path. Dust in the airflow rotation channel can easily settle under the action of a centrifugal force when moving along the airflow rotation channel, and the other end of the airflow rotation channel is communicated with the air outlet channel to discharge air.
B01D 45/16 - Séparation de particules dispersées dans des gaz ou des vapeurs par gravité, inertie ou force centrifuge en utilisant la force centrifuge produite par le mouvement hélicoïdal du courant gazeux
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
35.
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
The method of forming the semiconductor structure comprises operations of: forming a substrate, and forming active regions located above the substrate and arranged at intervals in a first direction parallel to a top face of the substrate; and performing a modifying treatment to a part of the substrate below the active regions from at least one side face of the substrate, to form bit lines each of which extends in the first direction and is electrically connected with a plurality of the active regions arranged at intervals in the first direction
A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the multiple bit lines are disposed in one-to-one correspondence; local data buses that are divided into local data buses O and local data buses E, adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit; and a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data.
The semiconductor structure comprises: semiconductor channels, first gate structures, second gate structures and bit lines. Each semiconductor channel extends in a third direction and has an L-shaped cross-section in a plane perpendicular to the third direction, each of the semiconductor channels comprises a first L-shaped sidewall and a second L-shaped sidewall which are opposite to each other and extend in the third direction, the first L-shaped sidewall comprises a first face extending in a first direction and a second face extending in a second direction. Each first gate structure is in contact with the first face. Each second gate structures is in contact with the second face, each first gate structure is in contact with the respective second gate structure. The bit lines extend in the second direction and are located on a side of each of the semiconductor channels in the third direction.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
38.
ANTI-FUSE CIRCUIT AND ANTI-FUSE UNIT PROGRAMMING STATE REAL-TIME VERIFICATION METHOD
The disclosed anti-fuse circuit includes: an anti-fuse unit; a programming circuit, configured to program the anti-fuse unit according to a programming signal; a verification unit, including a first input terminal, a second input terminal and a first output terminal, the programming signal of the anti-fuse unit is the input signal of the first input terminal, and the data signal stored in the anti-fuse unit is the input signal of the second input terminal. The verification unit verifies the programming state of the anti-fuse unit according to the input signals of the first input terminal and the second input terminal, and the first output terminal outputs a verification signal. The anti-fuse circuit does not need to read out the data signal of the anti-fuse unit to a test machine followed by verifying the programming state of the anti-fuse unit. This anti-fuse circuit saves time and enables high verification accuracy.
G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles
G11C 17/18 - Circuits auxiliaires, p.ex. pour l'écriture dans la mémoire
39.
DELAY CONTROL CIRCUIT AND METHOD, AND SEMICONDUCTOR MEMORY
Provided in the embodiments of the present disclosure are a delay control circuit and method, and a semiconductor memory. The delay control circuit includes a clock circuit and a delay circuit. The clock circuit is configured to receive a temperature adjustment signal, and generate a first clock signal according to the temperature adjustment signal; and a clock cycle of the first clock signal is a preset value. The delay circuit is configured to receive the first clock signal and an initial command signal, and perform delay processing on the initial command signal according to the first clock signal, so as to obtain a target command signal; and a time interval between the target command signal and the initial command signal meets a preset timing condition.
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
H03K 5/133 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard
A control circuit is provided, including a random module and an output module. A first input terminal of the random module receives a refresh count signal, a second input terminal receives random data, and a control terminal is connected to an output terminal of the output module. The random module processes the refresh count signal and the random data based on a row hammer refresh (RHR) signal output by the output module to obtain and output a random signal. A first input terminal of the output module receives the refresh count signal, a second input terminal is connected to an output terminal of the random module. The output module generates and outputs the RHR signal according to the random signal and the refresh count signal.
A counting control circuit includes a logic control circuit and a counting statistic circuit, an output terminal of the logic control circuit is connected to a clock terminal of the counting statistic circuit. The logic control circuit is configured to receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under a control of the first identification signal. The counting statistic circuit is configured to receive the counting clock signal, count according to the counting clock signal, and generate the first identification signal which indicates a generation of a command signal for performing a first operation, here, the first identification signal is in a valid state when a counting value meets a preset condition.
A delay control circuit includes a delay circuit. The delay circuit is configured to receive an initial command signal, and to perform a non-clock-triggered delay processing on the initial command signal to obtain a target command signal. The initial command signal is generated based on an ECS operation mode, a time interval between the target command signal and the initial command signal meets a preset timing condition, the initial command signal is used for performing a first operation and the target command signal is used for performing a second operation.
A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes: a substrate having a bit line extending along a first direction; a semiconductor channel located on the bit line; a semiconductor doping layer located on the side of the bit line, wherein the top surface of the semiconductor doping layer is connected to the semiconductor channel contact; a word line extending in the second direction, encircling part of the semiconductor channel, and the bottom surface of the word line is higher than the top surface of the bit line; a word line dielectric layer located between the word line and the semiconductor channel; an isolation layer located between the word line and the bit line and between the word line and the semiconductor doping layer. The device and method improve the prior weak electrical conductivity between the bit line structure and the active structure.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
44.
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
Provided are a semiconductor structure and a method for forming the same. The method for forming a semiconductor structure includes the following operations. A stack is formed on a substrate. The stack includes interlayer insulating layers and sacrifice layers alternately stacked in a first direction. The stack includes a plurality of storage regions arranged at intervals in a second direction. Part of the sacrifice layers of storage regions is removed to form first trenches between adjacent interlayer insulating layers. Transistor structures are formed in the first trenches. The transistor structures include gate layers covering inner walls of the first trenches and active structures located in the gate layers. A word line extending in the second direction is formed. The word line envelops gate layers of the plurality of storage regions arranged at intervals in the second direction.
The application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a substrate and multiple Word Lines (WLs), the multiple WLs extend along a first direction and are arranged on the substrate at intervals along a second direction, a WL isolation structure is arranged between every two adjacent WLs and includes at least a first isolation layer and a second isolation layer stacked along the second direction and made of different materials, and the first direction and the second direction intersect with each other.
The present disclosure relates to the technical field of semiconductors and provides a semiconductor structure, a method of forming same, and a memory. The method of forming a semiconductor structure of the present disclosure includes: providing a carrier board; forming a chipset on one side of the carrier board, where the chipset includes multiple chips stacked in a direction perpendicular to the carrier board; where among multiple chips, an orthographic projection of a chip closer to the carrier board on the carrier board is within an orthographic projection of a chip farthest from the carrier board on the carrier board; forming an insulating dielectric layer covering the chipset; and performing a grinding process to expose a predetermined surface of the chip farthest from the carrier board outside the insulating dielectric layer.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A memory includes a substrate, a control circuit layer located in the substrate, and at least two memory structure layers. The control circuit layer includes at least part of control circuits of the memory. The at least two memory structure layers are sequentially stacked on the control circuit layer. Each memory structure layer includes multiple memory blocks arranged in an array. The memory block includes multiple parallel Word Lines (WLs) extending in a first direction. The first direction is parallel to a surface of the substrate. An opening is provided between adjacent memory blocks located in the same memory structure layer. The openings located in different memory structure layers go through each other. WLs in the at least one memory structure layer are connected to the control circuit layer through the openings that go through each other.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
The present disclosure provides a semiconductor package structure, relating to the technical field of semiconductors. The semiconductor package structure includes: a substrate; and at least one chip stack structure provided on the substrate, where the at least one chip stack structures include a plurality of first chips vertically stacked, each of the first chips includes a first conductive plug set, a connection layer is provided between two adjacent first chips, a wire structure is provided in the connection layer, the wire structure is electrically connected to the first conductive plug sets in two first chips adjacent to the wire structure, projections of two first conductive plug sets electrically connected to a same wire structure on the substrate are staggered from each other, and the first conductive plug sets in the plurality of first chips are connected in series through the wire structures to form an inductor structure.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A semiconductor structure includes: a high-speed circuit module including a clock signal with a frequency greater than a first threshold; a first conductive metal layer including power conductive wires extending along a first direction and arranged at intervals, and the power conductive wires being electrically connected with the high-speed circuit module; and a redistribution layer located above the first conductive metal layer and including power pads and electrical wires connected with the power pads, in which the power pads are located at one side of the high-speed circuit module, a projection of the power pads does not overlap with that of the high-speed circuit module, the electrical wires include a first electrical wire region where the electrical wires are repeatedly bent, the first electrical wire region at least partially covers the high-speed circuit module, and the electrical wires are used for electrically connecting the power conductive wires and power pads.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
50.
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a semiconductor structure includes: forming first base which includes first substrate and active areas arranged in an array along first direction and second direction in first substrate, word lines being disposed in first base, extending along second direction and covering at least opposite sides of each active area; forming charge storage structures electrically connected with first ends of active areas on first base; forming second base which includes second substrate and bit lines disposed in second substrate, bit lines extending along first direction; connecting first base and second base by using a first surface of first base away from charge storage structures and a second surface of second base having structures of bit lines as connection surfaces, bit lines being electrically connected with second ends of active areas, and each first end being disposed opposite to a corresponding second end.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
51.
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The manufacturing method includes the following operations. A substrate is provided, and a first groove and a second groove are formed in the substrate, each of the first groove and the second groove having a depth in a first direction. The first groove includes multiple first sub-grooves arranged in the first direction, the second groove includes multiple second sub-grooves arranged in the first direction, and sidewalls of the first sub-grooves and sidewalls of the second sub-grooves are convex outwards. Word lines protruding away from the first groove each are formed at an interface of adjacent first sub-grooves. First source-drain layers formed on the sidewalls of the first sub-grooves, and second source-drain layers protruding away from the second groove each are formed at an interface of adjacent second sub-grooves.
A semiconductor structure includes a plurality of dies. The plurality of dies are stacked sequentially along a first direction. The first direction is a direction perpendicular to a plane of the dies. Each of the dies includes a base and n first conductive structures penetrating the base along the first direction, where n is greater than or equal to 2. In at least one group of the corresponding first conductive structures in the dies, projections of the group of the first conductive structures in two adjacent layers of the dies along the first direction are not overlapped with each other.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
53.
DATA SAMPLING CIRCUIT, DELAY DETECTION CIRCUIT AND MEMORY
A data sampling circuit includes a first signal path and a second signal path. The first signal path is arranged to receive a first signal, process and transmit the first signal. The first signal path has a first delay, and the first delay includes a first physical delay and a compensation delay. The second signal path is arranged to receive a second signal, receive processed first signal from the first signal path, and sample the second signal according to the processed first signal.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
54.
Semiconductor Structure and Method Making the Same
The present disclosure provides a semiconductor structure including: a channel on a semiconductor substrate for a first transistor; first bit lines are in contact with the first doped region arranged along the first direction; first word lines surround the channel region; the gate conductive layer and the second doped region, the channel layer arranged around the outer side of the gate conductive layer; the first semiconductor doped layer and the second semiconductor doped layer arranged on the outer side of the channel layer, so the channel layer and the gate conductive layer constitute the second transistor. The second bit line is in contact with either the first semiconductor doped layer or the second semiconductor doped layer; the second word line is in contact with the other one of the first semiconductor or the second semiconductor doped layer. The structure forms a new 2T0C DRAM structure.
A method for manufacturing a semiconductor structure includes: providing a substrate including a transistor structure; forming a laminated structure on the substrate, the laminated structure including a dielectric layer and an insulating layer which are sequentially stacked in a thickness direction of the substrate, and the insulating layer being arranged on a side, away from the substrate, of the dielectric layer; forming a through hole penetrating through the laminated structure in the laminated structure to expose a source/drain of the transistor structure; and etching at least part of a side wall of the through hole located in the dielectric layer to form a conductive hole in the insulating layer and the dielectric layer. An aperture size of a medial part of the conductive hole is greater than an aperture size of each of both ends of the conductive hole.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
A memory includes: a storage cell array; a write driver; and a first column decoder, the first column selection line includes a dummy route and a loaded route, the dummy route is coupled to the first column decoder and the loaded route and transmits a first column selection signal to the loaded route; the loaded route is coupled to a first storage cell area and transmits the first column selection signal to the first storage cell area; the first column selection signal selects a storage cell column, on which a write operation is performed, from the first storage cell area. A transmission direction of a data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A semiconductor structure includes a base, a chip stack located on the base, and first conductive structures. The chip stack includes chips stacked in sequence in a direction perpendicular to a plane of the base, a chip includes first and second sub-portions, a first surface of the first sub-portion is flush with that of the second sub-portion, a second surface of the first sub-portion protrudes from that of the second sub-portion, and the first and second surfaces are oppositely arranged. A first conductive structure includes a first conductive bump and a first through-silicon via, the first conductive bump is located between first sub-portions of two adjacent chips, the first through-silicon via penetrates through the first sub-portion in the direction perpendicular to the plane of the base and is connected to the first conductive bump, and the materials of the first conductive bump and the first through-silicon via are same.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
58.
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND MEMORY
A semiconductor structure includes: multiple active areas arranged in an array along intersecting first and second directions and spaced apart by an isolation structure; a bit line select structure comprising a first gate, a second gate, a third gate and a fourth gate located on four mutually adjacent active areas, and at least one connecting line located on the isolation structure; and multiple contact structures, each of the multiple contact structures being located on one side, close to the connecting line, of both sides of a respective gate and connected with a respective one of the multiple active areas, and an orthographic projection of the contact structure on a plane where the active area is located being at a position, close to the connecting line, in the active area.
A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a substrate, a chip stack disposed on the substrate through a plurality of first conductive structures. Each of the plurality of the first conductive structures includes a first conductive bump, and the first conductive bump includes at least one concave surface. Concave surfaces of adjacent first conductive bumps are disposed facing each other.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
60.
SEMICONDUCTOR STRUCTURE AND FORMING METHOD AND OPERATING METHOD THEREFOR
A semiconductor structure includes: a substrate; a memory array, including a plurality of storage cells arranged in a first direction and a second direction, where each storage cell includes an active pillar including a first channel region and a second channel region that are arranged at intervals in a third direction; a word line structure, including a first word line extending in the first direction and a second word line extending in the second direction, where the first word line covers the first channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the first direction, and the second word line covers the second channel regions of the active pillars of the plurality of storage cells that are arranged at intervals in the second direction; and a common bit line, electrically connected to all the storage cells in the memory array.
The present disclosure provides a single-loop memory device, a double-loop memory device, and a ZQ calibration method. The single-loop memory device includes: a master chip and a plurality of slave chips each provided with a first transmission terminal and a second transmission terminal, where the second transmission terminal of the master chip is connected to the first transmission terminal of the slave chip of a first stage, and the second transmission terminal of the slave chip of each stage is connected to the first transmission terminal of the slave chip of a next stage; and the master chip is provided with a first signal receiver, and the slave chip is provided with a second signal receiver.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. mémoires tampon de données
H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion
A memory includes: a memory cell array; a first column decoder, coupled to the memory cell array and configured to perform a write operation on the memory cell array; a second column decoder, coupled to the memory cell array and configured to perform a read operation on the memory cell array; and a read amplifier, the read amplifier and the second column decoder being located on two opposite sides of the memory cell array, the read amplifier being coupled to the memory cell array and configured to receive read data information output by the memory cell array based on the read operation. The read amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
63.
TRANSISTOR, SEMICONDUCTOR STRUCTURE, MEMORY, AND METHOD FOR FORMING SAME
A transistor includes a source structure, a trench, a drain structure, and a gate structure. The trench sequentially has first and second end faces which are arranged opposite in a first direction. The source structure extends from the first end face in a second direction. The source structure sequentially has third and fourth end faces which are arranged opposite in the first direction. The fourth end face is connected to the first end face. The drain structure extends from the second end face in a direction opposite to the second direction. The drain structure sequentially has fifth and sixth end faces which are arranged opposite in the first direction. The fifth end face is connected to the second end face. The second direction intersects the first direction. The gate structure surrounds the trench and is connected to the fourth and the fifth end face.
A semiconductor structure, a method for preparing the semiconductor structure and a memory are provided. The method includes: providing a wafer in which multiple conductive pillars are formed; inverting the wafer and performing etching on a back plane of the wafer to expose each conductive pillar from the back plane of the wafer, and lengths of the multiple conductive pillars exposed to the back plane are different; depositing an insulation layer on the back plane of the wafer and the conductive pillars, and depositing a filling layer on the insulation layer, the filling layer completely covering back ends of the multiple conductive pillars; and performing polishing on the filling layer and back ends of a part of the conductive pillars, until a back end of each conductive pillar is exposed and the back ends of the multiple conductive pillars are flush with a back plane of the filling layer.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
65.
DATA RECEIVING CIRCUIT, DATA RECEIVING SYSTEM, AND STORAGE APPARATUS
A data receiving circuit includes a decision feedback equalization circuit, configured to perform decision feedback equalization on a receive circuit based on a feedback signal to adjust a first output signal and a second output signal, where the feedback signal is obtained based on previously received data, the decision feedback equalization circuit responds to a first control signal group and a second control signal group to change an adjustment capability, the first control signal group corresponds to one data port corresponding to a data signal, and the second control signal group corresponds to all data ports. The capability of the decision feedback equalization circuit can be controlled to adjust the first output signal and the second output signal, where the adjustment capability has a wide adjustable range, to reduce impact of intersymbol interference of received data on the data receiving circuit.
Embodiments provide a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate; forming, on a surface of the substrate, stacked structures arranged at intervals in a first direction and a first isolation layer located between adjacent stacked structures, the stacked structure including a first interlayer dielectric layer, an initial active layer, and a second interlayer dielectric layer; etching a portion of the initial active layer to form a first trench; forming a metal conductive layer in the first trench, the metal conductive layer being in contact connection with the remained initial active layer; and etching a portion of the metal conductive layer to form lower electrode structures arranged in an array in the first direction and a second direction, where the first direction is perpendicular to the surface of the substrate, and the second direction is parallel to the surface of the substrate.
A write leveling circuit applied to a memory includes a write signal generation unit and a sampling unit. The write signal generation unit is configured to receive a first clock signal and a first indication signal, and delay a first write signal according to the first clock signal, the first indication signal and a specified bit in the first indication signal, and output a second write signal. The sampling unit is connected to the write signal generation unit, and configured to receive a first data strobe signal and the second write signal, and output a second sampling signal according to received first Data Strobe Signal (DQS) and the second write signal.
G11C 8/18 - Circuits de synchronisation ou d'horloge; Génération ou gestion de signaux de commande d'adresse, p.ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
68.
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREFOR
A semiconductor structure and a fabrication method are provided. The semiconductor structure includes: a substrate, where a plurality of capacitor contact structures arranged at intervals are formed on the substrate; an isolation structure, where the isolation structure is disposed on the substrate and between adjacent capacitor contact structures, and a top surface of the isolation structure is not higher than a top surface of each capacitor contact structure; and an isolation groove, where the isolation groove extends from the top surface of the isolation structure to an interior of the isolation structure, and a spacing is provided between the isolation groove and the capacitor contact structure.
A semiconductor structure includes a substrate and a word line structure. The substrate includes an array region and a peripheral region. The word line structure includes a first conductive layer disposed on the substrate, and the first conductive layer penetrates the array region and extends to the peripheral region in a first direction. In a normal direction of the substrate, a height of the first conductive layer on a surface of the peripheral region is higher than a height of the first conductive layer on a surface of the array region.
The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a word line, and at least two dielectric layers. The word line is arranged in the substrate; the at least two dielectric layers are located between the word line and the substrate and have different dielectric constants.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
71.
LAYOUT STRUCTURE, SEMICONDUCTOR STRUCTURE AND MEMORY
A semiconductor structure includes: a logic device including a first power line and a second power line located on a same wiring layer, extending along a first direction and arranged in parallel along a second direction, the first direction and the second direction intersecting with each other and being parallel to a plane where the wiring layer is located; and a switch driving device, the switch driving device and the logic device being arranged in parallel along the first direction, the switch driving device including a first input line and a first output line located on the same wiring layer as the first power line, extending along the first direction and arranged in parallel along the second direction, the first output line being connected with the first power line or the second power line.
H01L 27/118 - Circuits intégrés à tranche maîtresse
H03K 19/0948 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs à semi-conducteurs utilisant des transistors à effet de champ utilisant des transistors MOSFET utilisant des dispositifs CMOS
72.
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
A semiconductor structure includes a substrate and a word line (WL) structure. The WL structure includes: a work function stacking structure located in the substrate, where the work function stacking structure includes multiple sequentially and alternately stacked first work function layers and second work function layers, and a work function of the first work function layer is greater than a work function of the second work function layer; a WL conductive layer located in the substrate, and located on an upper surface of the work function stacking structure; and a gate oxide layer located between the work function stacking structure and the substrate as well as between the WL conductive layer and the substrate.
A clock system and a memory are disclosed. The clock system includes a system on chip (SoC) configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal of a same frequency and amplitude. Further, the clock system includes a memory chip configured to output a data signal based on signal edges of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal, and output a command/address signal based on the signal edges of the first oscillation signal and the third oscillation signal. The signal edges are rising edges or falling edges.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
H03L 7/093 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/099 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
74.
SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR MEMORY
A semiconductor structure includes: a substrate; and a plurality of device structures, a plurality of bit line structures and a plurality of word line structures formed on the substrate. The device structure extends in a first direction, and the word line structure extends in a second direction, and the bit line structure extends in a third direction. The device structure includes a capacitor area and an active area. The bit line structure is electrically connected to the active areas arranged in the third direction. Herein, at least some of the bit line structures are formed with air gaps around them.
The method for manufacturing the semiconductor structure includes: providing a substrate, and forming contact holes in the substrate; depositing a metal at a bottom of each contact hole, and performing a reverse sputtering treatment to form a metal layer; in the reverse sputtering treatment, metal atoms or metal ions are sputtered onto at least a part of a side wall of each contact hole; performing a annealing treatment, to cause the substrate reacts with the metal layer to form a metal silicide layer.
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p.ex. condensation
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
The disclosed driver and memory include: a phase driver that receives a first voltage signal, configured to output a second phase signal according to the first phase signal and the first voltage signal; a complementary phase driver includes: a first inverter for generating a complementary inverted phase signal based on a first complementary phase signal, the first phase signal and the first complementary phase signal are mutually inverted; a second inverter for receiving an output signal of the first inverter and a second voltage signal, the voltage value of the second voltage signal is smaller than that of the first voltage signal, and the second inverter is configured to be based on the first complementary inverted phase signal, and the second voltage signal outputs a second complementary phase signal. The driver of the embodiment provides the second phase signal and the second complementary phase signal.
G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
A semiconductor structure includes a substrate and a stack structure located on the substrate. The stack structure includes a plurality of memory units arranged at intervals in a first direction. Each memory unit includes a transistor structure. The transistor structure includes an active structure and a gate layer. At least part of the active structure is distributed around a periphery of part of the gate layer, and the projection of the active structure on a top surface of the substrate is in the shape of a U which opens toward a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects with the second direction. A method for forming the semiconductor structure is also provided.
A semiconductor structure and a memory are provided. The semiconductor structure includes multiple active regions, a column selector and multiple bit lines. The column selector includes a first gate, a second gate, a third gate, a fourth gate and a connection line. The first gate and the second gate intersect at a first node, the third gate and the fourth gate intersect at the second node, and the connection line connects the first node and the second node. Each of the multiple bit lines includes a first portion, a second portion and a connection portion. Each of the multiple bit lines is connected to a respective one of the multiple active regions, the active regions connected to different bit lines among the multiple bit lines are different.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
The present disclosure provides a memory and a memory system thereof, relating to the technical field of semiconductors. The memory includes: memory sections and a plurality of bit lines (BLs) corresponding to a same memory section; sense amplifiers electrically connected to the plurality of BLs in one-to-one correspondence, where two of the sense amplifiers corresponding to adjacent two of the BLs are located on two sides of the memory section; and a first error checking and correction (ECC) module and a second ECC module, where one of two adjacent sense amplifiers located on a same side of the memory section is electrically connected to the first ECC module, and the other one of the two adjacent sense amplifiers located on the same side of the memory section is electrically connected to the second ECC module.
G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
G11C 7/12 - Circuits de commande de lignes de bits, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
G11C 7/18 - Organisation de lignes de bits; Disposition de lignes de bits
80.
MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE
The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate, and forming a stacked structure on the substrate; forming a hard mask layer on the stacked structure, where the hard mask layer includes a first etched window, and the first etched window exposes part of a top surface of the stacked structure; forming a photoresist layer, where the photoresist layer covers the first etched window; and trimming the photoresist layer for a plurality of times, after each trimming of the photoresist layer, etching the stacked structure according to a trimmed photoresist layer, and forming a plurality of steps in the stacked structure along a direction away from the substrate.
A semiconductor structure, a method for forming a semiconductor structure, and a memory are provided. The method for forming the semiconductor structure in the disclosure includes: providing a base, the base including a substrate and an insulating dielectric layer, the substrate including a plurality of first trenches spaced apart from each other in a first direction, and the insulating dielectric layer being filled in each of the plurality of first trenches; patterning and etching the base to form a plurality of second trenches spaced apart from each other in a second direction, the second direction intersecting with the first direction; forming a word line structure in each of the plurality of second trenches; forming an air gap between each two adjacent word line structures of a plurality of word line structures; and sealing the air gap.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
82.
METHOD FOR CONTROLLING SENSE AMPLIFIER AND ELECTRONIC DEVICE
A method for controlling a sense amplifier chronologically includes an idle phase, an offset cancellation phase, a charge sharing phase, and a sensing and amplification phase. In the charge sharing phase, the method includes controlling the first node to connect to the complementary bit line for a first predetermined duration and the second node to connect to the bit line for the first predetermined duration, and then disconnecting the connection between the bit line and the second node and the connection between the first node and the complementary bit line. In the sensing and amplification phase, the method include controlling the first node to connect to the complementary bit line and the second node to connect to the bit line, so as to transmit an amplified voltage to the bit line and the complementary bit line.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
A failure analysis method includes: obtaining failure data of IO channels in a target chip particle, the target chip particle including a plurality of physical modules, a number of the plurality of physical modules is M, and each physical module including a plurality of IO channels, wherein M is a positive integer greater than or equal to 2; splitting the failure data to form M groups of module failure data corresponding to the physical modules; determining a partial failure type of each physical module according to each module failure data; and determining a storage failure type of the target chip particle according to the partial failure type of each physical module.
G11C 29/56 - Vérification du fonctionnement correct des mémoires; Test de mémoires lors d'opération en mode de veille ou hors-ligne Équipements externes pour test de mémoires statiques, p.ex. équipement de test automatique [ATE]; Interfaces correspondantes
84.
SEMICONDUCTOR DEVICE LAYOUT STRUCTURE, METHOD FOR FORMING SAME, AND TEST SYSTEM
Embodiments relate to the field of semiconductor, and disclose a semiconductor device layout structure, a method for forming the same, and a test system. The semiconductor device layout structure includes: an active layout layer including active pattern regions arranged along a first direction; device layout sublayers, where each of the device layout sublayer includes a gate pattern region; and a plurality of contact plug sets, where each of the contact plug sets includes a source contact plug and a drain contact plug. Along the first direction, in adjacent two gate pattern regions of the device layout sublayers, a pitch between the latter gate pattern region and the corresponding source contact plug and/or the drain contact plug and a pitch between the former gate pattern region and the corresponding source contact plug and/or the drain contact plug form an arithmetic progression.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/482 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
85.
SEMICONDUCTOR STRUCTURE, FORMING METHOD OF SAME AND MEMORY
A semiconductor structure includes a base, a chipset and a heat conduction adjusting layer. The chipset is disposed at one side of the base and includes multiple chip units arranged at intervals along a direction perpendicular to the base. Each of the chip units includes a substrate and a circuit module disposed on a surface of the substrate. The substrate includes a circuit interconnection region and a non-circuit interconnection region distributed adjacently. The circuit module is disposed on a surface of the circuit interconnection region, and adjacent chip units are electrically connected by the circuit module. The heat conduction adjusting layer is in contact with at least one of the substrates for reducing the difference of heat conduction rates between surfaces of the substrates.
H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
86.
METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE
A method for manufacturing a semiconductor structure includes operations as follows. A substrate is provided, and a mask layer is formed on the substrate. An etching process is performed to form a plurality of first trenches in the mask layer, where the first trench has an inverted trapezoid cross-sectional shape. An epitaxy layer is formed on the substrate, where the epitaxy layer is filled in each of the first trenches to form an active area. The mask layer is removed to form a plurality of second trenches, where the second trench is arranged between adjacent active areas, and the second trench has a regular trapezoid cross-sectional shape. A dielectric layer is filled in the second trench to form an isolation structure.
H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate, where the substrate includes a first region and a second region, the first region includes a plurality of independent first active regions, adjacent two of the first active regions are isolated by a first trench, and an isolating lamination layer is formed in the first trench; forming a barrier layer covering a top surface of the second region; forming an epitaxial layer covering a top surface of the first active region; and etching off the barrier layer and part of the isolating lamination layer in the first region, where joints of top surfaces of layers in the isolating lamination layer retained in the first region are basically consistent in height.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
The present disclosure provides a voltage generating circuit and a memory. The voltage generating circuit includes: a voltage output module configured to receive a reference voltage, generate a first output voltage, and provide the first output voltage to a power supply node, where the power supply node is connected to a load to supply power to the load; a voltage stabilizing module configured to receive the reference voltage and generate and output a control signal; and a compensation module configured to receive a power voltage, a flag signal and the control signal, be turned on in response to the flag signal, and configured to provide a second output voltage to the power supply node in response to a voltage value of the control signal, such that a voltage of the power supply node is recovered to the first output voltage.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
G05F 1/577 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final par charges multiples
89.
SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAME
Embodiments provide a semiconductor structure and a fabricating method. The structure includes: a substrate including a capacitor structure and a peripheral device structure; a first wiring layer including a first wiring sub-layer and a second wiring sub-layer, a first conductive plug including a first conductive sub-plug and a second conductive sub-plug, where the first wiring sub-layer is positioned above the peripheral device structure, a terminal of the first conductive sub-plug is electrically connected to the first wiring sub-layer, other terminal of the first conductive sub-plug is electrically connected to the peripheral device structure, the second wiring sub-layer is positioned above the first wiring sub-layer, a terminal of the second conductive sub-plug is electrically connected to the second wiring sub-layer, and other terminal of the second conductive sub-plug is electrically connected to the first wiring sub-layer or the peripheral device structure; and a second wiring layer positioned above the capacitor structure.
A monitoring circuit includes: a sampling module, configured to sample an initial address to obtain a monitoring address; a counting module, configured to adjust a counting value of a first counter corresponding to the monitoring address and set a predetermined value for the monitoring address, and a magnitude of the set predetermined value is positively correlated with duration for which the monitoring address is stored in the counting module; and a processing module, configured to compare the counting value of the first counter corresponding to each monitoring address with the predetermined value, where if the counting value of the first counter is greater than or equal to the predetermined value, the monitoring address is retained, and if the counting value of the first counter is less than the predetermined value, the monitoring address is released, and the first counter and the predetermined value corresponding to the monitoring address are reset.
A write leveling circuit applied to a memory includes: a write signal generation circuit configured to perform delay processing on a first write signal according to a received first clock signal, and output a second write signal; a delay circuit configured to perform delay processing on a received first data strobe signal, and output a second data strobe signal; and a sampling circuit connected to both the delay circuit and the write signal generation circuit, and configured to output a first sampling signal according to the received second data strobe signal and the received second write signal. The sampling circuit is further configured to receive the first data strobe signal, and output a second sampling signal according to the first data strobe signal and the second write signal.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 8/18 - Circuits de synchronisation ou d'horloge; Génération ou gestion de signaux de commande d'adresse, p.ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
92.
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
A semiconductor structure includes a carrier structure, and a stack structure located on the carrier structure. The stack structure includes at least one heat dissipation panel and at least one die module stacked onto one another, and the at least one die module includes at least one die. An area of an orthographic projection of the at least one heat dissipation panel on the carrier structure is greater than an area of an orthographic projection of the at least one die module on the carrier structure.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
93.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SAME
Embodiments relate to the field of semiconductors, and provide a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an active pillar including a channel region and a source/drain region arranged on two sides of the channel region; and a gate structure surrounding at least part of the channel region. The channel region includes a peripheral portion and a central portion, the peripheral portion is positioned between the gate structure and the central portion, the source/drain region and the peripheral portion have a first doping type, and the central portion has a second doping type, where the first doping type is one of N-type and P-type, and the second doping type is other one of the N-type and the P-type. At least problems of greater difficulty in turning off existing junctionless field effect transistor and poorer turn-off effect may be solved.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Embodiments relate to a semiconductor structure, including: an active layer including a channel region; a first dielectric layer covering a top surface of the channel region; a gate layer covering a top surface of the first dielectric layer, where the active layer, the first dielectric layer and the gate layer constitute a first capacitor, and the first capacitor is coupled between a first potential and a second potential; two groups of first conductive layers, where the first conductive layers among the two groups of first conductive layers are electrically connected to each other; two groups of second conductive layers, where each of the second conductive layers clads a side surface and a bottom surface of the first conductive layer, one group of the second conductive layers is electrically connected to a third potential, and the other group of the second conductive layers is electrically connected to a fourth potential.
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
95.
Memory device with error per row counter (EpRC) performing error check and scrub (ECS)
The present disclosure provides a counter circuit and a memory. The counter circuit includes: a counting circuit configured to output a count value when the count value exceeds a predetermined threshold; a decoding circuit coupled to the counting circuit, and configured to decode the count value to obtain decoding information corresponding to the count value, where the decoding information represents a numerical interval in which the count value is located; and a comparison circuit coupled to the decoding circuit, and configured to compare the decoding information with historical maximum decoding information and latch and output current maximum decoding information.
A circuit for receiving data includes a voltage generating circuit, a data circuit and a selection circuit. The voltage generating circuit is configured to output, in a first mode, a first reference voltage signal and a second reference voltage signal. The data circuit is configured to compare the data signal with the first reference voltage signal, output a first target signal, compare the data signal with the second reference voltage signal, and output a second target signal. The data signal is one of a plurality of data signals arranged in series. The selection circuit is configured to determine one of the first target signal and the second target signal as a target data signal based on a level state of a previous data signal of the data signal.
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. mémoires tampon de données
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
A delay locked loop includes a preprocessing module, a first regulable delay line, a second regulable delay line and a first regulation module. The preprocessing module is configured to receive an initial clock signal, preprocess the initial clock signal, and output a first clock signal and a second clock signal. The first regulable delay line is configured to receive the first clock signal, regulate and transmit the first clock signal, and output a first target clock signal. The second regulable delay line is configured to receive the second clock signal, regulate and transmit the second clock signal, and output a second synchronization clock signal. The first regulation module is configured to regulate delay of the second synchronization clock signal based on the first target clock signal, and output a second target clock signal.
H03L 7/087 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence y compris le filtrage ou l'amplification de son signal de sortie utilisant au moins deux détecteurs de phase ou un détecteur de fréquence et de phase dans la boucle
H03L 7/183 - Synthèse de fréquence indirecte, c. à d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur entre des nombres fixes ou le diviseur de fréquence divisant par un nombre fixe
H03K 19/21 - Circuits OU EXCLUSIF, c. à d. donnant un signal de sortie si un signal n'existe qu'à une seule entrée; Circuits à COÏNCIDENCES, c. à d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
The embodiment the disclosure provides a monitoring circuit and a storage system. The monitoring circuit includes a voltage detection module and a logic circuit module. The voltage detection module is configured to output a first detection signal, a second detection signal and a third detection signal through a first node, a second node and a third node, respectively. The logic circuit module is configured to output a monitoring signal through a fourth node; determine whether the first detection signal has a first preset level, whether the second detection signal has a second preset level, and whether the third detection signal has a third preset level, respectively; determine the monitoring signal to be in a valid state in response to the first detection signal having the first preset level, the second detection signal having the second preset level and the third detection signal having the third preset level.
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
H03K 19/003 - Modifications pour accroître la fiabilité
99.
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME
The disclosure relates to a semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate; a storage array located on the substrate and including a plurality of memory cells arranged in an array along a first direction and a second direction, each memory cell including a transistor structure that includes a gate electrode and an active area that includes a first active area and a second active area distributed on opposite sides of the gate electrode along the first direction; a word line extending along the second direction, being continuously and electrically connected with a plurality of gate electrodes in the memory cells arranged at intervals along the second direction; a bit line extending along the first direction and located on outside of each of the memory cells along the second direction. The bit line is continuously and electrically connected with the first active area and the second active area in a plurality of the memory cells arranged at intervals along the first direction.
Embodiments provide a control circuit and a dynamic random access memory. A first connector of the memory chip connects to an input terminal of a functional circuit via a first switch circuit, and an output terminal of the functional circuit connects to a second connector via a second switch circuit, where the first switch circuit and the second switch circuit correspond to a first switch state. A second connector is connected to an input terminal of a functional circuit via a third switch circuit, and an output terminal of the functional circuit is connected to the first connector via a fourth switch circuit, where the third switch circuit and the fourth switch circuit correspond to a second switch state. The switch circuit can control the first switch state or second switch state to be an on state on a basis of a location parity signal of the memory chip.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p.ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 11/4072 - Circuits pour l'initialisation, pour la mise sous ou hors tension, pour l'effacement de la mémoire ou pour le préréglage
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