An operation method for a memory system, a memory system and a storage medium, the method comprising: providing a logic block management table, the logic block management table comprising a first sequence corresponding to identifiers of M first logic blocks, the identifiers of the M first logic blocks being constructed as a ring queue, allocation states of the M first logic blocks being managed by means of the logic block management table, and M being an integer greater than or equal to 2 (S502); and, according to the sequence of the identifiers of the M first logic blocks in the ring queue, allocating a certain first logic block having an allocation state being a first state representing "unallocated" to a certain second logic block among N second logic blocks, N being an integer greater than M, and updating in the logic block management table the allocation state of the certain first logic block from the first state to a second state representing "allocated" (S504).
Methods for fabricating memory devices including capacitors are disclosed. In one aspect, a method of fabricating a memory device including capacitors is described, where each capacitor includes a first electrode and a second electrode separated by an isolation layer. The method includes providing a first wafer including a sacrificial material and the first electrodes disposed in first holes and in contact with the sacrificial material, hybrid bonding the first wafer with a second wafer including a complementary metal-oxide-semiconductor (CMOS) device, removing the sacrificial material to expose the first electrodes, depositing the isolation layer on the first electrodes, and forming the second electrodes on the isolation layer.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
3.
THREE-DIMENSIONAL MEMORY DEVICE UTILIZING DUMMY MEMORY BLOCKS TO MITIGATE DEFECTS
Structures of a three-dimensional (3D) memory device and systems containing the same are disclosed. In one example, the 3D memory device includes a memory plane, where the memory plane includes a first edge and an array of blocks. The array of blocks includes a plurality of memory blocks configured to store data, where the plurality of memory blocks are separated by continuous slit structures, and a first dummy region between the first edge and the plurality of memory blocks. The first dummy region includes alternating first slit structures and second slit structures, where the first slit structures and the second slit structures are discontinuous slit structures.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
4.
3D MEMORY CELL WITH DUAL-SIDE CONTACTS AND METHOD OF FABRICATION
Disclosed herein is a memory device that includes a stack structure. The stack structure (400) has alternating first layers (418) and dielectric layers (412). The stack structure has a first surface (424) and a second surface (426) opposite to the first surface. First contact structures (500, 502) include a conductive material. The first contact structures penetrate from the first surface into the stack structure to be in contact respectively with a first portion of first layers. Second contact structures (700, 702) include a conductive material. Each of the second contact structures penetrates from the second surface into the stack structure to be in contact respectively with a remainder portion of conductive layers other than the first portion of the first layers.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/50 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
5.
SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, MEMORY AND STORAGE SYSTEM
The present application discloses a semiconductor device, a manufacturing method therefor, a memory, and a storage system. The semiconductor device comprises multiple semiconductor columns. A gate electrode strip and a shielding strip are disposed between adjacent semiconductor columns along a second direction. A barrier strip extends along a first direction, and the barrier strip and the shielding strip are connected at one end along a third direction, the barrier strip being located on the same side of the shielding strip and the gate strip in the third direction. The present application can improve yield and reliability.
The present invention relates to the technical field of storage. Disclosed are a memory, a storage system, and a memory operation method. The method comprises: receiving an operation instruction from a controller; mapping a plurality of initial word line identifiers in the operation instruction into a plurality of physical word line identifiers; and by means of a plurality of first-type word lines indicated by the plurality of physical word line identifiers, executing an operation corresponding to the operation instruction on a plurality of first-type memory cell rows, wherein at least one third-type memory cell row is distributed between a first memory cell row and a second memory cell row among the plurality of first-type memory cell rows, and data stored in the plurality of first-type memory cell rows corresponds to a same piece of verification data. By means of the method, a plurality of pieces of data corresponding to a same piece of verification data can be written into discontinuous memory cell rows. In this way, the data stored in the adjacent memory cell rows can be respectively corrected by means of at least two pieces of verification data, thereby improving the data protection capability.
A decoder, which performs message updating by using inter-block serial decoding on the basis of multiple cyclic permutation matrices in a layer of a check matrix corresponding to a codeword frame; a posterior probability storage module (701) is configured to store posterior probability messages corresponding to each cyclic permutation matrix; a node message storage module (702) is configured to store messages that are transmitted from a check node to a variable node and correspond to each cyclic permutation matrix; a message updating module (703) is configured to sequentially receive, according to a first sequence, posterior probability messages corresponding to each cyclic permutation matrix and messages transmitted by a check node to a variable node, and sequentially output, according to a second sequence, updated messages that are transmitted from the check node to the variable node and correspond to each cyclic permutation matrix and updated posterior probability messages, the first sequence being the same as or different from the second sequence.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
8.
STORAGE SYSTEM, OPERATION METHOD FOR STORAGE SYSTEM, AND COMPUTER-READABLE STORAGE MEDIUM
The present application relates to the technical field of storage, and discloses a storage system, an operation method for the storage system, and a computer-readable storage medium. The storage system comprises: a memory and a memory controller; the memory comprises a storage array, the storage array is coupled to n word lines, the n word lines are sequentially arranged according to physical word line identifiers, and n≥2; the memory controller is configured to map the n physical word line identifiers into n virtual word line identifiers, wherein the physical word line identifiers corresponding to m adjacent virtual word line identifiers are spaced apart from each other, and 2≤m≤n; and the memory controller is configured to generate verification data on the basis of data corresponding to the m adjacent virtual word line identifiers. Verification data is generated on the basis of data corresponding to a plurality of adjacent virtual word line identifiers, that is, verification data is generated on the basis of data corresponding to a plurality of non-adjacent physical word line identifiers, thereby reducing the influence on verification data due to interaction between adjacent physical word lines, improving the success rate of data recovery, and improving the reliability of data storage and reading.
A memory system and an operation method therefor, a host-end apparatus and an operation method therefor, and a computer readable storage medium. The memory system comprises a memory device and a memory controller coupled to the memory device. The memory controller is configured to: receive a read command, wherein the read command instructs to read event log information generated during running by firmware, and the event log information comprises an index number and a parameter value of an event log; when firmware runs different functional modules, different event log elements are correspondingly generated, and the different event log elements correspond to different index numbers (S1001).
The present application provides a semiconductor structure and a manufacturing method therefor, a memory, and a memory system. The method comprises: forming a plurality of capacitor holes running through a first stacking layer in a stacking direction, wherein the first stacking layer comprises a first region and a second region, and the capacitor holes are located in the first region and the second region; forming a first electrode layer on the inner wall of the capacitor holes; forming a dielectric layer in the first region and the second region; forming a second electrode layer on the side of the dielectric layer facing away from the first stacking layer; removing the second electrode layer on the first stacking layer in the second region; and forming a contact structure running through the first stacking layer in the second region in the stacking direction. According to the method, the occurrence of severe etch loading effect in the first region when the capacitor holes are formed can be greatly avoided, thereby facilitating formation of a capacitor structure having uniform size in the first region, and thus improving the reliability of the capacitor structure.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
11.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR, AND STORAGE SYSTEM
The present application discloses a semiconductor device and a manufacturing method therefor, and a storage system. The device comprises a plurality of semiconductor pillars extending in a third direction, a plurality of gate structures extending in a first direction, and a plurality of shielding structures extending in the first direction; the gate structures and the shielding structures are distributed in a staggered manner in a second direction, and each semiconductor pillar is located between one shielding structure and a corresponding gate structure which are adjacent to each other; the size of the gate structure in the first direction is smaller than that of the shielding structure in the first direction, and the orthographic projection of the gate structure in the second direction is located within the range of the orthographic projection of the shielding structure.
Provided in the embodiments of the present disclosure are a memory device and an operation method therefor, and a memory system. The memory device comprises: a storage unit array and a peripheral circuit coupled with the storage unit array. The operation method for the memory device comprises: receiving a first instruction, wherein the first instruction instructs to write dummy data at a specified position in the storage unit array; in response to the first instruction, generating dummy data to be written; and writing the dummy data to be written at the specified position.
In certain aspects, a memory system includes a volatile memory device and a memory controller operatively coupled to the volatile memory device. The volatile memory device is configured to store a logical-to-physical (L2P) mapping table. The memory controller is configured to maintain the L2P mapping table stored in the volatile memory device, such that the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of memory blocks of a cache, respectively.
In certain aspects, a memory controller includes a logical-to-physical (L2P) search engine. The L2P search engine is configured to maintain an L2P mapping table that maps logical addresses to physical addresses, respectively. The L2P search engine is also configured to organize the physical addresses mapped by the L2P mapping table into address categories based on at least one address boundary.
Provided in the present application are a semiconductor device and a preparation method therefor, and a memory system. The semiconductor device comprises a first semiconductor structure. The first semiconductor structure comprises a first selection transistor, which comprises a first channel layer; a second selection transistor, which comprises a gate electrode; and a capacitor structure, which comprises a first electrode layer, wherein two ends of the first electrode layer are connected to the gate electrode of the second selection transistor and the first channel layer of the first selection transistor, respectively. The present application can prevent the problem of a state being broken by means of a reading operation.
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
16.
MEMORY SYSTEM, OPERATION METHOD THEREFOR, STORAGE MEDIUM AND MEMORY CONTROLLER
A memory system, an operation method therefor, a storage medium and a memory controller. The memory system comprises: at least one nonvolatile memory apparatus and a memory controller coupled to the at least one nonvolatile memory apparatus. Multiple levels of mapping tables are stored in the memory apparatus, the multiple levels of mapping tables being used for achieving mapping from logic addresses to physical addresses. The memory controller comprises a cache, part of the multiple levels of mapping tables being stored inside the cache. The memory controller is configured to perform a random read operation on data stored in the memory apparatus, and, in response to a random read range corresponding to the random read operation meeting a preset condition, adjust capacities used for storing different levels of mapping tables in the cache.
In one aspect, a method for operating a memory system that comprises a memory device is provided. The method includes, in response to determining a power-off occurrence of the memory system, initiating a power-off recovery (POR) procedure on the memory system; and in response to determining that a read error occurs during the POR procedure, performing one or more first read-retry operations on the memory device based on a plurality of first read-retry levels. The plurality of first read-retry levels are a portion of a plurality of second read-retry levels that are applied, during a standard read error handling procedure, in one or more second read-retry operations on the memory device.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p.ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G11C 16/20 - Initialisation; Présélection de données; Identification de puces
18.
SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREFOR, AND STORAGE SYSTEM
Embodiments of the present application provide a semiconductor device and a preparation method therefor, and a storage system. The semiconductor device comprises: a first semiconductor structure, the first semiconductor structure comprising a first well region; and a second semiconductor structure, the second semiconductor structure being bonded to the first semiconductor structure, and the second semiconductor structure comprising a second well region, wherein the second well region of the second semiconductor structure is provided with a fin field-effect transistor. In this way, the performance of a transistor can be improved while reducing the area of a chip.
Embodiments of the present application provide a semiconductor structure and a cutting method therefor, and a memory. The semiconductor structure comprises: a first wafer, wherein the first wafer comprises a plurality of first peripheral circuit dies, a first cutting channel located between the first peripheral circuit dies, and a first mark located at an edge of the first wafer, the pointing direction of the first mark is the same as the extension direction of the first cutting channel, the cleavage plane of the first wafer is parallel to the pointing direction of the first mark, and the pointing direction of the first mark is the extension direction of the symmetry line of the first wafer; and a second wafer, wherein the second wafer and the first wafer are stacked, and the second wafer comprises a plurality of storage array dies.
H01L 21/304 - Traitement mécanique, p.ex. meulage, polissage, coupe
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Embodiments of the present disclosure provide a wafer cutting apparatus and a wafer cutting method. The wafer cutting apparatus comprises: a carrying table, a first sub-cutting apparatus, and a second sub-cutting apparatus. The carrying table is used for carrying a wafer to be cut; the first sub-cutting apparatus is used for cutting said wafer from a first side; the second sub-cutting apparatus is used for cutting said wafer from a second side; and the first side and the second side are two opposite sides of the carrying table in a first direction, and the first direction is the thickness direction of the carrying table.
H01L 21/301 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour subdiviser un corps semi-conducteur en parties distinctes, p.ex. cloisonnement en zones séparées
B23K 26/00 - Travail par rayon laser, p.ex. soudage, découpage ou perçage
21.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR, MEMORY AND STORAGE SYSTEM
The present application discloses a semiconductor device and a manufacturing method therefor, a memory and a storage system. At least one cracking surface guide structure extending in a second direction is provided in a first scribe line block of a semiconductor device adjacent to a first device block in a first direction, wherein the second direction intersects with the first direction, the cracking surface guide structure comprises a first part and a second part which extend in the second direction, and the second part has better cracking surface permeability than the first part, so that during stealth die sawing, the die can be cracked in a predetermined direction and position.
H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
22.
OPERATION METHOD, MEMORY SYSTEM, SYSTEM, AND READABLE STORAGE MEDIUM
Provided are an operation method, a memory system, a system, and a readable storage medium. The memory system comprises a communication interface, which is configured to: receive an executable file of a set format; the executable file comprises: a file header and a plurality of segments of executable code; each of the plurality of segments of executable code comprises code segment data and a code segment header; and the code segment header is configured to indicate the storage location of the code segment data in the memory system.
A semiconductor structure and a manufacturing method therefor, a memory, and a memory system. The method comprises: forming a plurality of capacitor holes penetrating through stacked layers in a first region and a second region; forming a first electrode layer on inner walls of the capacitor holes; forming a dielectric layer on one side of the stacked layers; removing at least part of the dielectric layer from the second region; forming second electrode layers, the second electrode layers in the first region and the second region being spaced apart, and the first electrode layer being connected to the second electrode layer in the second region.
A semiconductor structure and a manufacturing method therefor, and a memory system. The method comprises: forming a stack layer and a channel structure, wherein the channel structure comprises a channel layer and a plug structure, and the plug structure is located on the side of the channel layer close to a first surface and comprises an exposed surface; oxidizing the exposed surface to form an oxide; forming an upper selective gate layer on the first surface; and forming an upper selective channel structure passing through the upper selective gate layer in a stacking direction and extending to the plug structure.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
25.
HOST, INFORMATION PROCESSING METHOD, ELECTRONIC SYSTEM, AND READABLE STORAGE MEDIUM
Embodiments of the present disclosure disclose a host, an information processing method, an electronic system, and a readable storage medium. Wherein, the host comprises a processor; and the processor comprises a first central processing unit (CPU) core bound with a first thread and a second CPU core bound with a second thread; wherein the first CPU core is configured to send an input/output (I/O) request to a storage device coupled to the host in response to control of the first thread, and the second CPU core is configured to receive feedback information related to the I/O request and sent by the storage device in response to control of the second thread.
An operation method for a memory system. The memory system comprises a memory controller and one or more memory apparatuses, which are coupled to the memory controller. The operation method comprises: determining one or more available sub-regions in a storage region, which is marked as a bad block, in a memory apparatus (S701); and writing, into the one or more available sub-regions, first data to be stored (S702). Further provided are a memory system, an electronic device and a computer-readable storage medium.
The present disclosure involves methods, apparatuses, and computer-readable storage media for media scan in a memory system. In one example, a method for a memory system includes receiving commands from a host coupled to the memory system, wherein the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a number of memory cells. The method further includes performing operations on the memory device based on the commands. The method further includes scanning at least a group of memory cells of the memory cell array by performing a number of scans within a scan period among the operations.
A voltage calibration method and apparatus, a memory, and a memory system. The method comprises: measuring a current target temperature of a storage unit array; by means of a standard reading voltage, separately performing a reading operation on the storage unit array at a plurality of candidate times, and obtaining corresponding target reading failure bit numbers; and, according to the target temperature, the target reading failure bit numbers, the candidate times and a stored target offset function, determining a target reading voltage offset parameter, and calibrating the reading voltage.
Provided in the embodiments of the present disclosure are a memory system and an operation method therefor, and a computer-readable storage medium. The memory system comprises at least one non-volatile storage apparatus and a controller, which is coupled to the non-volatile storage apparatus, wherein each non-volatile storage apparatus comprises a plurality of storage blocks, and at least one storage block in the at least one non-volatile storage apparatus forms a super block; and the controller is configured to: determine the ordering of a plurality of super blocks according to the number of erasures of each super block and the number of bad blocks in each super block, wherein the numbers of erasures of any two adjacent super blocks in the ordering meet a preset requirement, a first super block in the ordering is set in a spaced manner, and the number of bad blocks in the first super block is greater than a preset value; and determine, according to the ordering of the plurality of super blocks, the priority of performing a writing operation on the plurality of super blocks.
Embodiments of the present disclosure provide a memory system and an operation method thereof, and a computer readable storage medium. The memory system comprises a memory device and a memory controller coupled to the memory device. The memory controller is configured to: trigger an assertion when firmware of the memory system is abnormal in the operation process; when a hardware sequence command is not released within a preset duration after the firmware is abnormal, configure a flag for stopping the hardware sequence command; and in response to the flag for stopping the hardware sequence command, stop the hardware sequence command such that the hardware sequence command is released.
Disclosed in embodiments of the present application are a semiconductor device and a manufacturing method therefor, and a storage system. The device comprises: a stack structure, the stack structure comprising a first area and a second area; trench structures located in the first area and passing through the stack structure in a first direction; and a gate line isolation structure located in the second area and extending in a second direction, the gate line isolation structure passing through the stack structure in the first direction, and the gate line isolation structure being in a relief shape in a third direction.
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
32.
SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREFOR
Provided in the present disclosure are a semiconductor device and a preparation method therefor. The semiconductor device comprises a body structure and a peripheral structure, which is located on the periphery of the bottom of the body structure. The body structure comprises a top face and a bottom face, which are arranged opposite each other, and a side face, which is located between the top face and the peripheral structure. The side face comprises a first side face, which is connected to the peripheral structure, the transverse distance of the first side face relative to the peripheral structure gradually decreasing from the top face to the bottom face.
H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
33.
MEMORY CONTROLLER AND MEMORY SYSTEM PERFORMING WRITE DISTURBANCE MANAGEMENT
In certain aspects, a method for operating a non-volatile memory device is provided. The non-volatile memory device includes memory units. A write count of a first memory unit of the memory units is determined. In response to the write count of the first memory unit reaching one of preset values, a flipped bit count (FBC) of a second memory unit of the memory units that is physically adjacent to the first memory unit is obtained. In response to the FBC of the second memory unit exceeding a threshold, the second memory unit is refreshed.
In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.
Provided in the embodiments of the present application are a three-dimensional memory and a manufacturing method therefor, and a memory system. The three-dimensional memory comprises: a stack structure, wherein the stack structure comprises gate layers and dielectric layers which are alternately stacked; a plurality of channel pillars, wherein each channel pillar penetrates the stack structure in a first direction, and comprises a blocking layer, a storage layer, a tunneling layer and a channel layer which are arranged in sequence; and a plurality of isolation structures, wherein each isolation structure is located between the dielectric layer and the tunneling layer in a second direction perpendicular to the first direction, and penetrates at least part of the storage layer in the second direction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
36.
MEMORY DEVICE AND OPERATION METHOD THEREFOR, AND MEMORY SYSTEM
Embodiments of the present disclosure provide a memory device and an operation method therefor, and a memory system. The memory device comprises: a memory cell array, the memory cell array comprising a plurality of memory blocks; and a peripheral circuit, coupled to the memory cell array and configured to: apply a first effective erase voltage to a selected memory block among the plurality of memory blocks, and then apply a plurality of different erase verify voltages to the selected memory block; and determine a second effective erase voltage applied to the selected memory block according to a plurality of erase verify results corresponding to the plurality of different erase verify voltages, wherein the second effective erase voltage is greater than the first effective erase voltage.
Disclosed in the present application are an integrated package device, a manufacturing method therefor and a storage system. The integrated package device comprises at least one package module, and the package module comprises: a first sub-package module comprising a plurality of first electronic components; a second sub-package module comprising a plurality of second electronic components; a first circuit redistribution layer connected to each first bonding pad; and a second circuit redistribution layer connected to each second bonding pad.
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
Example memory devices, memory systems, and methods for reducing program disturb in NAND flash memory are disclosed. One example method includes applying, at a first time, a first voltage to a first select line coupled to a first select gate transistor, where the memory device includes a memory cell array. The memory cell array includes a memory string. The memory string includes the first select gate transistor, multiple memory cells, and a source select gate transistor. The multiple memory cells are positioned between the first select gate transistor and the source select gate transistor. The source select gate transistor is coupled to a source line of the memory cell array. A second voltage is applied at a second time to the first select line, where the second time is after the first time, and the second voltage is larger than the first voltage.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
39.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR, MEMORY, AND STORAGE SYSTEM
Disclosed in embodiments of the present application are a semiconductor device and a manufacturing method therefor, a memory, and a storage system. The method comprises: providing a substrate; forming a stop layer on one side of the substrate; forming a semiconductor layer on the side of the stop layer facing away from the substrate; forming a first through hole running through the semiconductor layer and the stop layer; and forming a gate structure on part of the inner wall and part of the bottom of the first through hole.
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for management of suspend and resume operations in a memory system are described. An example system includes a memory device and a controller. The controller is configured to: while performing data transfer to the memory device for a first operation corresponding to a first command, check whether a second command is received, wherein performing the data transfer to the memory device comprises performing the data transfer in terms of allocation units (AUs). In response to determining that the second command is received and that data transfer in a current AU is completed, the controller sends a suspend command to the memory device.
Embodiments of 3D memory devices and methods for forming the 3D memory device are disclosed. In one example, a 3D memory device includes a memory array and a peripheral circuit bonded to the memory array. The memory array includes a first multi-layer stacked structure, first capacitor structures penetrating the first multi-layer stacked structure, and a blocking structure penetrating the first multi-layer stacked structure. The first multi-layer stacked structure includes alternately stacked dielectric layers and conductive layers. Each of the first capacitor structures includes a dielectric layer and an electrode layer, where the dielectric layer of a first capacitor structure is disposed between the electrode layer of the first capacitor structure and the dielectric layers or the conductive layers of the first multi-layer stacked structure. The blocking structure separates one subset of the first capacitor structures from another subset of the first capacitor structures, and the blocking structure includes a dielectric layer and a conductive layer.
A method of memory device fabrication includes, providing a structure that includes first layers including word lines interleaved respectively with first dielectric layers, second layers including second dielectric layers interleaved respectively with the first dielectric layers, wherein the second layers are adjacent to the first layers, forming vertical recesses each of which extend to a surface of a respective one of the second dielectric layers in a first direction through the second layers, etching a respective lateral recess to expose a surface of a respective one of the word lines, and filling each respective lateral recess with at least one conductive material, such that the at least one conductive material in the respective lateral recess is in contact with the respective one of the word lines through the exposed surface.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/50 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 51/50 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
The present disclosure provides a memory device, comprising a memory array having memory cells, a page buffer coupled to the memory array through bit lines. The page buffer comprises a latch, and a control logic coupled to the page buffer and configured to: perform a first read operation on the memory cells; select, from the memory cells, a first plurality of memory cells in a first state and a second plurality of memory cells in a second state, based on the first read operation; perform a second read operation on the first plurality of memory cells; select, from the first plurality of memory cells, a third plurality of memory cells based on the second read operation; perform a third read operation on the third plurality of memory cells; and determine a read develop time based on the third read operation.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
The present disclosure relates to methods and devices for performing a read operation in a memory. In one example, a method for operating a memory device includes performing first sensing operations on memory cells of the memory device based on a first read voltage and a first set of develop times. The memory cells are coupled to a word line. The method further includes selecting a first read develop time from the first set of develop times based on results of the first sensing operations and performing a read operation on the memory cells based on the first read voltage and the first read develop time.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
45.
METHOD FOR CONTROLLING TEMPERATURE OF CHIPS AND RELATED CHIPS
A method for controlling a memory system is disclosed. For example, the method can include performing an operation on a memory device of the memory system, calculating a remaining payload based on a current total payload and a payload associated with the operation performed on the memory device, and when the remaining payload meets a predefined requirement, measuring a current temperature of the memory device and setting the current total payload associated with the current temperature for the memory device.
A method can include performing a single-read operation at a read reference voltage to detect bits from memory cells. Dummy data is previously programmed into the memory cells. Original bits of the memory cells can be determined based on a default read reference voltage and known values of the dummy data. The detected bits and the original bits are compared to determine an upper-state failed bit count (FBC) corresponding to the memory cells having threshold voltages shifted from above the read reference voltage to below the read reference voltage and a lower-state FBC corresponding to the memory cells having threshold voltages shifted from below the read reference voltage to above the read reference voltage. When a difference between the upper-state FBC and the lower-state FBC being smaller than a threshold, the read reference voltage can be determined to be a best read reference voltage.
A memory controller coupled to a memory device including an array of memory cells, each memory cell being set to one of 2 Nstates corresponding to a piece of N-bits data, where N is an integer greater than 1, and the array of memory cells being partitioned into one or more units. The memory controller is coupled to the memory device and configured to, upon executing instructions, obtain, from the memory device, a number P of memory cells in a unit of the units that are in one or more programmed states of the 2 N states; calculate, based on the number P, a compensated read voltage with an offset from a default read voltage; and provide, to the memory device, the compensated read voltage for a read operation performed on a selected memory cell of the memory cells in a unit of the units.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
A three-dimensional (3D) memory includes a first semiconductor structure having a 3D memory array, wherein the 3D memory array includes a plurality of memory planes, and a second semiconductor structure having a plurality of page buffer circuits, wherein each memory plane has a plurality of bit lines oriented in a bit line direction, a memory-plane-boundary, and a fixed location on the first semiconductor structure, each page buffer circuit has a page-buffer-circuit-boundary, the first semiconductor structure and the second semiconductor structure are bonded to each other in a face-to-face orientation, and a first memory-plane-boundary of a first memory plane, and a first page-buffer-circuit-boundary of a first page buffer circuit, are vertically aligned with each other such that a first portion of the first page-buffer-circuit-boundary is offset from the first memory-plane-boundary in the bit line direction so as to be non-overlapping with an area defined by the first memory-plane-boundary.
G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p.ex. NON-ET
In certain aspects, a memory device includes an array of memory cells, word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the array of memory cells through the word lines and configured to read a select row of the rows of the memory cells. The peripheral circuit includes a word line driver coupled to the select row through a select word line of the word lines and to an unselect row of the rows of the memory cells through an unselect word line of the word lines, and configured to apply a pass voltage to the unselect word line, and discharge the unselect word line from the pass voltage to a first recovery voltage that is greater than a supply voltage of the array of memory cells.
A memory device includes a memory array structure and a peripheral structure. The memory array structure includes at least one memory bank, and each memory bank includes a plurality of memory blocks. The peripheral structure includes a word line driver circuit and a sense amplifier circuit. A first area including the word line driver circuit and the sense amplifier circuit at least partially overlaps a second area including a memory block in a plan view of the memory device.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
51.
DUTY CYCLE CORRECTION CIRCUIT AND DUTY CYCLE CORRECTING METHOD
A duty cycle correction circuit (300) and a duty cycle correction method are disclosed. The disclosed duty cycle correction circuit (300) can comprise at least one low pass filter (320) configured to convert a clock signal to a voltage, and a voltage comparator (330) configured to compare the voltage with a reference voltage to output a comparison signal. The disclosed duty cycle correction circuit can further comprise a controller (340) configured to select, based on the comparing voltage, a duty cycle correction method from a first method and a second method different from the first method. The disclosed duty cycle correction circuit can further comprise a duty regulator (310) configured to perform a duty tuning operation to adjust a duty of the clock signal using the selected duty cycle correction method.
In certain aspects, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. At least one of the memory cells is set to one of 2Nlevels corresponding to a piece of N-bits data, where N is an integer greater than 1. The peripheral circuit is configured to apply a first program voltage to a select row of the memory cells, perform a first verification of the select row of the memory cells at a last level of the 2N levels after applying the first program voltage, perform a first verify fail count (VFC) based on a result of the first verification and a first VFC criterion, apply a second program voltage greater than the first program voltage to the select row of the memory cells after performing the first VFC, and perform a second VFC based on the result of the first verification and a second VFC criterion different from the first VFC criterion within a period of applying the second program voltage.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
In certain aspects, a memory device includes an array of memory cells in columns and rows, word lines respectively coupled to rows of the memory cells, and a peripheral circuit coupled to the rows of memory cells through the word lines. Each memory cell is set to one of 2Nfinal levels corresponding to a piece of N-bits data, where N is an integer greater than 2. The peripheral circuit is configured to program, in a first pass, a select row of the rows of the memory cells based on N data pages, such that each memory cell of the selected row is set to one of k intermediate levels, where k is an integer not greater than 2N. The peripheral circuit is also configured to read M data pages of the N data pages from the select row after the first pass, where M is an integer smaller than N.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
G11C 16/20 - Initialisation; Présélection de données; Identification de puces
G11C 16/22 - Circuits de sécurité ou de protection pour empêcher l'accès non autorisé ou accidentel aux cellules de mémoire
54.
THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF
Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The third semiconductor structure and the fourth semiconductor structure are sandwiched between the first semiconductor structure and the second semiconductor structure in a vertical direction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
55.
BEST READ REFERENCE VOLTAGE SEARCH OF 3D NAND MEMORY
A memory system includes a memory controller configured to determine a first best read offset of a first best read reference voltage with respect to a first default read reference voltage, and determine an anchor read reference voltage having a same offset as the first best read offset with respect to a second default read reference voltage. The first and second default read reference voltages are set for reading a page from a set of MLCs in a semiconductor memory device. A first scan range can be determined based on the anchor read reference voltage. A second best read offset of a second best read reference voltage with respect to the second read reference voltage can be determined by searching in the first scan range. A reading process can be performed to read the page from the set of MLCs based on the first and second best read reference voltages.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
56.
DIE, SEMICONDUCTOR PACKAGE STRUCTURE, ENABLE PIN CONFIGURATION METHOD AND MEMORY
The embodiments of the present disclosure relate to the technical field of storage. Disclosed are a die, a semiconductor package structure, an enable pin configuration method and a memory, which solve the problems in the prior art of high production costs and low production efficiency due to the fact that a flash memory chip comprises a fixed number of chip enable pins. The specific solution is: providing a die, in which a peripheral circuit is configured to: first, receive a control command and generate indication information according to the control command, wherein the control command is used for instructing the die to determine the address of the die, and the indication information is used for indicating that M dies share the same enable pin, with M being a positive integer greater than or equal to 1; and then, determine the address of the die according to the indication information and send the address of the die, wherein the address is used for the addressing of an enable signal provided by the enable pin.
3D memory devices are disclosed. In an implementation, a 3D memory device includes a stack structure having a core area and a staircase area. The core area includes conductive layers interleaved with first dielectric layers. Each stair of the staircase area has a different number of conductive layers interleaved with a different number of first dielectric layers. The staircase area has contact structures that penetrate through the first surface, a respective one of the stairs, and dielectric material. Each of the contact structures is electrically connected to a contacting conductive layer of the different number of conductive layers of one of the stairs. The staircase area has second dielectric layers, each of which isolates a remainder of the different number of conductive layers of the respective one of the stairs other than the contacting conductive layer from a respective contact structure.
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 41/50 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
58.
MEMORY AND CONTROL METHOD THEREFOR, AND MEMORY SYSTEM
The embodiments of the present application provide a memory and a control method therefor, and a memory system. The memory comprises a memory cell array and a peripheral circuit. The peripheral circuit at least comprises: a trigger circuit, which comprises a reference signal output circuit and a failbit signal output circuit, wherein the failbit signal output circuit is configured to generate a failbit signal according to a detection signal obtained by verifying the memory, and the reference signal output circuit is configured to output a plurality of reference signals; and a comparator, which is coupled to the trigger circuit, wherein the comparator is configured to compare the failbit signal with at least one of the reference signals so as to output a verification result.
Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a disclosed 3D memory device comprises a first semiconductor structure including a core region, a spacer region, and a periphery region, and a second semiconductor structure including a second periphery circuit on a substrate. The first semiconductor structure comprises a memory stack on a semiconductor layer in the core region, a first periphery circuit on the semiconductor layer in the periphery region, and a spacer structure in the spacer region to separate the memory stack and the first periphery circuit. The second semiconductor structure is connected to the first semiconductor structure.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
60.
CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE
The present invention relates to the technical field of semiconductors, and provides a chip packaging structure and a manufacturing method therefor, and an electronic device, for use in reducing the area of a chip packaging structure and improving the signal transmission speed. A semiconductor structure comprises a package substrate, the package substrate having a first surface; a first chip located on the first surface of the package substrate and electrically connected to the package substrate; a conductive column located on the first surface of the package substrate and electrically connected to the package substrate; and a second chip located on the side of the first chip and the conductive column distant from the package substrate, and electrically connected to the conductive column. The orthographic projection of the conductive column on the package substrate is located within the orthographic projection of the first chip or the second chip on the package substrate. The chip packaging structure is used for being connected to a circuit board in the electronic device.
The present disclosure relates to the technical field of storage. Provided are a storage system and an operation method for a storage system, which aim to solve the problem of the cache efficiency of check data. The storage system comprises a controller and a three-dimensional non-volatile memory, which are coupled, wherein the three-dimensional non-volatile memory comprises a three-dimensional storage array, and the three-dimensional storage array comprises a plurality of word lines and a plurality of pages, which are coupled. The controller is configured to: calculate, by taking as a unit page data corresponding to one word line, page data corresponding to a received first word line to obtain a first piece of RAID check data, and store the first piece of RAID check data in a check cache space; and calculate page data corresponding to a received (i +1)th word line and an ith piece of RAID check data to obtain an (i+1)th piece of RAID check data, and store the (i+1)th piece of RAID check data in the check cache space, wherein the (i+1)th piece of RAID check data covers the ith piece of RAID check data, i being a positive integer greater than or equal to 1.
G11B 33/04 - ENREGISTREMENT DE L'INFORMATION BASÉ SUR UN MOUVEMENT RELATIF ENTRE LE SUPPORT D'ENREGISTREMENT ET LE TRANSDUCTEUR - Éléments de structure, détails ou accessoires non prévus dans les autres groupes de la présente sous-classe Ébénisterie; Boîtiers; Bâtis; Disposition des appareils dans ou sur ceux-ci modifiés pour le rangement des supports d'enregistrement
62.
THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF
Three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. In certain aspects, a method for forming a 3D memory device can comprise forming a first semiconductor structure, comprising forming a stack structure on a first substrate, and forming a gate line slit structure including a filling structure penetrating the stack structure and extending into the first substrate. The method can further comprise forming a second semiconductor structure including a periphery circuit on a second substrate, and bonding the second semiconductor structure to the first semiconductor structure. The method can further comprise removing a portion of the first substrate and a portion of the gate line slit structure extended into the first substrate, and forming a supplemental semiconductor layer on a remaining portion of the first substrate.
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
63.
MEMORY SYSTEM PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREFOR
A memory system packaging structure and a manufacturing method therefor. The memory system packaging structure comprises: a memory chip, which comprises a first surface; a memory controller, which is located on the first surface; and a rewiring layer, which is located on the side of the memory controller away from the memory chip, wherein the memory chip and the memory controller are respectively electrically connected to the rewiring layer.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p.ex. contacts planaires
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
64.
VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME
In certain aspects, a semiconductor device includes a vertical transistor, a metal bit line, and a pad layer. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The metal bit line extends in a second direction perpendicular to the first direction and coupled to a terminal of the vertical transistor via an ohmic contact. The pad layer is positioned between the gate electrode and the metal bit line in the first direction. The gate dielectric and the pad layer have different dielectric materials.
In certain aspects, a memory device includes a plurality of memory cells and a peripheral circuit coupled to the plurality of memory cells. The peripheral circuit includes a page buffer, which includes a page buffer circuit and control logic coupled to the page buffer circuit. The page buffer circuit includes a dynamic storage unit and a first non-dynamic storage unit. The control logic is configured to determine whether an information swapping process is performed between the dynamic storage unit and the first non-dynamic storage unit based on a type of an operation to be performed on the page buffer circuit and an information storage manner between the dynamic storage unit and the first non-dynamic storage unit. The control logic is further configured to perform the operation on the page buffer circuit based on the determining whether the information swapping process is performed.
The present disclosure relates to the technical field of storage. Provided are a method for operating a storage system, and a storage controller, a storage system and an electronic device, which aim to solve problems such as the excessively long waiting time caused by data migration during a cache refresh process. The method for operating a storage system comprises: in response to a first space refresh instruction, when the size of an idle space of a memory is greater than or equal to a first threshold value, configuring part of the idle space to be an available space of a first space.
Embodiments of the present disclosure relate to, but are not limited to, the field of semiconductors, and disclosed are a storage system, a controller, a memory and an operation method, and an electronic device. The storage system comprises a controller and a memory which are coupled, wherein each storage unit of the memory is used for storing m pieces of bit information, and the controller comprises at least one of an Exclusive-OR circuit, an inverter and an access circuit. The controller is used for receiving n groups of logical page data, and selectively generating at least one group of logical page data by means of at least one of the Exclusive-OR circuit, the inverter and the access circuit under different values of m and n. The controller is also used for transmitting the m groups of logical page data to the memory so as to generate 2n different data states in the memory, the m groups of logical page data comprising the n groups of logical page data and the at least one group of logical page data, and the m groups of logical page data comprising the m pieces of bit information of one group of storage units. In this way, the memory can realize multiple storage unit modes.
A method for controlling cache programming of a NAND flash memory is disclosed. A programming failure signal is received by a memory controller from the NAND flash memory indicative of failure of the cache programming. After receiving the programming failure signal, a first page buffer release command is sent by the memory controller to the NAND flash memory to release new programming data cached by the NAND flash memory. The cached new programming data is received by the memory controller from the NAND flash memory. After receiving the cached new programming data, a second page buffer release command is sent by the memory controller to the NAND flash memory to release current programming data used for the cache programming. The current programming data is received by the memory controller from the NAND flash memory. The current programming data is reconstructed by the NAND flash memory after releasing the cached new programming data.
G06F 15/16 - Associations de plusieurs calculateurs numériques comportant chacun au moins une unité arithmétique, une unité programme et un registre, p.ex. pour le traitement simultané de plusieurs programmes
69.
THREE-DIMENSIONAL FERROELECTRIC FIELD EFFECT TRANSISTOR RANDOM ACCESS MEMORY DEVICES AND FABRICATING METHODS THEREOF
The present disclosure provides a memory device that includes a film stack having functional tiers stacked in a first direction. Each functional tier includes a first dielectric layer and a conductive layer. The memory device also includes channel structures disposed in an array core region, wherein each channel structure extends through the film stack in the first direction. Each channel structure includes a control gate in a center, a memory film that is disposed on a sidewall of the control gate and includes a ferroelectric film. Each channel structure also includes a channel layer disposed on a sidewall of the memory film.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H10B 51/10 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la configuration vue du dessus
H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/51 - Matériaux isolants associés à ces électrodes
Embodiments of 3D memory devices and methods for forming the same are disclosed. In one example, a 3D memory device includes a multi-layer stacked structure, where the multi-layer stacked structure includes a plurality of alternately stacked conductive layers and dielectric layers. The 3D memory device further includes a semiconductor layer over the multi-layer stacked structure, and a plurality of channel structures penetrating into the multi-layer stacked structure and the semiconductor layer. A first end of each channel structure is located within the semiconductor layer, and the first ends of the channel structures are aligned with one another.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
71.
ON-DIE TERMINATION CONFIGURATION FOR INTEGRATED CIRCUIT
A method of configuring an on-die termination circuit in each non-volatile memory die of a plurality of non-volatile memory dice that have one or more pads coupled in common, includes determining, by each of the non-volatile memory dice whether that non-volatile memory die is a target or a non-target for a memory operation; setting, by each of the non-volatile memory die that determines it is a target, a first on-die termination configuration value; setting, by each of the non-volatile memory die that determines it is a non-target, a second on-die termination configuration value; configuring, by each of the target non-volatile memory die, its corresponding on-die termination circuit to provide a first impedance based, at least in part, on the first on-die termination configuration value; and concurrently with the configuring by each target non-volatile memory die, configuring, by each non-target non-volatile memory die, its corresponding on-die termination circuit to provide a second impedance based, at least in part, on the second on-die termination configuration value.
In certain aspects, a memory device includes an array of memory cells columns and rows, word lines respectively coupled to rows of the memory cells, bit lines respectively coupled to the columns of the memory cells, and a peripheral circuit coupled to the array of memory cells through the bit lines and the word lines and configured to program a select row of the rows of the memory cells based on a current data page. Each memory cell is set to one of 2 N levels corresponding a piece of N-bits data, where N is an integer greater than 2. The peripheral circuit includes page buffer circuits respectively coupled to the bit lines. Each page buffer circuit includes one cache storage unit, N-1 data storage units, and a multipurpose storage unit. The cache storage unit is configured to sequentially receive N bits of the current data page and N bits of a next data page, and sequentially store one of the N bits of the current data page and each of the N bits of the next data page. The data storage units each is configured to sequentially store a respective one of the N bits of the current data page and a respective one of the N bits of the next data page. The multipurpose storage unit is configured to store at least one of the N bits of the current data page.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
73.
MEMORY SYSTEM AND OPERATION METHOD THEREFOR, MEMORY CONTROLLER, AND MEMORY
Disclosed in embodiments of the present disclosure are a memory system and an operation method therefor, a memory controller, and a memory. The memory system comprises a memory; the memory comprises a memory cell array and a peripheral circuit coupled to the memory cell array; and the memory cell array comprises memory cells capable of storing m pieces of bit information, wherein m is a positive integer greater than 1. The operation method comprises: the peripheral circuit determining an (n+1)-th group of logical page data according to a received prefix command and received n groups of logical page data, wherein n is a positive integer, and n+1 is a positive integer less than or equal to m; and writing the n groups of logical page data and the (n+1)-th group of logical page data into the memory cell array, so as to generate 2n different data states in the memory cell array.
In certain aspects, a memory system includes a memory system, coupled to a host memory, comprising a memory device, comprising first memory cells and second memory cells; a memory controller, coupled to a host and the memory device, configured to write a first data to the first memory cells and/or a second data to the second memory cells, wherein the first data comprises user data, and the second data comprises swap data from the host memory.
Provided in the present application is a three-dimensional memory, comprising: a stacked layer, which is located on a semiconductor layer; a storage channel structure, which penetrates through the stacked layer and comprises a first channel layer; a selective gate structure, which is located on the side of the stacked layer that faces away from the semiconductor layer; a selective channel structure, which penetrates through the selective gate structure and comprises an insulating layer and a second channel layer that are arranged from outside to inside; and a barrier layer, which comprises: a first barrier portion located on the end face of the insulating layer that is close to the semiconductor layer; and a second barrier portion located on the surface of the insulating layer that faces away from the second channel layer. The barrier layer provided in the three-dimensional memory in the embodiments of the present application can effectively prevent the diffusion of impurity particles doped in a conductive layer to a gate dielectric layer, such that the quality of the gate dielectric layer is ensured, thereby facilitating control over the stability of a TSG transistor.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
76.
THREE-DIMENSIONAL MEMORY, MANUFACTURING METHOD THEREFOR, AND MEMORY SYSTEM
Provided in the present application are a three-dimensional memory and a manufacturing method therefor. The three-dimensional memory comprises: a stacked layer, located on a semiconductor layer; a memory channel structure, penetrating through the stacked layer and comprising a first channel layer; a selective gate structure, located on the side of the stacked layer facing away from the semiconductor layer; and a selective channel structure, penetrating through the selective gate structure, and comprising a barrier layer and a second channel layer which are arranged from outside to inside. The barrier layer arranged in the three-dimensional memory in some embodiments of the present application can effectively prevent impurity particles doped in a conductive layer from diffusing to a gate dielectric layer, thereby ensuring the quality of the gate dielectric layer, and facilitating controlling the stability of TSG transistors.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
77.
THREE-DIMENSIONAL MEMORY AND MANUFACTURING METHOD THEREFOR, AND MEMORY SYSTEM
Provided in the present application are a three-dimensional memory and a manufacturing method therefor. The three-dimensional memory comprises: a stacked layer, located on a semiconductor layer; a memory channel structure, passing through the stacked layer and comprising a first channel layer; and a selective gate structure, located on the side of the stacked layer facing away from the semiconductor layer; and a selective channel structure, passing through the selective gate structure, and comprising a second channel layer, wherein a first end portion of the first channel layer away from the semiconductor layer is in contact with a second end portion of the second channel layer close to the semiconductor layer. The first channel layer and the second channel layer of the three-dimensional memory provided in the present application can be in direct contact connection, thereby avoiding lead-in channel plugging, and ameliorating the problem of programming interference.
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
H10B 41/23 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés
H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
78.
MEMORY DEVICE, OPERATING METHOD THEREOF, AND MEMORY SYSTEM
A memory device includes at least one memory cell array block and a control logic. The memory cell array block includes multiple layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The memory cell array block is divided into at least two memory cell array subblocks, each memory cell array subblock comprising a number of layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The control logic is coupled to the memory cell array block, and configured to: erase, read or program the memory cell array block using a block mode or a subblock mode, and when the memory cell array block is erased, read, or programmed under the subblock mode, determine, at least based on a state of one of the two memory cell array subblocks, an operation strategy of the other memory cell array subblock.
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
79.
THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME
In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.
In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
81.
MEMORY DEVICE, OPERATING METHOD THEREOF, SYSTEM, AND STORAGE MEDIUM
A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a peripheral circuit. The memory string includes a memory cell and a select transistor including a storage layer. The word line is coupled to the memory cell. The select line is coupled to the select transistor. The peripheral circuit is coupled to the SL, the BL, the select line, and the word line. The peripheral circuit is configured to: apply a first voltage to the select line; and apply a second voltage to the SL and/or the BL, in which a first peak level of the first voltage is greater than a second peak level of second voltage.
G11C 16/20 - Initialisation; Présélection de données; Identification de puces
G11C 16/12 - Circuits de commutation de la tension de programmation
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
82.
WORD-LINE-PICKUP STRUCTURE AND METHOD FOR FORMING THE SAME
A memory device, having a plurality of first-word-lines, each first-word-line having a first portion, a second portion, and a third portion; a plurality of second-word-lines, each second-word-line having a first portion, a second portion, and a third portion; and a memory array having a first side, a second side laterally opposite the first side, and a third side. The first portions of each first-word-line and each second-word-line are spaced apart from their respective third portions. The second portion of each first-word-line and the second portion of each second-word-line are non-parallel and non-co-linear with their respective first portions and third portions. Each first-word-line is disposed such that its second portion is adjacent to the first side, and each second-word-line is disposed such that its second portion is adjacent to the second side. The memory device further has a plurality of first-side-word-line-pickup-structures, and a plurality of second-side-word-line-pickup-structures.
Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device comprises a first semiconductor structure comprising: an array of first-type through stack structures in a first region and an array of second-type through stack structures in a second region, and a slit structure separating the array of first-type through stack structures from the array of second-type through stack structures. The 3D memory device further comprises a second semiconductor structure comprising, a first periphery circuit and a second periphery circuit at different levels. The second semiconductor structure and the first semiconductor structure are bonded together, such that the first periphery circuit is located between the second periphery circuit and the first semiconductor structure.
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10B 53/40 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
84.
THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF
Three-dimensional (3D) memory devices and fabricating methods are disclosed. A disclosed 3D memory device comprises: a first semiconductor structure, comprising: an array of first type through stack structures in a first region of a memory stack; an array of second type through stack structures in a second region of the memory stack; a semiconductor layer including a first portion on the array of first type through stack structures and a second portion on the array of second type through stack structures; multiple vias each penetrating the semiconductor layer and in contact with a corresponding one of the first type through stack structures or the array of second type through stack structures; and a slit structure separating the array of first type through stack structures from the array of second type through stack structures, and separating the first portion of the semiconductor layer from the second portion of the semiconductor layer.
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10B 53/40 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
85.
MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD THEREOF
A memory device, a memory system, and a method thereof are provided. In the method, an N-th programming pulse is applied to a word line coupled to memory cells of the memory device each with a target programming state being an i-th programming state. A first sub-verification and an M-th second sub-verification are performed on the memory cells to obtain a first sub-result and an M-th second sub-result, respectively. Based on the M-th second sub-result, a subset of the memory cells is determined to be programmed with an (N+1) -th programming pulse. Then, the (N+1) -th programming pulse is applied to the word line. After applying the (N+1) -th programming pulse to the word line, the memory cells are determined to be successfully programmed to the i-th programming state based on the first sub-result indicating that a number of failed bits in the first sub-verification is less than a first preset value.
A memory device includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a vertical transistor having a first terminal and a second terminal, a storage unit having a first end coupled to the first terminal of the vertical transistor, and a bit line coupled to the second terminal of the vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction, and a gate structure coupled to at least one side of the semiconductor body. The vertical transistor is disposed between the bit line and the storage unit along the first direction.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 7/12 - Circuits de commande de lignes de bits, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
87.
SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME
A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a vertical transistor. The vertical transistor includes a semiconductor body extending in a first direction. The semiconductor body includes a source/drain at one end of the semiconductor body. The vertical transistor also includes a gate structure coupled to at least one side of the semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The vertical transistor further includes a silicide. At least part of the silicide is above the source/drain. An area of the silicide is larger than an area of a first surface of the source/drain. The first surface is vertical to the first direction.
A memory device, a memory system, and a program operation method are disclosed. In one example, at an ithprogramming loop, in response to determining that index i is greater than or equal to a first preset value and less than an initial verification loop number corresponding to a target state of memory cells in the memory device, an ith programming inhibition operation may be performed on the memory cells of the target state. Index i may be a positive integer, and the initial verification loop number may indicate a programming loop number that starts a verification operation corresponding to the target state of the memory cells.
A semiconductor device and methods for forming the same are provided. The method includes: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, where the spacer is laterally extending along the first lateral direction; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.
A semiconductor device and methods for forming the same are provided. The semiconductor device includes an array of vertical transistors. Each transistor includes a semiconductor body extending in a vertical direction, and a gate structure located adjacent to a sidewall of the semiconductor body. The gate structures of each row of vertical transistors are connected with each other and extend along a first lateral direction to form a word line. A first word line of a first row of vertical transistors is located at a first side of the semiconductor bodies of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and a second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located at a second side of the semiconductor bodies of the second row of vertical transistors along the second lateral direction.
A three-dimensional memory device having vertical transistors and a method for forming the same are disclosed. In an example, the memory device includes an array of memory cells each including a vertical transistor. Along a first direction, one of the vertical transistors is arranged between two of separation structures in a plan view. Each of the separation structures includes a protrusion, and the separation structure and a corresponding protrusion are integral. The memory device also includes a plurality of bit lines that include at least one conductive layer. The at least one conductive layer is arranged between two protrusions of the two separation structures and on the one of vertical transistors to couple one of the bit lines with the one of the vertical transistors.
Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a 3D semiconductor device includes: an array of vertical transistors each comprising a semiconductor body extending in a vertical direction; a plurality of word lines each extending in a first lateral direction, wherein each word line is shared by a row of the vertical transistors arranged along the first lateral direction; and a plurality of bit lines each extending in a second lateral direction perpendicular to the first lateral direction; wherein the semiconductor bodies are further arranged along a third lateral direction different from the first lateral direction and the second lateral direction.
A memory device includes a memory array including memory blocks, and a control circuit coupled to the memory array. The control circuit is configured to when multi-pass program operations are performed, during a non-last pass program of the memory cells in a first memory sub-block of a first memory block, determine verify loop counts of verify operations after programming the memory cells in the first memory sub-block of the first memory block to one or more first target program states; and when programming the memory cells in a second memory sub-block of the first memory block to the one or more first target program states using the same program and verify conditions as for the first memory sub-block of the first memory block, during the non-last pass program, not perform at least the verify operation corresponding to the last of the verify loop counts.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
94.
THREE-DIMENSIONAL MEMORY AND PREPARATION METHOD THEREFOR, STORAGE SYSTEM, AND ELECTRONIC DEVICE
The present disclosure relates to the technical field of semiconductor chips. Provided are a three-dimensional memory and a preparation method therefor, a storage system, and an electronic device. The three-dimensional memory comprises a stacked structure, an etching stop layer, a protective layer and a plurality of connecting columns, wherein the stacked structure comprises gate layers and dielectric layers, which are alternately arranged; the stacked structure comprises a plurality of steps; the etching stop layer is arranged on each step; the protective layer covers the stacked structure and the etching stop layer; and each connecting column penetrates the protective layer and the etching stop layer on the corresponding step and is electrically connected to the gate layer of the corresponding step.
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
95.
THREE-DIMENSIONAL MEMORY AND PREPARATION METHOD THEREFOR, STORAGE SYSTEM, AND ELECTRONIC DEVICE
The present disclosure provides a three-dimensional memory and a preparation method therefor, a storage medium, and an electronic device. The three-dimensional memory comprises a stacked structure, a plurality of first stop portions arranged along a first direction, a protective layer, and a plurality of contact columns. The stacked structure comprises a step structure, and the step structure comprises a plurality of staircase structures arranged along the first direction and having different heights along a second direction. The plurality of first stop portions are located on a plurality of steps of at least one staircase structure. The protective layer covers the step structure and the first stop portions, and the protective layer is at least partially located between the first stop portions and steps adjacent to the first stop portions. The contact columns pass through the protective layer and the first stop portions, and are connected to gate layers in the steps corresponding to the first stop portions.
H10B 51/50 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région limite entre la région noyau et la région de circuit périphérique
96.
PAGE BUFFER, MEMORY DEVICE, AND METHOD FOR PROGRAMMING THEREOF
A page buffer includes a first charge/discharge circuit and a second charge/discharge circuit coupled to a bit line. The first charge/discharge circuit is configured to store first bit line forcing information and apply a first bit line forcing voltage to the bit line based on the first bit line forcing information. The second charge/discharge circuit coupled to the bit line and configured to store a second bit line forcing information, and apply a second bit line forcing voltage, different from the first bit line forcing voltage, to the bit line based on the second bit line forcing information. The first bit line forcing voltage and the second bit line forcing voltage are both higher than a programming bit line voltage and lower than a programming-inhabit bit line voltage.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 7/12 - Circuits de commande de lignes de bits, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
97.
THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF
A method for forming a 3D memory device is provided. The method comprises forming an array wafer including a core array region, a staircase region, and a periphery region. Forming the array wafer includes forming an alternating dielectric stack on a first substrate, forming a plurality of channel structures in the alternating dielectric stack in the core array region, each channel structure including a functional layer and a channel layer, forming a staircase structure in the staircase region, and forming a plurality of dummy channel structures. The method further comprises bonding a CMOS wafer to the array wafer; and removing the first substrate; removing a portion of functional layer of each channel structure to expose channel layer, and doping the exposed portion of the channel layer.
H01L 27/11548 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région limite entre la région noyau et la région de circuit périphérique
H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H01L 27/11575 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région limite entre la région noyau et la région de circuit périphérique
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
98.
THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR FORMING THE SAME
A three-dimensional memory device includes memory arrays stacking in a first direction. Each of the memory arrays includes a stack structure including interleaved conductive layers and first dielectric layers extending in a second direction perpendicular to the first direction and a third direction perpendicular to the first direction and the second direction. The conductive layers include word lines and a drain select gate line, and the drain select gate line is separated by a second dielectric layer in the second direction.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
99.
METHOD FOR PROGRAMMING MEMORY DEVICE, MEMORY DEVICE AND MEMORY SYSTEM
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p.ex. de tension, de courant, de phase, de fréquence
100.
THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF
Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure can comprises a memory cell, a bit line contact coupled to the memory cell, a bit line coupled to the bit line contact, a source line contact coupled to the memory cell, and a source line coupled to the source line contact. The memory cell comprises a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact surrounding a first portion of the insulating layer, the word line contact coupled to a word line, and a plurality of plate line contact segments surrounding a second portion of the insulating layer, the plurality of plate line contact segments coupled to a common plate line.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques
brevets
