A multi-layered vertically stacked memory device and a method of forming. The vertically stacked memory device includes a hybrid bonding of a single layer memory die having a layer of memory devices and a back-side power delivery circuit network (BSPDN) with another single layer memory die having memory devices and a BSPDN. The BSPDN layers of each single layer memory die are hybrid bonded to form a 2-layer memory die. The structure includes a formed TSV at one side and C4 or solder bumps at an opposite side such that the 2-layer memory dies can be stacked to form a vertically stacked structure having multiple memory device layers. Similarly formed is a 4-layer memory die that can be stacked to form a vertically stacked structure having multiple memory device layers. The vertical stacked memory device of such 2-layer or 4-layer memory dies can be formed over an interposer.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
2.
MULTI-HOP QUESTION ANSWER RETRIEVAL AND REASONING FOR LARGE LANGUAGE MODELS
Mechanisms are provided for answering a multi-hop question. The mechanisms extract one or more entities included in the multi-hop question and generate, for each entity, a plurality of sub-questions to help answer the multi-hop question. The mechanisms obtain an answer to each sub-question from a knowledge base to convert each pair of the answer and the sub-question into each affirmative sentence. The mechanisms generate one or more reasoning sentences to answer the multi-hop question by using one or more affirmative sentences and determine whether the multi-hop question is answerable or not by using the one or more reasoning sentences. The mechanisms, in response to a positive determination, output an answer to the multi-hop question by using the one or more affirmative sentences and the one or more reasoning sentences.
Mechanisms are provided for optimizing a deep learning (DL) computer model for homomorphic encryption (HE) workload processing. The mechanisms receive an original DL computer model architecture that is to be optimized for HE workload processing, and modifying the original DL computer model architecture by replacing a self-attention layer of the original DL computer model with an HE friendly self-attention layer that comprises a Power SoftMax function that does not have exponent terms, to thereby generate a modified DL computer model architecture. The mechanisms execute a machine learning training of the modified DL computer model architecture, approximate one or more elements of the Power SoftMax function with polynomials to generate a trained HE optimized DL computer model, and output the trained HE optimized DL computer model for execution on HE workloads.
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p. ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
4.
MEDIATING COUPLING OF QUANTUM BITS USING CHAINS OF RESONATORS AND TUNABLE INDUCTIVE COUPLERS
Techniques are provided for mediating interactions (e.g., long range interactions) between quantum bits to facilitate quantum computing operations such as two-qubit gate operations. A device comprises a first quantum bit, a second quantum bit, and a coupling bus connecting the first quantum bit and the second quantum bit. The coupling bus comprises a plurality of transmission line resonators which are coupled in series, and at least one tunable inductive coupler to control a coupling between a first transmission line resonator and a second transmission line resonator of the plurality of transmission line resonators.
H03K 17/92 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs supraconducteurs
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
5.
DETERMINING AN OPTIMAL PATH TO SEARCH A BRANCH TARGET BUFFER
An approach is provided for determining an optimal path for searching a branch target buffer (BTB). Initial BTB search index results are generated by searching a prediction latency-optimized first accelerator. The initial BTB search index results are added as tentative items in a search index list. Other BTB search index results are generated by searching a capacity-optimized second accelerator. The first and second accelerators run concurrently. Difference(s) are determined between one or more results of the other BTB search index results and one or more results of the initial BTB search index results based on a comparison between respective results in the other BTB search index results and the initial BTB search index results. The one or more results of the initial BTB search index results are replaced in the search index list with the one or more results of the other BTB search index results.
Semiconductor devices include stacked nanosheet channels with inner spacers between respective pairs of the stacked nanosheet channels. Dummy nanosheet remnants are below respective inner spacers, vertically aligned with the respective inner spacers. A source/drain structure is on sidewalls of the plurality of stacked nanosheet channels. A backside contact makes contact with the source/drain structure.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
Execution of an instruction includes obtaining from an application program a request to execute of an instruction to perform an action defined by the instruction. Machine code accesses a function code in the instruction to locate a version number of firmware code of the instruction and a hash comprising a firmware code level of the instruction. Machine code locates the hash and the version number in a storage of the at least one computing device. Machine code provides the hash and the version number to the application program, wherein the application program issues the instruction if the hash is certified by a certification authority.
A computer hardware fuzzy logic system includes a controlled system and a fuzzy logic application configured to control the controlled system. A dataset defined by a period of time is retrieved from a store of historical input values for the controlled system. K clusters are generated from the dataset, and new fuzzy set definitions are generated for the K clusters. The fuzzy logic application updates old fuzzy set definitions with the new fuzzy set definitions. The fuzzy logic application also generates variable adjustments to the control system using the new fuzzy set definitions and received input values for the controlled system. The controlled system is modified using the variable adjustments.
According to a present invention embodiment, a system for processing queries for secure searches comprises one or more memories and at least one processor. The system determines for a query, via a first machine learning model, a region of an embedding space corresponding to search results. The region of the embedding space is distorted along one or more dimensions to produce distorted regions in the embedding space corresponding to different search results. A second machine learning model determines modified queries corresponding to the different search results of the distorted regions to produce obfuscated queries. Results are obtained from processing the obfuscated queries. A response to the query is produced based on the results for the obfuscated queries. Embodiments of the present invention further include a method and computer program product for processing queries for secure searches in substantially the same manner described above.
A computer-implemented method for creating an intermediate representation (IR) of a source program by disassembling a compiled executable file and accessing source information describing the source program. In embodiments, the method further includes matching individual statements of the source program to corresponding portions of the IR of the source program, where the mapping is based at least in part on the source information and determining a source program line number for at least one constraint of a plurality of constraints based on the matching. In embodiments, the method further includes outputting the source program line number and any user variables for the at least one constraint.
Computer-implemented methods for mitigating oscillation of a lift cable on a crane are provided. Aspects include obtaining characteristics of a load affixed to the lift cable via a hook, wind conditions in a location of the lift cable, and operational characteristics of the crane. Aspects also include calculating an estimated oscillation of the load based on a simulation of the crane lifting the load in the wind conditions and the operational characteristics of the crane, calculating a counter force to be applied to the lift cable via the hook, wherein the counter force will reduce the oscillation of the lift cable, and instructing a propulsion system affixed to the hook to apply the counter force to the hook.
B66C 13/06 - Dispositifs auxiliaires pour commander les mouvements des charges suspendues ou pour empêcher le câble de prendre du mou pour limiter ou empêcher le balancement longitudinal ou transversal des charges
An approach for generating time-series dynamic-system training data. The approach may comprise providing a plurality of dynamic systems to a dynamic system dictionary. Where the dynamical system dictionary may comprise a library of functions. The approach may further comprise classifying each of the plurality of dynamic systems. Where classifying may comprise, generating a hierarchical dynamic system data, based on constraint learning, with an encoder and noise generator. The approach may further comprise training a diffusion decoder to generate a time-series segment, based on the classified plurality of dynamical systems. Further, the approach may comprise providing a first time series data segment and generating time-series dynamical training data based on the diffusion decoder using the first time-series data segment as input.
Mechanisms are provided to perform application modernization through data modularization by using complex networking analysis. A static network of a data model is generated comprising nodes for database objects. Use case information is collected for use cases and community detection is performed on the static network to generate communities of database objects. A cohesion index for each community is determined and the use case information is integrated into the static model to generate a dynamic model having use case node(s) and edges representing interactions between the use case with database objects of the static model. A dispersion index is generated for each use case node and, in response to the dispersion index having a predetermined condition, the communities are dynamically optimized based on the cohesion index and the dispersion index to thereby generate a decomposed data model which is used for application modernization and/or migration.
In an approach to improve computer-based virtual world collaboration environments, embodiments of the present invention embodiments identify a context associated with a current state of a virtual environment and determines a physical object that is being rendered as a virtual display in the virtual environment based on the context. Further, embodiments render a virtual object representing the physical object according to the context using a generative model in a such a manner that the virtual object is rendered visually distinct from the physical object being represented.
An exemplary interconnect structure includes a first substrate, a second substrate vertically below the first substrate; and an underlayer structure between and in contact with the first and second substrates in which the underlayer structure between and in contact with the first and second substrates, a conductive connector between and electrically connecting the first and second substrates. The underlayer structure comprises an electromagnetic curable layer and a high thermal conductive layer and the underlayer structure laterally surrounds the conductive connector.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
16.
INTEGRATED CIRCUIT PACKAGE WITH DRAM LOCATED WITHIN INTEGRATED COOLING CHANNELS
An apparatus including a stack of a plurality of substrates, wherein the stack includes a plurality of channels extending therethrough. The plurality of channels are configured to allow air to flow therethrough; a plurality of dynamic random-access memory (DRAM) chips. Respective ones of the plurality of DRAM chips are attached to one of the plurality of substrates and located within one of the plurality of channels. The apparatus also includes a plurality of processor chips located on an outer surface of the stack, and a plurality of wires electrically connecting the plurality of DRAM chips to the plurality of processor chips.
H01L 23/467 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de gaz, p. ex. d'air
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
Methods and systems for code translation include translating source code for an original program, written in a first programming language, to source code for a translated program, written in a second programming language, using a language model. The original program and the translated program are instrumented, using comparison regions of each, to configure the original program and the translated program to generate respective outputs at equivalent points. The original program and the translated program are executed concurrently to generate an original output and a translated output. The language model is updated to correct the translated program based on a discrepancy between the original output and the translated output.
A processor chip includes hardware, multiple processor cores, multiple caches, and an accelerator. The processor chip is configured to receive a prefetch command from an external processor chip. The prefetch command is associated with a request for the external processor chip to utilize the accelerator. The hardware is configured to select one of the multiple caches for storing data that is to be prefetched to facilitate the requested utilization of the accelerator.
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec pré-lecture
G06F 12/0844 - Accès à une mémoire cache à accès multiples simultanés ou quasi-simultanés
19.
DYNAMIC CONTROL OF OPERATIONAL PARAMETERS IN LASER-BASED SHEET METAL CUTTING
An embodiment for dynamic control of operational parameters in laser-based sheet metal cutting is provided. The embodiment may include receiving real-time and historical data from one or more sources. The embodiment may also include computing one or more operational parameters during a cutting of a piece of sheet metal. The embodiment may further include identifying a cut profile and one or more specifications of the piece of sheet metal. The embodiment may also include based on determining a problem condition occurs in at least one region of one or more regions of the piece of sheet metal, correlating the one or more operational parameters with the at least one region where the problem condition occurred. The embodiment may further include identifying at least one operational parameter that resulted in the problem condition. The embodiment may also include adapting the at least one operational parameter.
A semiconductor device includes a first field effect transistor stacked on a second field effect transistor. The first field effect transistor has a metallic source/drain region. A second source/drain region of the second field effect transistor is separated from the metallic source/drain region by a middle dielectric isolation layer. A through contact passes through the middle dielectric isolation layer to connect the metallic source/drain region to the second source/drain region.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Methods and systems for printing an object include matching biological patterns of an original object, shown in an input image, to a database of biological information to generate an engineering parameter. A baseline design is generated using the engineering parameter derived from the input image. Performance of the baseline design is simulated according to a metric. The baseline design is iteratively adjusted to improve the simulated performance and generate a final design. A physical object is printed based on the final design.
A device includes a dielectric layer and a conductor in the dielectric layer including a first conductive material. A conductive liner wraps around the conductor and includes a second conductive material. A barrier layer is at an interface between the conductive liner and the dielectric layer, including a first oxide and a second oxide.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
23.
OPTIMIZATION TOOL WITH DYNAMIC, SCALABLE ACQUISITION FUNCTION
A multi-state acquisition function engine is provided for enhancing operation of an optimization tool to optimize a circuit device feature. Running the acquisition function engine facilitates tailoring optimization samples for objective function evaluation. The process includes configuring input parameters for running a genetic algorithm engine based, in part, on a current acquisition function state to tune the genetic algorithm engine based on the state. Further, the process includes running the genetic algorithm engine for one or more generations using the configured input parameters to generate a plurality of candidate samples, and providing selected sample(s) of the plurality of candidate samples to the objective function for generating a respective fitness score for optimizing the circuit design feature. The process further includes selecting, based at least in part on the generated fitness score(s), a new acquisition function state of the acquisition function engine for a next iteration.
A method for receiving a domain specific language description of a chemical structure; converting the domain specific language description of the chemical structure into a first graphical representation of the chemical structure; encoding the first graphical representation of the chemical structure into a first vector; and storing the first vector into a searchable database.
A semiconductor device comprises a plurality of channel layers in a stacked configuration, and a gate structure disposed through respective ones of the plurality of channel layers. The gate structure is surrounded on at least three sides by portions of the respective ones of the plurality of channel layers. The gate structure is disposed from an uppermost channel layer of the plurality of channel layers to a lowermost channel layer of the plurality of channel layers.
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
A method and system for managing servers by obtaining a configuration of a plurality of server groups, the configuration including information about virtual machines on servers of the server groups, and the plurality of server groups including at least one pool of standby servers that is at least operatively distinct from a rest of the plurality of server groups. The method further includes detecting a failure event of a failed server, automatically allocating, a standby server of the at least one pool of standby servers to a server group of the failed server based on a server priority value of the failed server and/or a virtual machine priority value of one or more virtual machines of the failed server, and remotely restarting the one or more virtual machines of the failed server on the standby server.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
27.
Automated data protection workflow for containerized applications
A system includes a processor that executes computer executable components stored in a memory. The computer executable components include an application identification component that identifies a new imperative application where recovery workflow for the new imperative application is unavailable. The computer executable components include an analysis component that analyzes the new imperative application to determine resources required to be protected; the analysis component determines an order of steps to be performed within a workflow to guarantee recovery of the new imperative application. The computer executable components include a recovery design component that utilizes a subset of legacy recovery plans to create, at least in part, a preliminary recovery plan for the new imperative application; the recovery design component tests the preliminary recovery plan and iteratively updates the preliminary recovery plan until a failure-free recovery plan is developed for the new imperative application.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
Updating of object model data of interface elements based on emission scores includes receiving first interaction data associated with an interaction session between a specific user and one or more interface elements of an operation of an application. A user emission score associated with the interaction session is generated based on the interaction data. A first cluster from a plurality of clusters is identified for the specific user based on the user emission score and cluster data. A cluster emission score associated with the first cluster is generated based on the user emission score and the cluster data associated with the first cluster. Further, object model data associated with each interface element of the one or more interface elements is received. The object model data associated with at least one interface element is updated. The updated object model data is output.
A computer-implemented method is provided. Aspects include receiving first waveform data of a first format, wherein the first waveform data includes event-based simulation data. Aspects include generating second waveform data of a second format based on the first waveform data, wherein the second waveform data is compatible with a cycle-based simulation environment. Aspects include performing one or more debugging operations by processing the second waveform data within the cycle-based simulation environment.
Provided are techniques for proactive message conversion. One or more messages in a first format are stored in a message queue. It is determined that the one or more messages in the message queue are to be converted from the first format to a second format based on a format usage pattern of a consuming application. The one or more of the messages are proactively converted from the first format to the second format. The proactively converted one or more messages in the second format are stored in a converted messages storage. A request is received, from the consuming application, for a message of the one or more messages, where the request indicates that the message is to be in the second format. The message in the second format is returned from the converted messages storage to the consuming application.
An integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a memory array including a plurality of memory macros including at least first and second memory macros. Each of the plurality of memory macros includes multiple partial arrays and a shared macro controller configured to control read and write access to the multiple partial arrays. The memory array also includes spare access control logic configured to direct an access to a first partial array in the first memory macro to a second partial array in the second memory macro.
A wafer test probe includes a pillar, a conductive line isolated from and extending through the pillar, a probe tip forming an opening, and a first conductive coating isolated from the pillar to coat the probe tip at least at the opening. The probe time includes blade features disposed in electrical contact with the conductive line via the first conductive coating. The blade features terminate at the opening and are configured to conductively penetrate a solder bump. A second conductive coating is disposed over the first conductive coating to coat the blade features.
A semiconductor integrated circuit (IC) device includes a first conductive source/drain region connected to a second conductive source/drain region by a plurality of active 2D material channels. The device further includes a conductive contact directly coupled to a bottom of the first conductive source/drain region, a liner directly coupled around an upper portion of the conductive contact, and a backside contact directly coupled to a lower portion of the conductive contact. The liner may reduce damage to the conductive contact that may occur during the formation of the backside contact.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/24 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des matériaux semi-conducteurs inorganiques non couverts par les groupes , , ou
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A computer-implemented method for updating a node in an orchestration platform. A processor set receives a patch of a disruptive update for the node in the orchestration platform. The node is a control plane node that is configured to run workloads. The processor set generates a copy for the node in the orchestration platform. The processor set allocates the workloads for the node to the copy for the node. The processor set updates the node using the patch of the disruptive update. The workloads are running on the copy for the node when the node is updating. The processor set allocates the workloads from the copy for the node back to the node upon finishing the disruptive update.
G06F 8/656 - Mises à jour pendant le fonctionnement
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
35.
INCREASING THE SPEED OF HOMOMORPHIC ENCRYPTION ENCODING
Mechanisms are provided for increasing the speed of an encoding process. The mechanisms classify operations in the encoding process based on learned associations between patterns of input data and corresponding encoding result types generated from encoding the patterns of input data. The mechanisms identify operations in the encoding process that can be pruned based on the classifications, to thereby generate a set of prune operations. In addition, the mechanisms replace operations in the set of prune operations with replacement operations that retrieve a corresponding previously generated result. Moreover, the mechanisms emit optimized encoding code comprising the replacement operations in replacement of the set of prune operations that are pruned, for execution of the encoding process using the optimized encoding code.
Electrical loads from an electrically powered unit plugged into a receptacle of a power distribution unit (PDU) can be detected, using a computer communicating with the PDU. The electrical load is analyzed by comparing an electrical cycle waveform of the electrical load to electrical cycle waveforms of problem waveforms accessible by the computer. When the electrical cycle waveform of the electrical load matches an electrical cycle waveform of one of the problem waveforms. In response to the electrical cycle waveform of the electrical load matching the electrical cycle waveform of one of the problem waveforms, the computer initiates an action to disable electrical power to the receptacle of the PDU.
H02J 3/14 - Circuits pour réseaux principaux ou de distribution, à courant alternatif pour règler la tension dans des réseaux à courant alternatif par changement d'une caractéristique de la charge du réseau par interruption, ou mise en circuit, des charges du réseau, p. ex. charge équilibrée progressivement
H02J 13/00 - Circuits pour pourvoir à l'indication à distance des conditions d'un réseau, p. ex. un enregistrement instantané des conditions d'ouverture ou de fermeture de chaque sectionneur du réseauCircuits pour pourvoir à la commande à distance des moyens de commutation dans un réseau de distribution d'énergie, p. ex. mise en ou hors circuit de consommateurs de courant par l'utilisation de signaux d'impulsion codés transmis par le réseau
37.
MONOLITHIC STACKED COMPLEMENTARY TRANSISTOR STRUCTURES WITH DUAL WORK FUNCTION METAL GATES
A device comprises a stacked transistor structure, and a shared gate structure. The stacked transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type, and disposed over the first transistor. The shared gate structure comprises a first metal gate structure of the first transistor, and a second metal gate structure of the second transistor. The second metal gate structure is embedded in the first metal gate structure.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
An adapter module executing on a computing device of a computing environment is to be used to transmit packets from a network interface card of the computing environment to a control program executing within the computing environment. The adapter module obtains packet information of a packet received at the network interface card. Based on obtaining the packet information, a packet completion queue entry is generated in a packet completion queue and the packet information is stored in the packet completion queue entry. The packet information is to be used to locate a data buffer into which the packet is stored. The packet completion queue entry is provided to the control program to be used by the control program to retrieve the packet from the data buffer.
A control program executing on a computing device of a computing environment transmits control request information to an adapter module executing within the computing environment. The transmitting uses a control plane transmit queue of a set of queues. The control plane transmit queue identifies a location to store the control request information to be retrieved by the adapter module. The control program receives from the adapter module an indication of another location storing control reply information replying to the control request information. The indication is obtained from a control plane receive queue of the set of queues. The control program retrieves from the another location the control reply information and performs processing based on the control reply information.
H04L 61/103 - Correspondance entre adresses de types différents à travers les couches réseau, p. ex. résolution d’adresse de la couche réseau dans la couche physique ou protocole de résolution d'adresse [ARP]
40.
INSTRUCTIONS USED IN COMMUNICATIONS BETWEEN COMPUTING DEVICE(S) AND A SHARED ADAPTER
An instruction executing within a computing environment is used to perform at least one operation on one or more controls of a queue to be used in communications between a control program executing within the computing environment and an adapter module of the computing environment. Execution of the instruction includes obtaining an indication of the queue for which at least one operation is to be performed on the one or more controls of the queue. At least one operation is performed on the one or more controls of the queue and a result of executing the instruction is provided.
Computer program products, computer-implemented method, and computer systems include a trusted element enabling host translation for a large page for a given block of memory of a secure guest. The enabling can include executing, in a trusted computing environment, a call from a host to import a page to a memory of the secure guest. The trusted element can determine that a page virtual address matches a page corresponding absolute address and based on this determination can increase a counter associated with the large page; the counter indicates small pages comprising the large page imported to guest memories. When the counter indicates that all the small pages were imported and based on this determination, the trusted element determines if that all the small pages meet pre-defined security requirements and if they do, enables host translation for the large page for the given block of memory of the secure guest.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
Tensor transformation includes obtaining an input tensor having a first data-layout format and elements of a first data type, and reformatting the input tensor to provide an output tensor having a second data-layout format and elements of a second data type, where the second data-layout is different from the first data-layout format and the second data type is different from the first data type. Optionally, the reformatting includes element quantization on input elements of the input tensor, where the element quantization performed on an input element of the input tensor includes converting the input element to an output element, of the second data type, as an element of the output tensor, using the scale value to scale to the input element, the offset value to apply an offset, and the clip maximum and clip minimum values to enforce a maximum value and a minimum value for the output element.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
43.
TENSOR PROCESSING FOR WITH MASKED ARTIFICIAL INTELLIGENCE FUNCTION BEHAVIOR
Tensor processing includes obtaining an input tensor, the input tensor including a dimension of index size n, determining an element count, c, based on an indicator, the indicator specified by the instruction, and the element count specifying a number of vector elements on which to perform an artificial intelligence function, obtaining an input vector, of the input tensor, of size n, and performing the artificial intelligence function, the performing the artificial intelligence function including performing the artificial intelligence function on a first c number of elements of the input vector to provide a corresponding c number of elements of an output vector of index size n of an output tensor.
An exemplary semiconductor structure includes first, second and third field effect transistor (PET) stack on a substrate. Each of the first, second and third FET stacks includes a top and a bottom transistor. Each transistor has a channel region, a gate insulator and a gate work function layer. Each of the gate work function layers in the top transistors of the first, second and third FETs having a different composition.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Integration of a set of robots to perform an activity includes obtaining a mobility parameter of each of a plurality of robots. The collective mobility of the set of robots from the plurality of robots is determined. The set of robots are integrated in an environment to perform an activity in case the collective mobility satisfies a target mobility threshold. The set of robots further performs, based on the integration of the set of robots, the activity in the environment.
G05D 1/69 - Commande coordonnée de la position ou du cap de plusieurs véhicules
G05D 1/224 - Dispositions de sortie sur les dispositifs de commande à distance, p. ex. écrans, dispositifs haptiques ou haut-parleurs
G05D 1/648 - Exécution d’une tâche au sein d’une zone ou d’un espace de travail, p. ex. nettoyage
G05D 101/10 - Détails des architectures logicielles ou matérielles utilisées pour la commande de la position utilisant des techniques d’intelligence artificielle [IA]
A nanosheet 1T-4R mask programed multi-level read-only memory component includes a plurality of nanosheet channels between a first source/drain and a second source/drain and a gate around the plurality of nanosheet channels. The component includes a first resistor upon a frontside surface of the first source/drain, a second resistor upon a frontside surface of the second source/drain, a third resistor upon a backside surface of the first source/drain, and a fourth resistor upon a backside surface of the second source/drain. Respective frontside contacts electrically connect the first resistor, the second resistor, and the gate to a frontside backend of line (BEOL) network. Respective backside contacts electrically connect the third resistor and the fourth resistor to a backside power delivery network (BSPDN).
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Embodiments relate to threshold voltage adjustable transistor using an interfacial dipole layer. A semiconductor structure includes a transistor having source/drain regions coupled to a channel region and a gate structure formed on the channel region. The gate structure includes a second layer stacked on a first layer, and an interfacial layer is between the first and second layers, the interfacial layer including a group 2A element or a group 3B element. A biomolecule layer formed on top of the gate structure.
G01N 27/414 - Transistors à effet de champ sensibles aux ions ou chimiques, c.-à-d. ISFETS ou CHEMFETS
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
48.
RESTAURANT MENU CUSTOMIZATION USING COMPUTER VISION AND NATURAL LANGUAGE PROCESSING
An approach is provided for customizing a restaurant menu. Dietary restrictions of a user are received. Text is extracted from a digital version of a menu of a restaurant. Ingredient(s) of a first menu item are identified within the extracted text. Using natural language processing (NLP), it is determined that the ingredient(s) include at least one ingredient that does not comply with the dietary restrictions. Ingredient(s) of a second menu item are identified within the extracted text. Using NLP, it is determined that the ingredient(s) of the second menu item comply with the dietary restrictions. Based on the at least one ingredient being in non-compliance and the ingredient(s) of the second menu item being in compliance, a digital menu is generated that includes the second menu item, but does not include the first menu item. The digital menu is displayed to the user.
G06K 7/14 - Méthodes ou dispositions pour la lecture de supports d'enregistrement par radiation électromagnétique, p. ex. lecture optiqueMéthodes ou dispositions pour la lecture de supports d'enregistrement par radiation corpusculaire utilisant la lumière sans sélection des longueurs d'onde, p. ex. lecture de la lumière blanche réfléchie
A semiconductor integrated circuit (IC) device includes a bottom source/drain region and a top source/drain region stacked above the bottom source/drain region. The semiconductor IC device further includes a bottom channel that is composed of a first two dimensional (2D) material and is connected to the bottom source/drain region. The semiconductor IC device further includes a top channel that is composed of a second 2D material that is different than the first 2D material and that is connected to the top source/drain region. In examples, the semiconductor IC device further includes a bottom channel interfacial region between the bottom source/drain region and the one or more gates and/or a top channel interfacial region between the top source/drain region and the one or more gates.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Interpretative execution is performed by a physical processor of a computing environment for a virtual processor executing on the physical processor. The performing interpretative execution includes obtaining an order code indicating an action to be taken for the virtual processor and accessing a shadow state description of the virtual processor to obtain an original state description origin. The original state description origin indicates the location of an original state description of the virtual processor, and the original state description includes state information of the virtual processor. An action is performed using an indicator of the state information of the virtual processor. The indicator is selected based on the order code, and the action is performed by the physical processor on behalf of the virtual processor.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
51.
SINGLE INSTRUCTION REGISTER PROVIDING MULTIPLE INSTRUCTION OPERANDS
An instruction is executed within a computing environment. Executing the instruction includes obtaining a plurality of operands of the instruction. Obtaining the plurality of operands includes retrieving from a register of the instruction multiple designations of multiple operand locations. The multiple operand locations are used to provide multiple operands of the plurality of operands of the instruction. Multiple operands of the instruction are determined from the multiple operand locations. One or more operations of the instruction are performed using one or more operands of the plurality of operands of the instruction to obtain a result of the instruction.
An automated signal electromigration violation resolution process is provided for a logic circuit design of an integrated circuit. The automated resolution process includes simulating, by at least one processor set, signal electromigration (SEM) for a logic circuit design of an integrated circuit, where the simulating generates signal electromigration metrics for the logic circuit design. Further, the process includes automatedly resolving, based on evaluating the signal electromigration metrics for violations, a signal electromigration metric violation of the logic circuit design. The automatedly resolving includes generating a signal electromigration limit-to-metric ratio for the metric violation, and auto-adjusting, using the generated limit-to-metric ratio, a switching factor of the logic circuit design to facilitate resolving the signal electromigration violation. Further, the process includes reevaluating the signal electromigration metrics of the logic circuit design using the auto-adjusted switching factor to confirm automated resolution of the signal electromigration metric violation.
G06F 30/3308 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation
G06F 30/323 - Traduction ou migration, p. ex. logique à logique, traduction de langage descriptif de matériel ou traduction de liste d’interconnections [Netlist]
53.
MONOLITHIC STACKED COMPLEMENTARY TRANSISTOR STRUCTURES WITH DUAL WORK FUNCTION METAL GATES
A device comprises a stacked transistor structure and a shared gate structure. The stacked transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type, and which is disposed over the first transistor. The shared gate structure comprises a first metal gate structure of the first transistor, a second metal gate structure of the second transistor, and a metallic connection layer. The second metal gate structure is embedded in the first metal gate structure with a dielectric layer disposed between the first metal gate structure and the second metal gate structure. The metallic connection layer electrically connects upper regions of the first metal gate structure and the second metal gate structure.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
The computer-implemented methods, computer program products, and computer systems include computer operations that include executing, in a trusted computing environment, a call from a host in an untrusted computing environment, where the call is to determine a status of a large page of memory for use by a secure guest, where the secure guest is managed by the host in the untrusted computing environment. The executing includes determining that all small pages comprising the large page and the large page meet pre-defined security requirements. The executing also includes, based on the determining, setting security properties of the large page and the small pages comprising the large page to enable translation for the large page for a given block of memory of the secure guest. The executing also includes storing in a computing element, a designation identifying the large page as belonging to the secure guest.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
Semiconductor devices are provided that include a conductor structure located in a shallow trench isolation structure that is positioned between two field effect transistors of a same conductivity type. The conductor structure is electrically connected to a backside contact structure, and the backside contact structure is electrically connected to at least one well region that straddles a sidewall of the backside contact structure. The area of contact between the backside contact structure and the well region provides a local well tap to the semiconductor device.
In an approach to improve three-dimensional (3D) manufacturing, methods determine, based on shape and dimensions of a hollow portion of a three-dimensional (3D) object, to create the 3D object using self-assembling cube robots submerged in a photosensitive resin tank. Additionally, methods instruct the self-assembling cube robots to collaborate to form an approximate shape of the hollow portion of the 3D object. Further, methods causing an ultraviolet (UV) projection system to emit holographic light beams around a structure of the self-assembling cube robots to create the 3D object with the hollow portion.
B29C 64/40 - Structures de support des objets en 3D pendant la fabrication, lesdites structures devant être sacrifiées après réalisation de la fabrication
B29C 64/129 - Procédés de fabrication additive n’utilisant que des matériaux liquides ou visqueux, p. ex. dépôt d’un cordon continu de matériau visqueux utilisant des couches de liquide à solidification sélective caractérisés par la source d'énergie à cet effet, p. ex. par irradiation globale combinée avec un masque
B29C 64/188 - Procédés de fabrication additive impliquant des opérations supplémentaires effectuées sur les couches ajoutées, p. ex. lissage, meulage ou contrôle d’épaisseur
B29C 64/386 - Acquisition ou traitement de données pour la fabrication additive
Dimension control in tensor multiplication includes obtaining first and second input tensors for matrix multiplication, obtaining a dimension control indicator that indicates a first dimension for the first input tensor to use as a common dimension for the matrix multiplication and indicates a second dimension for the second input tensor to use as the common dimension for the matrix multiplication, and performing the matrix multiplication to obtain one or more results, where performing the matrix multiplication includes selecting at least one vector of the first input tensor based on the first dimension indicated by the dimension control indicator and selecting at least one vector of the second input tensor based on the second dimension indicated by the dimension control indicator.
Tensor multiplication with quantization includes obtaining first and second input tensors, obtaining elements of a selected data type based on elements of the first input tensor and elements of the second input tensor, performing matrix multiplication on the elements of the selected data type, the matrix multiplication including performing quantization of intermediate results, and the quantization scaling the intermediate results to provide scaled results of the matrix multiplication, and generating output elements, for an output tensor, using the scaled results. Optional additional quantization is performed on elements of an input tensor to provide at least some of the elements of the selected data type for the matrix multiplication.
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
Tensor processing with broadcasting includes obtaining a first input tensor, the first input tensor including a dimension of index size one, and performing an artificial intelligence processing operation using the first input tensor and a second input tensor to obtain results, the second input tensor including a dimension of index size greater than one, where performing the artificial intelligence processing operation includes broadcasting the dimension of index size one of the first input tensor to match the dimension of index size greater than one of the second input tensor.
A method for identifying a connector and routing data and/or power to the connector include determining one or more pins from a plurality of pins are depressed on a universal interface for cable connectors device. The method further includes comparing a pin depression pattern for the one or more pins from the plurality of pins to a plurality of supported depression patterns associated with a plurality of supported connectors. The method further includes determining the pin depression pattern matches a first supported depression pattern from the plurality of supported depression patterns for a first supported connector from the plurality of supported connectors. The method further includes enabling, on the universal interface for cable connectors device, one or more internal switches to allow for an electrical connection to at least one pin from the one or more pins from the plurality of pins based on the first support depression pattern.
Provided are a computer program product, system, and method for reclaiming addresses used to communicate with machines over a network. A determination is made of a first machine using the first network protocol addressing scheme to communicate with a second machine over a network. A determination is made of whether the second machine supports a second network protocol addressing scheme. The first machine is configured to communicate with the second machine using the second network protocol addressing scheme to free a network address in the first network protocol addressing scheme used by the first machine to communicate with the second machine in response to determining that the second machine supports the second network protocol addressing scheme.
H04L 61/5046 - Résolution des conflits d'allocation d'adressesTest des adresses
H04L 61/251 - Traduction d'adresses de protocole Internet [IP] entre versions IP différentes
H04L 61/4511 - Répertoires de réseauCorrespondance nom-adresse en utilisant des répertoires normalisésRépertoires de réseauCorrespondance nom-adresse en utilisant des protocoles normalisés d'accès aux répertoires en utilisant le système de noms de domaine [DNS]
H04L 69/18 - Gestionnaires multi-protocoles, p. ex. dispositifs uniques capables de gérer plusieurs protocoles
H04L 101/686 - Types d'adresses de réseau en utilisant des hôtes à double pile, p. ex. dans les réseaux à protocole Internet de version 4 [IPv4]/protocole Internet de version 6 [IPv6]
62.
QUANTUM CIRCUIT COMPILATION INDEPENDENT OF CALIBRATION
A method, system, and computer program product for performing quantum circuit compilation independent of calibration. A calibration library is created with waveform or pulse generation instructions based on calibration data. A calibration library corresponds to pre-compiled code for the possible gates of the quantum circuit. Such pre-compiled code includes the waveform or pulse generation instructions. Furthermore, transpilation of a quantum circuit into a transpiled object is performed. After compiling the transpiled object into a binary, the calibration library is bound to the binary for execution on a quantum device. In this manner, by being able to compile the quantum circuit without knowing the exact calibration outcome, the requirement to re-compile the quantum circuit, such as when a calibration determines changing the waveform or pulse generation instructions between the compilation and execution of the quantum circuit, is precluded. As a result, there is increased efficiency of compute resources used for compilation.
G06N 10/80 - Programmation quantique, p. ex. interfaces, langages ou boîtes à outils de développement logiciel pour la création ou la manipulation de programmes capables de fonctionner sur des ordinateurs quantiquesPlate-formes pour la simulation ou l’accès aux ordinateurs quantiques, p. ex. informatique quantique en nuage
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
63.
Efficient data synchronization and segregation using virtualized and modular representations
Embodiments of the present invention involve composing synchronization structures that enable increased synchronization control. A virtual synchronization structure enables synchronization using structure traversal without replicating the full data set. This results in computing systems that are at a desired level of synchronization without full data replication. This method has the advantage of enabling limited sharing between systems and also speed.
G06F 16/27 - Réplication, distribution ou synchronisation de données entre bases de données ou dans un système de bases de données distribuéesArchitectures de systèmes de bases de données distribuées à cet effet
G06F 16/22 - IndexationStructures de données à cet effetStructures de stockage
H04L 67/1097 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau pour le stockage distribué de données dans des réseaux, p. ex. dispositions de transport pour le système de fichiers réseau [NFS], réseaux de stockage [SAN] ou stockage en réseau [NAS]
A computer-implemented method (CIM), according to one embodiment, includes performing a determination process for determining a satellite to transmit a first packet to a datacenter on Earth's surface, where the first packet originates on a parent satellite. The determination process includes determining a plurality of candidate satellites that each have a sufficient amount of processing resources for transmitting at least a predetermined amount of the first packet to the datacenter, where the candidate satellites include the parent satellite. The determination process further includes determining environmental conditions for the candidate satellites, and determining a first of the candidate satellites having environmental conditions associated with a first relatively lowest estimated energy expenditure during packet transmission. The CIM further includes causing the first candidate satellite to transmit at least a portion of the first packet to the datacenter.
A metal-insulator-metal capacitor (MIMCAP) structure of a semiconductor device is provided. The MIMCAP structure includes a substrate, first and second contacts formed at opposite sides of the substrate to define a MIMCAP region between the first and second contacts, vertical mandrels extending vertically upwardly from an uppermost surface of the substrate within the MIMCAP region and a MIMCAP. The MIMCAP is disposed in operable contact with the first and second contacts, on exposed sections of the uppermost surface of the substrate and over and around the vertical mandrels within the MIMCAP region. The MIMCAP includes horizontal sections between and over the vertical mandrels and outside outermost ones of the vertical mandrels and vertical sections along respective sidewalls of each of the vertical mandrels.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
66.
COLD PLATE HEAT REMOVAL DEVICES WITH ENHANCED INTERNAL FLOW DISTRIBUTION AND EXTERNAL HOSE ROUTING
Heat removal devices and a method for manufacturing heat removal devices. The heat removal devices are configured to enhance external hose routing and enhance internal flow distribution.
Layout methods and systems include determining an inter-chiplet communication model for chiplets of a semiconductor device design. A layout of the chiplets is optimized using an objective function that is a weighted combination of different objectives. A semiconductor device is fabricated in accordance with the layout of the chiplets by mounting the chiplets to a base substrate.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 119/06 - Analyse de puissance ou optimisation de puissance
G06F 119/08 - Analyse thermique ou optimisation thermique
Mechanisms are provided for dynamically implementing reactive actions in edge nodes of a network in response to user equipment (UE) behaviors. Data of UE events are collected to infer UE movements and UE behavior within the network. A machine learning computer model is executed on the collected data of UE events to predict UE movements and UE behavior and their impact on edge node conditions within the network with regard to quality of service (QoS) metrics. An accuracy of the precited impacts of the predicted UE movements and UE behavior is evaluated and, based on the accuracy, reactive action(s) to execute to reduce the predicted impact of inaccurate predictions on edge node conditions with regard to the QoS metrics are determined and recommended to a control plane of the network for implementation of at least one of the one or more reactive actions on edge node(s) of the network.
H04L 43/08 - Surveillance ou test en fonction de métriques spécifiques, p. ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p. ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: performing natural language processing to process a text string of a user, wherein the text string specifies characteristics of a container image to be built; processing, with use of natural language processing, instances of text-based data that describe respective ones of a plurality of container images stored within a container image repository; selecting, in dependence on a result of the performing natural language processing, and the processing, a base image from the plurality of container images; and presenting prompting data to the user that prompts building of a new container image, wherein the prompting data references the base image.
An embodiment for AI enabled 3D printing for a controlled microstructure through insulation integration is provided. The embodiment may include receiving real-time and historical data from one or more sources in a 3D printing environment. The embodiment may also include identifying a temperature and a cooling rate of a first material of a 3D printed object printed by a first 3D printing nozzle. The embodiment may further include identifying one or more required properties of one or more microstructures. The embodiment may also include computing a required cooling rate of the first material. The embodiment may further include predicting a time at which to apply a second material onto the first material. The embodiment may also include computing one or more specifications of the second material. The embodiment may further include causing a 3D printing nozzle to print the second material onto the first material.
B29C 64/393 - Acquisition ou traitement de données pour la fabrication additive pour la commande ou la régulation de procédés de fabrication additive
B29C 64/188 - Procédés de fabrication additive impliquant des opérations supplémentaires effectuées sur les couches ajoutées, p. ex. lissage, meulage ou contrôle d’épaisseur
A system may include a memory and a processor in communication with the memory. The processor may be configured to perform operations. The operations may include analyzing input source code and building a project instance based on the input source code. The operations may include matching a project instance to a template and generating, automatically, a command file based on the template.
Methods, systems, and products for socket downstop creep detection includes monitoring one or more creep detection sensors included within one or more downstops within a socket, where the socket is included on a printed circuit board (PCB) and a module is coupled to the socket, detecting socket downstop creep associated with the module based on data received from the one or more creep detection sensors, and performing one or more actions based on detecting the socket downstop creep.
An embodiment includes configuring a configuration of a crossbar of a memory management unit comprising a set of regions of N workers and D partitions. The embodiment includes writing by a worker, to D partitions in the set of regions of the crossbar. The embodiment also includes reading by a partition, N regions in the set of regions of the crossbar where each of the N regions is assigned an address that is mapped to a physical memory address and where an access control is achieved by the configuration of a N plus D mapping of workers to partitions of the crossbar of the memory management unit.
Mechanisms are provided for generating a cryptographic asset bill of materials of a source code. The mechanisms generate flow graph of the source code and execute a parsing and analyzing the source code based on a cryptographic asset knowledge base to identify an initial set of cryptographic artifacts referenced in the source code. The mechanisms execute, for each cryptographic asset in the initial set of cryptographic artifacts, a flow graph analysis to identify one or more dependent cryptographic artifacts to form sets of related cryptographic artifacts. In addition, the mechanisms generate, for each set of related cryptographic artifacts, a cryptographic asset, compile the generated cryptographic assets into a cryptographic bill of materials, and generate and output a report of the cryptographic bill of materials.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
75.
REBUILDING FAILED DRIVES WITH REDUCED WRITE OVERHEAD
A computer-implemented method according to one approach, is for rebuilding a drive in a redundant array of independent disks (RAID) array. The method includes causing blocks in a replacement drive to be pre-formatted in response to: a failed drive in the RAID array being replaced with the replacement drive, and a determination that the replacement drive can be pre-formatted. The method also includes recreating blocks of data that were stored in the failed drive, and determining whether the recreated blocks are equivalent to deallocated blocks. In response to determining one or more of the recreated blocks are not equivalent to deallocated blocks, data in the one or more recreated blocks is written to corresponding blocks in the replacement drive. However, in response to determining one or more of the recreated blocks are equivalent to deallocated blocks, the method includes intentionally refraining from modifying corresponding blocks in the replacement drive.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
76.
COHERENT HYPEREDGES FOR DOCUMENT QUESTION ANSWERING
Systems or techniques that facilitate coherent hyperedges for document QA are provided. In various embodiments, a system can generate, via a foundation model, a hypergraph comprising nodes and hyperedges, wherein the nodes represent entities in an information source, wherein the hyperedges represent relationships between two or more of the nodes, and wherein the hyperedges are associated with respective probabilistic weights. In various cases, the system can further select, from the hyperedges, a set of coherent hyperedges for a natural language question that represents coherent information from the information source.
A method, system, and computer program product for visualizing information regarding both a quantum circuit and a quantum device. A qubit architecture (e.g., two-dimensional qubit architecture) of the quantum circuit is displayed depicting operational characteristics of the quantum device in a first circuit layer. Furthermore, one or more images of the qubit architecture of the quantum circuit are displayed as being propagated along a third dimension axis across one or more circuit layers plotted with circuit instructions. Additionally, an image of the qubit architecture of the quantum circuit is displayed in a final circuit layer depicting measurement information about the quantum circuit and the quantum device. In this manner, information about both the quantum circuit and the quantum device upon which it is executed may be effectively visualized.
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
78.
REAL-TIME ASSISTANT FOR SOFTWARE INSTALLATION AND DEPLOYMENT
An example operation may include one or more of receiving a report of an error from an installation process of a software program as the installation process is being performed by a computer, executing an artificial intelligence (AI) model to predict at least one instruction to fix the error based on the report of the error, and presenting the at least one instruction via a graphical user interface of the computer associated with the installation process.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
In some implementations, a computing device may obtain a set of log lines associated with operations performed at a computing device. The computing device may select a first sample of the set of log lines. The computing device may identify a first set of log templates from the first sample, the first set of log templates having a first quantity of log templates. The computing device may select a second sample of the set of log lines. The computing device may identify a second set of log templates from the second sample, the second set of log templates having a second quantity of log templates. The computing device may apply the first set of log templates to the set of log lines for log templatization based at least in part on the first quantity of log templates being equal to the second quantity of log templates.
Techniques are provided for tuning junction resistances of superconducting tunnel junction devices (e.g., Josephson junctions) by localized thermal annealing of the superconducting tunnel junction devices. An exemplary embodiment includes a device which comprises a substrate, a quantum device comprising a superconducting tunnel junction device disposed on the substrate, and at least one heater element disposed on the substrate. The at least one heater element is configured to generate heat through resistive heating in response to a current applied to the at least one heater element, to heat a region of the substrate on which the superconducting tunnel junction device is disposed to thermally anneal the superconducting tunnel junction device.
A magnetoresistive device is provided comprising an active channel comprises an extremely large magnetoresistance (XMR) material. A gate electrode surrounds the active channel, wherein the gate electrode has a first portion on one side of the active channel and a second portion on the opposite side of the active channel. An insulating spacer electrically isolates the active channel from the gate electrode. Electrical current through the gate electrode generates and focuses a magnetic field applied to the active channel.
Embodiments of the invention include a semiconductor structure having nanosheets formed over a substrate and connected to source/drain regions, the nanosheets including a bottom nanosheet. Hidden spacers are formed between and below the nanosheets, where a bottom hidden spacer of the hidden spacers is a single continuous piece formed on the substrate and extending up the source/drain regions to the bottom nanosheet. Gate material is formed on the nanosheets and the hidden spacers.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A semiconductor IC device is presented and includes a first region and a second region. The first region includes a first channel above a backside interlayer dielectric (ILD). The first channel includes a vertically orientated top channel segment stacked over a vertically orientated bottom channel segment and has a first effective channel width. The second region includes a second channel above the backside ILD. The second channel has a second effective channel width that is less than the first effective channel width. The reduced second effective channel width may be provided by removing an associated vertically orientated bottom channel segment of the second channel from the backside of the semiconductor IC device.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. Active regions are longitudinally disposed on each of the two levels. The active regions include source/drain regions and channel regions. An active region of the active regions includes a transition region wherein longitudinal portions of the one active region are laterally offset within a same level by the transition region to provide an offset space. The offset space includes a vertical interconnect.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A method, computer system, and a computer program product for data-free knowledge amalgamation are provided. Multiple pre-trained teacher machine learning models are obtained. Each is trained on a respective different set of training data. Pseudo-data samples that mimic original training data of the teacher models are generated. A block-wise amalgamation with a self-regulative strategy to integrate knowledge from the multiple teacher models is implemented by inputting the pseudo-data samples into the teacher models and into a student machine learning model. The implementing also includes aligning intermediate representations of the student model with a unified representation capturing relevant features from the teacher models.
Provided are a computer program product, system, and method for verifying compliance of a workload executing in a trusted execution environment. A control program for a trusted execution environment has a plurality of control elements provided by users. A control element of the control elements includes a command to execute to verify compliance of an element in a workload in the trusted execution environment with a requirement. A trigger event, associated with a triggered control element of the control elements, is detected during execution of the workload in the trusted execution environment. The command for the triggered control element is executed to verify compliance of an element in the workload. The triggered control element is executed multiple times during execution of the workload to verify compliance of the element in the workload in response to multiple instances of detecting the trigger event.
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
87.
CONTEXT BASED RESOLUTION FOR VIRTUAL PRIVATE CLOUDS IN A HUB AND SPOKE MODEL
A computer-implemented method (CIM), according to one embodiment, includes creating virtual private endpoints (VPEs) for service endpoints for virtual private clouds (VPCs) of a cloud network, and creating, for the VPCs, buckets having names that include VPC identifiers (IDs). In response to receiving, from a first of the VPCs, a first query for a first of the service endpoints, a name included within the first query is caused to be used for parsing for one of the buckets, where the parsing identifies a first of the buckets. The CIM further includes causing a VPC ID to be extracted from the first bucket, and using the extracted VPC ID as context for resolving the first query.
Decreasing latency of high latency microservices is provided. A Hypertext Transfer Protocol (HTTP) request is sent to an in-browser microservice running in an in-browser container of an in-browser container execution engine within a web browser of the host device to process the HTTP request. The HTTP request is processed using the in-browser microservice running in the in-browser container of the in-browser container execution engine within the web browser to decrease latency of the in-browser microservice that is marked as a high latency microservice. An HTTP response to the HTTP request is returned to the web browser based on the in-browser microservice running in the in-browser container of the in-browser container execution engine within the web browser processing the HTTP request.
Integrated circuit devices and methods of operation are provided which include a memory array having an array of memory cells arranged in rows and columns, and circuitry operatively couple to the memory array. In one aspect, the circuitry includes a fail counter circuit, and the circuitry is configured to facilitate preforming a testing operation on the memory array, with the fail counter circuit being operable during the testing operation in a selected one of a plurality of fail counter modes. The plurality of fail counter modes include an address fail counter mode to determine a number of failing addresses of the memory array during the testing operation, and a cell fail counter mode to determine the number of failing memory cells of the memory array during the testing operation. In another aspect, the circuitry includes a diagnostic column fail circuit to determine a type of column fail.
G11C 29/20 - Dispositifs pour la génération d'adressesDispositifs pour l'accès aux mémoires, p. ex. détails de circuits d'adressage utilisant des compteurs ou des registres à décalage à rétroaction linéaire [LFSR]
G11C 29/44 - Indication ou identification d'erreurs, p. ex. pour la réparation
90.
FLUID ORCHESTRATION OF MULTI-USER CONTENT GENERATION IN A MOBILE COMPUTING ENVIRONMENT
Orchestrating multi-user content generation includes generating metrics based, at least in part, on a plurality of demands for content, a context of a mobile computing environment, sensor data for the mobile computing environment and a plurality of users within the mobile computing environment, and operating states of a plurality of generative artificial intelligence (AI) computing systems. An offloading strategy that defines which demands of the plurality of demands are to be performed by different ones of the plurality of generative AI computing systems is generated based on the metrics. The plurality of demands are distributed to one or more selected generative AI computing systems selected from the plurality of generative AI computing systems based on the offloading strategy. Content generated by the one or more selected generative AI computing systems is provided to devices corresponding to the plurality of users.
A computer-implemented method for automating addition of power supply rails, fences, and level translators in a circuit design, includes annotating initial component instance pins as belonging to a design region based on user specification and connectivity tracing with a design region. The design region is a clock region and global voltage domain pair. The method propagates a design region forward from the component instance pins to sequential components by assigning a design region to a sequential component based on the design region of a previous component, identifies crossing endpoints where the design region changes and places at least one of a fence, power supply rail, and a level translator at the crossing endpoints.
A branch prediction unit of the processor powers-up and accesses only a subset of a plurality of prediction structures to obtain a first set of branch prediction information for a conditional branch. During the access, at least one of the plurality of prediction structures remains powered-down. The branch prediction unit thereafter determines whether all of the plurality of prediction structures having branch prediction information relevant to the conditional branch were accessed. Based on a determination that fewer than all of the plurality of prediction structures having branch prediction information relevant to the conditional branch were accessed, the branch prediction unit refrains from outputting a branch prediction based on the first set of branch prediction information, powers-up and accesses a greater number of the plurality of prediction structures to obtain a second set of branch prediction information, and outputs a branch prediction based on the second set of branch prediction information.
A computer-implemented method, a system and a computer program product for adaptive derivation of meeting content is provided. In the method, for a meeting held for a program, a current phase can be determined from a plurality of phases of the program. A speaker can be detected in the meeting from a plurality of participants of the program. Meeting content associated with the meeting can be obtained based on analyzing input data from the speaker. A file can be activated based on the current phase, the meeting content and a phase context profile model which is trained with history data associated with past meetings held for the program in terms of file inputs. Then, the file can be updated based on the meeting content.
G06Q 10/0631 - Planification, affectation, distribution ou ordonnancement de ressources d’entreprises ou d’organisations
G10L 17/02 - Opérations de prétraitement, p. ex. sélection de segmentReprésentation ou modélisation de motifs, p. ex. fondée sur l’analyse linéaire discriminante [LDA] ou les composantes principalesSélection ou extraction des caractéristiques
94.
CREATING COMPLEX THREE-DIMENSIONAL WAX MODELS FOR INVESTMENT CASTING
Described are techniques for creating complex three-dimensional wax models for investment casting. A digital three-dimensional model of an object (e.g., transmission part, engine part, brake, bracket, housing, rod, gear, door handle, etc.) is analyzed. Segmented wax models to be formed from the digital three-dimensional model of the object are then identified. A production line using robots is then established for assembling the identified segmented wax models into a complete three-dimensional wax model of the object for investment casting. In this manner, complex three-dimensional wax models may be created for investment casting with less defects than creating such wax models using single injection molding.
An integrated circuit includes a frontside structure which includes a plurality of power gating transistors and at least one metalization layer above the power gating transistors. The circuit includes a backside structure below the power gating transistors of the frontside structure. The backside structure includes at least one global power rail, one local power rail and one ground rail. The global power rail, the local power rail and the ground rail are spatially separated from each other and are not laterally aligned.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
An approach is provided for controlling an alert suppression policy. Using historical training data and for a time period, an expected alert reduction for an alert suppression policy (ASP) is computed. The ASP is recommended for an information technology (IT) environment. During runtime and for the time period, an observed alert reduction for the ASP is computed. A visualization of a benefit of the ASP is generated by generating a visualization of a comparison of the observed alert reduction and the expected alert reduction. An explanation of why the ASP is recommended for the IT environment is generated by determining persistent regions for respective event time series from the historical training data and generating a visualization of the persistent regions on a time graph that includes a duration and a number of events for a given persistent region. Each event time series corresponds to a given resource for the ASP.
Methods, computer program products, and systems are presented. The methods, computer program products, and systems can include, for example, processing multiple datasets using metadata, wherein the metadata can characterize relationships among datasets. In dependence on such metadata, production datasets can be, e.g., generated, versioned, and/or merged. The resulting production datasets can support subsequent computing uses such as analytics, machine learning, application testing, and/or enterprise processing.
G06F 16/901 - IndexationStructures de données à cet effetStructures de stockage
G06F 7/14 - Interclassement, c.-à-d. association d'au moins deux séries de supports d'enregistrement, chacun étant rangé dans le même ordre de succession, en vue de former une série unique rangée dans le même ordre de succession
98.
DISPARATE RENEWABLE POWER ENERGY SOURCED SERVER NODES
According to one embodiment, a method, computer system, and computer program product for managing a computer network based on energy sources powering nodes of the computer network is provided. The present invention may include identifying the power source powering each of the nodes comprising the computer network; calculating a carbon footprint associated with the nodes of the computer network based on the power source; receiving a sustainability goal from the client; provisioning one or more nodes of the computer network based on the sustainability goal and the carbon footprint associated with the nodes; and managing a workload of the client based on the sustainability goal and the carbon footprint associated with the nodes.
H04L 41/0816 - Réglages de configuration caractérisés par les conditions déclenchant un changement de paramètres la condition étant une adaptation, p. ex. en réponse aux événements dans le réseau
G06Q 30/018 - Certification d’entreprises ou de produits
H04L 41/0823 - Réglages de configuration caractérisés par les objectifs d’un changement de paramètres, p. ex. l’optimisation de la configuration pour améliorer la fiabilité
H04L 41/22 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p. ex. des réseaux de commutation de paquets comprenant des interfaces utilisateur graphiques spécialement adaptées [GUI]
H04L 67/1012 - Sélection du serveur pour la répartition de charge basée sur la conformité des exigences ou des conditions avec les ressources de serveur disponibles
Semiconductor devices are provided in which at least recessed inner dielectric spacers are used in forming a PFET having stressed semiconductor channel material nanosheets. The use of the recessed inner dielectric spacers facilitates an increase in strain transfer from the source/drain regions of the PFET to the semiconductor channel material nanosheets. Thus, the semiconductor channel material nanosheets of the present application have enhanced stress as compared to equivalent semiconductor channel material nanosheets in which non-recessed inner dielectric spacers are used.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Computer implemented methods, systems, and computer program products include program code executing on a processor(s) initializes a process model for runtime reconfiguration. The program code extracts dependencies for components comprising the process model. The program code generates or updates a dependency graph representing the dependencies, based on the extracting. The program code initializes a protocol across a stack for executing the process based on the dependencies. The program code, after initializing initiates the transaction. During runtime, the program code receives an input related to the transaction performed by the process model. The program code cognitively analyzes the input utilizing a large language model (LLM) to determine an urgency level for the transaction. The program code determines that the urgency level is above a pre-determined threshold. The program code reconfigures the process model to comport with the urgency level.
brevets
