A semiconductor device of embodiments includes an element region, a termination region, and an intermediate region between the element region and the termination region. The element region includes: a silicon carbide layer having a first conductive type silicon carbide region and a second conductive type of silicon carbide regions; and a gate electrode. The intermediate region includes a silicon carbide layer having a second conductive type silicon carbide region outside the second conductive type silicon carbide regions. The width of the second conductive type silicon carbide region in the intermediate region is equal to or more than 0.5 times and equal to or less than 3 times the width of the second conductive type silicon carbide region in the element region.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/60 - Distribution ou concentrations d’impuretés
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
2.
ELECTRONIC CIRCUITRY, DRIVE CIRCUIT, AND DETERMINATION METHOD
According to one embodiment, an electronic circuitry includes a processing circuitry configured to determine a current polarity being a polarity of a current flowing through at least one of a first switching element and a second switching element, based on a first voltage between a first electrode and a second electrode of the first switching element during a dead time of a half-bridge circuit, the half-bridge circuit including the first switching element and the second switching element.
According to one embodiment, a disk device includes a housing filled with a low density gas containing oxygen and having a density lower than a density of air, a disk-shaped recording medium provided in the housing to be rotatable, a spindle motor provided in the housing and supporting and rotating the recording medium, and a magnetic head including a heat assist element which heats the recording medium. A surface of magnet of the spindle motor is covered with a shielding film blocking oxygen permeation.
G11B 33/14 - Diminution de l'influence des paramètres physiques, p. ex. changements de température, humidité, poussière
G11B 25/04 - Appareils caractérisés par la forme du support d'enregistrement employé mais non spécifiques du procédé d'enregistrement ou de reproduction utilisant des supports d'enregistrement plats, p. ex. disques, cartes
G11B 33/02 - ÉbénisterieBoîtiersBâtisDisposition des appareils dans ou sur ceux-ci
A semiconductor device includes a first electrode, a substrate that has a first semiconductor region, a second semiconductor region and a third semiconductor region and a second electrode provided on the substrate. The semiconductor device has a conductor, an insulator, a gate electrode provided around the conductor and a gate insulating film. The gate insulating film has a plurality of curves. The plurality of curves includes a curve that has a first radius of curvature R1 and a curve that has a second radius of curvature R2 smaller than the first radius of curvature R1.
According to one embodiment, a head suspension assembly includes a support plate including a proximal end portion, a distal end portion, a lift tab, and a first opening, a wiring member on the support plate, including a gimbal portion opposed to the distal end portion, and a head including a slider mounted on the gimbal portion, a head element on the slider, and a laser oscillator on the slider, opposed to the first opening. The support plate includes a first protrusion provided on the distal end portion and brought into contact with a central part of the slider via the gimbal portion, and a second protrusion that is provided between the first protrusion and the lift tab and that protrudes toward the gimbal portion.
G11B 5/48 - Disposition ou montage des têtes par rapport aux supports d'enregistrement
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
6.
MAGNETIC RECORDING AND REPRODUCTION DEVICE AND CONTROL METHOD OF THE SAME
According to an embodiment, a control method for a heat-assisted magnetic recording and reproducing device including a heat-assisted magnetic recording head including a main pole, a near-field transducer generating near-field light, a waveguide propagating light to the near-field transducer, and a laser light source supplying light to the waveguide, and a heat-assisted magnetic recording medium that has a lubricant layer on a recording surface opposing the head, includes irradiating the near-field light on the medium with a second laser current value set lower than a first laser current value at a time of write, and operating the head, thereby performing a smoothing process on the surface of the lubricant layer.
G11B 23/50 - Reconditionnement des supports d'enregistrementNettoyage des supports d'enregistrement
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
G11B 5/60 - Maintien dynamique de l'écartement entre têtes et supports d'enregistrement à l'aide d'un fluide
According to one embodiment, a magnetic disk device includes a first disk having a first data track and a second data track, a first write head, a write processing unit, an error correction unit, a correction limit prediction unit, and a determination unit. During a write period, the correction limit prediction unit calculates an excess amount, calculates a metric value by multiplying a first weight coefficient by the excess amount, updates a cumulative metric value, and generates first prediction information. The determination unit determines whether or not to allow the write processing unit to continue write processing for the second data track based on the first prediction information.
G11B 19/04 - Dispositions prévenant, évitant ou signalant la surimpression sur le même support, ou d'autres fonctionnements défectueux de l'enregistrement ou de la reproduction
A second surface-side region includes a fourth semiconductor layer contacting a second electrode, a fifth semiconductor layer contacting the second electrode, the fifth semiconductor layer having a higher first-conductivity-type impurity concentration than a first semiconductor layer, a sixth semiconductor layer having a lower first-conductivity-type impurity concentration than the fifth semiconductor layer, and a seventh semiconductor layer positioned between the fifth semiconductor layer and the sixth semiconductor layer, the seventh semiconductor layer facing a second gate electrode. An eighth semiconductor layer faces at least the sixth semiconductor layer. A distance in a first direction between the eighth semiconductor layer and the second electrode is less than a distance in the first direction between the eighth semiconductor layer and a first electrode.
According to one embodiment, during a first write period, an adjustment unit derives a first predicted excess amount and a predicted upper limit threshold value, and a correction limit prediction unit calculates a first cumulative predicted excess amount. The determination unit causes the write processing unit to continue the write processing if determining that the first cumulative predicted excess amount is smaller than or equal to the predicted upper limit threshold value, and causes the write processing unit to suspend the write processing if determining that the first cumulative predicted excess amount exceeds the predicted upper limit threshold value.
According to one embodiment, a magnetic recording device includes a housing having an internal dew point of 5° C. or less, a disk-shaped recording medium provided inside the housing, and a magnetic head provided inside the housing and performing information processing with respect to the recording medium.
G11B 33/14 - Diminution de l'influence des paramètres physiques, p. ex. changements de température, humidité, poussière
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
A controller calculates, based on a positional error signal, an evaluation amount of damage on data of an adjacent track caused by a write operation, and compares a first amount being the evaluation amount with a first threshold value corresponding to a correction limit of an error correction in units of tracks. The controller interrupts the write operation in response to determining that the first amount is greater than the first threshold value. The controller executes a read operation on the adjacent track, acquires a metric representing a signal quality of the data of the adjacent track read by the read operation, calculates the evaluation amount based on the metric, and compares a second amount being the evaluation amount with the first threshold value. The controller continues the write operation in response to determining that the second amount is smaller than a first threshold value.
G11B 20/18 - Détection ou correction d'erreursTests
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'un disque
According to one embodiment, in a disk device, a disk medium has a recording surface configured to face the head, the disk medium being medium where multiple tracks defined on the recording surface, each of the multiple tracks including multiple sectors. A controller is configured to perform error correction for each of the sectors on a per track basis. The controller is configured to predict, while writing data to a first track of the multiple tracks by a head, that the number of error sectors of a second track adjacent to the first track reaches a correction limit number of sectors, according to a track margin identified by first management information and an off-track amount of the first track. The controller is configured to update the first management information according to a bit error rate reference value and a bit error rate of information read from a track.
A semiconductor device includes a substrate, a first electrode and a second electrode. The semiconductor device includes a MOSFET that has the first electrode as a drain electrode and the second electrode as a source electrode. The first electrode has a layer region provided on a first main surface and a first region extending from the first main surface into the substrate in a first direction from the first electrode to the second electrode. A lower surface of the first electrode protrudes in a direction opposite to the first direction.
A semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a gate electrode and a second electrode. The gate electrode has a first region opposite to the second semiconductor region and a second region opposite to the third semiconductor region. The gate electrode has a first length from a lower surface to an upper surface of the second region and a second length from the lower surface to an upper surface of the first region, and the first length is greater than the second length.
A magnetic disk device according to an embodiment includes a housing in which a base, an inner cover provided with a first through-hole, and an outer cover are combined in this order and hermetically sealed, a magnetic disk that is stored in the housing, a first desiccant unit that is provided at the inner cover to face the base at a position away from the base, and a second desiccant unit that is provided at the outer cover and inserted into an internal space of the housing through the first through-hole provided in the inner cover to face the base at a position away from the base.
Write commands in a shingled magnetic recording (SMR) drive are efficiently executed when a write command and associated write data are received by an SMR HDD from a host while the target SMR band for storing the write data is undergoing a refresh operation. In response to the write command, the HDD suspends the refresh operation, stores the write data in nonvolatile memory, and informs the host that the write command has been completed. After the write data are stored in nonvolatile memory, the HDD resumes the refresh operation, and the remaining unrefreshed data in the target SMR band are refreshed by being rewritten to the spare SMR band. The nonvolatile memory can include the spare SMR band in some instances, the target SMR band in some instances, and in both the spare SMR band and the target SMR band in some instances.
A semiconductor device according to an embodiment includes: a first electrode and a second electrode disposed on a first main surface and a second main surface of a semiconductor layer, respectively; a first conductivity type first semiconductor region; a first conductivity type second semiconductor region extending from the first semiconductor region toward the second electrode, and having an upper region having an impurity concentration higher than the first semiconductor region, and a lower region including a region narrower than the upper region; a third electrode disposed in the semiconductor layer via an insulating region and aligned with the lower region along a second direction; a first conductive portion facing the third electrode, electrically connected to the second electrode, and in Schottky contact with the lower region; and a second conductive portion electrically connected to the second electrode and in ohmic contact with the upper region.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
A semiconductor device of embodiments includes: a semiconductor layer having a first face and a second face opposite to the first face and including a first trench, a second trench, and a third trench provided on a first face side; a first gate electrode in the first trench; a second gate electrode in the second trench; a third gate electrode in the third trench; a fourth gate electrode and a fifth gate electrode provided on a second face side; a first electrode contacting the first face; a second electrode contacting the second face; a first electrode pad electrically connected to the first gate electrode; a second electrode pad electrically connected to the second gate electrode; a third electrode pad electrically connected to the third gate electrode; a fourth electrode pad electrically connected to the fourth gate electrode; and a fifth electrode pad electrically connected to the fifth gate electrode.
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H03K 17/567 - Circuits caractérisés par l'utilisation d'au moins deux types de dispositifs à semi-conducteurs, p. ex. BIMOS, dispositifs composites tels que IGBT
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
19.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a first electrode; a first semiconductor region of a first conductivity type on the first electrode and including a first region and a second region positioned around the first region; a second semiconductor region of a second conductivity type on the first region; a third semiconductor region of the first conductivity type on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer; a fourth semiconductor region of the second conductivity type on the second region and spaced apart from the second semiconductor region; a second electrode provided on the third semiconductor region via a first contact; a third electrode provided on the fourth semiconductor region via a second contact. The first and second contacts each include a titanium-containing layer, a titanium nitride-containing layer on the titanium-containing layer, and a tungsten-containing layer on the titanium nitride-containing layer.
A magnetic disk device according to an embodiment includes: a magnetic disk including a plurality of tracks; a magnetic head that performs data reading and data writing on the magnetic disk; a plurality of servo regions that is provided in each of the plurality of tracks, and at least partially includes a first physical pattern, the first physical pattern being a physical pattern after writing of a first data pattern including position information of each of the plurality of tracks; and a controller that controls the magnetic head, wherein the plurality of servo regions includes one of a first servo region including the first physical pattern, and a second servo region including a second physical pattern, the second physical pattern being a physical pattern after writing of a second data pattern different from the first data pattern, for each of the plurality of tracks, and the controller performs determination as to which of the first and second physical patterns a third servo region has, the third servo region being one of a servo region among the plurality of servo regions included in the plurality of tracks.
A semiconductor device of embodiments includes: a transistor region including a semiconductor layer having a first face and a second face opposite to the first face, a first transistor having a first gate electrode provided on a first face side of the semiconductor layer, and a second transistor having a second gate electrode provided on a second face side of the semiconductor layer; and an adjacent region adjacent to the transistor region and including the semiconductor layer and a third transistor having a third gate electrode electrically connected to the second gate electrode and provided on the second face side of the semiconductor layer and the third transistor having an absolute value of a threshold voltage smaller than an absolute value of a threshold voltage of the second transistor.
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 84/60 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors BJT
A semiconductor device includes first, second and control electrodes, and a semiconductor part between the first and second electrode. The semiconductor part includes first and third layers of a first conductive type, and second, fourth and fifth layers of a second conductive type. The first layer extends between the first and second electrodes. The second layer is provided between the first layer and the second electrode. The third layer is partially provided on the second layer between the second layer and the second electrode. A first fourth layer and a second fourth layer are provided in the first layer. The fifth layer is provided between the first layer and the second layer. The fifth layer is partially provided on the first layer between the first fourth layer and the second fourth layer. The control electrode is provided between the second electrode and each of the fourth layers.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
A semiconductor device includes first and second electrodes, a semiconductor part, a gate electrode, and a first part that is insulative. The first and second electrodes are located in first, second, and third regions. The semiconductor part is located between the first electrode and the second electrode. The gate electrode is located in the semiconductor part in the first region. The first part is located on the first electrode in the third region. The first region is an IGBT region. The second region is a diode region. The third region separates the first region and the second region between the first region and the second region. In the third region, a bottom surface of the first part contacts the first electrode; an upper surface of the first part contacts a fourth semiconductor layer; and a side surface of the first part contacts a third semiconductor layer.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
According to one embodiment, a magnetic disk device includes a rotatable disk-shaped recording medium including a plurality of concentric recording tracks, a magnetic head including a write element which writes data to the recording tracks, a heating element, and a sensor which detects a surface condition of the recording medium, and a controller including an inspection circuit which detects, based on an sensor output of the sensor, presence or absence of a bump on a surface of the recording medium, a height and a width of the bump, and a memory which records the detected height and width of the bump.
G11B 5/54 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour amener la tête dans sa position de travail, pour l'en écarter ou pour la déplacer en travers des pistes
G11B 5/012 - Enregistrement, reproduction ou effacement sur des disques magnétiques
G11B 5/55 - Changement, sélection ou acquisition de la piste par déplacement de la tête
G11B 5/60 - Maintien dynamique de l'écartement entre têtes et supports d'enregistrement à l'aide d'un fluide
G11B 20/18 - Détection ou correction d'erreursTests
25.
SEMICONDUCTOR STORAGE DEVICE INCLUDING SENSE AMPLIFIER THAT SENSES DATA FROM MULTIPLE MEMORY CIRCUITS
A semiconductor storage device according to an embodiment comprises: a first memory circuit; a second memory circuit having a storage capacity smaller than that of the first memory circuit; a readout line commonly connected to the first memory circuit and the second memory circuit; a sense amplifier configured to compare a voltage of a first bit signal or a second bit signal with a reference voltage, where the first bit signal being inputted from the first memory circuit through the readout line and the second bit signal being inputted from the second memory circuit through the readout line; and a readout conditioning circuit configured to change at least one of an operation timing of the sense amplifier and the reference voltage corresponding to the first bit signal and the second bit signal.
G11C 7/06 - Amplificateurs de lectureCircuits associés
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/18 - Organisation de lignes de bitsDisposition de lignes de bits
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
A vapor phase growth apparatus according to an embodiment has a susceptor on which a wafer is to be placed. The vapor phase growth apparatus has a drive portion for rotating the susceptor. The susceptor has a wafer support portion. The wafer support portion supports the wafer. The wafer support portion has an annular shape. The wafer support portion has a support surface. The support surface supports the wafer from below. The support surface has an inclined surface and a flat portion. The inclined surface is connected to an inner edge of the wafer support portion. The flat portion faces upward. The inclined surface is positioned upward as the inclined surface approaches an outward side of the wafer support portion in a radial direction. The flat portion is connected to an outer end portion of the inclined surface in the radial direction.
According to one embodiment, a disk device includes a magnetic disk, a housing, a constrained layer, and a first adhesive material. The housing includes a base, a first cover, and a second cover, the base being provided with a housing space in which the magnetic disk is disposed, the first cover being mounted on the base to cover the housing space, the second cover being mounted on the base to cover the first cover. The constrained layer includes a first face and a second face, the first face facing the first cover, the second face being located opposite to the first face, facing the second cover, and being inclined to the first face. The first adhesive material is interposed between the first face and the first cover.
According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first and third semiconductor regions are of a first conductivity type. The second, fourth, and fifth semiconductor regions are of a second conductivity type. The first semiconductor region includes first and second parts. The fourth semiconductor region is located on the second part and is positioned around the second semiconductor region. The second electrode includes first and second metal parts. The first metal part contacts the first part and the second semiconductor region. The second metal part contacts the second part and the fourth semiconductor region. The first and second metal parts include a first element selected from titanium, molybdenum, and vanadium. The fifth semiconductor region is located lower than the fourth semiconductor region and is positioned directly under the second metal part.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, first and second insulating members. The semiconductor member includes a first semiconductor region. The first semiconductor region includes first to fourth partial regions. The first electrode portion is in contact with the fourth partial region. The first insulating member includes first and second insulating regions. The first insulating region is between the third electrode and the fourth partial region in the second direction. The second insulating region is between the first partial region and the third electrode in the first direction. The second insulating member includes a first insulating portion. The first insulating portion is between the second partial region and the first electrode portion in the first direction.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/64 - Électrodes comprenant une barrière de Schottky à un semi-conducteur
A semiconductor device of embodiments includes: a first electrode; a second electrode; a semiconductor layer having a first face and a second face; a gate electrode including a second portion and a first portion extending in a first direction in the semiconductor layer; a field plate electrode between the gate electrode and the second face in the semiconductor layer and electrically connected to the first electrode; a conductive layer in the semiconductor layer, provided between the first portion and the second portion, and electrically separated from the first electrode; and a field plate insulating layer between the field plate electrode and the semiconductor layer. A first distance in the first direction between an end of the field plate insulating layer in the first direction on the first face and the conductive layer is smaller than a second distance between the end and the gate electrode in the first direction.
A semiconductor device of embodiments includes: a semiconductor layer having a first face and a second face and including a first trench provided on a first face side; a first field plate electrode provided in the first trench; a gate electrode provided in a gate trench; a first electrode provided on the first face side of the semiconductor layer and electrically connected to the first field plate electrode; a second electrode provided on the second face side of the semiconductor layer; and a connection portion provided between the first electrode and the first field plate electrode, electrically connected to the first electrode and the first field plate electrode, and having an electrical resistance higher than an electrical resistance of the first field plate electrode.
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
A semiconductor device according to an embodiment includes: a semiconductor layer including a first conductivity type first semiconductor region; a first electrode; a second electrode; a second conductivity type second semiconductor region; a first conductivity type third semiconductor region electrically connected to the first electrode; a third electrode disposed in the semiconductor layer; a fourth electrode disposed in the semiconductor layer and electrically connected to the first electrode; a conductive portion in Schottky contact with the first semiconductor region; and a second conductivity type fourth semiconductor region disposed in the semiconductor layer. The conductive portion is disposed in the semiconductor layer so as to be electrically insulated from the second semiconductor region and electrically connected to the fourth electrode. The fourth semiconductor region extends downward from the second semiconductor region and faces the conductive portion with the first semiconductor region interposed therebetween.
An information processing device includes a processing unit including a hardware processor. The hardware processor calculates plural exogenous-noise-estimation values corresponding to plural variables for each of one or more pieces of result data including plural result values respectively corresponding to the plural variables based on the result data and a structural-causal-model representing a causal-relationship of the plural variables. Each of the exogenous-noise-estimation values represents an estimation value of influence by an exogenous-noise different from influences from the plural variables on corresponding variables among the plural variables. The hardware processor generates a contribution-degree representing an influence-magnitude by the exogenous-noise given to a source variable as one of two variables to a target variable that is another variable for each combination of the two variables in the plural variables for the result data based on the structural-causal model and the plural exogenous-noise-estimation values for each result data.
According to the present embodiment, a second electrode, a third electrode, an electrode part, and a region. The second nitride semiconductor layer is a nitride semiconductor layer located on the first nitride semiconductor layer and having a larger bandgap than that of the first nitride semiconductor layer. The first electrode is located on the second nitride semiconductor layer. The second electrode is located on the second nitride semiconductor layer. The third electrode is located on the second nitride semiconductor layer between the first electrode and the second electrode. The electrode part is electrically connected to at least any of the first electrode, the second electrode, and the third electrode and is arranged above the third electrode. The region is a region separate from the third electrode and including negative fixed charges implanted therein in the second nitride semiconductor layer.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/60 - Distribution ou concentrations d’impuretés
H10D 62/824 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe III-V, p. ex. des hétérojonctions GaN/AlGaN
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
35.
Magnetic disk drive and control method of the same
According to one embodiment, a magnetic disk drive comprising, a magnetic disk, a magnetic head, a voice coil motor, and a controller. The controller includes a seek control section, a velocity calculation section, a back electromotive voltage estimation section, and a coil resistance estimation section.
A semiconductor device according to an embodiment has a circuit board having a first surface facing a first side, and a second surface facing a second side on a side opposite to the first side. The semiconductor device has a chip mounted on the first surface. The semiconductor device has a heat transfer member joined to the second surface with a first joint layer therebetween. The semiconductor device has a heat dissipation member joined to a surface of the heat transfer member facing the second side with a second joint layer therebetween. Each of the first joint layer and the second joint layer is a sintered body.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/053 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H05K 3/12 - Appareils ou procédés pour la fabrication de circuits imprimés dans lesquels le matériau conducteur est appliqué au support isolant de manière à former le parcours conducteur recherché utilisant la technique de l'impression pour appliquer le matériau conducteur
H10D 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe
H10D 80/20 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex des ensembles comprenant des condensateurs, des transistors FET de puissance ou des diodes Schottky
37.
Preamplifier, disk device, control device, and analysis method
A preamplifier is included in a head assembly of a disk device. The preamplifier includes: an abnormality detecting circuit connected to a structural element included in a head device of the head assembly; a reference resistance element having a resistance value corresponding to the resistance value of the structural element and connected to the abnormality detecting circuit; and a switching circuit switchable to a first state and a second state. The first state is a state in which the abnormality detecting circuit and the structural element are connected to each other, and the abnormality detecting circuit and the reference resistance element are disconnected. The second state is a state in which the abnormality detecting circuit and the reference resistance element are connected to each other, and the abnormality detecting circuit and the structural element are disconnected.
G11B 5/455 - Dispositions pour l'essai fonctionnel des têtesDispositions de mesure pour têtes
H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
G11B 5/60 - Maintien dynamique de l'écartement entre têtes et supports d'enregistrement à l'aide d'un fluide
A semiconductor device of embodiments includes: a semiconductor layer having a first face and a second face; a first semiconductor region of a first conductive type in the semiconductor layer, in contact with the second face, and including a first portion having a first minimum width, a second portion having a second minimum width smaller than the first minimum width, and a third portion connecting the first portion and the second portion and having a third minimum width smaller than the second minimum width; a plurality of second semiconductor regions of a second conductive type in contact with the second face; a third semiconductor region of the second conductive type between the first semiconductor region and the first face; a fourth semiconductor region of the first conductive type; a fifth semiconductor region of the second conductive type; a gate electrode facing the fourth semiconductor region.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 84/60 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors BJT
39.
Magnetic disk device and method of controlling the same
According to one embodiment, a magnetic disk device comprises a first actuator which displaces magnetic heads in a radial direction of the magnetic disks, second actuators which displace the magnetic heads in a direction along the radial direction of the magnetic disks independently from each other, third actuators which displace the magnetic heads in directions opposite to each other along the radial direction of the magnetic disks by a same amount at a same time, and a controller which controls driving of the first actuator, driving of the second actuators and driving of the third actuators.
G11B 5/55 - Changement, sélection ou acquisition de la piste par déplacement de la tête
G11B 5/012 - Enregistrement, reproduction ou effacement sur des disques magnétiques
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'un disque
According to one embodiment, a method for inspecting semiconductor device according to the embodiment includes providing a semiconductor substrate. The method further includes capturing a transmission polarization image of the semiconductor substrate. The method further includes setting coordinate representing respective positions. The method further includes performing image processing on the first image data. The method further includes forming an epitaxial layer. The method further includes forming the plurality of semiconductor elements. The method further includes sequentially performing an electrical inspection on one of a remaining semiconductor elements. The method further includes performing a process of identifying a semiconductor element. The method further includes performing a process of identifying the one of the remaining semiconductor elements.
G06T 7/73 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés basés sur les caractéristiques
G06T 7/77 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés statistiques
G06V 10/60 - Extraction de caractéristiques d’images ou de vidéos relative aux propriétés luminescentes, p. ex. utilisant un modèle de réflectance ou d’éclairage
41.
SEMICONDUCTOR DEVICE, POWER CONVERSION APPARATUS, AND METHOD FOR MANUFACTURING THE SAME
According to an embodiment, a semiconductor device includes a semiconductor chip having a first surface on which a source electrode and a gate electrode are provided and a second surface that is opposed to the first sur face and on which a drain electrode is provided, a source terminal having a fourth surface exposed from a third surface of a package and a fifth surface coupled to the source electrode and having a shape different from a sha pe of the fourth surface, a gate terminal having a sixth surface exposed from the third surface of the package and a seventh surface coupled to the gate electrode and having a shape different from a shape of the sixth surface, and a drain terminal coupled to the drain electrode and having an eighth surface exposed from the third surface of the package.
H10D 80/20 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex des ensembles comprenant des condensateurs, des transistors FET de puissance ou des diodes Schottky
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/498 - Connexions électriques sur des substrats isolants
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
A semiconductor device includes: a semiconductor portion having a cell region and a terminal region; a first electrode; a second electrode; a control electrode in the semiconductor portion via one of a plurality of first insulators arranged in a direction from the cell region to the terminal region; and a third electrode in the semiconductor portion via a second insulator between itself and the control electrode. The control electrode includes a first controller in contact with the first insulator, and a second controller in contact with the first insulator and opposed to the first controller via the second insulator. Among the plurality of first insulators, an adjacent insulator adjacent to the terminal insulator provided closer to the terminal region than to the control electrode has a slope inclined toward the lower side of the first controller, and the second controller is not present in the slope.
According to one embodiment, a head gimbal assembly (HGA) of a disk device includes a load beam. The load beam includes two side rails, a plate between the two side rails, a first plane of the plate, a lift tab protruding from an end of the plate, and a protrusion protruding from the first plane and supporting a slider. An edge of each of the two side rails has a first edge, a second edge extending from the first edge toward the lift tab, and a third edge extending from the second edge to the lift tab while being inclined with respect to the first plane so as to approach the first plane. An end of the slider is at the same position as an end of the third edge or is farther from the lift tab than the end of the third edge.
According to one embodiment, a semiconductor drive device includes a circuit section. The circuit section is configured to output a first output signal and a second output signal based on a first sawtooth wave and a second sawtooth wave different from the first sawtooth wave. The first output signal is configured to change from a first potential to a second potential at a first time. The first output signal is configured to change from the second potential to the first potential at a second time. The second output signal is configured to change from a third potential to a fourth potential at the first time. The second output signal is configured to change from the fourth potential to the third potential at a third time. The third time is after the first time and before the second time.
H03K 17/567 - Circuits caractérisés par l'utilisation d'au moins deux types de dispositifs à semi-conducteurs, p. ex. BIMOS, dispositifs composites tels que IGBT
H03K 17/78 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs opto-électroniques, c.-à-d. des dispositifs émetteurs de lumière et des dispositifs photo-électriques couplés électriquement ou optiquement
A semiconductor device according to an embodiment includes: a semiconductor portion having a cell region and a terminal region provided outside the cell region; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a front surface side of the semiconductor portion; a control electrode provided in the semiconductor portion via one of a plurality of first insulators arranged in a direction from the cell region to the terminal region; and a third electrode provided in the semiconductor portion via a second insulator between itself and the control electrode. A hollow portion is provided inside a terminal insulator, which is provided closer to the terminal region side than to the control electrode, among the plurality of first insulators.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
First and second switches are electrically connected. A capacitor includes first and second terminals and a capacitor having an end electrically connected to the first terminal and another end electrically connected to the second terminal. The first and second terminals are electrically connected to the first and second switches, respectively. The capacitor is located above the first and second switches along a first direction. A width of the capacitor in a second direction that is a direction connecting the end and the another end of the capacitor is larger than a width of a set of the first and second switches in the second direction. The first switch and the second switch are arranged in the second direction.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
According to one embodiment, a semiconductor device includes: a first conductive layer provided on a substrate; a second conductive layer provided on the substrate and to which a first voltage is supplied; a third conductive layer corresponding to an output node and provided on the substrate between the first conductive layer and the second conductive layer; a first switching device provided above the first conductive layer and including a first terminal to which a second voltage higher than the first voltage is supplied and a second terminal connected to the third conductive layer; and a second switching device provided above the second conductive layer and including a third terminal connected to the third conductive layer and a fourth terminal connected to the second conductive layer.
H01L 25/11 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
According to one embodiment, a semiconductor device includes: first, second, and third lead frames; a first transistor which is GaN transistor provided on the first lead frame and electrically connected to the first lead frame; a second transistor which is GaN transistor provided on the second lead frame and electrically connected to the third lead frame; a third transistor which is MOS transistor provided on the third lead frame and electrically connected to the third lead frame and the first transistor; a fourth transistor which is MOS transistor provided on the second lead frame and electrically connected to the second lead frame and the second transistor; and a capacitor electrically connected to the first and the second lead frame; wherein the first, the third, the second, and the fourth transistor are arranged side by side in this order in a first direction.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
According to one embodiment, a semiconductor device includes a first switch provided with a first electrode and a second electrode, a second switch provided with a third electrode and a fourth electrode, a first capacitor including a first wiring layer connected to the third electrode, a second wiring layer connected to the first electrode, and a first dielectric layer, a substrate, a third wiring layer connected to the first wiring layer and applied with a first voltage, a fourth wiring layer connected to the second wiring layer and applied with a second voltage, and a fifth wiring layer connected to the second and fourth electrodes, and applied with a third voltage. The first capacitor is arranged between the first and second switches. The third electrode faces the first electrode. The fourth electrode faces the second electrode and is connected to the second electrode in series.
H01L 25/11 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
A first conductor includes a first portion, a second portion, and a third portion. The first portion is in contact with the first electrode and has a second length in the first direction that is shorter than the first length. The second portion is located farther in a second direction than the first portion, is connected to the first portion, and has a third length in the first direction that is longer than the second length. The third portion is located farther in the second direction than the second portion, is connected to the second portion, and is exposed from a sealing resin.
A semiconductor device includes: a substrate having a lower surface and a side surface and the substrate containing a semiconductor material; and an electrode provided on the lower surface, wherein the side surface has a first side surface portion, a second side surface portion provided on the first side surface portion, and a third side surface portion provided on the second side surface portion, the third side surface portion protrudes in a plane parallel to the lower surface more than the second side surface portion, and the first side surface portion protrudes in a plane parallel to the lower surface more than the third side surface portion.
According to one embodiment, a semiconductor device includes: a substrate; a first electrode provided on the substrate; a second electrode provided on the substrate distant from the first electrode; and a sheet-like conductive sheet configured to connect the first electrode and the second electrode, in which the conductive sheet includes a first fixing portion connected to the first electrode, a second fixing portion connected to the second electrode, and a wiring portion positioned between the first fixing portion and the second fixing portion, having a length in a first direction from the substrate toward the first electrode that is longer than a length of the first fixing portion in the first direction, and having a convex shape with its central part is curving away from the second fixing portion at a first end that is connected to the first fixing portion.
According to one embodiment, multiple first positions are set in a radial direction of a magnetic disk. The multiple first positions include multiple second positions and a third position different from the multiple second positions. A controller of a magnetic disk apparatus executes a first process in which an RRO correction value is measured at each of the multiple second positions and measurement of an RRO correction value at the third position is skipped. After the first process, the controller executes a second process of performing write or read access to multiple tracks. The second process includes acquiring a position error signal by a read head during the write or read access, and calculating an RRO correction value for the third position based on the position error signal.
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'un disque
According to one embodiment, a magnetic recording device includes a recording medium, a magnetic head including a light source, a light emitting element, and a sensor, and a controller including an inspection circuit which detects a height of a defect of the recoding medium based on output of the sensor, a memory recording the height of the defect, and a setting circuit which sets an upstream side record/reproduce prohibited sector on an upstream side of the defect, in a travel direction of the magnetic head, on a track of the recording medium on which the defect is present, and which sets a downstream side record/reproduce prohibited sector longer in track direction than the upstream side record/reproduce prohibited sector on a downstream side of the defect.
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
G01N 21/88 - Recherche de la présence de criques, de défauts ou de souillures
G01N 21/898 - Irrégularités des surfaces texturées ou structurées, p. ex. des textiles, du bois
G11B 5/702 - Supports d'enregistrement caractérisés par l'emploi d'un matériau spécifié comportant une ou plusieurs couches de particules magnétisables mélangées de façon homogène avec un produit de liaison sur une couche de base caractérisés par le produit de liaison
G11B 27/36 - Contrôle, c.-à-d. surveillance du déroulement de l'enregistrement ou de la reproduction
A semiconductor device, includes a nitride semiconductor layer; a plurality of source electrodes; a plurality of drain electrodes; a gate electrode being positioned between source and drain electrodes adjacent to each other in a first direction; an insulating layer located on the plurality of source electrodes, the plurality of drain electrodes, and the gate electrode; and a source wiring part located on the insulating layer. The source wiring part includes a plurality of source pad parts electrically connected with the plurality of source electrodes, and a source connecting part connecting two source pad parts adjacent to each other in the first direction. A width in a second direction of the source connecting part is less than widths in the second direction of the plurality of source pad parts.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
According to one embodiment, a power module including a first conductive pattern, a second conductive pattern, a first power device, a third conductive pattern, a first capacitive element, a fourth conductive pattern, a second capacitive element, a first conductive plug, a fifth conductive pattern, a second conductive plug, and a second power device is provided. In the power module, a first power loop and a second power loop are formed. The first power loop includes the first conductive pattern, the first power device, the second conductive pattern, the first capacitive element, the third conductive pattern, and the second power device. The second power loop includes the first conductive pattern, the first power device, the first conductive plug, the fifth conductive pattern, the second conductive plug, the fourth conductive pattern, the second capacitive element, the third conductive pattern, and the second power device.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
57.
INSPECTION APPARATUS, INSPECTION SYSTEM, INSPECTION METHOD, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
According to one embodiment, an inspection apparatus includes a controller configured to be electrically connected to a semiconductor device. The semiconductor device includes a semiconductor member, a transistor section, and a diode section. The transistor section and the diode section are provided in the semiconductor member. The transistor section includes a source electrode, a drain electrode, and a gate electrode. The diode section includes a first end and a second end. The first end is electrically connected to the source electrode. The second end is electrically connected to the drain electrode. The controller is configured to perform a first operation, a first progress operation, a second operation, and a first determination operation. The first progress operation is performed after the first operation. The second operation is performed after the first progress operation.
According to one embodiment, a semiconductor device includes first to third electrodes, first to fifth semiconductor members, and a first insulating member. The first semiconductor member is of a first conductivity type, and includes a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region. The second semiconductor member is of a second conductivity type, and includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The third semiconductor member is of the first conductivity type, and includes a first semiconductor portion and a second semiconductor portion. The fourth semiconductor member is of the second conductivity type. The fifth semiconductor member is of the second conductivity type. The third electrode includes a first conductive portion. The first insulating member includes a first insulating region.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
According to one embodiment, a disk device includes a disk medium, a head, and a controller. The disk medium includes a recording surface. The head includes a first read element and a heater. The first read element faces the recording surface. The controller is configured to detect a first noise during heating of the head, in response to a signal read from the disk medium by the first read element when starting supply of an electric power to the heater.
According to one embodiment, a power module including a power device, a first conductive pattern, a shunt resistor element, and a second conductive pattern is provided. One end of the first conductive pattern is connected to the power device. The first conductive pattern extends from the power device in at least a first direction. One end of the shunt resistor element in the first direction is connected to the other end of the first conductive pattern. The second conductive pattern is connected to the other end of the shunt resistor element. The second conductive pattern includes a portion. The portion extends in the first direction along the shunt resistor element and the first conductive pattern from a position separated from the shunt resistor element in the second direction. The second direction intersects the first direction.
G01R 1/20 - Modifications des éléments électriques fondamentaux en vue de leur utilisation dans des appareils de mesures électriquesCombinaisons structurelles de ces éléments avec ces appareils
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor member of a first conductivity type, a second semiconductor member of a second conductivity type, a third semiconductor member of the first conductivity type, a fourth semiconductor member, and a first insulating member. The first semiconductor member includes first to third partial regions. The second semiconductor member includes first and second regions. The third semiconductor member is electrically connected to the second electrode. The fourth semiconductor member is electrically connected to the second electrode. The fourth semiconductor member is of the first conductivity type, or does not include an impurity of the second conductivity type.
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor member of a first conductivity type, a second semiconductor member of a second conductivity type, a third semiconductor member of the first conductivity type, a fourth semiconductor member, and a first insulating member. The first semiconductor member includes first to third partial regions. The second semiconductor member includes first and second regions. The third semiconductor member is electrically connected to the second electrode. The fourth semiconductor member is electrically connected to the second electrode. The fourth semiconductor member is of the first conductivity type, or does not include an impurity of the second conductivity type.
The first insulating member includes a first insulating region provided between the third partial region and at least a portion of the third electrode.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
A semiconductor of an embodiment includes a lead frame including a first bed; a first post; a second post; a semiconductor chip provided on the first upper surface; a first bonding material provided between the first upper surface and the semiconductor chip, the first bonding material joining the first upper surface and the semiconductor chip, a first film thickness of the first bonding material portion being thinner than a second film thickness of the second bonding material portion; a first connector; a second bonding material; and a third bonding material.
According to one embodiment, a disk device includes a disk-shaped recording medium, an actuator assembly, a magnetic head supported in the actuator assembly, a first stopper which is provided contactably with the actuator assembly and defines a move of the actuator assembly in a first direction, and a first auxiliary stopper which is provided at a position where the actuator assembly comes into contact with the first auxiliary stopper after the actuator assembly comes into contact with the first stopper, and which defines the move of the actuator assembly in the first direction.
A drive circuit of an embodiment is a drive circuit that normally-off drives a transistor circuit constituted of a normally-on-type first transistor and a normally-off-type second transistor which are connected in series. The drive circuit of the embodiment has a clamping transistor that is disposed between a wiring, which is connected between the first transistor and the second transistor, and a drive terminal of the first transistor, and a capacitor that is disposed between the clamping transistor and the wiring and is connected to the clamping transistor in series.
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
A drive circuit normally-off drives a transistor circuit which is constituted of a normally-on-type first transistor and a normally-off-type second transistor connected in series. A power source voltage wiring is connected between first transistor and the second transistor. The drive circuit has a diode which is disposed between a drive terminal of the first transistor and the second transistor, a third transistor which is disposed between the power source voltage wiring and the drive terminal of the first transistor, a fourth transistor which is disposed between a ground and the drive terminal of the first transistor, a fifth transistor which is disposed between the drive terminal of the first transistor and the fourth transistor, and a control circuit unit which switches states of the second, third, fourth, and fifth transistors.
A digital filter completes a portion of digital filter operations performed on a control signal before the control signal has been determined. Calculation delay associated with performing digital filter operations on the control signal can be reduced and stability of the servo control system improved. For a particular servo wedge of a storage disk, an estimated control signal is used to determine a pre-computed first output of a digital filter before an actual control signal for that particular servo wedge has been determined. Then, once the actual control signal for the servo wedge has been determined, an implemented second output of the digital filter is determined based on the pre-computed first output and a difference between the estimated control signal and the actual control signal. The implemented second output of the digital filter is used to control magnetic head position in response to crossing the servo wedge.
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'un disque
G11B 5/55 - Changement, sélection ou acquisition de la piste par déplacement de la tête
A magnetic disk device includes a magnetic disk to which positional information for each track is written, an assist mechanism that heats the magnetic disk, a magnetic head that performs data reading and data writing on the magnetic disk, and a controller that controls the magnetic disk device. The controller is configured to cause the magnetic head to read the positional information written to the magnetic disk to learn a correction amount of a positional deviation generated in synchronization with rotation of the magnetic disk, in parallel with reading the positional information, cause, while supplying assist power to the assist mechanism to heat a learning target portion of the magnetic disk, the magnetic head to write a data pattern used for detection of a defective portion of the magnetic disk, and while supplying the assist power to the assist mechanism to heat a writing target portion of the correction amount of the magnetic disk, cause the magnetic head to write the learned correction amount to the magnetic disk.
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'un disque
G11B 20/18 - Détection ou correction d'erreursTests
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
H10D 62/60 - Distribution ou concentrations d’impuretés
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/824 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe III-V, p. ex. des hétérojonctions GaN/AlGaN
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, a conductive body, and a gate electrode. The first semiconductor region is located on the first electrode and electrically connected with the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on a portion of the second semiconductor region. The conductive body is located in the first semiconductor region with an insulating part interposed. A lower surface of the conductive body includes first and second surfaces. The gate electrode is located in the insulating part. The gate electrode faces the second semiconductor region via a gate insulating layer. The second electrode is located on the second and third semiconductor regions. The second electrode is electrically connected with the second and third semiconductor regions.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
70.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device 100 includes: a substrate; a mounting material disposed on the substrate; and a semiconductor element disposed on the mounting material. A wall-shaped wall and a non-wall region in which the wall is not provided are formed along a perimeter of the mounting material on the substrate.
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
71.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A method for manufacturing a semiconductor device includes forming an electrode on a structure body. The structure body includes a first insulating film, a second insulating film, and a semiconductor part. The electrode includes a first electrode part and a second electrode part. The first electrode part extends in a first direction and travers a region directly above the semiconductor part. The second electrode part extends from the first electrode part in a second direction. The method includes forming a first semiconductor part. The method includes forming a first mask on the structure body. The method includes forming a second semiconductor part in a portion of the first semiconductor part by using the first mask and the electrode as a mask to ion-implant an impurity. The method includes removing the first mask. The method includes forming a contact connected to the one part.
According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a conductive portion, a gate electrode, and a second electrode. The first semiconductor region including a first portion. The second semiconductor region is provided on the first portion. The gate electrode faces the first portion via a gate insulating layer. The second electrode includes platinum, cobalt, or nickel. The second electrode includes a first electrode portion and a second electrode portion. The first electrode portion is arranged with the first portion and the second semiconductor region in the second direction. The first portion is positioned between the first electrode portion and the gate electrode. The second electrode portion is provided on the gate electrode via an insulating layer. The second semiconductor region is positioned between the first electrode portion and the second electrode portion.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
A semiconductor device according to one embodiment includes a semiconductor part including a first semiconductor layer, a second semiconductor layer located on the first semiconductor layer, and a third semiconductor layer located in a first trench of the second semiconductor layer, a first electrode located on a back surface of the first semiconductor layer, a first metallic film in contact with the second semiconductor layer in the first trench, a second metallic film in contact with the third semiconductor layer and the first metallic film in the first trench, and a second electrode in contact with the second metallic film in the first trench. The first metallic film includes a high work function metal, and the second metallic film includes a low work function metal having a lower work function than that of the first metallic film.
A method for manufacturing a semiconductor device includes forming a trench and a mesa part in a semiconductor layer; forming a field plate electrode inside the trench with a field insulating film interposed; forming a silicon nitride film on the field plate electrode, on the mesa part, and on an upper sidewall of the mesa part adjacent to the trench above the field plate electrode; forming a silicon oxide film by chemical vapor deposition inside the trench and on the mesa part; exposing the silicon nitride film on the mesa part by removing the silicon oxide film on the mesa part by chemical mechanical polishing; removing the silicon nitride film on the upper sidewall of the mesa part and the silicon nitride film on the mesa part; and forming a gate electrode on the silicon oxide film inside the trench.
A semiconductor switch includes an electromotive force generation circuit that generates an electromotive force by receiving light, a first switching transistor that is connected between a first output terminal and a reference voltage node and drives a load when the electromotive force is generated, a second switching transistor that is connected between a second output terminal and the reference voltage node and drives the load when the electromotive force is generated, and a protection circuit that protects the first switching transistor and the second switching transistor from overcurrent and overheating using the electromotive force as a power supply voltage.
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
H03K 17/08 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension
76.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device according to an embodiment includes: a first electrode including a first metal layer, a second metal layer, and an insulator; a second electrode; a semiconductor layer provided between the first electrode and the second electrode; and an insulating layer provided between the first electrode and the semiconductor layer, wherein the first electrode includes a first portion electrically connecting the semiconductor layer and the first electrode, the first portion is provided between one part of the insulating layer and another part of the insulating layer in a cross section parallel to a first direction connecting the first electrode and the second electrode, and the first portion includes the first metal layer in contact with the semiconductor layer, the second metal layer, and the insulator provided between the first metal layer and the second metal layer.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
According to one embodiment, a ramp of a magnetic disk device, includes a ramp main body and a support bracket molded to be integrated as one body from resin and a metal reinforcement plate embedded in the ramp main body and opposing the support bracket. The reinforcement plate includes an opening filled with the resin and opposing a border portion between the ramp main body and the support bracket.
G11B 5/54 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour amener la tête dans sa position de travail, pour l'en écarter ou pour la déplacer en travers des pistes
G11B 5/012 - Enregistrement, reproduction ou effacement sur des disques magnétiques
G11B 21/22 - Supports de têtesSupports des douilles pour les têtes embrochables pendant que la tête est écartée de sa position de travail
A semiconductor device manufacturing method according to the present embodiment includes forming a recess on a second surface of a wafer, the wafer including a first surface on which a semiconductor element is provided and the second surface on a side opposite to the first surface, so as to form, on the second surface, a thin plate portion and an annular protrusion portion that surrounds the thin plate portion. The present manufacturing method includes forming a first film on the second surface. The present manufacturing method includes removing a part of the first film such that at least a part of the first film remains in a boundary portion between the thin plate portion and the annular protrusion portion.
According to one embodiment, a suspension assembly includes a wiring member. The tail connector of the wiring member includes a base layer, a cover layer, and a conductive layer interposed between the base layer and the cover layer. The cover layer includes a groove. The conductive layer includes a first wire, a second wire, and a connection terminal extending between the first wire and the second wire across the groove. The base layer includes a first base covering the first wire, a second base covering the second wire first protrusion pair protruding from the first base to partially cover the connection terminal, and second protrusion pair protruding from the second base to partially cover the connection terminal.
According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a metal layer, and a second electrode. The gate electrode faces the second semiconductor region via a gate insulating layer in a second direction. The second direction is perpendicular to a first direction from the first electrode toward the first semiconductor region. The metal layer is provided on the gate electrode via a first insulating layer. The metal layer includes at least one selected from the group consisting of titanium, lanthanum, and vanadium. The second electrode is provided on the metal layer via a second insulating layer. The second electrode is electrically connected to the second semiconductor region and the third semiconductor region.
According to one embodiment, a semiconductor device has first and second electrodes with a semiconductor layer therebetween. An insulating layer is between the first electrode and the semiconductor layer. A gate electrode is adjacent to a mesa part of the semiconductor layer. A conductive member is also adjacent to the mesa part. A first connector is between the first electrode and the mesa part at a first position. A second connector is between the first electrode and the first conductive member at a second position. The first electrode has a first recess above the first conductive member at the first position. The first position and the second position are offset from each other in a length direction.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
According to one embodiment, a semiconductor device includes a semiconductor layer with a plurality of first and second trenches extending lengthwise in a first direction. A first gate electrode is in each first trench. A second gate electrode is in each second trench. A first gate wiring has an upper metal layer and a lower metal layer and a second gate wiring also has an upper metal layer and a lower metal layer. At position where the first gate wiring and the second gate wiring cross without being electrically connected, the lower metal layer of one the first or second gate wirings and the upper metal layer of the other of the first or second gate wirings are not present.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
A semiconductor integrated circuit includes a first terminal and a second terminal. A resistance value between the first terminal and the second terminal changes with a change of an input voltage which is externally input.
A semiconductor device according to an embodiment includes a semiconductor layer, a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of the first conductivity type. The semiconductor layer includes a first portion and a second portion. The first portion includes a third electrode provided in the second semiconductor region via an insulating region, and a fourth semiconductor region of the second conductivity type provided in the second semiconductor region. The second portion includes a conductive connection part having a length in a third direction smaller than that of the third electrode; and a fifth semiconductor region of the second conductivity type that is provided in the second semiconductor region, and has a length, in the third direction, of the fifth semiconductor region larger than that of the fourth semiconductor region.
A semiconductor device according to an embodiment includes: a semiconductor layer including a first principal surface, and a second principal surface on the opposite side from the first principal surface; a first conductive portion provided on the first principal surface of the semiconductor layer; a second conductive portion that is provided on the second principal surface of the semiconductor layer, and is joined to a metal piece via a joining material having conductivity, the joining material not being in contact with the first conductive portion; and a blocking portion that is provided on the first principal surface on the outer side of the first conductive portion, and is electrically insulated from the first conductive portion and the second conductive portion.
A semiconductor device according to the present embodiment includes a semiconductor area, a first electrode, a second electrode, a control electrode, and a third electrode. The semiconductor area includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type. The semiconductor area further includes a fourth semiconductor layer of the second conductivity type provided between the second semiconductor layer and the second electrode and electrically connected to the second electrode. A distance between the second semiconductor layer, which is in contact with the fourth semiconductor layer, and the first electrode, in a second region surrounding the first region is smaller than a distance between the second semiconductor layer, which is in contact with the fourth semiconductor layer, and the first electrode, in the first region.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A semiconductor device includes a first electrode, a second electrode disposed separately from the first electrode in a first direction, a control electrode disposed to face the second electrode in a second direction intersecting the first direction, a first insulating portion provided between the second electrode and the control electrode, a semiconductor layer provided between the first electrode and the second electrode, a first region provided between the second electrode and the first insulating portion in the semiconductor layer and connected to the second electrode by a Schottky junction, and a second region joined to the first region, disposed on the first electrode side, connected to the second electrode by a Schottky junction, and having a smaller width in the second direction than at least a part of the first region.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
A semiconductor device according to an embodiment includes first and second electrode, and a semiconductor layer between the first and second electrode. The semiconductor layer includes a plurality of first trenches and a second trench adjacent to the first trenches. The semiconductor device includes a first gate electrode, a second gate electrode in the second trench and in the second gate electrode a second length on a first trench side is larger than a third length on a opposite side, a first gate insulating layer between the first gate electrode and the semiconductor layer, a second gate insulating layer having a second thickness between the second gate electrode and the semiconductor layer on the first trench side, and a second gate insulating layer having a third thickness between the second gate electrode and the semiconductor layer on the opposite side, the third thickness being larger than the second thickness.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
A semiconductor device according to an embodiment includes: a semiconductor layer; a first and gate electrode extending in a first direction; a second gate electrode extending in the first direction; a first electrode provided on the semiconductor layer; and a second electrode provided on opposites side of the semiconductor layer. The first electrode includes a first portion and a second portion, the first portion and the second portion are provided between the first gate electrode and the second gate electrode, the first portion and the second portion are in contact with the semiconductor layer, the second portion is in the first direction with respect to the first portion, and a second width of the second portion is larger than a first width of the first portion, or a second depth of the second portion is larger than a first depth of the first portion.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
A semiconductor device of an embodiment includes a semiconductor substrate that includes a first principal surface and a second principal surface, the first principal surface and the second principal surface facing each other in a first direction, a drift region, a buffer region that includes a plurality of concentration peaks, a first electrode provided on the first principal surface, a second electrode provided on the second principal surface, and a transistor region, in which the plurality of concentration peaks includes a first concentration peak that is disposed closest to the second principal surface, a second concentration peak that is disposed farther from the second principal surface than the first concentration peak and has a higher impurity concentration than that of the first concentration peak, and a third concentration peak that is selectively providedbetween the first principal surface and the second concentration peak.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 27/07 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive les composants ayant une région active en commun
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/36 - Corps semi-conducteurs caractérisés par la concentration ou la distribution des impuretés
According to an embodiment, the method for adjusting a head flying height in a magnetic disk device including a disk, a head that writes or reads data along tracks of the disk, and a heater provided near the head includes: determining a threshold of the head flying height; calculating a statistic from the chronological data of the head flying height; and adjusting the head flying height if the statistic exceeds the threshold.
According to one embodiment, a magnetic disk device includes a disk, a write head, a write processing unit, an error correction unit, a correction limit prediction unit, and a determination unit. During a write period in which the write processing is executed on the second data track, the correction limit prediction unit is capable of determining whether or not data of each of the target sectors of the first data track is damaged, and generates prediction information, and the determination unit determines whether or not to cause the write processing unit to continue the write processing on the second data track based on the prediction information.
G11B 19/04 - Dispositions prévenant, évitant ou signalant la surimpression sur le même support, ou d'autres fonctionnements défectueux de l'enregistrement ou de la reproduction
A semiconductor device includes a first electrode; a semiconductor layer located on the first electrode; and a second electrode located on the semiconductor layer. The semiconductor layer includes a first semiconductor layer including a rare-earth element, and a second semiconductor layer located on the first semiconductor layer and electrically connected with the second electrode, the second semiconductor layer contacting the first semiconductor layer. The first semiconductor layer includes an impurity region positioned between the second semiconductor layer and the first electrode, and a crystal defect region positioned between the impurity region and the first electrode. The crystal defect region includes crystal defects. A concentration peak of the rare-earth element is in the impurity region.
H01L 29/32 - Corps semi-conducteurs ayant des surfaces polies ou rugueuses les défectuosités étant à l'intérieur du corps semi-conducteur
H01L 21/22 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire
A semiconductor device includes a first electrode, a first semiconductor layer located on the first electrode, a second semiconductor layer located on the first semiconductor layer, a third semiconductor layer located on the second semiconductor layer, a second electrode facing the second semiconductor layer via an insulating layer, a plurality of contacts, and a third electrode connected to the plurality of contacts. The first semiconductor layer and the third semiconductor layer are of a first conductivity type. The second semiconductor layer is of a second conductivity type. The second semiconductor layer includes a first part and second parts. Distances between the first electrode and the second parts are less than a distance between the first electrode and the first part. The contacts are located respectively in regions directly above the second parts. The contacts are connected to the second and third semiconductor layers.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
95.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device according to an embodiment includes: a first electrode; a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type; a third semiconductor layer of a second conductivity type; a fourth semiconductor layer of the first conductivity type; a fifth semiconductor layer provided around the second semiconductor layer on the first semiconductor layer, the fifth semiconductor layer of the first conductivity type, or the fifth semiconductor layer of the second conductivity type; a second electrode; a third electrode facing the second semiconductor layer and the third semiconductor layer; and a fourth electrode provided in the fifth semiconductor layer adjacent to the second semiconductor layer, the fourth electrode being spaced apart from the first insulating film, and the fourth electrode facing the fifth semiconductor layer.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, and a conductor. The conductor includes first and second gate electrode portions, a first wiring portion, and first and second connection portions. The first connection portion is connected between a first end portion of the first gate electrode portion and an end portion of the first wiring portion. The second connection portion is connected between a second end portion of the second gate electrode portion and the end portion of the first wiring portion. In the second direction, a position of the first wiring portion is between a position of the first gate electrode portion and a position of the second gate electrode portion. The first connection portion and the second connection portion have inclined surfaces that are inclined with respect to the second direction and the third direction.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
97.
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
A semiconductor device manufacturing method according to this embodiment includes forming a first insulation film, on a first face of a semiconductor substrate, such that a film thickness of the first insulation film at a step portion of a protrusion portion provided in a first region of the first face is thinner than a film thickness of the first insulation film at an upper surface of the protrusion portion or a film thickness of the first insulation film at a second region of the first face, the second region different from the first region. The manufacturing method includes removing part of the first insulation film using a mask material as a mask to form an opening portion of the first insulation film and a projection portion of the first insulation film. The manufacturing method includes removing the second insulation film together with part of the projection portion.
According to one embodiment, a control device includes: a control circuitry configured to control an electric motor; and a failure sensing circuitry configured to sense a failure of the electric motor, wherein the failure sensing circuitry executes frequency analysis concerning an electric signal for driving the electric motor, calculates a phase of the electric signal, calculates a phase difference between a phase of a fundamental wave of a power supply frequency of the electric signal and the calculated phase of the electric signal, extracts a first signal indicating an outflow component from the electric motor based on a calculation result of the phase difference, extracts a second signal indicating an inflow component to the electric motor based on the calculation result of the phase difference, and senses the failure based on the first signal.
H02H 7/08 - Circuits de protection de sécurité spécialement adaptés aux machines ou aux appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou de ligne, et effectuant une commutation automatique dans le cas d'un changement indésirable des conditions normales de travail pour moteurs dynamo-électriques
G01R 23/12 - Dispositions pour procéder à la mesure de fréquences, p. ex. taux de répétition d'impulsionsDispositions pour procéder à la mesure de la période d'un courant ou d'une tension par conversion de la fréquence en déphasage
According to one embodiment, a semiconductor device includes a lead frame, a semiconductor chip, a lead terminal and a package. The package includes an upper surface, a lower surface, and first and second side surfaces between the upper surface and the lower surface. The first side surface has a first surface, a second surface and a third surface. The first surface is continuous with the upper surface and is provided in an oblique direction with respect to the upper surface. The second surface is continuous with the first surface and is provided in a direction parallel to the upper surface. The third surface is continuous with the second surface and is provided in a direction orthogonal to the upper surface. The lead terminal protrudes from the first side surface and does not protrude from the second side surface.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a gate electrode, and a third semiconductor layer. The first semiconductor layer contains Alx1Ga1-x1N (0≤x1<1). The second semiconductor layer is provided on the first semiconductor layer and contains Alx2Ga1-x2N (0
H01L 29/267 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, des éléments couverts par plusieurs des groupes , , , , dans différentes régions semi-conductrices
H01L 29/36 - Corps semi-conducteurs caractérisés par la concentration ou la distribution des impuretés
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
brevets
