Abrégé

An electrostatic discharge protection device includes a voltage division adjustment circuit connected to a signal input end and generating a voltage signal. A trigger circuit is connected to the voltage division adjustment circuit to output a trigger signal. A detection circuit generates a detection signal according to the voltage signal. A control circuit generates an output signal according to the trigger signal and the detection signal, to control first and second switch circuits. The first and second inverters are respectively connected to the first and second switch circuits to control a discharge circuit. When static electricity is inputted into the signal input end, the output signal transitions to a high-voltage level to turn on the discharge circuit for discharging. The trigger signal transitions to a low-voltage level, to control the control circuit to extend output time of the output signal at the high-voltage level.

Classes IPC  ?

• H02H 9/02 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de courant
• H02H 9/00 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion

Abrégé

A wireless communication chip includes an amplifier stage, a first radio frequency circuit, and a second radio frequency circuit. The amplifier stage is configured to receive and amplify a radio frequency signal. The first radio frequency circuit includes a mixer, a baseband transconductor, an output stage, and a switch unit. The mixer is configured to receive an oscillation signal and the radio frequency signal from the amplifier stage, and is configured to adjust a frequency of the radio frequency signal based on the oscillation signal. The switch unit is electrically connected between an input terminal of the baseband transconductor and an output terminal of the baseband transconductor. The first radio frequency circuit and the second radio frequency circuit support different wireless transmission technologies, and are jointly coupled to an output terminal of the amplifier stage.

Classes IPC  ?

• H04B 1/04 - Circuits
• H03F 3/19 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs
• H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
• H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]

Abrégé

A monitor includes a display device, a current sensing device, and a scaler. The current sensing device is configured to detect a total current to generate current information when a power source of the monitor is a non-utility power source device. The scaler is coupled to the current sensing device and the display device. The scaler is configured to perform a power consumption reduction process on the display device according to the current information.

Classes IPC  ?

• G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides
• G09G 3/34 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante

Abrégé

A power management method includes: executing an initialization procedure to obtain a remaining available power value; sequentially executing a power supply procedure for each of the communication ports; calculating the power consumed by each of the communication ports that are powered on; summing the power consumed by all the communication ports that are powered on to obtain a local used power value; subtracting the used power value of the storage unit of the chip having the previous priority and the local used power value from the total power value to obtain a second remaining available power value; and in response to that the second remaining available power value is greater than or equal to 0, adding the local used power value to the used power value of the storage unit of the chip having the previous priority to obtain the used power value.

Classes IPC  ?

• H04L 12/10 - Dispositions pour l'alimentation

Abrégé

A slew rate control circuit includes a ground wire, a power wire, an output end, two switches, two switching circuits, and two grounding capacitors. The switches are respectively connected between the power wire and the output end and between the output end and the ground wire. The switching circuits are respectively connected between the power wire and the ground wire and controlled by two driving signals and thus inversely driven. One of the switching circuits is configured to drive one of the switches through the first resistance, and the other is configured to drive the other one of the switches through the second resistance. One of the grounding capacitors is connected to a control end of the first switch and one of the switching circuits, and the other is connected to a control end of the second switch and the other one of the switching circuits.

Classes IPC  ?

• H03K 5/04 - Mise en forme d'impulsions par augmentation de duréeMise en forme d'impulsions par diminution de durée
• H01R 13/66 - Association structurelle avec des composants électriques incorporés

Abrégé

An occlusion judgment system, an occlusion judgment method, a computer readable recording medium with a stored program, and a non-transitory computer program product are provided. The occlusion judgment system includes: a pre-processing unit configured to receive an image from a lens and perform a pre-processing procedure on the image to obtain a pre-processed image; a depth image generating unit configured to perform a depth image computation procedure on the pre-processed image to obtain a depth image; and a judgment unit configured to determine a lens state of the lens based on the depth image.

Classes IPC  ?

• H04N 23/60 - Commande des caméras ou des modules de caméras
• G06V 10/26 - Segmentation de formes dans le champ d’imageDécoupage ou fusion d’éléments d’image visant à établir la région de motif, p. ex. techniques de regroupementDétection d’occlusion
• G06V 10/28 - Quantification de l’image, p. ex. seuillage par histogramme visant à discriminer entre les formes d’arrière-plan et d’avant-plan
• G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
• H04N 23/61 - Commande des caméras ou des modules de caméras en fonction des objets reconnus

Abrégé

A radio frequency power amplifier (RFA) including: an n-type common-source amplifier (NCSA) used to convert a first voltage signal into a first current signal; an n-type common-gate amplifier (NCGA) relaying the first current signal into a second current signal directed to an output node based on a first bias voltage; a p-type common-source amplifier (PCSA) powered by a first power supply to convert a second voltage signal into a third current signal; a p-type common-gate amplifier (PCGA) relaying the third current signal into a fourth current signal directed to the output node based on a second bias voltage; and an inductor attached to the output node and featuring a center tap, wherein while in a low-power mode, the second bias voltage is set to a level that turns off the PCGA, and the central node has a low impedance and a DC voltage determined by a second power supply.

Classes IPC  ?

• H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie

Abrégé

A circuit with calibration function includes a fully differential amplifier circuit, two voltage generation circuits, two multiplexers, a comparator and a digital logic circuit. The fully differential amplifier circuit amplifies a pair of differential input voltages to generate a pair of differential output voltages. One voltage generation circuit utilizes a first current to flow through a capacitor to generate a first voltage. The other voltage generation circuit utilizes a second current to flow through a resistor to generate a second voltage. The multiplexers provide the pair of differential output voltages or the first and second voltages to the comparator according to a digital control signal. The digital logic circuit generates a first digital code to adjust a capacitance of the capacitor or a second digital code to adjust DC voltage levels of the pair of differential output voltages according to the comparison signal provided by the comparator.

Classes IPC  ?

• H03K 19/00 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion
• H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface

Abrégé

An audio compression method, comprising: dividing an audio signal into at least one block signal, wherein each of the at least one block signal comprises a plurality of channel signals and has a block data size; performing a lossless compression on one of the at least one block signal; in response to the block data size of the compressed one of the at least one block signal being equal to or smaller than a budget data size, outputting the compressed audio signal; in response to the block data size of the compressed one of the at least one block signal being greater than the budget data size, performing a lossy compression on at least one of the plurality of channel signals based on a scale factor; and in response to all of the plurality of channel signals having been compressed based on the scale factor, reducing the scale factor.

Classes IPC  ?

• G10L 19/008 - Codage ou décodage du signal audio multi-canal utilisant la corrélation inter-canaux pour réduire la redondance, p. ex. stéréo combinée, codage d’intensité ou matriçage
• G10L 19/00 - Techniques d'analyse ou de synthèse de la parole ou des signaux audio pour la réduction de la redondance, p. ex. dans les vocodeursCodage ou décodage de la parole ou des signaux audio utilisant les modèles source-filtre ou l’analyse psychoacoustique

Abrégé

A radar device includes a transmitter and receiver circuit and an estimation circuit. The transmitter and receiver circuit is configured to generate a second signal according to a first signal. The estimation circuit is coupled to the transmitter and receiver circuit, is configured to generate an estimated path delay according to the second signal, and is configured to generate an estimated phase noise according to the estimated path delay for a back-end circuit to execute a related application.

Classes IPC  ?

• G01S 7/02 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe

Abrégé

A reference voltage supply circuit includes a first transistor, a second transistor, a first resistor, and a second resistor. The first transistor is coupled to a high voltage level terminal. The second transistor is coupled to a low voltage level terminal. The first resistor is coupled with the first transistor at a reference node for providing a reference voltage. The second resistor is coupled between the first resistor and the second transistor. The first resistor and the second resistor include variable resistors.

Classes IPC  ?

• G05F 3/16 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs

Abrégé

A relaxation oscillator includes first to the sixth transistor, a resistor, a capacitor, an inverter, a pulse generator, and first to the third switch. The resistor is coupled between the third source and the third gate of the third transistor. The capacitor is coupled between the fourth source and the fourth gate of the fourth transistor. The input terminal of the inverter is coupled to the sixth drain of the sixth transistor. The pulse generator generates a pulse signal. The first switch is coupled between the inverter and a first reference voltage. The second switch is coupled between the inverter and the fifth transistor. The third switch is coupled between the fourth transistor and a second reference voltage. The first to third switches are turned on or off according to the pulse signal.

Classes IPC  ?

• H03B 5/24 - Élément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p. ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
• H03K 3/037 - Circuits bistables

Abrégé

An information transceiving method, applied to an information transceiving system comprising a transmission device and a reception device. The transmission device comprises a first TX input interface following a first transceiving specification and a second TX input interface following a second transceiving specification. The reception device comprises a first RX output interface following a third transceiving specification. The information transceiving method comprises: (a) respectively receiving first, second information by the first, second TX input interface; (b) classifying according to information characteristics of the first, second information by the transmission device, to acquire first, second classifying results of the first, second information; and (c) transmitting the first information or the second information to the first RX output surface via a physical transmission line, corresponding to the first, second classifying results by the transmission device.

Classes IPC  ?

• H04B 10/25 - Dispositions spécifiques à la transmission par fibres
• H04B 10/40 - Émetteurs-récepteurs

Abrégé

An image data transceiving system, comprising: a transmitting device, configured to output a first target image stream, wherein the first target image stream comprises a plurality of first target images; and a receiving device, configured to decode the first target image stream to obtain a plurality of second target images. The transmitting device or the receiving device generates a reference image stream according to the first target image stream. The reference image stream comprises first reference images generated by the transmitting device or second reference images generated by the receiving device. Data amount of the first reference images is less than data amount of corresponding ones of the first target images, and data amount of the second reference images is less than data amount of corresponding ones of the corresponding second target images. The transmitting device further receives the reference image stream through the receiving device.

Classes IPC  ?

• H04N 19/146 - Débit ou quantité de données codées à la sortie du codeur

Abrégé

A voltage supply circuit includes a first loop and a second loop. The first loop includes a first and second transistor, and a first and second resistor. The first resistor couples to the first transistor. The second resistor couples between the first and second transistor. The second loop includes a third and fourth transistor, and a third and fourth resistor. The third resistor and the third transistor couple at an output node for providing an output voltage. The fourth resistor couples between the third resistor and the fourth transistor. The first and third transistor couple to a high-voltage level terminal. A control terminal of the first transistor couples to that of the third transistor. The second and fourth transistor couples to a low-voltage level terminal. A control terminal of the second transistor couples to that of the fourth transistor. The first resistor to the fourth resistor include variable resistors.

Classes IPC  ?

• H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs

Abrégé

A radar device includes a transmitter and receiver circuit and an estimation circuit. The transmitter and receiver circuit is configured to generate a second signal according to a first signal. The estimation circuit is coupled to the transmitter and receiver circuit and is configured to generate an estimated path delay according to the second signal for a back-end circuit to execute a related application.

Classes IPC  ?

• G01S 7/40 - Moyens de contrôle ou d'étalonnage
• G01S 7/35 - Détails de systèmes non impulsionnels

Abrégé

A method for enhancing timing performance of ultra-wideband (UWB) ranging with aid of phase detection and associated apparatus such as a communication circuit and an electronic device are provided. The method may include: utilizing a time coarse estimation circuit within a UWB ranging processing circuit to perform time coarse estimation according to a UWB signal to generate at least one time estimation result; and utilizing a time fine estimation circuit within the UWB ranging processing circuit to perform time fine estimation according to the at least one time estimation result to generate an estimated time; where the time coarse estimation circuit performs the phase detection according to a feature database within the communication circuit and at least one feature obtained from the UWB signal, to generate at least one fractional part of the at least one time estimation result, for enhancing time accuracy in advance to enhance the timing performance.

Classes IPC  ?

• G01S 7/295 - Moyens pour transformer des coordonnées ou pour évaluer des données, p. ex. en utilisant des calculateurs
• G01S 13/02 - Systèmes utilisant la réflexion d'ondes radio, p. ex. systèmes du type radar primaireSystèmes analogues
• G01S 13/10 - Systèmes pour mesurer la distance uniquement utilisant la transmission de trains discontinus d'ondes modulées par impulsions

Abrégé

A signal receiving circuit is provided. The signal receiving circuit includes an input transistor and a capacitor compensation circuit, where the capacitor compensation circuit is coupled to a gate terminal of the input transistor. The gate terminal of the input transistor is configured to receive an input signal, where a parasitic capacitance of the input transistor changes in response to a change in a voltage level of the input signal based on a first change direction. The capacitor compensation circuit is configured to provide a compensation capacitance according to the voltage level of the input signal, where the compensation capacitance changes in response to the change in the voltage level of the input signal based on a second change direction. More particularly, the first change direction is opposite to the second change direction.

Classes IPC  ?

• H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites

Abrégé

A wireless communication device includes a mixer, a low-pass filter (LPF), an in-band analog-to-digital converter (ADC), a wideband ADC, and a baseband processor. The mixer is configured to mix a radio frequency signal and a carrier signal for performing frequency conversion on the radio frequency signal to obtain a mixed signal. The LPF is coupled to the mixer and configured to perform filtering on the mixed signal to filter out signal components of the mixed signal out of a passband to obtain a baseband signal. The in-band ADC is configured to convert the baseband signal into an in-band signal. The wideband ADC is configured to convert the mixed signal into a wideband signal. The baseband processor is coupled to the in-band ADC and the wideband ADC, and configured to compare the wideband signal with the in-band signal to determine whether an out-of-band interference exists.

Classes IPC  ?

• H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission

Abrégé

The present invention provides a LDO including an operational amplifier, a first transistor and a buffer. The operational amplifier is configured to receive a reference voltage and a feedback voltage to generate a control signal. A gate electrode of the first transistor receives the control signal, a first electrode of the first transistor is coupled to a supply voltage, and a second electrode of the first transistor is coupled to a node, wherein the node is used to generate an output voltage of the LDO. An input terminal of the buffer is connected to a bias voltage, and an output terminal of the buffer is connected to the node.

Classes IPC  ?

• G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction

Abrégé

A method of operating a communication device includes amplifying a preset proportion of symbols in a set of input symbols to generate a set of amplified symbols, accumulating the set of amplified symbols to generate an enhanced symbol, searching for a first path according to the enhanced symbol, accumulating unamplified symbols in the set of input symbols to generate an normal symbol, and searching for the first path according to the normal symbol. The method further includes generating a first path signal if the first path is found according to the enhanced symbol and/or the normal symbol, and generating a first path dynamic range (FPDR) according to at least the first path signal.

Classes IPC  ?

• H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
• H04B 1/04 - Circuits
• H04W 72/044 - Affectation de ressources sans fil sur la base du type de ressources affectées

Abrégé

A detection system includes a visible light detector, an infrared detector, and a processing circuit. The visible light detector is configured to detect visible light. The infrared detector is configured to detect infrared light. The processing circuit is configured to determine whether a parameter of the visible light detector is larger than a threshold. If the parameter of the visible light detector is larger than the threshold, the processing circuit executes a human presence detection according to the infrared light detected by the infrared detector, and generates a human presence detection result.

Classes IPC  ?

• G01J 5/00 - Pyrométrie des radiations, p. ex. thermométrie infrarouge ou optique
• G01J 5/02 - Détails structurels
• G01J 5/03 - Dispositions pour l’indication ou l’enregistrement spécialement adaptées aux pyromètres à radiations
• G08B 21/22 - Alarmes de situation réagissant à la présence ou à l'absence de personnes

Abrégé

The present invention provides an encoder including a quantization circuit, a quantized data adjustment circuit and an encoding circuit. The quantization circuit is configured to perform a quantization operation on multiple blocks of current frame data in sequence, to generate multiple quantized data respectively corresponding to the multiple blocks. For each of the multiple blocks in the current frame data, the quantized data adjustment circuit adjusts multiple coefficients in the quantized data corresponding to the block according to an optimization level of the block, to generate adjusted quantized data. The encoding circuit is configured to encode the adjusted quantized data of each of the multiple blocks to generate encoded data.

Classes IPC  ?

• H04N 19/124 - Quantification
• H04N 19/159 - Type de prédiction, p. ex. prédiction intra-trame, inter-trame ou de trame bidirectionnelle
• H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une image, une trame ou un champ
• H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant un bloc, p. ex. un macrobloc
• H04N 19/184 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant des bits, p. ex. de flux vidéo compressé
• H04N 19/50 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage prédictif

Abrégé

A method for a station to obtain resource unit allocation information, includes: receiving a first data unit, obtaining resource allocation information corresponding to the first data unit and obtaining a format description of a common field in a first signal field of the first data unit; receiving a second data unit, obtaining a format description of a common field in a first signal field of the second data unit; when the format descriptions of the common fields of the two data units are identical, comparing bits of the common fields between the two data units; and when the bits of the common fields of the two data units are identical, using the resource allocation information corresponding to the first data unit to parse a user-specific field of the first signal field of the second data unit, and accordingly configuring the station.

Classes IPC  ?

• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
• H04W 72/0453 - Ressources du domaine fréquentiel, p. ex. porteuses dans des AMDF [FDMA]

Abrégé

A method for determining equalizer coefficients includes the following operations: (a) setting low-frequency equalizer coefficients of a low-frequency equalizer circuit; (b) establishing a network connection via the low-frequency equalizer circuit and a decision feedback equalizer circuit, in which the decision feedback equalizer circuit operates according to an output of the low-frequency equalizer circuit; (c) recording a sum of absolute values of decision feedback equalizer coefficients of the decision feedback equalizer circuit and a signal-to-noise ratio; (d) repeatedly performing the operations (a) to (c) to obtain sums of absolute values and signal-to-noise ratios; (e) selecting a first sum of absolute values from sums of absolute values according to a predetermined threshold value and signal-to-noise ratios; and (f) setting low-frequency equalizer coefficients as a value combination corresponding to the first sum of absolute values.

Classes IPC  ?

• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs

Abrégé

An embedded system includes a clock controller circuit, a clock gating circuit, and a bus controller circuit. The clock controller circuit is configured to set a memory control signal according to a sleep signal from a processor to control a first memory to enter a sleep mode and to set a clock control signal and a request signal according to the sleep signal. The clock gating circuit is configured to stop transmitting a plurality of clock signals to the processor and the first memory according to the clock control signal. The bus controller circuit is configured to stop sending an access request to the processor and the first memory according to the request signal.

Classes IPC  ?

• G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci

Abrégé

An integrator operating based on a variable current is provided. The integrator includes an operational amplifier, wherein the operational amplifier includes an amplifying stage circuit and a bias circuit. The amplifying stage circuit is configured to provide an amplification gain. The bias circuit is coupled to the amplifying stage circuit and is configured to control a bias condition of the amplifying stage circuit according to the variable current output from a variable current source. In a sampling phase of the integrator, the variable current source switches the variable current to a sampling current value. In an integration phase of the integrator, the variable current source switches the variable current to an integration current value. More particularly, the sampling current value is less than the integration current value.

Classes IPC  ?

• H03M 1/00 - Conversion analogique/numériqueConversion numérique/analogique
• H03F 3/45 - Amplificateurs différentiels

Abrégé

A signal processing circuit includes a channel estimation device, a data processing circuit and a false path detection circuit. The channel estimation device estimates transmission paths of a received signal based on a preamble portion of the received signal to generate channel parameter information. The data processing circuit processes a data portion of the received signal according to the channel parameter information to generate a data demodulation result associated with each transmission path. The false path detection circuit determines a characteristic value based on the data demodulation result associated with each transmission path, determines whether corresponding transmission path is a false path according to the characteristic value and the channel parameter information, and updates the channel parameter information to generate updated channel parameter information in response to the corresponding transmission path being determined as a false path. The updated channel parameter information does not comprise information regarding the false path.

Classes IPC  ?

• H04L 25/02 - Systèmes à bande de base Détails
• H04L 43/08 - Surveillance ou test en fonction de métriques spécifiques, p. ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux

Abrégé

A method for correcting local-dimming parameters through global backlight adjustment and a circuit system are provided. The circuit system connects with a backlight control circuit of a display. In the method operated in the circuit system, when an image is received, the pixel values of each of the regions divided from the image can be counted so as to obtain a local maximum and a local average of every region, and a global average of the image. The region having a dark-field halo can be detected based on a local difference between the local maximum and the local average. A leakage level can be obtained by determining an impact of the dark-field halo on the whole image based on a threshold. The leakage level and the global average are referred to for calculating a gain for global backlight adjustment after performing local dimming.

Classes IPC  ?

• G09G 3/34 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante

Abrégé

A method and a system for fixed pattern detection in motion images are provided. In the method, continuous motion images are obtained, and frames at multi-layer resolutions can be retrieved from the motion images. Multiple fixed patterns in multiple frames at the multi-layer resolutions can be detected based on features of previous and current frames. A first fixed pattern at a higher resolution can be to a lower-resolution fixed pattern, and the lower-resolution fixed pattern is merged with a second fixed pattern at the same lower resolution so as to generate a merged fixed pattern. The merged fixed image at the lower resolution is eroded and converted to a higher-resolution image. A boundary detection process is performed on the higher-resolution image. The first fixed image at the higher resolution is eroded according to a result of boundary detection so as to obtain a clear fixed pattern.

Classes IPC  ?

• G06T 7/207 - Analyse du mouvement pour l’estimation de mouvement sur une hiérarchie des résolutions

Abrégé

A Bluetooth communication method is suitable for a remote controller device. The remote controller device is configured to be Bluetooth-paired with a host terminal. The Bluetooth communication method includes following steps. In a lasting duration since the remote controller device resumes from a power-off mode into a power-on mode and a Bluetooth connection is not yet re-established between the remote controller device and the host terminal, key-input information generated by the remote controller device is temporarily recorded in a buffer memory of the remote controller device. The key-input information temporarily recorded in the buffer memory is attached to a payload of a re-connection advertising packet. The re-connection advertising packet is transmitted, and the re-connection advertising packet is configured to trigger re-establishing of the Bluetooth connection between the remote controller device and the host terminal.

Classes IPC  ?

• H04W 48/16 - ExplorationTraitement d'informations sur les restrictions d'accès ou les accès
• H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
• H04W 48/10 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p. ex. distribution de données d'exploration utilisant des informations radiodiffusées
• H04W 76/19 - Rétablissement de connexion

Abrégé

A receiving module of a transmission interface includes an analog front-end (AFE) circuit and a track-and-hold circuit. The AFE circuit receives an input signal to generate a first intermediate signal. The track-and-hold circuit samples the first intermediate signal according to a first clock to generate a second intermediate signal, and comprises at least one first switch, at least one second switch, at least one first capacitor, and at least one second capacitor. The first and second switches are turned on or off according to the first clock. The first capacitor has first and second terminals. The first terminal is coupled to the AFE circuit. The second terminal receives a second clock. The second capacitor has third and fourth terminals. The third terminal is coupled to the AFE circuit. The fourth terminal receives the second clock. The first clock and the second clock are inverted signals of each other.

Classes IPC  ?

• H04B 1/16 - Circuits
• H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission

Abrégé

The present disclosure discloses an electronic apparatus having low power wake-up mechanism that includes an upper layer circuit and a physical layer. The upper layer circuit is powered off in a sleep state. The physical layer wakes up the upper layer circuit in the sleep state according to a logic state transition event that switches a pair of differential signal lines of a USB interface from a sleep logic state to a wakeup logic state such that a power of the upper layer circuit is restored. The physical layer modifies a voltage state of the differential signal lines to drive a host apparatus to detect a pull-out event and a plug-in event in series. The physical layer controls the upper layer circuit to perform initialization and enumeration process with the host apparatus to reconnect with the host apparatus.

Classes IPC  ?

• H02M 3/04 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques

Abrégé

An RFA (radio frequency amplifier) includes an NCSA (N-type common-source amplifier) established upon a first source node and configured to receive a first signal and output a first internal current; a first NCGA (N-type common-gate amplifier) configured to receive the first internal current and output a second internal current; a second NCGA configured to receive the second internal current and output a first output current; a PCSA (P-type common-source amplifier) established upon a second source node and configured to receive a second signal and output a third internal current; a first PCGA (P-type common-gate amplifier) configured to receive the third internal current and output a fourth internal current; a second PCGA configured to receive the fourth internal current and output a second output current; and a load network comprising a parallel connection of a primary inductor and a tuning capacitor configured to establish an output signal.

Classes IPC  ?

• H03F 3/193 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
• H03F 1/30 - Modifications des amplificateurs pour réduire l'influence des variations de la température ou de la tension d'alimentation
• H03F 3/45 - Amplificateurs différentiels

Abrégé

An image processing method includes following operations: receiving a visible-light image; receiving an infrared image; determining a shooting scene according to the infrared image; determining whether to perform a high dynamic range processing on the visible-light image according to the shooting scene; and when it is determined to perform the high dynamic range processing on the visible-light image, generating and outputting a high dynamic range image for a back-end system to display.

Classes IPC  ?

• G06T 5/92 - Modification de la plage dynamique d'images ou de parties d'images basée sur les propriétés globales des images
• G06T 5/50 - Amélioration ou restauration d'image utilisant plusieurs images, p. ex. moyenne ou soustraction
• G06T 11/00 - Génération d'images bidimensionnelles [2D]
• G06V 20/00 - ScènesÉléments spécifiques à la scène
• G06V 40/10 - Corps d’êtres humains ou d’animaux, p. ex. occupants de véhicules automobiles ou piétonsParties du corps, p. ex. mains

Abrégé

An analog-to-digital conversion apparatus having signal calibration mechanism is provided. Capacitors in an odd and an even conversion circuits in a conversion circuit are switched to perform conversion on a signal feeding to generate odd and even digital signals such that an odd and an even calibration circuit performs mapping thereon according to odd and even capacitance offset tables to generate odd and even calibrated signals. A digital filtering circuit performs digital filtering on the odd and the even calibrated signals according to odd and even filtering parameters and merges the filtered results to generate a merged output digital signal such that a calibration parameter calculation circuit performs filtering thereon to generate an odd and an even inverted error signal and further performs calculation thereon with the corresponding odd and even digital signals to generate odd and even updating parameter to update the odd and the even capacitance offset tables.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests
• H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques

Abrégé

A successive approximation register analog-to-digital converter includes a digital-to-analog conversion circuit. The digital-to-analog conversion circuit includes a first set of switches and a first capacitor group. The first capacitor group samples an analog input signal during a sampling period and receives a first set of reference signals through the first set of switches during a holding period so as to accomplish charge redistribution and thereby generate a sampling-and-switching operation result. The first capacitor group includes a first subsidiary capacitor group and a second subsidiary capacitor group. Each capacitor of the first subsidiary capacitor group is composed of one or more first unit capacitor(s). Each capacitor of the second subsidiary capacitor group is composed of one or more second unit capacitor(s). The layouts of the first and the second unit capacitors are different. The designed capacitance value of the second unit capacitor is greater than that of the first unit capacitor.

Classes IPC  ?

• H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur

Abrégé

A synchronization method of image sensors includes: obtaining a first current time of a first current frame of a first image sensor; obtaining a first previous time of a first previous frame and a second current time of a second current frame of a second image sensor; calculating a first difference between the first current time and the second current time; calculating a second difference between the first current time and the first previous time; and adjusting a line length or a frame length of the second image sensor according to a first determination result of the first difference and the second difference to synchronize the first image sensor and the second image sensor.

Classes IPC  ?

• H04N 23/60 - Commande des caméras ou des modules de caméras
• H04N 23/45 - Caméras ou modules de caméras comprenant des capteurs d'images électroniquesLeur commande pour générer des signaux d'image à partir de plusieurs capteurs d'image de type différent ou fonctionnant dans des modes différents, p. ex. avec un capteur CMOS pour les images en mouvement en combinaison avec un dispositif à couplage de charge [CCD] pour les images fixes

Abrégé

A radar device includes a frequency modulated continuous wave (FMCW) generator, a radio frequency (RF) circuit, a computing circuit, and a coherent subtractor. The FMCW generator is configured to generate an FMCW signal. The RF circuit is configured to modulate the FMCW signal into an RF signal and demodulate a reflection signal reflected at a target from the RF signal, so as to obtain a received signal. The computing circuit is configured to reconstruct a short-range leakage signal according to the FMCW signal and an estimated channel coefficient, a delay coefficient, a phase coefficient, and an amplitude coefficient obtained in a short-range leakage estimation stage of the radar device. The coherent subtractor is configured to compensate the received signal by the reconstructed short-range leakage signal.

Classes IPC  ?

• G01S 7/35 - Détails de systèmes non impulsionnels
• G01S 7/02 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe

Abrégé

A hub includes a first up-stream port (USP), a second USP, a down-stream port (DSP), a first control unit, and a second control unit. The first USP is configured to connect to a first electronic device. The second USP is configured to connect to a second electronic device. The DSP is configured to connect to a third electronic device. The first control unit is connected to the first USP and the DSP, to select whether to bring the DSP into data communication with the first USP. The second control unit is connected to the second USP and the DSP, to select whether to bring the DSP into data communication with the second USP.

Classes IPC  ?

• G06F 13/40 - Structure du bus

Abrégé

A multiple charging path control device includes: first and second charging paths, respectively utilized for selectively providing first and second charging currents from first and second power sources to an electronic device based on first and second path switching signals; first and second path control circuits, respectively utilized for generating the first and second path switching signals based on at least first and second path main control signals; and a control signal generation unit utilized for generating the first and second path main control signals and adjusting the first and second path main control signals according to connection status of power sources and the electronic device. When the first power source is coupled to the electronic device, the control signal generation unit asserts the first path main control signal to enable the first charging path and disable the second charging path.

Classes IPC  ?

• H02J 1/08 - Systèmes à trois filsSystèmes ayant plus de trois fils
• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries

Abrégé

A transistor-cascaded circuit is provided. The transistor-cascaded circuit includes a first transistor, a second transistor, a level shifter and an alternating current (AC) signal enhancement circuit. The level shifter is configured to receive a first input signal of a pair of differential input signals and shift the first input signal to a shifted bias voltage level, in order to generate a shifted input signal to at least one of a gate terminal of the first transistor and a gate terminal of the second transistor. In addition, the AC signal enhancement circuit is configured to enhance an AC signal of the shifted input signal according to a voltage difference between the first input signal and a second input signal of the pair of differential input signals. More particularly, one of the first transistor and the second transistor is an N-type transistor, and the other one is a P-type transistor.

Classes IPC  ?

• H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
• H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface

Abrégé

A voltage calibration circuit arranged in a chip and comprising a voltage monitor circuit, a calibration circuit and a storage circuit is provided. The voltage monitor circuit is coupled to at least one power management unit of the chip and configured to: calculate a voltage-code graph based on a received reference voltage and a received divided voltage; and output at least one output code based on the voltage-code graph and at least one output voltage received from the power management unit(s). The calibration circuit is coupled to the voltage monitor circuit and the power management unit(s), and configured to receive the output code(s) and adjust an output level of the power management unit(s) based on the output code(s) and a target code. The storage circuit is coupled to the calibration circuit, and configured to store the voltage-code graph and the output level of the power management unit(s).

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
• G01R 17/02 - Dispositions dans lesquelles la valeur à mesurer est automatiquement comparée à une valeur de référence

Abrégé

A method for processing audio data and an audio data processing system are provided. The method is operated between a transmitter and a receiver. The transmitter receives audio data, and forms a data set that includes multiple data points. The data points are rearranged in an interlaced manner, and are packetized to form multiple groups of network packets. The network packets are assigned with sequence-identifiable numbers according to a formation sequence. Further, delays can be added in between different groups of the network packets, and then the network packets are rearranged. The multiple groups of the network packets are transmitted to the receiver after data rearrangement, packetization, and packet rearrangement. The receiver then de-packetizes the network packets, and performs data recovery with error handling, so as to generate output audio data.

Classes IPC  ?

• H04L 49/55 - Prévention, détection ou correction des erreurs
• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
• H04L 49/9057 - Dispositions facilitant le réassemblage ou le reséquençage des paquets

Abrégé

A display device includes at least one video connection terminal, a display screen, a memory, and a processing circuit. The video connection terminal is arranged to receive at least one video source from at least one device. The display screen is arranged to display at least one divided frame corresponding to the device on an original frame corresponding to the display device. The memory is arranged to store a program code. The processing circuit is arranged to read and execute the program code from the memory, in order to share resources in the divided frame between the display device and the device according to a user input.

Classes IPC  ?

• G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
• G06F 3/14 - Sortie numérique vers un dispositif de visualisation
• G06F 9/54 - Communication interprogramme

Abrégé

A method of using optimized pitch for installing a processing circuit at a printed circuit board (PCB) and associated apparatus are provided. The method may include: providing a set of first terminals on a predetermined surface of a package of the processing circuit, the set of first terminals corresponding to a set of first pads within a first sub-region of a predetermined installation region of the PCB, where a first pitch of the set of first terminals along a predetermined direction is equal to a first predetermined value; and providing a set of second terminals on the predetermined surface of the package of the processing circuit, the set of second terminals corresponding to a set of second pads within a second sub-region of the predetermined installation region, where a second pitch of the set of second terminals along the predetermined direction is equal to a second predetermined value.

Classes IPC  ?

• H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés

Abrégé

A semiconductor capacitor structure includes a part on a routing-direction-non-turnable metal layer and a part on a routing-direction-turnable metal layer. The semiconductor capacitor structure includes: a first electrode unit layout located on the routing-direction-non-turnable metal layer, wherein all metal traces of the first electrode unit layout are parallel to a first direction; a second electrode unit layout located on the routing-direction-turnable metal layer, wherein each of a first potential part and a second potential part of the second electrode unit layout includes metal lines parallel to the first direction and metal lines parallel to a second direction; and a dielectric located between the first and the second potential parts of the second electrode unit layout, wherein at least a part of the metal traces of the first electrode unit layout is coupled to the first potential part of the second electrode unit layout through at least one via.

Classes IPC  ?

• H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel

Abrégé

A wireless communication device includes a buffer memory and a media access control (MAC) circuit. The MAC circuit is coupled to the buffer memory, and is configured to divide the buffer memory according to system information messages required by the wireless communication device, such that the buffer memory includes hybrid automatic repeat request (HARQ) buffer blocks, and assign HARQ processes for the system information messages required by the wireless communication device, so as to receive the system information message in parallel from a base station in a Narrowband Internet of Things (NB-IoT) downlink scheduling period, in which the HARQ processes respectively correspond to the HARQ buffer blocks.

Classes IPC  ?

• H04L 1/1812 - Protocoles hybridesDemande de retransmission automatique hybride [HARQ]
• H04W 72/1273 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux de flux de données en liaison descendante

Abrégé

A fingerprint data processing method is used for a wireless communication system including a host device and a wireless device, which communicate through a wireless communication interface. The method includes steps of: generating, by the host device, a fingerprint recognition command; driving, by the host device, a first wireless communication circuit to transmit a fingerprint recognition request to the wireless device through the wireless communication interface according to the fingerprint recognition command; receiving, by the wireless device, the fingerprint recognition request through the wireless communication interface, and obtaining, by the wireless device, fingerprint data according to the fingerprint recognition request; driving, by the wireless device, a second wireless communication circuit to transmit the fingerprint data to the host device through the wireless communication interface. The wireless communication interface forwards at least one of the fingerprint recognition request and the fingerprint data using an encrypted communication protocol.

Classes IPC  ?

• G06V 40/50 - Traitement de données biométriques ou leur maintenance
• G06V 10/74 - Appariement de motifs d’image ou de vidéoMesures de proximité dans les espaces de caractéristiques
• G06V 10/94 - Architectures logicielles ou matérielles spécialement adaptées à la compréhension d’images ou de vidéos
• G06V 40/12 - Empreintes digitales ou palmaires
• H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
• H04W 12/03 - Protection de la confidentialité, p. ex. par chiffrement
• H04W 12/06 - Authentification

Abrégé

A method and a system for automated speaker enrollment are provided. In the method, a camera is used to capture image data so that a facial position of a person can be recognized, a microphone array is used to generate speech data, and a sound localization technology is used to estimate a sound source direction. A target speaker can be determined by matching the facial position and the direction toward the sound source, and more particularly whether the target speaker is within a valid geometric range. After that, the speech produced by the target speaker along a target speaker direction is recorded, and the speech can be enhanced for generating speaker features with respect to the target speaker for enrolling to a specific system.

Classes IPC  ?

• G10L 17/04 - Entraînement, enrôlement ou construction de modèle
• G06T 7/521 - Récupération de la profondeur ou de la forme à partir de la télémétrie laser, p. ex. par interférométrieRécupération de la profondeur ou de la forme à partir de la projection de lumière structurée
• G06T 7/55 - Récupération de la profondeur ou de la forme à partir de plusieurs images
• G06T 7/70 - Détermination de la position ou de l'orientation des objets ou des caméras
• G06V 40/16 - Visages humains, p. ex. parties du visage, croquis ou expressions
• G10L 17/02 - Opérations de prétraitement, p. ex. sélection de segmentReprésentation ou modélisation de motifs, p. ex. fondée sur l’analyse linéaire discriminante [LDA] ou les composantes principalesSélection ou extraction des caractéristiques
• G10L 17/18 - Réseaux neuronaux artificielsApproches connexionnistes
• G10L 25/78 - Détection de la présence ou de l’absence de signaux de voix
• G10L 25/90 - Détermination de la hauteur tonale des signaux de parole

Abrégé

A wireless communication device includes a communication module and a processor. The communication module is configured to perform radio frequency signal transmissions and receptions. The processor is coupled to the communication module and is configured to perform the following operations: performing a channel sounding procedure with another wireless communication device and receiving a channel quality indicator (CQI) feedback of 26-tone resources units in a resource unit (RU) structure from the another wireless communication device through the communication module; and performing an RU allocation on the another wireless communication device according to average signal-to-noise ratios (SNRs) in the CQI feedback, including determining a selected RU, a modulation and coding scheme (MCS) index, and a number of spatial streams for being allocated to the another wireless communication device.

Classes IPC  ?

• H04W 72/542 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant la qualité mesurée ou perçue
• H04W 72/04 - Affectation de ressources sans fil

Abrégé

A WiFi radar communication circuit includes a radio frequency front-end circuit, an analog-to-digital converter, and a digital signal processor. The radio frequency front-end circuit is coupled to a transmitting antenna and a receiving antenna for transmitting a radar frame and receiving reflected echoes. The analog-to-digital converter is configured to convert the reflected echoes into radar echo digital signals. The digital signal processor is configured to operate an interference detector. The interference detector is configured to determine whether each reflected chirp among the reflected chirps is subject to interference based on a cumulative power difference between adjacent reflected chirps. The interference detector is further configured to determine whether the radar frame is subject to interference based on a statistical result of whether the reflected chirps are subject to interference. Accordingly, interference detection results for the radar frame and the reflected chirps are generated.

Classes IPC  ?

• G01S 7/35 - Détails de systèmes non impulsionnels
• G01S 7/40 - Moyens de contrôle ou d'étalonnage

Abrégé

A WiFi radar control method includes following steps. In a first radar transceiving slot, first radar frames are sequentially transmitted, and first reflections corresponding to the first radar frames are received. Waveforms of the first reflections are analyzed to determine whether the first radar frames are subject to interference. When interference is detected in the first radar frames, a retry count is incremented. When the retry count is not zero, at least one retry radar frame is transmitted in the first radar transceiving slot or in a second radar transceiving slot following the first radar transceiving slot.

Classes IPC  ?

• G01S 13/02 - Systèmes utilisant la réflexion d'ondes radio, p. ex. systèmes du type radar primaireSystèmes analogues
• G01S 13/90 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour la cartographie ou la représentation utilisant des techniques d'antenne synthétique

Abrégé

A multi-instance single loop topology adjustment method and network switch are provided. The single loop networks of each instance have distinct back-up ports, defaulted to a blocking state. Thus, when abnormalities occur in a link of the single loop network, the topology of each instance is adjusted by changing the back-up ports of each instance to a forwarding state.

Classes IPC  ?

• H04L 41/12 - Découverte ou gestion des topologies de réseau
• H04L 41/0654 - Gestion des fautes, des événements, des alarmes ou des notifications en utilisant la reprise sur incident de réseau

Abrégé

A calculation device and a calculation method are provided. The calculation method includes: selecting, by a selection unit, at least one first element from a one-axis tensor which satisfies a selection condition; selecting and loading, by a control unit, at least one second element from a two-axis tensor based on an operation between the two-axis tensor and the one-axis tensor and at least one position of the at least one first element in the one-axis tensor; and obtaining and outputting, by a calculation unit, an operation result corresponding to the operation between the two-axis tensor and the one-axis tensor based on the at least one first element and the at least one second element.

Classes IPC  ?

• G06F 17/16 - Calcul de matrice ou de vecteur

Abrégé

A bandgap voltage reference circuit comprises a current mirror circuit, a first sub-circuit and an output circuit. The current mirror circuit is coupled between an input source and a ground, is configured to generate a first current, and comprises first and second bipolar junction transistors (BJTs) and a first resistor. The two BJTs' bases are coupled together. The first resistor is coupled between the first BJT's emitter and the ground. The first sub-circuit comprises a transistor coupled to the first BJT's base and collector, comprises a second resistor coupled between the transistor and the ground, and is configured to generate a second current based on the second resistor and a base-emitter potential difference of the second BJT. The output circuit is coupled between the input source and the ground, and is configured to generate an output reference voltage based on the first, second currents and a third resistor.

Classes IPC  ?

• G05F 3/22 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor dans lesquelles les transistors sont uniquement du type bipolaire
• G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu

Abrégé

The present disclosure discloses an oscillating circuit having a temperature compensation mechanism. A NAND gate receives an input signal transiting from a low state level to a maintaining high state to initialize an oscillating behavior and a delayed control signal to generate an output oscillating signal. A first inverter having a negative temperature coefficient resistance inverts the output oscillating signal to generate an inverted output oscillating signal to be received and delayed by a RC delay circuit, including an oscillating resistor having a positive temperature coefficient resistance and an oscillating capacitor to generate a delayed and inverted control signal. A second inverter inverts the delayed and inverted control signal to generate a delayed control signal. A third inverter inverts the output oscillating signal to generate a final oscillating signal. The negative temperature coefficient resistance and the positive temperature coefficient resistance together determine an oscillating circuit temperature coefficient.

Classes IPC  ?

• H03K 5/134 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard avec des transistors à effet de champ
• H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe

Abrégé

An audio system control method, comprising: (a) establishing an OOB wireless communication channel between a first audio playing device and a second audio playing device; (b) computing a first time difference between a current time point and a first expected playing time point, when the first audio playing is ready to play the audio data; (c) sending a ready notification to the second audio playing device through the OOB wireless communication channel if the current time point is before the first expected playing time point; (d) sending a start playing notification to notify the first audio playing device to start playing, if the second audio playing device has received the ready notification, has received the audio data output by the audio source device and is ready to play the audio data; and (e) playing the audio data after the first audio playing device receiving the start playing notification.

Classes IPC  ?

• H04R 3/12 - Circuits pour transducteurs pour distribuer des signaux à plusieurs haut-parleurs

Abrégé

A multi-instance single loop topology adjustment method and network switch are provided. The single loop networks of each instance have distinct back-up ports, defaulted to a blocking state. Thus, when abnormalities occur in a link of the single loop network, the topology of each instance is adjusted by changing the back-up ports of each instance to a forwarding state.

Classes IPC  ?

• H04L 41/12 - Découverte ou gestion des topologies de réseau
• H04L 41/0654 - Gestion des fautes, des événements, des alarmes ou des notifications en utilisant la reprise sur incident de réseau

Abrégé

A multi-link device includes a multi-link controller, and first and second MAC controllers. The first MAC controller includes a first link queue to buffer a first set of packets from the common queue. The second MAC controller includes a second link queue to buffer a second set of packets from the common queue. In response to the first MAC controller being granted a first transmission opportunity of a first link, and the second MAC controller not being granted a second transmission opportunity of a second link, the multi-link controller determines whether to enable a link redirect mode according to an aspect of the second set of packets. In response to the link redirect mode being enabled, the first MAC controller receives a packet in the second set of packets from the second link queue, and transmits the packet in the second set of packets via the first link.

Classes IPC  ?

• H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
• H04W 48/02 - Restriction d'accès effectuée dans des conditions spécifiques
• H04W 88/12 - Dispositifs contrôleurs de points d'accès

Abrégé

A deep learning accelerator includes a controller circuit, a processing elements (PE) array circuit, and a memory access circuit. The controller circuit generates a control signal according to traffic data. The PE array circuit operates a neural network model. A layer computation of the neural network model includes first and second paths, and the PE array circuit selects a path from the first and second paths according to the control signal to execute the layer computation via the selected path. The PE array circuit accesses a memory circuit via the memory access circuit to execute the layer computation. When the layer computation is executed via the first path, the PE array circuit accesses the memory circuit with first bandwidth. When the layer computation is executed via the second path, the PE array circuit accesses the memory circuit with second bandwidth. The first bandwidth is higher than the second bandwidth.

Classes IPC  ?

• G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

Abrégé

The present disclosure an electronic apparatus having firmware overlay mechanism. A shared section of firmware and a first version section of the firmware corresponding to the first version firmware are retrieved from a firmware storage terminal to a memory circuit of a memory by a processing circuit. An address redirection process is performed on the first version firmware by an address decoding circuit of the memory to redirect first access addresses to physical addresses of the memory circuit. The first version firmware is executed through the address decoding circuit. A firmware version switching process is performed to retrieve a second version section of the firmware corresponding to the second version firmware to the memory circuit. The address re-defined process is performed on the second version firmware to redirect second access addresses to the physical addresses of the memory circuit. The second version firmware is executed through the address decoding circuit.

Classes IPC  ?

• G06F 8/71 - Gestion de versions Gestion de configuration
• G06F 9/32 - Formation de l'adresse de l'instruction suivante, p. ex. par incrémentation du compteur ordinal
• G06F 11/362 - Débogage de logiciel

Abrégé

An integrated transformer, substantially symmetrical about an axis of symmetry, having first to fourth terminals and including primary and secondary coils and first and second crossing structures. The primary coil, whose two terminals are the first and second terminals, includes a first trace. The secondary coil, whose two terminals are the third and fourth terminals, includes a second trace and a third trace. The first crossing structure is formed by the second trace and a first portion of the first trace. The second crossing structure is formed by the third trace and a second portion of the first trace. The first and second terminals are on two sides of the axis of symmetry. The third and fourth terminals are on two sides of the axis of symmetry. The first and second crossing structures are substantially symmetrical about the axis of symmetry.

Classes IPC  ?

• H01F 27/28 - BobinesEnroulementsConnexions conductrices
• H01F 19/00 - Transformateurs fixes ou inductances mutuelles fixes du type pour signaux
• H03H 7/42 - Réseaux permettant de transformer des signaux équilibrés en signaux non équilibrés et réciproquement, p. ex. baluns

Abrégé

A method for intelligent posture detection, an intelligent posture detection apparatus, and a circuit system are provided. The circuit system is disposed in the intelligent posture detection apparatus, and the method is performed in the circuit system. In the method, the circuit system retrieves an image from an image-retrieval circuit, and operates an intelligence model by an operating circuit for determining an object window that covers an object in the image and multiple key points of the object. Next, a first correlation among a whole or part of the key points of a current posture of the object, and a second correlation between the object window and the whole or part of the key points are established. The first correlation, the second correlation, and/or geometric information of the object window can be referred to for determining whether or not the current posture of the object is poor.

Classes IPC  ?

• G06T 7/73 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés basés sur les caractéristiques
• G06V 10/44 - Extraction de caractéristiques locales par analyse des parties du motif, p. ex. par détection d’arêtes, de contours, de boucles, d’angles, de barres ou d’intersectionsAnalyse de connectivité, p. ex. de composantes connectées
• G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo

Abrégé

A video super resolution system includes a motion estimation device, a warping device, and a neural network super resolution (NNSR) device. The motion estimation device calculates an optical flow according to a current frame and a previous frame. The warping device executes a warping process to the previous frame and a previous output to generate a warping frame and a warping output. The NNSR device executes a feature extraction to the current frame, the warping frame, the warping output, and a count value to generate at least one feature, executes a deep learning process to the at least one feature and a previous hidden state to generate a current hidden state and a deep learning result, and executes the feature extraction to the deep learning result to generate a current output. The NNSR device stores the current frame, the current hidden state, and the current output to a memory.

Classes IPC  ?

• G06T 3/4046 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement utilisant des réseaux neuronaux
• G06T 3/18 - Déformation d’images, p. ex. réarrangement de pixels individuellement
• G06T 3/4053 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement basé sur la super-résolution, c.-à-d. où la résolution de l’image obtenue est plus élevée que la résolution du capteur
• G06T 7/269 - Analyse du mouvement utilisant des procédés basé sur le gradient

Abrégé

The present invention provides an impedance calibration method of a RF transmitter, wherein the impedance calibration method includes the steps of: (a) generating a two-tone test signal to the RF transmitter to generate a RF signal; (b) calculating a IMD3 according to the RF signal; (c) calculating a IMD3 difference between the IMD3 and a default IMD3; and (d) if the IMD3 difference is not less than a threshold value, tuning an impedance of the RF transmitter, and repeating step (b) and step (c), until the IMD3 difference is less than the threshold value.

Classes IPC  ?

• H04B 17/13 - SurveillanceTests d’émetteurs pour l’étalonnage d’amplificateurs de puissance, p. ex. de gain ou de non-linéarité
• H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie

Abrégé

An operation method of a router which switches between a first network and a second network includes the following steps: advertising a packet including a network duration and a network switching period. The network duration represents a first duration for which the router continuously operates in the first network. The network switching period is substantially equal to the first duration plus a second duration for which the router continuously operates in the second network.

Classes IPC  ?

• H04L 45/02 - Mise à jour ou découverte de topologie
• H04L 45/122 - Évaluation de la route la plus courte en minimisant les distances, p. ex. en sélectionnant une route avec un nombre minimal de sauts

Abrégé

A signal conflict detecting method, which comprises: (a) the signal transceiving device performing a first detecting operation to detect whether a signal conflict may occur in a target frequency band; (b) the signal transceiving device transmitting a target signal if the signal conflict will not occur in the target frequency band; (c) the signal transceiving device performing a second detecting operation to detect whether the signal conflict may occur in the target frequency band, after transmitting the target signal in the step (b); (d) the signal transceiving device performing a third detecting operation to detect whether the signal conflict may occur in the target frequency band, if the step (c) determines that the signal conflict may occur in the target frequency band; and (e) the signal transceiving device retransmitting the target signal if the step (d) determines that the signal conflict will not occur in the target frequency band.

Classes IPC  ?

• G01S 7/02 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe

Abrégé

An electrical connector for reducing electromagnetic interference (EMI) and an associated wireless communication device are provided. The electrical connector includes multiple metal terminals, a plastic component, a wave absorbing material and a metal shell. The multiple metal terminals are configured to transmit at least one pair of differential signals from a host device to a wireless communication circuit via a printed circuit board (PCB). The plastic component is configured to fix positions of the multiple metal terminals in the electrical connector. The wave absorbing material is configured to absorb an electromagnetic wave signal sent from the multiple metal terminals. The metal shell is configured to cover the multiple metal terminals, the plastic component and the wave absorbing material. More particularly, the wave absorbing material overlaps at least a portion of the plastic component.

Classes IPC  ?

• H01R 12/71 - Dispositifs de couplage pour circuits imprimés rigides ou structures similaires
• H01R 4/02 - Connexions soudées ou brasées
• H01R 13/6461 - Moyens pour empêcher la diaphonie
• H01R 13/6581 - Structure du blindage

Abrégé

A phase interpolation circuit for generating a phase interpolation signal, comprising: a capacitor; a first charging circuit for selectively charging the capacitor according to a first clock signal and a first weighting control code; a second charging circuit for selectively charging the capacitor according to a second clock signal and a second weighting control code; a first discharge circuit for selectively discharging the capacitor according to the first clock signal and a third weighting control code; and a second discharge circuit for selectively discharging the capacitor according to the second clock signal and a fourth weighting control code. The first, second, third and fourth weighting control codes respectively control the weightings of the first clock signal and the second clock signal in the phase interpolation signal.

Classes IPC  ?

• H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
• H03K 5/08 - Mise en forme d'impulsions par limitation, par application d'un seuil, par découpage, c.-à-d. par application combinée d'une limitation et d'un seuil

Abrégé

A method and a packet detector for detecting a target detection packet are provided. The method includes: utilizing a match filter of the packet detector to perform match filtering on an input signal based on a reference sequence in order to generate a match filtering output, where the reference sequence corresponds to the target detection packet; utilizing a post-calculation circuit of the packet detector to perform calculation on the match filtering output to generate a calculation result; utilizing a comparator of the packet detector to compare the calculation result with a predetermine threshold to generate a comparison result; and determining whether the input signal is the target detection packet or not according to the comparison result.

Classes IPC  ?

• H04L 43/16 - Surveillance de seuil
• H04L 27/26 - Systèmes utilisant des codes à fréquences multiples

Abrégé

A package structure includes a first substrate, a die, a molding layer, a second substrate, vias, and a heat-dissipation layer. The first substrate has first lower contacts on its lower surface, and the first substrate has first upper contacts on its upper surface and electrically connected to the first lower contacts. A die is electrically connected to the first upper contacts. The molding layer laterally encapsulates the die. The second substrate on the molding layer has second upper contacts on its upper surface, and the second substrate has second lower contacts on its lower surface and electrically connected to the second upper contacts. Each of the vias is in the molding layer to electrically connect the first upper contacts and the second lower contacts. The heat-dissipation layer is on the die. The upper surface of the second substrate is higher or lower than an upper surface of the heat-dissipation layer.

Classes IPC  ?

• H01L 23/367 - Refroidissement facilité par la forme du dispositif
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
• H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides

Abrégé

A WPT circuit is provided. The WPT circuit includes a radio frequency (RF) front-end circuit, a power path circuit, an auxiliary path circuit, a control circuit and a switch circuit. The RF front-end circuit is configured to convert a single-end input signal received by an antenna into differential input signals. The power path circuit is configured to convert the differential input signals into a direct current (DC) output voltage. The auxiliary path circuit is configured to convert the differential input signals into a DC supply voltage. The control circuit is configured to utilize the DC supply voltage as a power source and generate a control signal according to the DC output voltage. The switch circuit is configured to determine whether to conduct the DC output voltage to the energy storage element according to the control signal.

Classes IPC  ?

• H02J 50/20 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant des micro-ondes ou des ondes radio fréquence
• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
• H02J 7/34 - Fonctionnement en parallèle, dans des réseaux, de batteries avec d'autres sources à courant continu, p. ex. batterie tampon
• H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
• H02M 1/00 - Détails d'appareils pour transformation
• H02M 1/44 - Circuits ou dispositions pour corriger les interférences électromagnétiques dans les convertisseurs ou les onduleurs

Abrégé

A voltage detection circuit is provided. A first and a second detection inverters of a detection circuit outputs an inverted detection signal and an output detection signal to a first and a second detection output terminals. A feedback detection circuit outputs an inverted feedback detection signal. A first transistor is coupled between the first detection output terminal and a ground terminal. A second transistor is coupled between the second detection output terminal and a first gate. A second gate is controlled by the inverted feedback detection signal. A third transistor is coupled between the first gate and the ground terminal. A third gate is controlled by the inverted feedback detection signal. The detection signal at a high state makes the inverted feedback detection signal turn on the second transistor and turn off the third transistor such that the first transistor turns on.

Classes IPC  ?

• H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].

Abrégé

A voice scoring system is configured to be computed through a processing unit to execute: transforming an audiovisual audio of an audiovisual data and a user audio into a spectral intensity of the audiovisual data and a spectral intensity of the user audio respectively through a transformation module; separating the spectral intensity of the audiovisual audio into a spectral intensity of an accompaniment audio and a spectral intensity of a singer audio through an audio separation module; analyzing the spectral intensity of the singer audio and the spectral intensity of the user audio to obtain a singer pitch and a user pitch through a pitch analysis module; and in real time comparing whether the user pitch is close to the singer pitch to calculate a user score through the score calculation module. A karaoke device having the voice scoring system is also provided.

Classes IPC  ?

• G10H 1/00 - Éléments d'instruments de musique électrophoniques
• G09B 15/00 - Enseignement de la musique
• G10H 1/36 - Dispositions pour l'accompagnement
• G10L 21/0308 - Séparation du signal de voix caractérisée par le type de mesure du paramètre, p. ex. techniques de corrélation, techniques de passage par zéro ou techniques prédictives
• G10L 25/18 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par le type de paramètres extraits les paramètres extraits étant l’information spectrale de chaque sous-bande
• G10L 25/30 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par la technique d’analyse utilisant des réseaux neuronaux

Abrégé

A communication device includes a transmitting circuit, for transmitting at least one first packet to other communication device in at least one first interval, and for transmitting at least one of at least one first channel reservation signal and at least one second channel reservation signal to the another communication device in the at least one first interval; and a receiving circuit, for receiving at least one second packet from the other communication device in at least one second interval; wherein the at least one first interval and the at least one second interval are staggered and do not overlap with each other.

Classes IPC  ?

• H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
• H04W 28/26 - Réservation de ressources
• H04W 74/08 - Accès non planifié, p. ex. ALOHA

Abrégé

An electronic device includes a first functional circuit, a second functional circuit, a memory, and a clock asynchronous processor. The first functional circuit operates at a first clock and generates a read command. The second functional circuit operates at a second clock. The memory is coupled to the first functional circuit and the second functional circuit. The clock asynchronous processor is coupled to the first functional circuit and the memory and configured to check, according to the first clock and the second clock, whether the read command exists. When the read command exists, the clock asynchronous processor provides the read command to the memory.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

The present invention discloses a chipset apparatus communication method that includes steps outlined below. A processor connection terminal having a total bandwidth is coupled to a processor. External apparatus connection terminals are coupled to external apparatuses. Individual packet transmission amounts and a total packet transmission amount of the external apparatus connection terminals between a first time point and a second time point are calculated, in which the external apparatus connection terminals have original bandwidth proportions. Amount ratios each between one of the individual packet transmission amounts and the total packet transmission amount are calculated. Weighting calculation is performed on the original bandwidth proportions and the amount ratios to generate un-normalized updated bandwidth proportions to be normalized to generate updated bandwidth proportions corresponding to the second time point. The total bandwidth is distributed according to the updated bandwidth proportions such that the external apparatus performs data transmission accordingly.

Classes IPC  ?

• G06F 13/38 - Transfert d'informations, p. ex. sur un bus

Abrégé

A wireless transceiver device includes a communication module and a processor. The processor is used for performing the following operations: determining whether to perform an active spatial reuse transmission when detecting an overlapping basic service set packet; entering a backoff phase when determining that the active spatial reuse transmission is to be performed; pausing the backoff phase when detecting a data packet of which a destination is the wireless transceiver device before the backoff phase ends, and receiving the data packet; determining a lower one of a minimum transmission power of a response frame in response to the data packet and an active transmission power corresponding to the wireless transceiver device as a passive transmission power of the response frame; and transmitting the response frame with the passive transmission power in a short inter-frame space after the data packet is received.

Classes IPC  ?

• H04W 74/0833 - Procédures d’accès aléatoire, p. ex. avec accès en 4 étapes
• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
• H04W 52/36 - Commande de puissance d'émission [TPC Transmission power control] utilisant les limitations de la quantité totale de puissance d'émission disponible avec une plage ou un ensemble discrets de valeurs, p. ex. incrément, variation graduelle ou décalages

Abrégé

A non-volatile memory device includes a non-volatile memory, a random number generator, a power supply, and a memory access controller. The non-volatile memory is configured to store at least one data. The random number generator is configured to generate a random number. The power supply is configured to generate a random power according to the random number, and provide the random power to the non-volatile memory. The memory access controller is configured to generate a random sequence according to the random number, obtain a random sequence data from the non-volatile memory according to the random sequence, and reconstruct the random sequence data according to the random sequence to generate the at least one data.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably couple with an MDI circuit to conduct data communication with a respondent-side circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit, and arranged to operably generate an echo cancellation signal.

Classes IPC  ?

• H04B 3/23 - Réduction des effets d'échos ou de sifflementSystèmes à ligne de transmission Détails ouverture ou fermeture de la voie d'émissionCommande de la transmission dans une direction ou l'autre utilisant une reproduction du signal transmis décalée dans le temps, p. ex. par dispositif d'annulation
• H04B 1/40 - Circuits

Abrégé

A method for operating a card reader is provided. The card reader is part of an electronic device. The method includes the following steps: executing a plurality of pieces of code or program instructions to detect a state of the electronic device; and controlling the card reader to operate in a target power-saving mode according to the state.

Classes IPC  ?

• G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
• G06F 1/3212 - Surveillance du niveau de charge de la batterie, p. ex. un mode d’économie d’énergie étant activé lorsque la tension de la batterie descend sous un certain niveau
• G06F 1/3218 - Surveillance de dispositifs périphériques de dispositifs d’affichage
• G06F 1/3296 - Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement

Abrégé

An electronic device and a clock jitter analysis method are provided. The electronic device includes a storage device and a processing device. The processing device is configured to: read timing simulation information and voltage drop information of a plurality of clock paths from the storage device; obtain a maximum voltage drop and a minimum voltage drop of each clock path based on the voltage drop information; perform a first static timing analysis (STA) with the maximum voltage drop based on the timing simulation information, to obtain a first timing report; perform a second STA with the minimum voltage drop based on the timing simulation information, to obtain a second timing report; calculate time information corresponding to each clock path based on the first timing report and the second timing report; and select largest time information of the plurality of pieces of time information as a clock jitter.

Classes IPC  ?

• G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci

Abrégé

A media access control address table updating device is provided. The device includes a processor, a storage, a learning controller, a packet generator, and a traffic manager. The traffic manager determines whether to generate a first back pressure signal based on a current traffic corresponding to a plurality of queues. In response to determining that the first back-pressure signal is generated, the traffic manager transmits the first back-pressure signal to the packet generator. In response to receiving the first back pressure signal from the traffic manager, the packet generator stops generating a notification packet corresponding to a notification event.

Classes IPC  ?

• H04L 47/30 - Commande de fluxCommande de la congestion en combinaison avec des informations sur l'occupation de mémoires tampon à chaque extrémité ou aux nœuds de transit
• H04L 47/12 - Prévention de la congestionRécupération de la congestion
• H04L 69/324 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche liaison de données [couche OSI 2], p. ex. HDLC

Abrégé

The present disclosure discloses an access point communication method having dynamic channel selection mechanism used in an access point apparatus that includes steps outlined below. A wireless communication is performed with a station apparatus through a neighboring relay access point apparatus. Communication parameters related to the wireless communication are collected periodically. A required data flow amount of the station apparatus is calculated according to the communication parameters and available data flow amounts of wireless channels between the access point apparatus and the relay access point apparatus are calculated. Ratios between the required data flow amount and the available data flow amounts are calculated as channel crowding parameters. One of the wireless channels corresponding to one of the channel crowding parameters having a smallest value is selected to be a selected wireless channel to perform packet transmission to the station apparatus through the relay access point apparatus.

Classes IPC  ?

• H04W 28/02 - Gestion du trafic, p. ex. régulation de flux ou d'encombrement
• H04W 88/08 - Dispositifs formant point d'accès

Abrégé

A media docking device includes an input interface controller, an output interface controller, and a processor. The input interface controller is connected to a media source device. The output interface controller is connected to media player devices and obtains device data of each media player device. The processer calculates a display bandwidth required by each media player device to display image based on the device data, and sums the display bandwidths of the media player devices to obtain a total display bandwidth. The processor determines an optimal support mode for connecting a video interface unit of the input interface controller to the media source device based on the total display bandwidth. A transmission bandwidth corresponding to the optimal support mode is greater than the total display bandwidth, and a difference between the transmission bandwidth and the total display bandwidth is less than a threshold.

Classes IPC  ?

• G09G 5/00 - Dispositions ou circuits de commande de l'affichage communs à l'affichage utilisant des tubes à rayons cathodiques et à l'affichage utilisant d'autres moyens de visualisation

Abrégé

An inquirer-side circuit of an automotive Ethernet system includes: a hybrid circuit arranged to operably conduct data communication with a respondent-side circuit through an MDI circuit; a transmitting circuit coupled with a hybrid circuit and arranged to operably generate and provide a transmission signal to the hybrid circuit; a receiving circuit coupled with the hybrid circuit and arranged to operably receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled with the receiving circuit and arranged to operably process the data signal; a physical coding sublayer circuit coupled with the processing circuit and arranged to operably conduct a physical coding operation according to the instruction of the processing circuit to control the operations of the transmitting circuit; and an echo cancellation circuit coupled between the transmitting circuit and the receiving circuit, and arranged to operably generate an echo cancellation signal.

Classes IPC  ?

• H04B 3/23 - Réduction des effets d'échos ou de sifflementSystèmes à ligne de transmission Détails ouverture ou fermeture de la voie d'émissionCommande de la transmission dans une direction ou l'autre utilisant une reproduction du signal transmis décalée dans le temps, p. ex. par dispositif d'annulation
• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

Abrégé

A method for optimizing model operation through weight arrangement and a computing system are provided. The method is operated in an operating device. In the method, a model framework is decided, and a training set is provided according to the model framework for training a model through a learning algorithm. A plurality of weights are computed for the model. The computing system relies on characteristics of the weights to select one of weight-arrangement rules, or a combination of the weight-arrangement rules, so that the locations of all or part of the weights can be re-arranged based on the selected weight-arrangement rule. The re-arranged weights are referred to for designating a corresponding loss function for simplifying the algorithm of the model. An application device can accordingly operate the model.

Classes IPC  ?

• G06N 3/0985 - Optimisation d’hyperparamètresMeta-apprentissageApprendre à apprendre

Abrégé

A memory control circuit includes a plurality of main terminal circuits, a monitoring unit, an arithmetic unit, and a memory controller. The main terminal circuits output a plurality of control commands. The monitoring unit generates an operation record based on each of the control commands. The arithmetic unit includes a recurrent neural network module. The arithmetic unit generates a corresponding first feature vector based on the operation record and generates a plurality of second feature vectors based on the first feature vectors corresponding to a plurality of candidate combinations. The recurrent neural network module obtains estimated efficiency information based on the second feature vectors and selects a candidate combination corresponding to one piece of the estimated efficiency information as a selected main terminal combination. The memory controller is configured to execute the control command corresponding to each main terminal circuit in the selected main terminal combination for a memory.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

An onlooker detection system and an onlooker detection method are provided. The onlooker detection system includes: a person detection module, configured to receive an image, and obtain, in response to presence of persons in the image, person information of each person, where the person information includes distance information relative to a device; and an onlooker determination module, configured to: determine whether the persons include at least one non-user present in a range based on the distance information of the person information of each person; and determine, in response to presence of the at least one non-user in the range, a security classification to which each non-user belongs based on the person information of each non-user, where the security classification includes an onlooker category.

Classes IPC  ?

• G06V 40/16 - Visages humains, p. ex. parties du visage, croquis ou expressions
• G06F 21/60 - Protection de données
• G06T 7/73 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés basés sur les caractéristiques
• G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux

Abrégé

An image processing method includes: training a first neural network model configured to execute a first image processing, according to multiple training data, to generate multiple first parameters associated with the first neural network model, in which the multiple first parameters includes multiple weights; training a second neural network model configured to execute a second image processing, which is different from the first image processing, according to the multiple training data and the multiple weights, to generate multiple second parameters associated with the second neural network model; and mixing the multiple first parameters with the multiple second parameters, to generate multiple blending parameters for a blending neural network model, in which the blending neural network model is configured to execute the first image processing and the second image processing on an input image, to output an optimized image.

Classes IPC  ?

• G06T 5/60 - Amélioration ou restauration d'image utilisant l’apprentissage automatique, p. ex. les réseaux neuronaux

Abrégé

An audio processing system and an audio processing method are provided. The audio processing system includes a receiving circuit and a processing circuit. The receiving circuit is configured to adjust original extended display capability identification data for generating optimized extended display capability identification data. The audio source device reads the optimized extended display capability identification data. The audio source device responds to the receiving circuit with a first multi-channel signal according to the optimized extended display capability identification data, and a quantity of sound channels of the first multi-channel signal is greater than a maximum quantity of sound channels supported by the audio processing system. The processing circuit is configured to convert the first multi-channel signal into a second multi-channel signal, and a quantity of sound channels of the second multi-channel signal is different from that of the first multi-channel signal.

Classes IPC  ?

• H04S 7/00 - Dispositions pour l'indicationDispositions pour la commande, p. ex. pour la commande de l'équilibrage
• H04S 3/00 - Systèmes utilisant plus de deux canaux, p. ex. systèmes quadriphoniques

Abrégé

A method, a mesh network controller and a topology center device for performing channel allocation in a mesh network are provided. The method includes: utilizing the mesh network controller to send a channel scan request to multiple mesh network agent devices; utilizing the multiple mesh network agent devices to detect wireless communication information in response to the channel scan request in order to generate multiple channel scan reports, respectively; utilizing the mesh network controller to receive the multiple channel scan reports from the multiple mesh network agent devices, respectively; and utilizing the mesh network controller to send corresponding channel selection requests to the multiple mesh network agent devices according to the multiple channel scan reports, in order to make the multiple mesh network agent devices select corresponding wireless communication channels according to the corresponding channel selection requests, respectively.

Classes IPC  ?

• H04W 72/542 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant la qualité mesurée ou perçue
• H04W 72/04 - Affectation de ressources sans fil
• H04W 84/18 - Réseaux auto-organisés, p. ex. réseaux ad hoc ou réseaux de détection

Abrégé

An inductor device including a first ring-type structure, a second ring-type structure, and a third ring-type structure is disclosed. The second ring-type structure is coupled to the first ring-type structure and formed an 8-shaped loop with the first ring-type structure. The third ring-type structure is coupled to the second ring-type structure. The first ring-type structure and the second ring-type structure are located at an area surrounded by the third ring-type structure.

Classes IPC  ?

• H01F 27/29 - BornesAménagements de prises
• H01F 27/40 - Association structurelle de composants électriques incorporés, p. ex. fusibles

Abrégé

The present application discloses a speech enhancement device. The speech enhancement device includes an audio input circuit and a processor. The audio input circuit is configured to convert an audio input signal to a first audio data. The processor is configured to: generate a plurality of audio frames according to the first audio data; perform formant analysis on the audio frames to determine whether to combine adjacent audio frames of the audio frames into an audio segment; apply gain processing to the audio segment including the combined audio frames; and combine the audio segment and one or more uncombined audio frames of the audio frames into a second audio data.

Classes IPC  ?

• G10L 21/007 - Changement de la qualité de la voix, p. ex. de la hauteur tonale ou des formants caractérisé par le procédé utilisé
• G10L 25/15 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par le type de paramètres extraits les paramètres extraits étant des informations sur les formants

Abrégé

A low-dropout regulator system includes a low-dropout regulator. A comparator circuit generates a comparison voltage according to a reference voltage and a feedback voltage. An amplifier circuit generates an amplifying voltage according to the comparison voltage. A transistor receives an input voltage and is controlled by the amplifying voltage to generate an output voltage at an output terminal. A first resistor circuit is coupled between a first node and a ground terminal. A second resistor circuit is coupled between the output terminal and the first node. At a start-up timing point of the low-dropout regulator, a resistance value of the second resistor circuit is a first resistance value. After the input voltage reaches a maximum voltage, the resistance value of the second resistor circuit is a second resistance value. The second resistance value is larger than the first resistance value.

Classes IPC  ?

• G05F 1/59 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de réglage final pour une charge unique
• G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
• G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction

Abrégé

The present invention discloses an image decoding method. Error report information related to an error block in an N-th image frame generated according to an inter-frame coding technology is received by an image encoding apparatus when the image decoding apparatus receives a block of an N+P−1-th image frame. The N+P-th image frame is encoded according to the inter-frame coding technology. Blocks in the N-th image frame before the error block are decoded according to the inter-frame coding technology. A panning motion vector of an N−1-th image frame serves as the motion vector information and the residue information is set to be zero to decode the blocks from the error block to the N+P−1-th image frame according to the inter-frame coding technology. The motion vector information and the residue information of the inter-frame coding blocks in the N+P-th image frame are retrieved to perform decoding according to the inter-frame coding technology.

Classes IPC  ?

• H04N 19/44 - Décodeurs spécialement adaptés à cet effet, p. ex. décodeurs vidéo asymétriques par rapport à l’encodeur
• H04N 19/159 - Type de prédiction, p. ex. prédiction intra-trame, inter-trame ou de trame bidirectionnelle
• H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant un bloc, p. ex. un macrobloc
• H04N 19/65 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant la tolérance aux erreurs
• H04N 19/89 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le pré-traitement ou le post-traitement spécialement adaptés pour la compression vidéo mettant en œuvre des procédés ou des dispositions de détection d'erreurs de transmission au niveau du décodeur

Abrégé

The present invention discloses an image decoding method. Error report information related to an error block in an N-th image frame generated according to an inter-frame coding technology is received by an image encoding apparatus at a time spot that the image decoding apparatus receives a corresponding block of an N+P−1-th image frame and an N+P-th image frame is encoded according to an inter-frame coding technology. Blocks in the N-th image frame before the occurrence of the error block are decoded according to the inter-frame coding technology. Motion vector information and residue information are set to be zero to decode the blocks from the error block to the N+P−1-th image frame according to the inter-frame coding technology. The motion vector information and the residue information of the inter-frame coding blocks in the N+P-th image frame are retrieved to decode the blocks therein according to the inter-frame coding technology.

Classes IPC  ?

• H04N 19/00 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques
• H04N 19/159 - Type de prédiction, p. ex. prédiction intra-trame, inter-trame ou de trame bidirectionnelle
• H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant un bloc, p. ex. un macrobloc
• H04N 19/65 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant la tolérance aux erreurs
• H04N 19/89 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le pré-traitement ou le post-traitement spécialement adaptés pour la compression vidéo mettant en œuvre des procédés ou des dispositions de détection d'erreurs de transmission au niveau du décodeur

Abrégé

A display system and a firmware updating method are provided. The display system includes displays connected in series to form a daisy-chain topology. Each of the displays includes firmware, and one of the displays is configured to be a publishing display. The publishing display is configured to execute a publishing program to provide a target version number of the firmware of the publishing display to each of the displays excluding the publishing display through the daisy-chain topology. Each of the displays excluding the publishing display is configured to execute a local program to determine whether or not the firmware needs to be updated based on a current version number of the firmware of the display and the target version number, and, in response to determining that the firmware needs to be updated, the firmware is updated based on a target file content provided by the publishing display.

Classes IPC  ?

• G06F 8/65 - Mises à jour

Abrégé

An amplifying circuit includes a floating inverter amplifier and a voltage generating circuit. A threshold voltage of transistors in the floating inverter amplifier varies corresponding to an environmental condition. The voltage generating circuit is coupled with the floating inverter amplifier. The voltage generating circuit is configured to provide an operating voltage to the floating inverter amplifier. The operating voltage provided by the voltage generating circuit is linearly correlated to the threshold voltage, and the voltage generating circuit modulates a variation of the operating voltage to keep track with a variation of the threshold voltage.

Classes IPC  ?

• G05F 3/26 - Miroirs de courant
• H03F 3/02 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des tubes