According to the present invention, a main semiconductor element (20) and a circuit unit such as a temperature sensing unit (10), for protecting and controlling the main semiconductor element (20), are provided on the same semiconductor substrate (101) having a wide bandgap semiconductor as a material. The temperature sensing unit (10) is a horizontal SBD comprising: an n--type anode region (3) and a n+-type cathode contact region (4) selectively provided between the front surface of the semiconductor substrate (101) and a p-type well region (2); an anode electrode (5) in Schottky contact with the n--type anode region (3); and a cathode electrode (6) in ohmic contact with the n+-type cathode contact region (4). The temperature sensing unit (10) is surrounded by the p-type well region (2) and is electrically separated from the main semiconductor element (20) or another circuit unit. Accordingly, an inexpensive semiconductor device having a plurality of semiconductor elements on the same semiconductor substrate can be provided.
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 64/64 - Électrodes comprenant une barrière de Schottky à un semi-conducteur
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
This semiconductor device comprises a semiconductor substrate having an upper surface. The semiconductor substrate includes: a main transistor part having a main gate trench part including a main gate conductive part; a sense transistor part having a sense gate trench part including a sense gate conductive part; a gate pad provided above the upper surface of the semiconductor substrate; main gate wiring provided above the upper surface of the semiconductor substrate and extending from the gate pad to the main gate conductive part; sense gate wiring disposed along the sense transistor part; and a gate wiring connection part connecting the main gate wiring and the sense gate wiring, wherein a resistance part is provided in the gate wiring connection part.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
A cooler (30): has a heat dissipation base (31) and a plurality of heat dissipation fins (32) that are positioned on the opposite side of the heat dissipation base (31) from a substrate (20); and is attached to a water jacket (110) that is for making cooling water (W) flow through the heat dissipation fins (32). An insulation material (40) integrates: a bottom part (41) that extends in the direction (D) in which the cooling water (W) flows through the heat dissipation fins (32) and is opposite at least a portion of the heat dissipation fins (32); and a side wall (42) that extends from the bottom part (41) toward the heat dissipation base (31) side and is opposite at least a portion of the heat dissipation fins (32).
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
Provided is a semiconductor device comprising a transistor part and a diode part, the semiconductor device comprising a drift region of a first conductivity type, a plurality of trench parts, a base region of a second conductivity type, an emitter region of the first conductivity type and of which the doping concentration is higher than that of the drift region, and a contact region of the second conductivity type and of which the doping concentration is higher than that of the base region, wherein: the plurality of trench parts have a gate trench part; the transistor part has a first transistor region which includes an emitter region and a gate trench part and a second transistor region which includes an emitter region and a gate trench part and which is provided between the first transistor region and the diode part; a first mesa part of the first transistor region has a first region of the first conductivity type; and a second mesa part of the second transistor region has a second region of the first conductivity type and of which the doping concentration is higher than that of the first region.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
5.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
The present invention provides a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device, with which it is possible to prevent uneven formation of Ni silicide and to reduce the contact resistance. In this method for manufacturing a silicon carbide semiconductor device, a silicide layer (18) is formed by: forming a film of Ni or a film of Ni and Ti; subjecting the film to a heat treatment at a temperature of 400°C or more and less than 600° C in an inert gas (group 18) atmosphere; removing the unreacted film; and subjecting the film to a heat treatment at a temperature of less than 1000°C in an inert gas (group 18) atmosphere.
Provided is a semiconductor device in which on-resistance can be further reduced. This semiconductor device comprises a gate electrode, a contact region of a first conductivity type, and a drift layer having a super junction structure. The drift layer has a first stripe pattern in which first column layers of the first conductivity type and second column layers of a second conductivity type extending in a first direction are alternately arranged in a second direction. The gate electrode has a second stripe pattern in which a plurality of trench gates extending in the second direction are arranged in the first direction. The first stripe pattern and the second stripe pattern intersect in plan view. When the period of repetition of the first column layers or the second column layers is regarded as a first period, and the period of repetition of the trench gates is regarded as a second period, the second period is shorter than the first period. The contact region has a higher concentration of the first conductivity type than the first column layers and has a greater second-direction width than the first column layers.
Provided is a semiconductor device in which resin leakage during transfer molding can be prevented, thus preventing poor appearance. This semiconductor device comprises semiconductor chips (8a to 8d), a frame (1) surrounding the semiconductor chips (8a to 8d) and covering the tops of the semiconductor chips (8a to 8d), control terminals (6a to 6l) conductively connected to the semiconductor chips (8a to 8d) and protruding from an upper-surface side of the frame (1), and an encapsulating resin (9) provided on the inside of the frame (1) and encapsulating the semiconductor chips (8a to 8d).
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
Provided is a three-level semiconductor device that can reduce the inductance between a positive electrode terminal and a negative electrode terminal. The present invention comprises an electroconductive plate (11) that is connected to lower surfaces of semiconductor chips (61a–61d), an electroconductive plate (12) that is connected to lower surfaces of semiconductor chips (62a–62d), an electroconductive plate (13) that is connected to lower surfaces of semiconductor chips (63a–63d, 64a–64d), an external terminal (21) that is connected to the electroconductive plate (11), an external terminal (22) that is connected to upper surfaces of the semiconductor chips (62a–62d), an external terminal (23) that is connected to upper surfaces of the semiconductor chips (63a–63d), and an external terminal (24) that is connected to upper surfaces of the semiconductor chips (61a–61d, 64a–64d), the external terminals (21–23) being provided on the opposite side from the external terminal (24), and the semiconductor chips (61a–61d, 62a–62d) being provided further to the side closer to the external terminals (21, 22) than the semiconductor chips (63a–63d, 64a–64d).
H01L 23/52 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
9.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
The purpose of the present invention is to increase the strength of a load on an external connection terminal. This semiconductor device (1) has a circuit board (30), a case (10), first external connection terminals (12a-12d, 12i, 12j), and a sealing member. The case (10) includes a housing member that forms a rectangular outer shape in plan view and houses the circuit board (30). The lower surface of a first edge facing the outside of the housing member in plan view faces the upper surface of the housed circuit board (30) with a gap therebetween. The first external connection terminals (12a-12d, 12i, 12j) protrude in a direction perpendicular to the upper surface of the first edge, and are held by the first edge. The sealing member seals between the upper surface of the circuit board (30) and the lower surface of the first edge.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
10.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention makes it possible to accurately maintain the spacing of a case and a plurality of layers of substrates. A case of this semiconductor device comprises: an exterior member (11a) facing the upper surface of a wiring board (20) and spaced a second distance from the upper surface of the wiring board (20); an external connection terminal (12a) which is fixed to the exterior member (11a) and the lower end of which is inserted into a wiring hole (22a) of the wiring board (20) and thus electrically connected to the wiring hole (22a); a first spacer member (14a) which protrudes from the lower surface of the exterior member (11a) and is inserted into a guide hole (23a) of the wiring board (20) and the lower end of which is in contact with the upper surface of a circuit board (30), the first spacer member (14a) maintaining a first gap (L1) between the lower surface of the exterior member (11a) and the upper surface of the circuit board (30); and a second spacer member (15a) which protrudes from the lower surface of the exterior member (11a) and the lower end of which is in contact with the upper surface of the wiring board (20), the second spacer member (15a) maintaining a second gap (L2) between the lower surface of the exterior member (11a) and the upper surface of the wiring board (20).
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
11.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device that can be made small. This semiconductor device comprises: an insulated circuit board (1) in which conductive layers (5a, 5c) are disposed on the upper surface (S1) side; semiconductor chips (2a, 2b, 2e, 2f) that are disposed on the conductive layers (5a, 5c); a wiring board (3) that is disposed on the semiconductor chips (2a, 2b, 2e, 2f); and an output terminal (19) and a negative electrode terminal (18) respectively having one end (31) side and one end (27) side positioned between the conductive layers (5a, 5c) and the wiring board (3). The upper end side is press-fitted into first through-holes (16a, 16h) provided to the wiring board (3), and the lower end side is provided with inter-board connection pins (24a, 24h) that are press-fitted into second through-holes (22a, 22h) provided to the upper surfaces of the output terminal (19) and the negative electrode terminal (18).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A purpose of the present invention is to maintain a desired heat dissipation property by maintaining the thickness of a bonding member for bonding a semiconductor module and a cooling module. A bonding member (4) has an adhesive portion (41) and spacer portions (42). The adhesive portion (41) bonds a lower surface (22a) of a semiconductor module (2) and a placement surface (30a) of a cooling module (3). The spacer portions (42) are provided on the outer periphery of the adhesive portion (41), bond a lower surface (27b) of the semiconductor module (2) and the arrangement surface (30a) of the cooling module (3), and contain a filler. That is, the spacer portions (42) at the outer peripheral portions of the bonding member (4) contain a filler. Therefore, the thickness of the bonding member (4) is maintained by the filler in the outer peripheral portions of the bonding member (4).
Provided is a semiconductor device in which a significant change in positional relationship between a pin terminal and an electrode of a semiconductor chip is suppressed. This semiconductor device is provided with: an insulating circuit board (1); a semiconductor chip (3) that is mounted on the insulating circuit board (1) using a solder and has an electrode (30) on the upper surface thereof; a printed circuit board (6) that is disposed above the semiconductor chip (3); pin terminals (51, 52) that are inserted into the printed circuit board (6) and are joined to the electrode (30) by a solder; and a solder resist (71) and a solder resist (72) that are provided on the upper surface side of the insulating circuit board (1) and are spaced apart along a first direction. The semiconductor chip (3) is positioned between the solder resist (71) and the solder resist (72) along the first direction.
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 21/50 - Assemblage de dispositifs à semi-conducteurs en utilisant des procédés ou des appareils non couverts par l'un uniquement des groupes ou
H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
Provided is a semiconductor device that makes it possible to suppress decrease in a threshold value while leaving a barrier metal on an interlayer insulating film. The semiconductor device comprises: a first semiconductor layer (1) of a first conductivity type; a gate insulating film (7) in contact with the first semiconductor layer (1); a gate electrode (8); an interlayer insulating film (9); a contact hole (20); an upper surface electrode (11); and a sealing film (31). Among a first region (43) covered by the sealing film (31), a second region (42) that is adjacent to the first region (43) and in which the upper surface electrode (11) is not covered by the sealing film (31), and a third region (41) that is not adjacent to the first region (43), is adjacent to the second region (42), and in which the upper surface electrode (11) is not covered by the sealing film (31), the second region (42) is provided with a first barrier metal (25) including a first metal between the upper surface electrode (11) and the interlayer insulating film (9), and the first barrier metal (25) is not provided between the upper surface electrode (11) and the interlayer insulating film (9) in the third region (41).
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
H10D 64/20 - Électrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
Provided is a semiconductor device with which, in a case where terminals having differing potentials are arranged via an insulating layer, insulation between the terminals can be ensured. This semiconductor device is provided with: a first terminal (5); a second terminal (3) a portion of which faces the first terminal (5) and which is provided with a first opening (34a, 34b) in a different portion that does not face the first terminal (5); and an insulating layer (6) having a body (61) that is provided in a space where the first terminal (5) and the second terminal (3) face each other, and a first protrusion (62) that is connected to the body (61) and is inserted into the first opening (34a, 34b).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
The present invention reduces the number of components required for wiring and wiring connection steps, thereby improving assembly properties and reducing costs. This semiconductor device comprises a first circuit board (10), a second circuit board (20) and a semiconductor chip group (30), and has a configuration in which the semiconductor chip group (30) is sandwiched between the first circuit board (10) and the second circuit board (20). The first circuit board (10) includes a first insulating board (11), a first conductive plate (12) and a second conductive plate (13). The first conductive plate (12) is embedded in the first insulating board (11) in a state in which a first front surface (12a) and a first rear surface (12b) thereof are exposed. The second conductive plate (13) is embedded in the first insulating board (11) so as to be separated from the first conductive plate (12) in a state in which a second front surface (13a) and a second rear surface (13b) thereof are exposed. The second circuit board (20) includes a second insulating board (21) on which a conductive pattern layer is laid.
The present invention improves positional accuracy of a terminal of a power semiconductor device. This power semiconductor device (10) has power semiconductor elements (12a, 12b), an insulating circuit board (11) on which the power semiconductor elements (12a, 12b) are mounted on a main surface, a wiring board (14), a plurality of terminals (15a to 15f) electrically connected to the power semiconductor elements (12a, 12b), and a sealing resin (16). The wiring board (14) has a plurality of wiring pattern layers (14b1 to 14b6) provided facing the main surface of the insulating circuit board (11) and electrically connected to the power semiconductor elements (12a, 12b) or the insulating circuit board (11), respectively. All the terminals (15a to 15f) are directly connected to the wiring board (14), and are electrically connected to the respective wiring pattern layers (14b1 to 14b6). The sealing resin (16) seals a part of the power semiconductor elements (12a, 12b), the insulating circuit board (11), the wiring board (14), and the plurality of terminals (15a to 15f).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
The present invention provides a semiconductor device which is capable of achieving resistance and capacitance by a single chip. This semiconductor device is provided with: a semiconductor substrate (1); a lower layer insulating film (2) that is provided on the upper surface side of the semiconductor substrate (1); a resistance layer (3) that is provided on the upper surface side of the lower layer insulating film (2); an interlayer insulating film (4) that is provided on the upper surface side of the lower layer insulating film (2) and the resistance layer (3); a first front surface electrode (5a) that is provided on the upper surface side of the interlayer insulating film (4) and is electrically connected to one end of the resistance layer (3); a second front surface electrode (5b) that is provided on the upper surface side of the interlayer insulating film (4) so as to be separated from the first front surface electrode (5a) and is electrically connected to the other end of the resistance layer (3); and a back surface electrode (9) that is provided on the lower surface side of the semiconductor substrate (1). A resistance (R1) by means of the resistance layer (3) and a first capacitance (C1) that uses the lower layer insulating film (2) below the resistance layer (3) as a dielectric are connected in parallel to the first front surface electrode (5a).
H10D 89/00 - Aspects des dispositifs intégrés non couverts par les groupes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10D 1/47 - Résistances n’ayant pas de barrières de potentiel
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
The present invention mitigates a decrease in thermal conductivity by reducing stress between a board and a cooling module. A semiconductor device (1) includes: an insulating circuit board (20) including a metal plate (22) as the lowermost layer; a stress relief layer (24) formed on the underside of the metal plate (22) and having a higher coefficient of linear expansion than the metal plate (22); and a cooling module (3) including a placement surface (3a) on which the underside of the stress relief layer (24) is provided via a bonding member (4) that is a thermally conductive adhesive. Since the stress relief layer (24) has a higher coefficient of linear expansion than the metal plate (22), the difference in the coefficients of linear expansion between the metal plate (22) (insulating circuit board (20)) and the placement surface (3a) of the cooling module (3) is reduced gradually and stress is reduced.
The present invention provides a semiconductor device in which warpage of a semiconductor module can be suppressed. The semiconductor device is configured such that a semiconductor module (1) has a heatsink plate (3), a conductive plate (4) bonded to the upper surface (S1) of the heatsink plate (3) by a first resin sheet (7), and a semiconductor chip (5) bonded to the upper surface of the conductive plate (4) by a bonding material (10). The semiconductor device is also configured such that a cooler (2) is bonded to the lower surface (S6) of the semiconductor module (1) by a second resin sheet (12). The semiconductor device is also configured such that a resin sheet with higher insulation than the second resin sheet (12) is used as the first resin sheet (7), and a resin sheet with higher heat conductivity than the first resin sheet (7) is used as the second resin sheet (12).
Provided is a semiconductor device in which excessive wetting and spreading of solder is suppressed. This semiconductor device comprises: an insulating circuit board (1) having an insulating substrate (11), and an upper conductor layer (12a) and an upper conductor layer (12b) that are provided separated from each other on the upper surface of the insulating substrate (11); a semiconductor chip (3) mounted, using solder, on the upper conductor layer (12a); an external terminal (4) having a bonding section (41), the bonding section (41) being bonded, using solder (2b), to a first bonding region (14), which is one region of the upper surface of the upper conductor layer (12b); a printed circuit board (6) disposed above the semiconductor chip (3); a pin terminal (51) inserted into the printed circuit board (6) and bonded, using solder (9a), to a second bonding region (15), which is another region of the upper surface of the upper conductor layer (12b); and a solder resist (7) provided on the upper surface side of the upper conductor layer (12b) and adjacent to the first bonding region (14).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
22.
SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SAME
A purpose of the present invention is to prevent a molding failure from occurring due to a sealing resin protruding outside of a case during transfer molding. A semiconductor module (1) has a case (11) and an encapsulating resin (40). The case (11) includes, on the upper surface thereof, a first region and a second region that is thinner than the first region. The second region is formed with a first opening (11a1) and a recess (11d1) that surrounds the first opening (11a1) in an annular shape. The encapsulating resin (40) is filled in the case (11).
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
In this cooling device, one expansion valve is provided in each of a plurality of branch refrigerant flow paths. One evaporator is provided such that the plurality of branch refrigerant flow paths pass therethrough so as to cool the same cooling region.
This silicon carbide semiconductor device (10) comprises: a first conductivity-type silicon carbide semiconductor substrate (11); a first conductivity-type first semiconductor layer (12); a parallel pn region (26) in which a first conductivity-type first column region (25) and a second conductivity-type second column region (24) are repeatedly alternately disposed; a second conductivity-type second semiconductor layer (13); a first conductivity-type first semiconductor region (14); a second conductivity-type second semiconductor region (15); a trench (16); a gate insulating film (17); a gate electrode (18); a second conductivity-type high-concentration region (21) provided at a position facing the trench (16) in a depth direction; a second conductivity-type connection region (23) selectively provided in contact with the high-concentration region (21) and the second semiconductor layer (13) further on the second semiconductor layer (13) side than the high-concentration region (21) and further on the silicon carbide semiconductor substrate (11) side than the second semiconductor layer (13); a first electrode (44); and a second electrode (45).
Provided is an electric power storage system comprising: a DC bus; a plurality of batteries that are connected to the DC bus and are connected in parallel with each other; a plurality of diagnostic units that are respectively provided to the plurality of batteries and measure the state of deterioration of the batteries by discharging the batteries at a constant electric current or constant electric power; and a power conditioner that is connected to the DC bus and that performs AC/DC power conversion, wherein at least a portion of the electric power discharged from a test subject battery among the plurality of batteries, the deterioration state of which test subject battery being measured by the diagnostic unit, is charged into at least one of the plurality of batteries or supplied to the power conditioner.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H02J 7/34 - Fonctionnement en parallèle, dans des réseaux, de batteries avec d'autres sources à courant continu, p. ex. batterie tampon
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
26.
INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD
The present invention obtains, as a more practical value, a reduction contribution amount of carbon dioxide gas as a result of replacement of a drive system having a drive device from a base system to an object system. A sensor 123 performs actual measurement of a first electric power consumption amount that an object system consumed by a drive device. A first conversion unit 201 converts the first electric power consumption amount, and acquires a first emission amount of carbon dioxide gas emitted in power generation of an electric power amount corresponding to the first electric power consumption amount. An acquisition unit 202 uses an electric power consumption model for deriving electric power consumption on the basis of a control pattern of the drive device, so as to acquire a second electric power consumption amount that will be consumed corresponding to a control pattern of a base system. A second conversion unit 203 converts the second electric power consumption amount and acquires a second emission amount of carbon dioxide gas that will be emitted in power generation of an electric power amount corresponding to the second electric power consumption amount. A calculation unit 204 calculates a difference between the first emission amount and the second emission amount as a reduction contribution amount.
This semiconductor device comprising transistor parts and diode parts includes: a drift region which has a first conductivity type and is provided on a semiconductor substrate; a plurality of trench parts; a base region which has a second conductivity type and is provided above the drift region; an emitter region which has the first conductivity type, is provided on the front surface of the semiconductor substrate, and has a higher doping concentration than the base drift region; a contact region which has the second conductivity type, is provided above the drift region, and has a higher doping concentration than the base region; cathode regions which have the first conductivity type, are provided on the rear surface of the semiconductor substrate, and have a higher doping concentration than the drift region; and collector regions which have the second conductivity type, are provided on the rear surface of the semiconductor substrate, and have a higher doping concentration than the base region. The semiconductor device comprises a mixture part in which transistor regions provided with the collector regions at the lower portions thereof and diode regions provided with the cathode regions at the lower portions thereof are alternately provided in a trench extending direction.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
The present invention provides a semiconductor device comprising a transistor portion and a diode portion. The semiconductor device includes: a first-conductivity type drift region provided on a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction on a front surface side of the semiconductor substrate; a second conductivity-type base region provided above the drift region; a first conductivity-type first emitter region provided on a front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a first conductivity-type second emitter region provided on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; and a second conductivity-type trench sidewall region provided above the drift region and having a doping concentration higher than that of the base region.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
Provided is a semiconductor device comprising: a fist conductivity-type drift region provided on a semiconductor substrate; a second conductivity-type base region; a first conductivity-type emitter region having a doping concentration higher than that of the drift region; a second conductivity-type contact region; a trench contact part; and a plurality of trench parts extending in a predetermined trench extension direction on the front surface side of the semiconductor substrate, wherein the plurality of trench parts have a gate trench part and a dummy trench part, and a mesa part between the plurality of trench parts has a contact formation region where the contact region is provided below the emitter region on a side wall of at least one trench part among the plurality of trench parts, and a contact non-formation region where the contact region is not provided below the emitter region on a side wall of the gate trench part.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
Provided is a semiconductor device in which a first cathode region and a second cathode region are repeatedly provided in a first direction, one or more first cathode regions are provided in a second direction intersecting the first direction, and a length Lx between both ends in the second direction of the one or more first cathode regions, and a width Dyn in the first direction of one first cathode region satisfy the following formula. 0.001 < Dyn/Lx ≤ 0.1
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
To provide a semiconductor device that is electrically stable. A semiconductor device (1) includes: a heat dissipation plate (22) including a heat dissipation surface (22a); a cooling module (3) including a cooling surface (3a) on which the heat dissipation surface (22a) of the heat dissipation plate (22) is disposed; and a bonding member (4) provided between the heat dissipation surface (22a) and the cooling surface (3a). The bonding member (4) includes: a heat conduction portion (4a) that bonds the heat dissipation surface (22a) and the cooling surface (3a); and a conductive portion (4b) that is directly connected to the heat dissipation plate (22) and the cooling surface (3a), respectively. Therefore, the heat dissipation plate (22) and the cooling module (3) can have the same potential.
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
This semiconductor device (70) comprises an active region (50) and a termination region (60) on a first conductivity-type semiconductor substrate (1). The active region (50) has a first conductivity-type first semiconductor layer (2) and second conductivity-type second semiconductor regions (4a, 6). The termination region (60) has: the first semiconductor layer (2); a second conductivity-type first semiconductor region (30) including a plurality of second conductivity-type first small regions (31); and a second conductivity-type third semiconductor region (34) provided continuously, from the edges of the second semiconductor regions (4a, 6) to a predetermined number of the first small regions (31), to be lower in concentration than the first small regions (31), the semiconductor substrate (1)-side surface of the second conductivity-type third semiconductor region (34) being shallower than the semiconductor substrate (1)-side surfaces of the first small regions (31).
First and second p+-type regions (21, 22) for electric field relaxation, and an n-type current diffusion region (23), are each selectively provided, at positions deeper than the bottom surfaces of trenches, between a p-type base region (3) and an n–-type drift region (2). Between the second p+-type region (22) and the n–-type drift region (2) between adjacent trenches, an n––-type region (24) is selectively provided in contact with these regions. The n-type current diffusion region (23) selectively surrounds the lower surface of the second p+-type region (22) between adjacent trenches, and surrounds the periphery of the n––b1b1) of the p-n junction between the second p+b3b3) of a p-n junction between the second p+-type region (22) and the n––-type region. This makes it possible to improve breakage resistance.
The present invention provides a vertical device including a semiconductor substrate that has an upper surface and a lower surface, and a lower surface electrode that is provided to the entire lower surface of the semiconductor substrate, wherein the lower surface electrode contains copper. The lower surface electrode has a lowermost layer exposed on the farthest surface from the lower surface of the semiconductor substrate, the lowermost layer contains copper, the percentage of copper in the lowermost layer is 50-90 wt%, and the thickness of the lowermost layer is 0.2-0.8 μm.
H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
35.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device includes a semiconductor substrate, an interlayer insulating film provided with a contact hole above the semiconductor substrate, and a first upper electrode provided above the interlayer insulating film. The semiconductor device has: a first region having a first contact part electrically connected to the first upper electrode via the contact hole; and a second region having a second contact part electrically connected to the first upper electrode via the contact hole. The second contact part has higher resistance than the first contact part.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
36.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention provides: a semiconductor device in which it is possible to suppress warpage and distortion of a wafer due to expansion or the like of a polysilicon film at the time when embedding the polysilicon film in a trench; and a method for manufacturing a semiconductor device. This semiconductor device is provided with: a semiconductor substrate (10) that has a first conductivity type; a first semiconductor layer (2) that has a second conductivity type; a first semiconductor region (3) that has the first conductivity type; a trench (6); a gate insulating film (7); a gate electrode (8); an interlayer insulating film (9); a first electrode (11); and a second electrode (24). With respect to the trench (6), a TEOS film (30) is embedded inside the gate electrode (8).
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
37.
SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
Before epitaxial growth of an epitaxial layer (40) including a buffer layer (11), a crystal defect introduction region (41) is formed by introducing point defects (42) at high density from a front surface (1a) of a starting substrate (1). Since an Si core partial dislocation of a BPD (30) becomes less likely to move in the vicinity of the front surface (1a) of the starting substrate (1) due to the crystal defect introduction region (41), even if the in-plane temperature distribution of the front surface (1a) of the starting substrate (1) is unstable during the epitaxial growth of the epitaxial layer (40), the distance between two Shockley partial dislocations constituting the BPD (30) in the starting substrate is less likely to increase, and the BPD (30) in the starting substrate (1) is converted into a TED (31) with high efficiency at an interface (12) between the starting substrate (1) and the buffer layer (11), and is less likely to propagate to the epitaxial layer (40). Consequently, the propagation of the BPD (30) in the starting substrate (1) to the epitaxial layer (40) can be suppressed.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p. ex. croissance épitaxiale
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
This semiconductor device is provided with a transistor part and a diode part. The semiconductor device is provided with: a drift region of a first conductivity type provided on a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction on a front surface side of the semiconductor substrate; and a collector region of a second conductivity type provided below the drift region. The transistor part may include: a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type having a doping concentration higher than that of the drift region; a first contact region of the second conductivity type having a doping concentration higher than that of the base region; a plurality of trench bottom regions of the second conductivity type provided repeatedly in the trench extension direction below the base region; and a plurality of trench bottomless regions provided repeatedly in the trench extension direction and sandwiched between the plurality of trench bottom regions. The diode part may have an anode region of the second conductivity type provided above the drift region and a rear surface-side region provided below the drift region. The rear surface-side region may include a first conductivity type part of the first conductivity type and a second conductivity type part of the second conductivity type. The first conductivity type part and the second conductivity type part may be provided in a manner so as to form, as seen from a top view, a repetitive structure in which a second conductivity type formation region in which the second conductivity type part is formed and a second conductivity type non-formation region in which the second conductivity type part is not formed are alternately and repeatedly arranged in a predetermined direction. As seen from the top view, the shortest distance from an end of each of the plurality of trench bottomless regions to the second conductivity type non-formation region may be 85-115% of a predetermined reference value.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
39.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device that comprises a semiconductor substrate having an upper surface and a lower surface, and that has a diode part provided on the semiconductor substrate. The diode part includes first cathode regions of a first conductivity type and second cathode regions of a second conductivity type, and the first cathode regions and the second cathode regions are repeatedly provided in a first direction. The repetition pitch of the first cathode regions and the second cathode regions in the first direction is 40-200 μm, and the ratio of the area of the second cathode regions to the sum of the areas of the first cathode regions and the second cathode regions is 0.1-0.8.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 89/00 - Aspects des dispositifs intégrés non couverts par les groupes
40.
SUPER JUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUPER JUNCTION SILICON CARBIDE SEMICONDUCTOR DEVICE
NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY (Japon)
Inventeur(s)
Tawara, Takeshi
Takenaka Kensuke
Harada, Shinsuke
Sometani Mitsuru
Abrégé
This super junction silicon carbide semiconductor device comprises: a silicon carbide semiconductor substrate (1); a first semiconductor layer (17) of a first conductivity type; a parallel pn region (21) in which a first column region (4) of the first conductivity type and a second column region (3) of a second conductivity type are alternately arranged repeatedly; a second semiconductor layer (5) of the first conductivity type; a first semiconductor region (7) of the first conductivity type; a trench (16); a gate electrode (10); a first electrode (12); and a second electrode (18). A second semiconductor region (19) of the second conductivity type which is doped with impurities of the second conductivity type is provided in the first semiconductor layer (1) on the bottom surface of the second column region (3) so as to be in contact with the second column region (3). At the boundary between the second semiconductor region (19) and the second column region (3), the concentration of the impurities of the second conductivity type has a concentration spike that decreases to 1/10 or less with respect to the maximum concentration of the impurities of the second conductivity type in the second semiconductor region (19).
The present invention provides a semiconductor device in which deterioration in pressure resistance performance is suppressed. This semiconductor device comprises: an active part (101); a terminal region (102) surrounding the active part in a plan view; a first conductivity type drift layer (3) provided over the active part and the terminal region; a second conductivity type base region (5) provided on the upper surface side of the drift layer in the active part; and a second conductivity type well region (12) provided on the upper surface side of the drift layer in the terminal region and surrounding the base region (5) in a plan view. The well region (12) has a recess (12a) on the lower side, and the dimension of the recess (12a) in the depth direction is 1/3 to 2/3 of the dimension of the well region (12) in the depth direction.
The present invention provides a semiconductor device, a semiconductor module, and a method for manufacturing a semiconductor device which make it possible to suppress a decrease in Vth due to a front surface electrode deficiency or a defect on a gate insulating film. This semiconductor device is provided with: a semiconductor substrate (10); an interlayer insulating film (9) provided over a first main surface of the semiconductor substrate (10); a contact hole (20) penetrating the interlayer insulating film (9) and reaching the semiconductor substrate (10); a plug electrode (15) filled in the contact hole (20); a first barrier metal (25a) provided over the plug electrode (15) and the interlayer insulating film (9); and a front surface electrode (11) provided over the first barrier metal (25a).
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
43.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a method for manufacturing a semiconductor device, the method comprising: a step for forming a plurality of trenches on a front surface of a semiconductor substrate; a step for forming an injection mask in a first trench among the plurality of trenches; and a step for injecting a second conductivity-type dopant into a second trench, in which the injection mask is not formed, among the plurality of trenches, in order to form a trench bottom part in a bottom part of the second trench. In the step of injecting the dopant, the second conductivity-type dopant is also injected into a first mesa part adjacent to the first trench and a second mesa part adjacent to the second trench.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
Provided is a kaolin powder capable of preventing quick setting and an increase in viscosity with respect to a geopolymer. This kaolin powder is derived from a coal-seam kaolin and has an ignition loss of 1.5 to 10 mass% and an amorphous content of 56 mass% or greater. Also provided is a composition for a geopolymer, the composition containing this kaolin powder.
Provided is a method for evaluating a semiconductor substrate, comprising: implanting hydrogen ions from an implantation surface of a silicon-containing semiconductor substrate; annealing the semiconductor substrate; measuring a differential carrier concentration that is a difference between a first carrier concentration in a conduction region of the semiconductor substrate through which the hydrogen ions have passed and a second carrier concentration in a non-conduction region of the semiconductor substrate where the hydrogen ions have not reached; and evaluating a carbon concentration in the semiconductor substrate on the basis of the differential carrier concentration.
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
46.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device comprising a transistor part and a diode part, wherein the semiconductor device comprises a drift region of a first conductivity type provided on the semiconductor substrate, and a plurality of trench parts extending in a predetermined trench extension direction, the transistor part having a base region of a second conductivity type, a plurality of emitter regions of a first conductivity type discretely provided in the trench extension direction and having a doping concentration higher than that of the drift region, a contact region of a second conductivity type having a doping concentration higher than that of the base region, a trench contact part provided extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate in a mesa part between two adjacent trench parts among the plurality of trench parts, and a thinning region provided between two emitter regions adjacent to each other in the trench extension direction among the plurality of emitter regions and having a lower doping concentration of the second conductivity type than the contact region.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
Provided is a beverage supply device 1 that discharges and supplies a beverage generated by an extractor 30 through a nozzle 22a into a cup C placed on a beverage supply part 22, wherein: the beverage supply device 1 comprises a control unit 12 for supplying hot water to the extractor 30 as rinsing hot water and cleaning the extractor 30, which discharges the rinsing hot water supplied for cleaning of the extractor 30 through the nozzle 22a, when a prescribed cleaning condition is provided; and the control unit 12 restricts supply of the rinsing hot water to the extractor 30 when the integrated value of beverage supply counts from a time point at which a previous cleaning condition is provided to a time point at which the current cleaning condition is provided is equal to or less than a predetermined reference value.
Provided is a semiconductor device comprising: a plurality of trench portions arranged in a predetermined arrangement direction on a front surface side of a semiconductor substrate, the plurality of trench portions having a repeating structure in which a gate trench portion and a dummy trench portion are repeated at predetermined intervals in the arrangement direction; a first conductivity type drift region provided on the semiconductor substrate; a second conductivity type base region provided above the drift region; a first conductivity type emitter region provided above the base region and having a doping concentration higher than that of the drift region; a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region; and a second conductivity type trench bottom region provided below the gate trench portion and having a doping concentration lower than that of the base region. The trench bottom region is provided below the emitter region, and the length of the trench bottom region in the arrangement direction is shorter than the length of the repeating structure.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
Provided is a vibration suppression circuit connected to a DC bus to which DC power is supplied. The DC bus is connected to at least two capacitors, and the vibration suppression circuit absorbs energy of the DC bus and emits the energy to the DC bus, whereby electric vibration of the DC bus is suppressed. The vibration suppression circuit may emit energy to the DC bus at a voltage lower than the voltage when absorbing the energy of the DC bus.
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
A silicon carbide semiconductor device (10) is provided with: a silicon carbide semiconductor substrate (11) that has a first conductivity type; a first semiconductor layer (12) that has the first conductivity type; a second semiconductor layer (13) that has a second conductivity type; a first semiconductor region (14) that has the first conductivity type; a second semiconductor region (15) that has the second conductivity type; a trench (16); a gate insulating film (17); a gate electrode (18); a high-concentration region (21) that has the second conductivity type and is positioned so as to face the trench (16) in the depth direction; and a connection region (23) that has the second conductivity type and is selectively provided so as to be in contact with the high-concentration region (21) and the second semiconductor layer (13) at a position that is closer to the second semiconductor layer (13) than the high-concentration region (21) and is closer to the silicon carbide semiconductor substrate (11) than the second semiconductor layer (13). The second semiconductor region (15) is periodically disposed in the longitudinal direction of the trench (16), and the connection region (23) is periodically disposed in the longitudinal direction of the trench (16) in a region where the connection region (23) does not overlap the second semiconductor region (15) in a plan view.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
Provided is an insulated gate type semiconductor device in which a mesa portion between trenches can be miniaturized. The insulated gate type semiconductor device comprises: a drift layer (1) of a first conduction type; base regions (3a-3d) of a second conduction type provided over the drift layer (1); contact regions (5a-5d) of the second conduction type provided in upper portions of the base regions (3a-3d); main electrode regions (4a-4h) of the first conduction type provided on the base regions (3a-3d) and the contact regions (5a-5d); gate electrodes (8a, 8c, 8e) filled in gate trenches (6a, 6c, 6e); dummy electrodes (8b, 8d) filled in dummy trenches (6b, 6d); and contact parts (9a-9d) filled in contact trenches (10a-10d). The contact trenches (10a-10d) are each located further toward the dummy trench (6b, 6d) side than a position equidistant from the gate trench (6a, 6c, 6e) and the dummy trench (6b, 6d).
The present invention provides a semiconductor device which includes an upper arm circuit and a lower arm circuit, and is provided with a positive electrode terminal, a negative electrode terminal, and an output terminal. The semiconductor device includes an insulating plate, a first wiring pattern that is provided on the insulating plate, and a second wiring pattern that is provided at a distance from the first wiring pattern on the insulating plate. The upper arm circuit includes a circuit where the positive electrode terminal, a first diode part that is provided on the first wiring pattern, a first transistor part that is connected in series with the first diode part and is provided on the first wiring pattern, and the output terminal are connected and arranged in this order. The lower arm circuit includes a second transistor part that is provided on the second wiring pattern, and a second diode part that is provided on the second wiring pattern.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
Provided is a semiconductor device which includes: a current detection part through which a detection current corresponding to a main current of a transistor part flows; a current detection pad disposed above a semiconductor substrate and disposed side by side with the current detection part in a first direction; a built-in resistance part which is provided above the semiconductor substrate and which connects the current detection part and the current detection pad; and gate wiring disposed above the semiconductor substrate and connected to a gate conductive part. The built-in resistance part and the gate wiring are disposed side by side, between the current detection part and the current detection pad, in the first direction.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
Provided is a semiconductor device including: a plurality of transistor regions; a gate pad provided over a semiconductor substrate; a built-in resistance part electrically connected to the gate pad; a plurality of gate wiring parts electrically connected to the built-in resistance part and provided in accordance with the plurality of transistor regions; and a plurality of wiring resistance parts provided in accordance with the plurality of gate wiring parts. The plurality of gate wiring parts may include a gate metal layer provided over the semiconductor substrate and a gate runner provided under the gate metal layer.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
The present invention maintains insulating properties between electroconductive plates. According to the present invention, a semiconductor device is equipped with: a first electroconductive plate (22a), which comprises copper or a copper alloy as a main component; a second electroconductive plate (23a), which has a second back surface (23a7) facing the first electroconductive plate (22a) and a side surface connected to the second back surface (23a7) and comprises copper or a copper alloy as a main component; and a second oxide film (23b), which is provided on the second back surface (23a7) and side surface of the second electroconductive plate (23a), has electrical insulating properties, and includes an oxide of a metal element differing from the metal(s) of the second electroconductive plate (23a). A first oxide film (22b) and the second oxide film (23b) are used as insulating members between a first wiring part (22a2) of the first electroconductive plate (22a) and a second wiring part (23a2) of the second electroconductive plate (23a).
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
Provided is a semiconductor device (100) comprising a floating region (202) of a second conductivity type which is disposed under a lower end (43) of a first gate trench part (40) on the upper surface side of a semiconductor substrate (10) and does not extend under a lower end (33) of a first dummy trench part. A first mesa part is provided in contact with the first gate trench part and includes: an emitter region (12) of a first conductivity type having a higher concentration than in a drift region (18); and a base region (14) of the second conductivity type provided between the emitter region and the drift region and being in contact with the first gate trench part. The lower end of the first dummy trench part is in contact with the region of the first conductivity type.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
A semiconductor device according to the present invention includes a transistor part and a diode part. The transistor part includes a first gate trench part provided closest to the diode part, and a first mesa part that is in contact with the first gate trench part and is provided between the first gate trench part and the diode part. A first floating region is provided below the first gate trench part, and the first mesa part has a non-covering region that does not overlap the first floating region.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
The present invention prevents decreases in heat dissipation. A semiconductor device (1) includes: an insulating circuit board (20) having a lower surface (23a); a heat dissipation base plate (40) including a front surface (40a), and having a placement region (40b) where the lower surface (23a) of the insulating circuit board (20) is placed on the front surface (40a) via a solder (27); a plating film (41) which is formed on the front surface (40a) of the heat dissipation base plate (40) except for at a solder region where the solder (27) is spread over the placement region (40b) of the front surface (40a); and an alloy layer which is included between the solder (27) and the placement region (40b) of the heat dissipation base plate (40), and contains solder components contained in the solder (27). In particular, in the semiconductor device (1), the plating film (41) is formed on the entire surface of the heat dissipation base plate (40) excluding an open region (41a) that surrounds the outer perimeter of the periphery of the placement region (40b) where the insulating circuit board (20) is placed via the solder (27).
An electric power conversion apparatus comprising an inverter that converts input DC power into AC power and a control device that controls the inverter, wherein the control device preferentially limits one current, out of an effective current and a reactive current output from the inverter, more than the other current so that an apparent current output from the inverter is equal to or less than a limit value.
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
61.
SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SAME
Provided is a method for manufacturing a silicon carbide semiconductor device, the method being capable of bringing an electrode into ohmic contact with a semiconductor layer made of silicon carbide without forming a silicide layer. The method for manufacturing a silicon carbide semiconductor device includes: a step for ion-implanting impurities into, on the upper surface thereof, a first semiconductor layer made of 4H-SiC silicon carbide at an angle of 30° or more but less than 90° with respect to a line normal to the upper surface of the first semiconductor layer, to form on the upper surface of the first semiconductor layer, a second semiconductor layer made of silicon carbide containing 3C-SiC at least on the upper surface side thereof; and a step for forming a main electrode on the upper surface side of the second semiconductor layer.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
A geothermal power generation system according to one embodiment of the present invention comprises: a gas-liquid separator; a first pipe; a first valve that opens and closes the flow path of the first pipe; a second pipe; an analysis device; a control device that performs control for determining at least one chemical agent from among a plurality of chemical agent candidates on the basis of the result of analysis performed by the analysis device, and for supplying the chemical agent; a chemical agent supply port which is provided to the first pipe and through which the chemical agent is supplied; a third pipe that branches off the second pipe; a chemical agent recovery line that branches off the second pipe and is connected to the second pipe; a waste liquid recovery part, a scale separation part, a first chemical agent recovery part, an impurity separation part, a second chemical agent recovery part, a chemical agent purification part, and a regenerated chemical agent tank, which are provided in midcourse of the chemical agent recovery line sequentially from the upstream side; and a waste liquid adjustment device. The waste liquid adjustment device is connected to the scale separation part, the impurity separation part, and the chemical agent purification part.
C02F 5/00 - Adoucissement de l'eauPrévention de l'entartrageAddition à l'eau d'agents antitartre ou détartrants, p. ex. addition d'agents séquestrants
B08B 3/08 - Nettoyage impliquant le contact avec un liquide le liquide ayant un effet chimique ou dissolvant
C02F 5/08 - Traitement de l'eau avec des produits chimiques complexants ou des agents solubilisants pour l'adoucissement, la prévention ou l'élimination de l'entartrage, p. ex. par addition d'agents séquestrants
C02F 5/10 - Traitement de l'eau avec des produits chimiques complexants ou des agents solubilisants pour l'adoucissement, la prévention ou l'élimination de l'entartrage, p. ex. par addition d'agents séquestrants en utilisant des substances organiques
F01D 25/00 - Parties constitutives, détails ou accessoires non couverts dans les autres groupes ou d'un intérêt non traité dans ces groupes
F01K 27/00 - Ensembles fonctionnels transformant la chaleur ou l'énergie d'un fluide en énergie mécanique, non prévus ailleurs
F03G 4/00 - Dispositifs produisant une puissance mécanique à partir d'énergie géothermique
63.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device comprising an active portion and a temperature-sensitive portion. The temperature-sensitive portion includes: a temperature-sensitive trench part provided on a front surface side of the semiconductor substrate; a temperature-sensitive anode region provided inside a trench of the temperature-sensitive trench part; and a temperature-sensitive cathode region provided in contact with the temperature-sensitive anode region inside the trench of the temperature-sensitive trench part. Provided is a semiconductor device comprising: an active portion provided in a semiconductor substrate; a temperature-sensitive portion provided over the semiconductor substrate; and an interlayer insulating film provided over the active portion and the temperature-sensitive portion. The temperature-sensitive portion includes a recess region having a recess on a front surface side of the semiconductor substrate, and a temperature-sensitive diode portion provided over the semiconductor substrate in the recess region. The height position of the upper surface of the interlayer insulating film in the active portion in the depth direction of the semiconductor substrate is the same as the height position of the upper surface of the interlayer insulating film in the recess region.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
64.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device comprising an active part provided to a semiconductor substrate, and a temperature-sensitive part provided above the semiconductor substrate. The temperature-sensitive part has: a temperature-sensitive diode provided above the semiconductor substrate; a first interlayer insulation film provided above the temperature-sensitive diode; a temperature-sensitive contact portion provided extending from the upper surface to the lower surface of the first interlayer insulation film; and a housing portion provided below the temperature-sensitive contact portion. A bottom-surface corner section of the temperature-sensitive contact portion is in contact with the temperature-sensitive diode, and the bottom surface of the temperature-sensitive contact portion is in contact with the housing portion.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
Provided is a semiconductor device comprising an active part and a temperature-sensitive part, the semiconductor device comprising: a semiconductor substrate; and an interlayer insulating film provided above the semiconductor substrate. The active part includes an active trench part provided on a front surface of the semiconductor substrate, and an active contact part provided in the interlayer insulating film above the active trench part. The temperature-sensitive part has a temperature-sensitive diode provided above the semiconductor substrate, and a temperature-sensitive contact part provided in the interlayer insulating film above the temperature-sensitive diode. The contact width of the temperature-sensitive contact part is larger than the contact width of the active contact part. In the depth direction of the semiconductor substrate, the extension depth of the temperature-sensitive trench contact portion extending from an upper surface of the temperature-sensitive diode in the depth direction of the semiconductor substrate is shallower than the extension depth of the plurality of active trench contact portions extending from the front surface of the semiconductor substrate in the depth direction of the semiconductor substrate.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
A geothermal power generation system including a binary power generation device having a medium evaporator comprises: a gas-liquid separator that separates geothermal water from geothermal fluid ejected from a production well; first piping that sends the geothermal water separated by the gas-liquid separator to the medium evaporator; a first valve that is provided to the first piping and opens and closes a flow path of the first piping; second piping that sends the geothermal water from which heat has been recovered by the binary power generation device from the medium evaporator to a reinjection well; an analysis device into which the geothermal water flowing through the second piping flows and which analyzes components of scale included in the inflow geothermal water; and a control device that determines at least one type of cleaning agent from among a plurality of types of cleaning agent candidates on the basis of the analysis result of the analysis device, and performs control to supply the selected cleaning agent, wherein the first piping has a cleaning agent supply port to which the cleaning agent is supplied on the downstream side of the first valve.
F03G 4/00 - Dispositifs produisant une puissance mécanique à partir d'énergie géothermique
B08B 3/08 - Nettoyage impliquant le contact avec un liquide le liquide ayant un effet chimique ou dissolvant
C02F 5/00 - Adoucissement de l'eauPrévention de l'entartrageAddition à l'eau d'agents antitartre ou détartrants, p. ex. addition d'agents séquestrants
C02F 5/08 - Traitement de l'eau avec des produits chimiques complexants ou des agents solubilisants pour l'adoucissement, la prévention ou l'élimination de l'entartrage, p. ex. par addition d'agents séquestrants
C02F 5/10 - Traitement de l'eau avec des produits chimiques complexants ou des agents solubilisants pour l'adoucissement, la prévention ou l'élimination de l'entartrage, p. ex. par addition d'agents séquestrants en utilisant des substances organiques
F01D 25/00 - Parties constitutives, détails ou accessoires non couverts dans les autres groupes ou d'un intérêt non traité dans ces groupes
F01K 27/00 - Ensembles fonctionnels transformant la chaleur ou l'énergie d'un fluide en énergie mécanique, non prévus ailleurs
A geothermal power generation system according to one aspect of the present invention comprises: a gas-liquid separator; a power generation device; a retention tank; a reinjection line; a reinjection pump; a chemical injection port provided in the reinjection line between the retention tank and the reinjection pump; a first chemical addition device that injects a chemical into the chemical injection port; a branch part that is provided in the middle of the reinjection line on the downstream side of the reinjection pump and above a reinjection well in the vertical direction, and branches a flow of the geothermal water; a first liquid analyzer; a scale piece collector; a dissolving agent addition device; and a control device that, on the basis of the analysis result of the first liquid analyzer, switches between injecting of the chemical and stopping of injection by the first chemical addition device, and switches between injecting of the dissolving agent and stopping of injection by the dissolving agent addition device.
F03G 4/00 - Dispositifs produisant une puissance mécanique à partir d'énergie géothermique
B08B 3/08 - Nettoyage impliquant le contact avec un liquide le liquide ayant un effet chimique ou dissolvant
C02F 5/00 - Adoucissement de l'eauPrévention de l'entartrageAddition à l'eau d'agents antitartre ou détartrants, p. ex. addition d'agents séquestrants
C02F 5/08 - Traitement de l'eau avec des produits chimiques complexants ou des agents solubilisants pour l'adoucissement, la prévention ou l'élimination de l'entartrage, p. ex. par addition d'agents séquestrants
C02F 5/10 - Traitement de l'eau avec des produits chimiques complexants ou des agents solubilisants pour l'adoucissement, la prévention ou l'élimination de l'entartrage, p. ex. par addition d'agents séquestrants en utilisant des substances organiques
F01D 25/00 - Parties constitutives, détails ou accessoires non couverts dans les autres groupes ou d'un intérêt non traité dans ces groupes
F01K 27/00 - Ensembles fonctionnels transformant la chaleur ou l'énergie d'un fluide en énergie mécanique, non prévus ailleurs
The present invention ensures sufficient withstand voltage characteristics. A control conductive pattern (13d) includes a connection region (13d1) electrically connected to a control electrode (15a1), and, in a plan view, is adjacent to the opposite side of a chip region of a terminal region of an output conductive pattern (13c). Furthermore, the terminal region of the output conductive pattern (13c) has a recess (13c3) recessed from a first side to a second side on the +X direction side, in a plan view. The connection region (13d1) of the control conductive pattern (13d) is provided in the recess (13c3). The connection region (13d1) of the control conductive pattern (13d) is separated from the output terminal (63a).
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
A beverage supply device 1 comprises a raw material box 51 in which a raw material is accommodated and stored, and which discharges the raw material to an extractor 30 by driving of a built-in raw material supply drive unit 51a, the beverage supply device 1 supplying a beverage produced with the extractor 30 to a cup C. The raw material box 51 includes: a delivery unit 511 having the built-in raw material supply drive unit 51a and delivering the raw material to the extractor 30 by driving of the raw material supply drive unit 51a; and an accommodation portion 512 which, by being engaged with the delivery unit 511 with a communication port 5122 of the accommodation portion 512 being in communication with an introduction port 5112 of the delivery unit 511, is disposed with a part thereof being exposed from a body cabinet 10, and is provided detachably with respect to the delivery unit 511. An operation unit 5115 for engaging and disengaging the accommodation portion 512 with or from the delivery unit 511 is disposed inside the body cabinet 10.
A47J 31/40 - Appareils à préparer des boissons avec des moyens de distribution pour ajouter une quantité mesurée d'ingrédients, p. ex. du café, de l'eau, du sucre, du cacao, du lait, du thé
B67D 1/07 - Nettoyage des appareils pour débiter des boissons
B67D 1/08 - Appareils ou dispositifs pour débiter des boissons à la pression Détails
Provided is a semiconductor device comprising: a drift region of a first conductivity type which is provided to a semiconductor substrate; an emitter region of the first conductivity type which is provided to a front surface of the semiconductor substrate and which has a higher doping concentration than the drift region; a plurality of trench parts which are provided above the drift region; a trench contact part which is provided to a mesa part between the plurality of trench parts; and a plug region of a second conductivity type which is provided in contact with a lower end of the trench contact part. The trench contact part may have a main trench contact which, in a plan view, extends in the trench extension direction, and a sub trench contact which, in a plan view, extends from the main trench contact in a direction differing from the trench extension direction.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
In the present invention, the cooling performance of a cooler applied to a semiconductor device is improved. A cooler (2) comprises: a top plate on a first surface of which a heat-dissipating surface is formed; a bottom plate that is disposed facing the top plate and that has a greater thickness than that of the top plate; a plurality of fins (210) connected to at least the top plate; and a peripheral wall part formed, between the top plate and the bottom plate, so as to surround the outer periphery of the plurality of fins. A refrigerant flow path (260) surrounded by the top plate, the bottom plate, and the peripheral wall part is formed, the refrigerant flow path having a refrigerant inflow port (251) provided toward one end in a first direction of the refrigerant flow path and a refrigerant outflow port (252) provided toward the other end thereof in the first direction. The plurality of fins each include an inclined portion that, in a first plan view when viewed from a second direction perpendicular to the first direction, extends in a direction of displacement toward the refrigerant inflow port as the distance from the first surface of the top plate increases and that, in a second plan view when viewed from the first direction, extends in a direction of displacement in the second direction as the distance from the first surface of the top plate increases.
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
72.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present invention provides a semiconductor device comprising: a transistor part; a current sensing part for detecting a current flowing in the transistor part; a gate pad provided above a semiconductor substrate; and a resistance adjustment part that is electrically connected to the gate pad and that adjusts the gate resistance of the transistor part and the current sensing part. The resistance adjustment part includes a main adjustment part that is electrically connected to a gate conductive part of the transistor part, and a sense adjustment part that is electrically connected to the gate conductive part of the current sensing part. Each of the main adjustment part and the sense adjustment part includes a diode element part having a plurality of diodes provided in reverse parallel, and a resistance part connected to the diode element part.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
This cooler comprises: a heat dissipation substrate (210) including a first main surface (210S1) on which one or more semiconductor elements (10) are mounted and a second main surface (210S2) which has a fin part provided thereto; a case body (200) which is in close contact with the second main surface and accommodates the fin part; and a structural body (240). The case body includes a first wall part (200M1), a second wall part (200M2) facing the first wall part, an introduction port (204A) through which a refrigerant is introduced into the case body, and a discharge port (204B) which is positioned in the direction of a main line (L) from the first wall part toward the second wall part with respect to the introduction port and through which the refrigerant is discharged from the inside of the case body. The structural body takes in the refrigerant flowing in from the introduction port, guides the refrigerant in a guide direction that intersects the main line, and causes the refrigerant to flow out from a position corresponding to the fin part.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
Provided is a semiconductor device for which a reduction in size can be achieved while maintaining insulation between terminals. According to the present invention, a case affixes a first terminal (10), a second terminal (20), and a first insulating member (30), while exposing respective exposure regions of the first terminal (10), the second terminal (20), and the first insulating member (30). A second insulating member (40) covers second portions (31a2, 31c2) that are less than or equal to a predetermined distance of the front surface of the exposure region of the second terminal (20) from terminal edge portions (11a, 11c) and a terminal outer end portion (11d) of the exposure region of the first terminal (10). The second portions (31a2, 31c2) of the first insulating member (30) extend outward from the terminal edge portions (11a, 11c) and the terminal outer end portion (11d) of the first terminal (10).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
A channel stopper electrode (52) and an n+-type channel stopper region (53) are respectively provided spaced apart from an outermost peripheral FLR (41) and an outermost peripheral FLR (41) outside a voltage-withstand structure (40). The n+-type channel stopper region (53) faces an inner end part (52a) of the channel stopper electrode (52) in a depth direction Z with an interlayer insulating film (21) therebetween. The width (L2) of an inner portion (53-1) of the n+-type channel stopper region (53) further inward than the inner end part (52a) of the channel stopper electrode (52) is less than or equal to half the distance (L1) between the channel stopper electrode (52) and one of the outermost peripheral FP (42) and the outermost peripheral FLR (41) of the voltage-withstand structure (40). The depth (d2) of the n+-type channel stopper region (53) is shallower than the depth (d1) of the FLR (41). Thus, a predetermined breakdown voltage of the semiconductor device (10) can be stably secured.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
According to the present invention, a screw is securely fastened to a case. A molding space (61a) is composed of: a molding inner surface (60d2) which defines an outer frame and a housing region; a molding outer surface (60d1) which is provided on the outer side of the molding inner surface (60d2), and in which an injection port (60da) that is in communication with the molding space (61a) is formed so as to be inwardly separated from each end in a plan view; and a molding bottom surface (60d3) which connects the molding inner surface (60d2) and the molding outer surface (60d1) to each other, and is in contact with the lower surface of the outer frame. A mold pin part (62) is disposed at a corner part of the molding space (61a) in a plan view so as to be perpendicular to the molding bottom surface (60d3). During an injection step, a rod-shaped second mold component (64) is disposed in parallel to the mold pin part (62) at a position between the mold pin part (62) and the injection port (60da) in the molding space (61a) in a plan view, the position being closer to the molding inner surface (60d2) than to the molding outer surface (60d1).
H01L 23/08 - ConteneursScellements caractérisés par le matériau du conteneur ou par ses propriétés électriques le matériau étant un isolant électrique, p. ex. du verre
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
outoutout) at a predetermined position in a system interconnection system, and outputs a difference (P*outoutoutrefref) of the active power, the difference (P*outout), and the virtual synchronous generator function.
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
H02J 3/24 - Dispositions pour empêcher ou réduire les oscillations de puissance dans les réseaux
H02J 3/38 - Dispositions pour l’alimentation en parallèle d’un seul réseau, par plusieurs générateurs, convertisseurs ou transformateurs
78.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device comprising a transistor part and a diode part. The semiconductor device comprises: a plurality of trench portions that are provided on the front surface of a semiconductor substrate; a drift region, of a first conductivity type, that is provided on the semiconductor substrate; a base region, of a second conductivity type, that is provided above the drift region; an emitter region, of the first conductivity type, that is provided above the base region and has a doping concentration higher than that of the drift region; a first contact region, of the second conductivity type, that is provided in a mesa portion of the transistor part and has a doping concentration higher than that of the base region; an anode region, of the second conductivity type, that is provided above the drift region in the diode part; and a second contact region, of the second conductivity type, that is provided in a mesa portion of the diode part and has a doping concentration higher than that of the anode region. The amount per unit volume of the dopant of the second conductivity type in the mesa portion of the diode part is equal to or more than the amount per unit volume of the dopant of the second conductivity type in the mesa portion of the transistor part.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
This semiconductor device comprises a transistor portion and a diode portion, the semiconductor device comprising: a plurality of trench portions that are provided on a front surface of a semiconductor substrate and include a gate trench portion; a first-conductivity-type drift region that is provided on the semiconductor substrate; a second-conductivity-type base region that is provided above the drift region; a first-conductivity-type emitter region that is provided above the base region and has a doping concentration higher than that of the drift region; a first-conductivity-type first accumulation region that is provided above the base region and has a doping concentration higher than that of the drift region; and a second-conductivity-type contact region that is provided above the base region and has a doping concentration higher than that of the base region. The transistor portion includes a boundary mesa portion that is sandwiched between the plurality of trench portions and has a boundary region that is provided adjacent to the diode portion. The boundary region includes the emitter region that is provided in the boundary mesa portion, a first-conductivity-type second accumulation region that is provided in the boundary mesa portion and has a doping concentration higher than that of the first accumulation region, and the gate trench portion that is provided in contact with the boundary mesa portion.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
Provided is a semiconductor device with which it is possible to improve the reliability of insulation around a bonding wire. This semiconductor device comprises: a semiconductor chip (3) having a first main electrode (31) on the upper surface side and a second main electrode (33) on the lower surface side; a bonding wire (4b) connected to the first main electrode (31); an insulating layer (9b) covering the outer periphery of the bonding wire (4b); and a sealing member (7) for sealing the semiconductor chip (3), the bonding wire (4b) and the insulating layer (4b). The ratio of the Young's modulus of the insulating layer (9b) to the Young's modulus of the sealing member (7) is 10 or more.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
81.
SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SAME
Provided is a manufacturing method for a semiconductor device capable of suppressing deformation of a lead member that is caused by pressure application and suppressing occurrence of non-bonding between a semiconductor chip and a bonding layer. The manufacturing method for a semiconductor device comprises: a step for preparing a lead member (4) provided with a bonding part (41) and a beam part (42) contiguous from the bonding part (41); a step for preparing a pressure application jig (8) having an opening (8a); a step for disposing the bonding part (41) on a semiconductor chip (3) with a sintered material (2x) therebetween, the semiconductor chip being provided on a conductive layer (12a) of an insulation circuit substrate (1) which has an insulating plate (11) and the conductive layer (12a) provided on the insulating plate (11); a step for disposing the pressure application jig (8) on the bonding part (41), the sintered material (2x), the semiconductor chip (3), and the conductive layer (12a) such that the opening (8a) overlaps the beam part (42); and a step for applying pressure to and heating the bonding part (41), the sintered material (2x), the semiconductor chip (3), and the conductive layer (12a) by means of the pressure application jig (8).
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
The present invention reduces turn-on loss of a switching element. A semiconductor module (10) has: a terminal case (11) in which first and second input terminals (11a1, 11a2) are disposed on a first short-side section (11a), and a second control terminal (11d1) and a second auxiliary terminal (11d2) are disposed on a second long-side section (11d); a first insulating circuit board (13a) disposed on the side of the second short-side section (11b) of the terminal case (11); and a second insulating circuit board (13b) disposed on the side of the first short-side section (11a). A fifth metal pattern (15b2) extending in the longitudinal direction of the terminal case (11) is provided on the front surface of the second insulating circuit board (13b). The semiconductor module (10) further includes a first wiring member (16a) having one end connected to a position on a fifth metal pattern (15b) further from the first short-side section (11a) than a position half the length of the second insulating circuit board (13b) in the longitudinal direction, and having the other end connected to the second auxiliary terminal (11d2).
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
The present invention provides a semiconductor device in which separation at an interface between a sintered bonding layer and a sealing resin can be prevented, and with which service life variability can be reduced. The semiconductor device is provided with: a conductive plate (11a) that has a main surface; a semiconductor chip (3) that is disposed so as to face the main surface of the conductive plate (11a); a sintered bonding layer (2a) that is disposed between the conductive plate (11a) and the semiconductor chip (3); a sealing resin (72) that seals the semiconductor chip (3) and the sintered bonding layer (2a); and a primer layer (71) that is disposed between the sintered bonding layer (2a) and the sealing resin (72). A first outer edge (21) of a bonding interface between the sintered bonding layer (2a) and the conductive plate (11a) is located inside an outer periphery of the semiconductor chip (3) and inside a second outer edge of a bonding interface between the sintered bonding layer (2a) and the semiconductor chip.
Provided is a semiconductor device comprising a transistor part and a diode part, the semiconductor device including: a plurality of trench parts provided on a front surface of a semiconductor substrate; a first conductivity-type drift region provided on the semiconductor substrate; a second conductivity-type base region provided above the drift region; a first conductivity-type emitter region provided above the base region and having a doping concentration higher than that of the drift region; a second conductivity-type contact region provided above the base region and having a doping concentration higher than that of the base region; an implantation suppression region provided on the front surface of the semiconductor substrate; and an emitter electrode provided above the semiconductor substrate, in which the transistor part has a main region for performing a transistor operation, and the implantation suppression region is provided in the main region of the transistor part.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
The present invention suppresses the occurrence of damage to a bonding member for bonding a semiconductor chip to a wiring board. A semiconductor device comprises: a semiconductor chip (12); and an insulating circuit board (11) that has a wiring board (11b2) on a front surface, has a rear surface facing downward, and is bent to protrude downward, with the semiconductor chip (12) being bonded via a bonding member (14a) to a bonding region on an upper surface of the wiring board (11b2) which is inclined on the front surface due to the bending. The semiconductor chip (12) is bonded to the bonding region, with an end of the rear surface of the semiconductor chip (12) on the side of an apex (16b) of the bent section of the insulating circuit board (11) being supported by a support part (15) provided in the bonding region. Therein, the semiconductor chip (12) is made substantially parallel to the bonding region of the wiring board (11b2) by the support part (15), and the thickness of the bonding member (14a) is substantially uniform. Due to this configuration, the occurrence of cracks in the bonding member (14a) is reduced.
H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
This power conversion device, which can be interconnected to a power system, has a virtual synchronous generator function. The power conversion device comprises: a frequency feedback unit that calculates a prescribed transfer function for a frequency of the virtual synchronous generator function or a voltage at an interconnection point with the power system, and then outputs a processing result to which upper and lower limits are applied; an addition unit that outputs a second amplitude command value obtained by adding the processing result and a prescribed first amplitude command value relating to the voltage at the interconnection point; an interconnection point voltage amplitude control unit that generates an inverter output voltage amplitude command value on the basis of the second amplitude command value and the amplitude of the voltage at the interconnection point; a voltage output unit that generates a three-phase AC voltage on the basis of the phase in the virtual synchronous generator function and the inverter output voltage amplitude command value; and an independent operation detection unit that detects that the power conversion device is in an independent operation state of being separated from the power system if the processing result has reached the upper/lower limit. The transfer function has at least a secondary polynomial of a Laplace operator in the denominator and a primary monomial of the Laplace operator in the numerator. With respect to the denominator of a closed-loop transfer function in which a phase change as the output of a virtual synchronous generator having an effective power as an input, a voltage amplitude change as the result of calculating a prescribed transfer function having the frequency of the virtual synchronous generator or the interconnection point voltage frequency as an input, and an effective power change due to the phase change and the voltage amplitude change are consolidated and considered one closed loop system, the coefficients in the polynomial and the monomial are given so that the denominator becomes a stable polynomial if the power conversion device is interconnected with the power system, and becomes an unstable polynomial if the power conversion device is operating independently.
H02J 3/38 - Dispositions pour l’alimentation en parallèle d’un seul réseau, par plusieurs générateurs, convertisseurs ou transformateurs
H02J 3/32 - Dispositions pour l'équilibrage de charge dans un réseau par emmagasinage d'énergie utilisant des batteries avec moyens de conversion
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
87.
HEAT DISSIPATION BASE, SEMICONDUCTOR MODULE AND ENERGY CONVERSION DEVICE
According to the present invention, a wiring board is prevented from being damaged by deformation of a heat dissipation base to which the wiring board is joined. This heat dissipation base (3) has a first surface to which a wiring board (4) is joined and a second surface which faces a cooler (10), and the second surface has a convex curved surface that has a substantially rectangular shape having a side extending in a first direction and another side extending in a second direction when viewed in plan view. When the second surface is directed downward, a first curve representing the shape of the second surface on a first straight line passing through the center of the second surface and extending in the first direction, and a second curve representing the shape of the second surface on a second straight line passing through the center of the second surface and extending in the second direction are each represented by a curve which includes end parts and the shape change of which in a direction from the end parts toward the center has a downward convex shape, while a third curve representing the shape of the second surface on a straight line in a diagonal direction is represented by a curve which includes end parts and the shape change of which in a direction from the end parts toward the center has an upward convex shape, and a curve which includes the center and the shape change of which in a direction from the center toward the end parts has a downward convex shape.
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/40 - Supports ou moyens de fixation pour les dispositifs de refroidissement ou de chauffage amovibles
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
88.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device equipped with a transistor and a diode comprises: a plurality of trenches which include a gate trench and which are provided to the front surface of a semiconductor substrate; a first-conductivity type drift region provided to the semiconductor substrate; a second-conductivity type base region provided above the drift region; a first-conductivity type emitter region which is provided above the base region and which is higher in doping concentration as compared to the drift region; a first-conductivity type first storage region which is provided below the base region and which is higher in doping concentration as compared to the drift region; a second-conductivity type trench bottom region which is provided below the first storage region and which is higher in doping concentration as compared to the base region; and a first-conductivity type second storage region which is provided deeper than the trench bottom region in the depth direction of the semiconductor substrate and which is higher in doping concentration as compared to the drift region.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
This power conversion apparatus is linked to a power system and operates as a virtual synchronization power generator. In the power conversion apparatus, a control device which is for controlling a voltage to be outputted from a power conversion unit: generates a first current command value, which is an output current command value of the power conversion apparatus, on the basis of an amplitude command value of an output voltage, a frequency command value of the output voltage, and an output voltage and an output current outputted to the power system; generates a second current command value obtained by limiting the first current command value to an upper limit value when the first current command value exceeds the upper limit value; and sets the second current command value to be an output current command value to be outputted from the power conversion apparatus.
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
The present invention provides a gas analysis device that can analyze a plurality of types of gases simultaneously. A gas analysis device (100) comprises: a light-emitting unit (10) that emits infrared light; a plurality of gas filters (21a)–(21d) that transmit light from the light-emitting unit (10) and encapsulate a plurality of high-purity gases to be measured and one gas that does not absorb infrared light; a gas filter wheel (20) in which the plurality of gas filters (21a)–(21d) are stored and which has a rotation mechanism (30); a sample gas cell (40) into which light transmitted through the gas filters (21a)–(21d) enters and through which a gas containing a gas to be measured flows; and a light-receiving unit (50) that receives infrared light transmitted through the sample gas cell (40).
G01N 21/3518 - Dispositifs utilisant des techniques de corrélation à filtres de gazDispositifs utilisant des techniques de modulation de la pression des gaz
The present invention addresses the problem of simplifying processes and easing restrictions on molding. The present invention provides a method for molding an insulating spacer (10) which comprises a cone-shaped spacer cone part (12) that is provided around a center conductor (11) so as to support the center conductor. In this molding method, a casting mold (31) that comprises a lower mold (32) and an upper mold (34), which form a cavity (33) that has a shape corresponding to the insulating spacer, and a nozzle (41) for injecting a resin material into the cavity are used. This molding method executes a stacking step for stacking a plurality of resin layers by repeatedly performing a pre-injection moving step, an injection step and a post-injection moving step. In the pre-injection moving step, the nozzle is inserted into the cavity by moving the casting mold in a state where the nozzle is stopped. In the injection step, the resin material is injected into the cavity from the nozzle. In the post-injection moving step, the nozzle is taken out from the cavity by moving the casting mold in a state where the nozzle is stopped.
B29C 39/10 - Moulage par coulée, c.-à-d. en introduisant la matière à mouler dans un moule ou entre des surfaces enveloppantes sans pression significative de moulageAppareils à cet effet pour la fabrication d'objets de longueur définie, c.-à-d. d'objets séparés en incorporant des parties ou des couches préformées, p. ex. coulée autour d'inserts ou sur des objets à recouvrir
One embodiment of the present invention is a removal method for removing deposited scale precipitated from a geothermal fluid containing dissolved silica in a geothermal power plant comprising a water pump that pumps the geothermal fluid from a production well, a steam separator that separates the geothermal fluid into geothermal water and geothermal steam, and a turbine that rotates as a result of being supplied with the geothermal steam separated by the steam separator, wherein in a first area leading to the turbine from the production well, the surfaces of sites in the geothermal plant that are in contact with the geothermal fluid are formed from diamond-like carbon, in areas other than the first area, at least the surfaces of such sites in the geothermal power plant are formed from at least one substance selected from among diamond-like carbon, polytetrafluoroethylene, and polyvinyl chloride, and a scale removal liquid is injected into a flow path that includes the surfaces of such sites.
NATIONAL UNIVERSITY CORPORATION TOKAI NATIONAL HIGHER EDUCATION AND RESEARCH SYSTEM (Japon)
Inventeur(s)
Nakashima, Yuya
Murakami, Kouhei
Kousaka, Hiroyuki
Umehara, Noritsugu
Tokoroyama, Takayuki
Abrégé
Provided is a steam turbine member that suppresses the adhesion of scales over a long period of time without impairing the corrosion resistance or the like of a turbine. A method for manufacturing a coated tubular member having an amorphous carbon deposition film m formed on the inner surface of a tubular member 1, the method comprising: a step for attaching lids 2, 3 to one end 12 and the other end 11 of the tubular member 1, the lids having openings 21, 31 through which gas can be introduced and discharged; a step for discharging the gas from inside the tubular member 1 through the opening 31 of the lid 3 at the one end 12 to reduce the pressure inside the tubular member 1; a step for applying a negative voltage to the tubular member 1, introducing a plasma-forming gas g into the tubular member 1 through the opening 21 of the lid 2 at the other end 11 to generate plasma inside the tubular member 1; and a step for introducing a raw material gas g for an amorphous carbon deposition film into the tubular member 1 through the opening 21 of the lid 2 at the other end 11.
C23C 16/50 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement au moyen de décharges électriques
Provided is a power conversion device that supplies power to a power system via a filter including a reactor and a capacitor, the power conversion device including: a first subtraction unit that calculates a first difference between the measured value of a first current flowing in the reactor and a current command value for the first current, the current command value being for setting the voltage of the capacitor to a target voltage; an addition unit that adds a value corresponding to the first difference and a voltage command value for the voltage of the capacitor; and a voltage output unit that outputs to the filter an output voltage corresponding to the addition result of the addition unit.
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
95.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Provided is a semiconductor device having a MOS gate structure, the semiconductor device comprising: a base layer provided on the front surface of a semiconductor substrate or above the semiconductor substrate; an interlayer insulating film provided above the base layer; a contact hole provided in the interlayer insulating film and reaching the base layer from the upper surface of the interlayer insulating film; a first alloy layer provided on the bottom part of the contact hole; and a second alloy layer provided on the side wall of the contact hole. Further provided is a semiconductor device manufacturing method comprising: a step for forming an initial polycrystalline film and a first initial metal film on the inner wall of the contact hole; and a step for heating the semiconductor substrate to form a first alloy layer on the bottom part of the contact hole, and to form a second alloy layer on the side wall of the contact hole.
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
One aspect of the present invention is a method for selecting a pipe material to be used for a pipe through which a geothermal fluid containing a monomer or a 2- to 4-mer of ortho-silicic acid is passed in a geothermal power plant. The method includes: comparing the molecular orbital energy levels of at least two resin materials having mutually different compositions or chemical structures to predict the adhesiveness of the resin materials to the monomer or the 2- to 4-mer of ortho-silicic acid; and selecting a resin material, which is selected on the basis of the adhesiveness, as a pipe material with which the adhesion of silica scales precipitated from the geothermal fluid is reduced.
The present invention provides a semiconductor device which is provided with a semiconductor substrate, wherein: the semiconductor substrate comprises transistor parts and diode parts, which are alternately arranged in a first direction and are long in a second direction, and current sense parts that are arranged so as to face the transistor parts in the second direction; the transistor parts, the diode parts and the current sense parts each have a drift region that has a first conductivity type and a base region that has a second conductivity type and is provided between the drift region and an upper surface of the semiconductor substrate; when viewed from above, the current sense parts are each surrounded by a sense well region that has the second conductivity type and has a higher concentration than the base region, and that is formed deeper from the upper surface than the base region; and in the first direction, the width of the sense well region is greater than the width of the transistor parts that face the current sense parts.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/41 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
The present invention provides a semiconductor device which is provided with a transistor part and a diode part that is disposed to be side by side with the transistor part. In the semiconductor device: the transistor part has a first contact part in which a first mesa part among a plurality of mesa parts and a metal electrode are in contact with each other, and a second contact part in which a second mesa part among the plurality of mesa parts and a metal electrode are in contact with each other, the second mesa part being disposed to be more distant from the diode part than the first mesa part; and the lower end of the second contact part is positioned above the lower end of the first contact part.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
Provided is a semiconductor device comprising diode units that are arranged lined up with transistor units, wherein the transistor units have a first contact portion with which a metal electrode and a first mesa portion among a plurality of mesa portions are in contact, and a second contact portion with which a metal electrode and a second mesa portion that is positioned away from the first mesa portion among the plurality of mesa portions are in contact, a lower end of the first contact portion being positioned above a lower end of the second contact portion.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
The present invention provides a semiconductor device that is provided with a transistor part and a diode part, which are arranged to be side by side in a first direction. This semiconductor device comprises a first mesa part and a second mesa part that is disposed to be more distant from the diode part than the first mesa part. The first mesa part has a first region which has a first conductivity type and is at least partially provided between the depth position of the lower end of the base region and the depth position of the lower end of the trench part. The second mesa part has a second region which has the first conductivity type and a higher dose than the first region, and is at least partially provided between the depth position of the lower end of the base region and the depth position of the lower end of the trench part.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
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