Abrégé

A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
• G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul

Abrégé

A hybrid type content addressable memory for implementing in-memory-search and an operation method thereof are provided. The CAM includes a plurality of CAM strings and at least one sense amplifier circuit. Each of the CAM strings includes a plurality of CAM cells. The CAM cells store a plurality of existing data. The sense amplifier circuit is connected to the CAM strings. A plurality of search data are inputted to the CAM strings. A plurality of cell matching results obtained from the CAM cells in each of the CAM strings are integrated via an AND operation to obtain a string matching result. The string matching results obtained from the CAM strings are integrated via an OR operation.

Classes IPC  ?

• G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristique utilisant des éléments semi-conducteurs

Abrégé

A semiconductor integrated circuit, a semiconductor device and a method for aligning semiconductor integrated circuits are provided. The semiconductor integrated circuit includes a substrate and an overlay mark structure in the substrate. The overlay mark structure includes first overlay marks and second overlay marks separated from each other. A first mark width of the first overlay marks is smaller than a second mark width of the second overlay marks.

Classes IPC  ?

• H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p.ex. marques de repérage, schémas de test
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

An in memory searching device, including multiple first memory cell strings, a controller, and a sensing circuit, is provided. The first memory cell strings are commonly coupled to a first common bit line. Each of the first memory strings includes multiple first data storage layers. The first data storage layers respectively include multiple first memory cell pairs. The first memory cell pairs are respectively coupled to multiple first word line pairs. The controller selects at least one of the first data storage layers to be at least one selected data storage layer, and provides search data to at least one selected word line pair corresponding to the at least one selected data storage layer. The sensing circuit senses a current on the first common bit line to generate a search result.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/408 - Circuits d'adressage
• G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits

Abrégé

A memory erase method for a memory device and a memory device therefore are provided. The memory device is a 3D NAND flash with high capacity and high performance. The memory erase method includes following steps: providing a memory block, wherein the memory block comprises memory cell strings, the memory cell strings include memory cells, string selection transistors and ground selection transistors; respectively applying corresponding erase voltages to corresponding word lines, a common source line, a corresponding bit line, the string selection transistor and the ground selection transistor of each of the memory cell strings. The voltage difference between a bit line erase voltage and a string selection line erase voltage or the voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells of the memory cell strings randomly classified as a type-1 erase bit or a type-2 erase bit.

Classes IPC  ?

• G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention

Abrégé

A memory device and a read method therefor are disclosed. The memory device includes first to third memory cell strings. The memory device is a three-dimensional NAND flash memory with high capacity and high performance. Each of the memory cell strings includes first to third memory cells. The read method includes: performing a first read operation of the memory device to the second memory cell in the second memory cell string, the first read operation includes applying a first bit line voltage to a first bit line, a second bit line, and a third bit line; in response to the failure of the first read operation, performing a second read operation of the memory device, the second read operation includes: applying a set of second bit line voltages to the first bit line, the second bit line and the third bit line.

Classes IPC  ?

• G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

Classes IPC  ?

• G11C 7/24 - Circuits de protection ou de sécurité pour cellules de mémoire, p.ex. dispositions pour empêcher la lecture ou l'écriture par inadvertance; Cellules d'état; Cellules de test
• G06F 21/44 - Authentification de programme ou de dispositif
• H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système

Abrégé

Electronic circuits, memory devices, and methods for compensating for data distortion from channel loss are provided. In one aspect, an electronic circuit includes a converter circuit configured to convert an input signal to a digital signal and a compensation circuit coupled to the converter circuit. The converter circuit includes a sampling circuit configured to receive the digital signal and generate an output signal. The output signal includes a stream of bits to be transmitted at a plurality of consecutive clock cycles. The converter circuit also includes one or more equalizing circuits coupled to the sampling circuit. Each equalizing circuit is configured to receive a bit of an output feedback signal at one of the consecutive clock cycles. The sampling circuit is configured to generate the output signal based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits.

Classes IPC  ?

• G11B 20/10 - Enregistrement ou reproduction numériques
• G11B 20/14 - Enregistrement ou reproduction numériques utilisant des codes auto-synchronisés

Abrégé

A 3D bit cost scalable memory device includes a stack of layers and a via electrode extending vertically through the stack of layers. The layers include a controllable conductivity layer and an electrode layer. The electrode layer has a conductor portion and a separator portion that separates the via electrode from the conductor portion of the electrode layer. At least a storage portion of the controllable conductivity layer is in electrical series between the via electrode and the conductor portion of the electrode layer. The via electrode comprises, for example, tungsten (W). The controllable conductivity layer comprises, for example, an ovonic threshold switch material. The conductor portion of the electrode layer comprises, for example, carbon (C).

Classes IPC  ?

• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]

Abrégé

A system having a data bus, a source node device on the data bus and a group of bus node devices on the data bus. The source node device is configured to transmit a group read status command on the data bus. The bus node devices in the group are configured to respond to the group read status command in sequence, by transmitting status data on the data bus in respective, non-overlapping timing windows. The system can be a memory system.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S

Abrégé

A non-volatile memory and a programming method thereof are provided. The programming method includes: performing a reading operation on a plurality of first memory cells of an Nth word line, and determining whether an equivalent threshold voltage is greater than a preset threshold value to generate a determination result, where N is a positive integer greater than 0; and in response to performing a programming operation on a plurality of second memory cells of an N+1th word line, deciding whether to adjust at least one selected programming verification voltage of a plurality of programming verification voltages by an offset value according to the determination result.

Classes IPC  ?

• G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

A memory device includes a substrate, a composite stacked structure, multiple first insulating structures, and multiple through vias. The substrate includes a memory plane region and a periphery region. The composite stacked structure is located on the substrate in the memory plane region and the periphery region, wherein the composite stacked structure includes a first stacked structure. The first stacked structure includes multiple first insulating layers and multiple intermediate layers alternately stacked on each other, and is located on the substrate in the periphery region. The first insulating structures are separated from each other, extend through the first stacked structure in the periphery region, and are respectively surrounded by the first insulating layers and the intermediate layers. The through vias extend through one of the first insulating structures.

Classes IPC  ?

• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/528 - Configuration de la structure d'interconnexion
• H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U

Abrégé

A memory cell circuit, a memory cell array structure and a manufacturing method thereof are provided. The memory cell circuit includes a first transistor, a second transistor and a capacitor. The first transistor has a first end electrically coupled to a bit line, and a gate of the first transistor is electrically coupled to a primary word line. The second transistor has a first end electrically coupled to a second end of the first transistor, and a gate of the second transistor is electrically coupled to an auxiliary word line. A first end of the capacitor is electrically coupled to a second end of the second transistor and a second end of the capacitor receives a reference voltage.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage

Abrégé

A memory device based on thyristors, comprises the following elements. A plurality of gate structures, are continuous structures in the first direction. A plurality of bit lines, extending in a second direction substantially perpendicular to the first direction. A plurality of source lines, extending in the first direction. A plurality of channels, extending in a third direction substantially perpendicular to the first direction and the second direction, and penetrating the gate structures. The first doped regions of the channels are coupled to the bit lines, and the second doped regions of the channels are coupled to the source lines. A plurality of memory units formed by the gate structures and corresponding channels. The source lines are arranged in sequence according to the second direction to form a stair structure, and the lengths of the source lines decrease in sequence in the first direction.

Classes IPC  ?

• H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• G11C 11/39 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des thyristors
• H01L 29/74 - Dispositifs du type thyristor, p.ex. avec un fonctionnement par régénération à quatre zones

Abrégé

The semiconductor device includes a substrate, a stack disposed on the substrate, a first common source line and a second common source line disposed in the stack and connected to the substrate. The stack includes insulating layers and conductive layers alternately arranged. The first common source line and the second common source line are extended along a first direction and are arranged in a second direction that is perpendicular to the first direction. The first common source line includes a first segment and a second segment spaced apart by a first common source line cut. The second common source line includes a third segment and a fourth segment spaced apart by a second common source line cut. The first common source line cut is shifted relative to the second common source line cut in the first direction. A method of forming the semiconductor device is also disclosed.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U

Abrégé

A memory device includes a substrate and first to fourth tiers. The first tier is located on the substrate and includes first transistors and second transistors. The first transistors includes multiple groups. The second tier includes a composite stack structure. The third tier includes local bit lines and local source lines. Each of the local bit lines is connected to a first terminal of one of the first transistors. Each of the local source lines is connected to a first terminal of one of the second transistors. The fourth tier includes multiple global bit lines and a common source line. Each of the global bit lines is connected to second terminals of the first transistors in one of the groups. The common source line is connected to a second terminal of each of the second transistors. Embodiments of the present disclosure may be applied to a 3D AND flash memory.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

An integrated circuit includes a memory and peripheral circuits with a temperature sensor used to automatically adjust operating voltages. The temperature sensor includes a reference circuit that generates a first reference with a first non-zero temperature coefficient and a second reference with a second temperature coefficient having a different magnitude than the first non-zero temperature coefficient. A detector circuit on the integrated circuit, having temperature and process variation compensation, converts a difference between the first and second references into a digital signal indicating temperature on the integrated circuit.

Classes IPC  ?

• G01K 7/42 - Circuits pour la compensation de l’inertie thermique; Circuits pour prévoir la valeur stationnaire de la température
• H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
• H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique

Abrégé

Systems, methods, and apparatus including computer-readable mediums for managing error corrections for memory systems are provided. In one aspect, a memory system includes a memory and a memory controller coupled to the memory. The memory controller is configured to: read data from a data page of the memory, perform a first phase Error-Correcting Code (ECC) test on the read data based on first ECC data associated with the data, and in response to determining that the read data fails to pass the first phase ECC test, perform a second phase ECC test on a portion of the read data based on second ECC data. The first ECC data is stored together with the data in the data page. The second ECC data is associated with a portion of the data corresponding to the portion of the read data, and stored in a redundancy page different from the data page.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
• G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p.ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange

Abrégé

The application discloses a semiconductor memory device and a data storage method. When determining that an input data conforms to a target format, an input data vector is generated based on the input data. When determining that the input data is similar to a stored data in a target block of the memory array, the input data is written to a blank target memory page of the target block of the memory array.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A memory array is arranged to store data words in respective sets of TCAM cells, where each TCAM cell is configured to store ternary states of a bit of the stored word. A circuit to select a set of TCAM cells in the set of TCAM cells, such as decoders and drivers for word lines, bit lines, block select gates. A circuit to apply an input search word to the TCAM cells in the selected set of TCAM cells, such as a search word buffer or driver on one of word lines or bit lines for the array. A circuit to generate an output indicating similarity of the stored word in the selected set of TCAM cells to the input search word, based on mismatch or possible mismatch of more than one bit of the search word.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 7/12 - Circuits de commande de lignes de bits, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
• G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
• G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristique utilisant des éléments semi-conducteurs

Abrégé

The application provides a content addressable memory (CAM) device and a method for searching and comparing data thereof. The CAM device comprises: a plurality of memory strings; and a sensing amplifier circuit coupled to the memory strings; wherein in data searching, a search data is compared with a storage data stored in the memory strings, the memory strings generate a plurality of string currents, the sensing amplifier circuit senses the string currents to generate a plurality of sensing results; based on the sensing results, a match degree between the search data and the storage data is determined as one of the follows: all-matched, partially-matched and all-mismatched.

Classes IPC  ?

• G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristique utilisant des éléments semi-conducteurs
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

An array of memory cells includes a resistive component disposed in thermal communication with a group of memory cells in the array of memory cells. A capacitor and a circuit to cause discharge of the capacitor via the resistive component induces thermal anneal of the group of memory cells. A charge pump and a circuit to enable the charge pump to precharge the capacitor can be used. The charge pump, the capacitor and the array of memory cells can be disposed on a single integrated circuit. The group of memory cells can be arranged in a 3D stack having multiple levels, and the resistive component can be “snaked” through the stack. The thermal anneal can be executing in timing coordination with erase operations in flash memory.

Classes IPC  ?

• G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
• G11C 16/16 - Circuits pour effacer électriquement, p.ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p.ex. des réseaux, des mots, des groupes
• G11C 16/30 - Circuits d'alimentation

Abrégé

A memory device, such as a three-dimensional AND or NOR flash memory, includes a first chip and a second chip. The first chip has multiple source line switches, multiple bit line switches, multiple page buffers, and multiple sensing amplifiers. The first chip has multiple first pads. The second chip has multiple memory cells to form multiple memory cell blocks. Multiple second pads are on a first surface of the second chip to be respectively coupled to multiple local bit lines and multiple local source lines of the memory cell blocks. Each of the first pads is coupled to the corresponding second pads.

Classes IPC  ?

• G11C 7/06 - Amplificateurs de lecture; Circuits associés
• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
• H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
• H10B 43/20 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
• H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

A 3D search engine receives searches for application to word lines of a nonvolatile memory array. The engine uses two word lines per bit of information of the searches and two memory devices per bit of stored feature to search against, optionally enabling don't care and/or wildcard encoding. The engine uses respective bit lines of the nonvolatile memory array as respective matching lines for searching. Respective memory strings (e.g., NAND memory strings) of the nonvolatile memory array are usable to store respective data words, e.g., corresponding to features to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. Various encodings of features and searches enable exact, approximate, and range matching. The engine has applicability to comparing and sorting, in addition to searching in application areas such as artificial intelligence (AI) and big data.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectation; Réadressage

Abrégé

A memory device is provided and includes a memory array. The memory array includes multiple strings, each of the strings including multiple memory cells and at least one compensation cell that are coupled in series to a corresponding one of multiple bit lines. In a read operation, the at least one compensation cell in each of the strings has a resistance responsive to at least one compensation voltage applied on the at least one compensation cell to adjust a read current in the corresponding bit line to a current value. The resistance is associated with a number of programmed cells in the memory cells coupled to the corresponding bit line.

Classes IPC  ?

• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
• G11C 7/02 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les signaux parasites
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/30 - Circuits d'alimentation

Abrégé

A memory device includes a stacked structure including conductive layers and first insulating layers alternately stacked along a first direction; a first array region; a second array region; and a connection region disposed between the first array region and the second array region, and including a staircase region, an unprocessed region, a top isolating member and a common wall, wherein the unprocessed region extends along the first direction, the staircase region is adjacent to a first side of the unprocessed region, the common wall is adjacent to a second side of the unprocessed region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region. The top isolating member extends along the first direction to separate the conductive layers disposed in a top portion of the stacked structure.

Classes IPC  ?

• H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p.ex. structures d'interconnexions enterrées
• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique

Abrégé

An integrated circuit structure includes a substrate, a first memory string, a source line, and a second memory string. The first memory string is over the substrate and comprises first memory cells stacked in a vertical direction. The source line laterally extends over the first memory string. The second memory string is over the source line and comprises second memory cells stacked in the vertical direction.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/528 - Configuration de la structure d'interconnexion
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET

Abrégé

A semiconductor device includes a staircase structure and an extension part. The stacked structure is located on a dielectric substrate. The staircase structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The extension part is located at an end of the lower stair part of the staircase structure. The resistance value of the extension part is different from the resistance value of the plurality of conductive layers.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U

Abrégé

A memory device for performing an in-memory computation, comprising a plurality of memory cells each stores a weight value and comprises a transistor and a resistor. A gate of the transistor receives an input voltage, the input voltage indicates an input value. When the transistor operates at a first operating point, the input voltage is equal to a first input voltage, when the transistor operates at a second operating point, the input voltage is equal to a second input voltage. The resistor is connected to a drain and a source of the transistor, when the resistor operates in a first state, the weight value is equal to a first weight value, when the resistor operates in a second state, the weight value is equal to a second weight value. Each of the memory cells performs a product computation of the input value and the weight value.

Classes IPC  ?

• G11C 17/18 - Circuits auxiliaires, p.ex. pour l'écriture dans la mémoire
• G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
• G11C 17/16 - Mémoires mortes programmables une seule fois; Mémoires semi-permanentes, p.ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p.ex. mémoires PROM utilisant des liaisons électriquement fusibles

Abrégé

An AI inference platform comprises a logic die including an array of AI processing elements. Each AI processing element including an activation memory storing activation data for use in neural network computations. The platform includes a memory die that includes an array of 3D memory cells and a page buffer that facilitates storage and retrieval of neural network weights for use in neural network computations. A plurality of vertical connections can directly connect AI processing elements in the logic die and page buffers of corresponding ones of the memory cells in the memory die, enabling storage or retrieval of a neural network weight to and from a particular page buffer of a corresponding 3D memory cell for use in neural network computations conducted by a corresponding AI processing element in the logic die.

Classes IPC  ?

• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
• G06N 3/048 - Fonctions d’activation

Abrégé

A system based on computational memory and memory systems, such as embodied in computational solid state drive (SSD) technology, as described herein, reduces processor utilization and/or bus bandwidth utilization. The system is enabled to perform computational techniques (e.g., searching, computing, and/or accessing) using resources of the computational SSDs, rather than processor and/or bus resources, thus reducing or minimizing information movement between processing elements and storage devices. Computational SSD technology enables managing, organizing, selecting, and analyzing ever increasing data volume in real time. A computational SSD is enabled to store and to operate on data locally, e.g., using resources of the computational SSD. Thus, processing, storage, and bandwidth requirements of a system are reduced by using the computational SSD.

Classes IPC  ?

• G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

A memory device and a reading method thereof are provided. A second word line and a third word line are adjacent to a first word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells of the first word line. When a read error occurs, a re-read procedure is executed for some of the memory cells belonging to a state marginal group. The read procedure includes: applying a read voltage to the first word line; applying a first pass voltage to the second word line and the third word line. The re-read procedure includes: applying the read voltage to the first word line; applying a second pass voltage and a third pass voltage different from the first pass voltage to the second word line and the third word line respectively.

Classes IPC  ?

• G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
• G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
• G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires

Abrégé

A memory device and a reading method thereof are provided. The memory device at least includes a first word line, a second word line and a third word line. The reading method includes the following steps. A read procedure is executed to read a plurality of memory cells connected to the first word line. A recognition procedure is executed in response to at least one memory cell has an error. A re-read procedure is executed on the memory cell. The recognition procedure includes: applying a pass voltage to the first word line; applying a recognition voltage to at least one of the second word line and the third word line. The re-read procedure including: applying a second read voltage to the first word line; and applying a second pass voltage to the second word line and a third pass voltage to the third word line.

Classes IPC  ?

• G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p.ex. compteurs de rafraîchissement défectueux
• G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
• G11C 29/52 - Protection du contenu des mémoires; Détection d'erreurs dans le contenu des mémoires

Abrégé

Methods, systems and apparatus for three-dimensional (3D) memory devices are provided. In one aspect, a semiconductor device includes: an array-side structure and a device-side structure. The array-side structure includes a memory array of memory cells and an array-side integrated circuit conductively coupled to the memory array. The device-side structure includes a device-side integrated circuit. The array-side structure and the device-side structure are integrated together with one or more connection pads therebetween. The array-side integrated circuit and the device-side integrated circuit are conductively coupled to each other through at least one of the one or more connection pads and configured to perform one or more operations on the memory array.

Classes IPC  ?

• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique

Abrégé

The application provides a panoramic perception method, system and a non-transitory computer readable medium. The panoramic perception method comprises: performing a first pretraining on a plurality of weights of a training model using the source database; performing a second pretraining with data augmentation on the plurality of weights of the training model using the source database; performing a combined training on the plurality of weights of the training model using both the source database and the target database; performing a quantization-aware training on the plurality of weights of the training model using the source database and the target database; performing a post training quantization on the plurality of weights of the training model using the target database; and performing panoramic perception by the training model.

Classes IPC  ?

• G06N 3/0495 - Réseaux quantifiés; Réseaux parcimonieux; Réseaux compressés
• G06N 3/08 - Méthodes d'apprentissage
• G06V 20/58 - Reconnaissance d’objets en mouvement ou d’obstacles, p.ex. véhicules ou piétons; Reconnaissance des objets de la circulation, p.ex. signalisation routière, feux de signalisation ou routes

Abrégé

The application discloses an integrated memory device, a manufacturing method and an operation method thereof. The integrated memory cell includes: a first memory cell; and an embedded second memory cell, serially coupled to the first memory cell, wherein the embedded second memory cell is formed on any one of a first side and a second side of the first memory cell.

Classes IPC  ?

• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

The application provides a content addressable memory (CAM) cell, a CAM memory device and an operation method thereof, and a method for searching and comparing data. The CAM cell includes a first flash memory cell having a first terminal for receiving a first search voltage; and a second flash memory cell having a first terminal for receiving a second search voltage, a second terminal of the first flash memory cell electrically connected to a second terminal of the second flash memory cell, wherein the first flash memory cell and the second flash memory cell are serially connected; and a storage data of the CAM cell is based on a combination of a plurality of threshold voltages of the first flash memory cell and the second flash memory cell.

Classes IPC  ?

• G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristique utilisant des éléments semi-conducteurs
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

A memory device and a method for manufacturing the same are provided. The memory device includes drain pillar structures, source pillar structures, memory structures surrounding the drain pillar structures respectively, a channel structure, and a gate structure surrounding the drain pillar structures, the source pillar structures and the channel structure. The channel structure is divided into arc channel parts by the drain pillar structures and the source pillar structures.

Classes IPC  ?

• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]
• H10B 61/00 - Dispositifs de mémoire magnétique, p.ex. dispositifs RAM magnéto-résistifs [MRAM]

Abrégé

An electronic device is provided. The electronic device comprises a computational memory. The computational memory comprises a first memory array and a second memory array. The first memory array and the second memory array contain same data. The first memory array and the second memory array are configured to perform operations in an out of phase manner.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S

Abrégé

A storage system capable of executing data processing, includes the following elements. A first control unit of a storage device, for cooperating with a sequencer to perform a clustering process on a plurality of original sequences to obtain a plurality of read sequences, generating a plurality of read binary vectors corresponding to the read sequences, and generating a pruned filtering binary vector according to a reference sequence. A first storage module of the storage device, for storing the read binary vectors and the pruned filtering binary vector, and executing an in-memory computing (IMC) according to the read binary vectors and the pruned filtering binary vector, so as to generate a filtered cluster read set. A processing device, for executing an aligning process according to the filtered cluster read set and the reference sequence.

Classes IPC  ?

• G11C 13/02 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou utilisant des éléments dont le fonctionnement dépend d'un changement chimique
• G16B 30/10 - Alignement de séquence; Recherche d’homologie
• G16B 50/30 - Entreposage de données; Architectures informatiques

Abrégé

A memory device and associated operation method are provided. The operation method is applied to the memory device to determine whether a search input and in-memory data are matched. The memory device includes a memory array and a control circuit, and the memory array includes M*N memory cells. The operation method includes the following steps. A select voltage is applied to an n-th word line. A pass-through voltage is applied to (N−1) word lines. A first search voltage is applied to an m-th first bit-line, and a second search voltage is applied to an m-th second bit-line. An m-th first sensing current and an m-th second sensing current bit are selectively generated. Then, a sensing circuit in the control circuit generates a sensing circuit output. The sensing circuit output represents whether the m-th first sensing current and the m-th second sensing current are generated.

Classes IPC  ?

• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

A memory device includes first and second interconnect structures, a stacked structure, a stop layer and channel pillar structures over a substrate. The stacked structure is located between the first and the second interconnection structures. The stop layer is located between the stacked structure and the second interconnect structure. Each channel pillar structure includes a channel pillar, a first channel plug and a second channel plug. The channel pillar extends through the stacked structure and the stop layer. The first channel plug is located at a first end of the channel pillar and connected to the first interconnection structure. The second channel plug is located at a second end of the channel pillar and connected to the second interconnection structure. A bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET

Abrégé

A memory device can be applied to a 3D AND flash memory. The memory device includes a substrate, a first stacked structure, a second stacked structure, a channel structure, an insulating pillar, a through via and a conductive layer. The substrate has a memory array region and a staircase region. The first stacked structure is disposed on the substrate in the memory array region and includes first dielectric layers and gates alternately stacked. The second stacked structure is disposed on the substrate in the staircase region and includes second dielectric layers and stairs alternately stacked. The channel structure penetrates through the first stacked structure in the memory array region. The insulating pillar penetrates through the second stacked structure in the staircase region. The through via penetrates through the insulating pillar in the staircase region. The conductive layer surrounds the sidewall of the insulating pillar.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p.ex. écrans Faraday

Abrégé

An in-memory computing memory device includes: a plurality of computing memory cells forming a plurality of memory strings, the computing memory cells storing a plurality of weight values; a loading capacitor; and a measurement circuit. In IMC operations, a plurality of input voltages, corresponding to a plurality of input values, are input into the computing memory cells; a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values; when a read voltage is applied to the plurality of computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents for charging the loading capacitor; and based a capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

A memory device includes a substrate, a plurality of conductive layers, a plurality of dielectric layers, a memory structure, a select gate structure and a bit line contact. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The memory structure penetrates through the conductive layers and the dielectric layers, and the memory structure includes a channel structure and a conductive plug disposed on the channel structure. The select gate structure is disposed on a sidewall of the memory structure. The select gate structure includes a select gate dielectric layer and a select gate electrode surrounded by the select gate dielectric layer. A top surface of the select gate electrode is between a top surface of the conductive plug and a top surface of a topmost layer of the conductive layers. The bit line contact is electrically connected to the memory structure.

Classes IPC  ?

• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U

Abrégé

An encoding method is provided for a memory device which includes an in-memory search (IMS) array having several memory units. The memory units in a same horizontal row are coupled to a first driving circuit through corresponding word lines and coupled to a sensing circuit through a match signal line. Every 2N adjacent memory units in the same horizontal row are arranged as a memory cell. An original data of M-bits is encoded to an encoded data of 2N-bits with a first encoded area including the first to N-th bits of the encoded data and a second encoded area including the (N+1)-th to 2N-th bits of the encoded data. The M bits of the original data have an equivalent binary value increased by an incremental step which is P times of an incremental step for the N bits of the first encoded area.

Classes IPC  ?

• G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
• G11C 16/30 - Circuits d'alimentation

Abrégé

A compensation method for wafer bonding includes bonding a first wafer and a second wafer, the first wafer including a first conductive pad and a second conductive pad. A first overlay check is performed. A result of the first overlay check is determined whether the result is within a first predetermined specification. If the result of the first overlay check is determined as beyond the first predetermined specification, performing a first compensation method to form a compensated first wafer and a compensated second wafer, wherein a position of a first conductive pad of the compensated first wafer is different from a position of the first conductive pad of the first wafer, and a position of a second conductive pad of the compensated first wafer is different from a position of the second conductive pad of the first wafer.

Classes IPC  ?

• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

A memory device and an intelligent operation method thereof are provided. The memory device includes a memory array, a signal generating circuit, an environment detecting circuit and an artificial intelligence (AI) circuit. The signal generating circuit is configured to generate an inputting signal. The environment detecting circuit is configured to detect at least one environment information. The AI circuit is connected among the memory array, the signal generating circuit and the environment detecting circuit. The AI circuit at least receives the inputting signal from the signal generating circuit, receives the environment information from the environment detecting circuit, receives a first performance information from the memory array, receives a second performance information from the AI circuit and outputs an ideal signal to the memory array according to the inputting signal, the environment information, the first performance information and the second performance information.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p.ex. neurone

Abrégé

A semiconductor chip including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes semiconductor devices. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the semiconductor devices. The semiconductor substrate or the interconnect structure includes at least one conductor, which includes a first conductive part and a second conductive part connected to the first conductive part. The first conductive part includes randomly oriented metal, and the second conductive part includes oriented metal. A bonding structure including the above-mentioned semiconductor chip and a fabricating method for fabricating the above-mentioned semiconductor chip are also provided.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

A memory device includes a stacked structure, a channel pillar, a plurality of conductive pillars, and a slit. The stacked structure is located on a dielectric substrate, and includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. The channel pillar extends through the stacked structure. The plurality of conductive pillars are located in the channel pillar and electrically connected with the channel pillar. The charge storage structure is located between the plurality of conductive layers and the channel pillar. The slit is located in the stacked structure. The slit includes a body part and an extension part. The body part extends through the stacked structure. The extension part is connected to the body part and located between the stacked structure and the dielectric substrate. The memory may be applied in 3D AND flash memory.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire

Abrégé

Systems, devices, methods, and circuits for managing read timing in semiconductor devices are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to read stored data from the memory array. The circuitry is configured to: obtain a starting address of target data to be read based on a read instruction, determine that the starting address is in a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective reading speed, and read out the target data from the memory array based on the starting address being in the first address group.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A semiconductor structure including a substrate, a stacked structure, a support pillar, and a channel pillar is provided. The substrate includes a peripheral region and an array region. The stacked structure is located on the substrate. The support pillar is located in the peripheral region. The support pillar passes through the stacked structure. The channel pillar is located in the array region. The channel pillar passes through the stacked structure. A thickness of the support pillar is greater than a thickness of the channel pillar.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U

Abrégé

A neural network computing method and a neural network computing device are provided. The neural network computing method includes the following steps. At least one chosen layer is decided. A plurality of front layers previous to the chosen layer are decided. A selected element is selected from a plurality of chosen elements in the chosen layer. A front computing data group related to the selected element is defined. The front computing data group is composed of only part of a plurality of front elements in the front layers. The selected element is computed according to the at least one front computing data group.

Classes IPC  ?

• G06N 3/0464 - Réseaux convolutifs [CNN, ConvNet]

Abrégé

Semiconductor devices and a method for forming a semiconductor device are provided. The semiconductor device includes a substrate, a first semiconductor structure on the substrate, a second semiconductor structure on the first semiconductor structure, and a wire coupled between the substrate and the first semiconductor structure. The first semiconductor structure and the second semiconductor structure are electrically connected to the substrate through the wire. A footprint of the first semiconductor structure is greater than a footprint of the second semiconductor structure.

Classes IPC  ?

• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

The disclosure provides a cache device, which includes: a first transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the first transistor is coupled to an input voltage, and the second terminal of the first transistor is coupled to a storage node; an inverter having an input terminal and an output terminal, in which the input terminal is coupled to the storage node; and a second transistor having a control terminal, a first terminal, and a second terminal, in which the first terminal of the second transistor is coupled to the output terminal of the inverter, and the second terminal of the second transistor is configured to output a read voltage.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. mémoires tampon de données

Abrégé

A memory device, such as a 3D AND type flash memory, and a compensation method of data retention thereof are provided. The compensation method includes the following. A reading operation is performed on each of a plurality of programmed memory cells of the memory device. Whether a charge loss phenomenon occurs in the programmed memory cells is determined through the reading operation to set the programmed memory cells to be charge loss memory cells. A refill program operation is performed on the charge loss memory cells.

Classes IPC  ?

• G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

Systems, methods, circuits, and devices for managing data transfers in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first interface for receiving higher-speed-type data, a second interface for receiving lower-speed-type data, a first logic circuit coupled to the first interface, a second logic circuit coupled to the second interface, and a driving circuit separately coupled to the first logic circuit and the second logic circuit. The first data interface, the first logic circuit, and the driving circuit are arranged in series to form a first data path for transferring the higher-speed-type data with a first speed. The second data interface, the second logic circuit, and the driving circuit are arranged in series to form a second data path for transferring the lower-speed-type data with a second speed. The first speed is higher the second speed.

Classes IPC  ?

• H03K 19/0185 - Dispositions pour le couplage; Dispositions pour l'interface utilisant uniquement des transistors à effet de champ
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• H03K 3/037 - Circuits bistables
• H03K 19/00 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion

Abrégé

A memory device includes a substrate, a stacked structure, a separation wall, first and second through vias. The substrate includes a memory array region and a staircase region. The stacked structure is located on the substrate in the memory array region and the staircase region. The stacked structure includes conductive layers and insulating layers stacked alternately. The separation wall extends through the stacked structure and divides the stacked structure into first and second blocks. The first through vias are in the first block of the staircase region. The second through vias are in the second block of the staircase region and adjacent to the first through vias. The number of layers of the stacked structure penetrated by the first through vias is smaller than the number of layers of the stacked structure penetrated by the second through vias. The memory device may be applied in a 3D AND flash memory.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U

Abrégé

The application provides an encoding method and an encoding circuit. The encoding method includes: performing linear conversion on an input into a first vector based on a weight by a convolution layer; comparing the first vector generated from the convolution layer with a reference value to generate a second vector by an activation function; binding the second generated by the activation function with a random vector to generate a plurality of binding results; adding the binding results to generate an adding result; and operating the adding result by a Signum function and a normalization function to generate an output vector.

Classes IPC  ?

• G06N 3/048 - Fonctions d’activation

Abrégé

A continuous time linear equalizer (CTLE) circuit is provided. The CTLE circuit can include a differential pair of first and second transistors, the first and second transistors having drains connected through first and second drain resistors to a drain-side supply voltage node, and sources connected together by a source resistor and connected to one or more current sources, the first transistor in the differential pair having a gate connected to a reference voltage, and the second transistor in the differential pair having a gate connected to an input voltage, the drains of the first and second transistors providing a differential pair of signals as an output voltage, a first coupling capacitor connected between the source of the first transistor and the input voltage, and a second coupling capacitor connected to the source of the second transistor.

Classes IPC  ?

• H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p.ex. réseaux de mise en forme adaptatifs

Abrégé

An artificial neural network operation circuit and an in-memory computation device of the artificial neural network operation circuit are proposed. The in-memory computation device includes a memory cell array, a compensation memory cell string, and an operator. The memory cell array has a plurality of memory cells to store a plurality of weight values. The memory cell array has a plurality of word lines and a plurality of bit lines. Each compensation memory cell of the compensation memory cell string stores a unit weight value. The operator multiplies a signal on a compensation bit line by peak weight information of the weight values to generate a first signal and adds the first signal to each signal on the bit lines to obtain a plurality of computation results, respectively.

Classes IPC  ?

• G11C 16/12 - Circuits de commutation de la tension de programmation
• G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
• G11C 16/24 - Circuits de commande de lignes de bits

Abrégé

A high bandwidth non-volatile memory (NVM) is described suitable for providing neural network weight data to an AI accelerator processing core or cores. An artificial intelligence (AI) inference memory device employing the high bandwidth NVM technology as described herein can comprise a logic layer die including channel logic implementing connections between a plurality of channels for conducting data to and from an accelerator core via a bus and a plurality of non-volatile memory (NVM) dies stacked vertically one above another, forming a layered vertical stack of NVM dies, each of the NVM dies including at least one memory chip and a plurality of direct vertical connections to a corresponding channel in the logic layer.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A method for storing weight data used to compute node values during inferencing operations conducted by a neural network comprises receiving a neural network definition. The neural network definition defines a neural network having a plurality of layers, each having a plurality of nodes. A set of weights used to compute a neural network inferencing result for each neural network node of the plurality of network nodes in the layer is determined. The set of weights determined for the layer in a page of memory can be stored in a high bandwidth non-volatile memory (NVM), such that any weights used to compute the neural network inference result for each neural network node of the plurality of nodes in the layer are stored together in the page of memory for retrieval together. Weights can be stored in different arrays across multiple memory channels.

Classes IPC  ?

• G06N 3/04 - Architecture, p.ex. topologie d'interconnexion
• G06N 3/063 - Réalisation physique, c. à d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

Abrégé

A memory device includes a substrate and a stack structure. A lower portion of the stack structure includes a first global selection line structure and a second global selection line structure. The first global selection line structure includes a first long strip, a first short strip and a first connection part connecting the first long strip and the first short strip. The first long strip and the second strip extend in a first direction, and the first connection part extends in a second direction different from the first direction. The first long strip passes through a staircase structure area from a first memory array area extending continuously to a second memory array area. The second global selection line structure is adjacent to the first global selection line structure and is divided into two portions separated from each other by the first connection part of the first global selection line structure.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U

Abrégé

A memory device, such as a three-dimensional AND or NOR flash memory includes a memory cell block, multiple first bit line switches, multiple second bit line switches, a first switch, and a second switch. The memory cell block is divided into a first sub memory cell block and a second sub memory cell block. The first bit line switches are respectively coupled to multiple first local bit lines and commonly coupled to a first sub global bit line. The second bit line switches are respectively coupled to multiple second local bit lines and commonly coupled to a second sub global bit line. The first switch is coupled between the first sub global bit line and a global bit line and controlled by a first control signal. The second switch is coupled between the second sub global bit line and the global bit line and controlled by a second control signal.

Classes IPC  ?

• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS

Abrégé

Compute-in-memory CIM operations using signed bits produce signed outputs. A circuit for CIM operations comprises an array of memory cells arranged in columns and rows, memory cells in columns connected to corresponding bit lines, and memory cells in rows connected to corresponding word lines. The array is programmable to store signed weights in sets of memory cells, the sets being operatively coupled with a corresponding pair of bit lines and a corresponding pair of word lines. Word line drivers are configured to drive true and complement voltages representing signed inputs on respective word lines in selected pairs of word lines. Sensing circuits are configured to sense differences between first and second currents on respective bit lines in selected pairs of bit lines and to produce signed outputs for the selected pairs of bit lines as a function of the difference.

Classes IPC  ?

• G11C 7/12 - Circuits de commande de lignes de bits, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
• G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
• G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots

Abrégé

An operation method for a memory device includes: selecting a selected word line from a plurality of word lines; applying a program voltage to the selected word line; and applying a pass voltage to a plurality of adjacent word lines adjacent to the selected word line. The pass voltage includes a first part and a second part. A timing of the first part of the pass voltage is earlier than a timing of the second part of the pass voltage. A voltage of the first part of the pass voltage is higher than a voltage of the second part of the pass voltage.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
• G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots

Abrégé

A hyperdimensional computing device includes a non-volatile memory cell array and a first operation circuit. The non-volatile memory cell array is coupled to a plurality of first word lines. The non-volatile memory cell array has a plurality of memory cell groups, a plurality of first memory cells of each of the memory cell groups are coupled to a same first word line of the first word lines, and the memory cell groups respectively store a plurality of data vectors. The first operation circuit receives at least one of the data vectors through bit lines and generates a bundled data vector according to the at least one of the data vectors.

Classes IPC  ?

• G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

A memory device and an in-memory search method thereof are provided. The in-memory search method includes: providing, in a first stage, a first voltage or a second voltage to a word line of at least one target memory cell according to a logical status of searched data, and reading a first current; providing, in a second stage, a third voltage or a fourth voltage to the word line of the at least one target memory cell according to the logical status of the searched data, and reading a second current; and obtaining a search result according to a difference between the second current and the first current.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots

Abrégé

A memory device for performing in-memory-search. A search voltage corresponding to a search data is applied to the first signal lines. A plurality of second signal lines of the memory device generate output currents. The threshold voltage of each of the memory cells of the memory device corresponds to a stored data, the stored data is compared with the search data to obtain a comparison result. The output current reflects the comparison result. Values of the stored data and search data of the first memory cells are equal to values of the stored data and the search data of the second memory cells. The threshold voltage of the first memory cells is complementary to the threshold voltage of the second memory cells. The search voltage applied to the first memory cells is complementary to the search voltage applied to the second memory cells.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 7/06 - Amplificateurs de lecture; Circuits associés

Abrégé

A memory structure, applicable to a three-dimensional AND flash memory device, is provided. The memory structure includes a substrate, a stack structure, a channel pillar, charge storage structures, a first conductive pillar, a second conductive pillar, and an isolation pillar. The stack structure is located on the substrate and includes first dielectric layers and conductive layers alternately stacked. The channel pillar passes through the stack structure. Each charge storage structure is located between the corresponding conductive layer and the channel pillar. The first conductive pillar and the second conductive pillar are located within the channel pillar. The first conductive pillar and the second conductive pillar are separated from each other. The isolation pillar is located between the first conductive pillar and the second conductive pillar. The top of the isolation pillar is higher than the top of the first conductive pillar and the top of the second conductive pillar.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U

Abrégé

A semiconductor structure is provided. The semiconductor structure includes a first substrate, a first circuit layer, a memory array structure, a bonding layer, a second circuit layer, and a second substrate. The first circuit layer is disposed on the first substrate. The memory array structure is disposed on the first circuit layer. The bonding layer is disposed on the memory array structure. The second circuit layer is disposed on the bonding layer. The second substrate is disposed on the second circuit layer.

Classes IPC  ?

• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
• H01L 23/528 - Configuration de la structure d'interconnexion
• H10B 41/20 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
• H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
• H10B 43/20 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
• H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique

Abrégé

Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a vertical channel pillar. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The vertical channel pillar penetrates through the stack structure. The vertical channel pillar includes a first source/drain pillar and a channel layer laterally surrounding the first source/drain pillar. The first source/drain pillar includes a first buffer pillar and a first semiconductor layer having a first conductivity type wrapping the first buffer pillar. The channel layer includes a polysilicon layer having a second conductivity type different from the first conductivity type. In some embodiments, the 3D memory device may be, but is not limited to, a AND flash memory.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET

Abrégé

Provided are a semiconductor structure for a 3D memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a substrate having a memory array region and a staircase region, an insulating layer, a stacked structure and a vertical channel (VC) structure. The insulating layer is disposed on the substrate. The stacked structure is disposed on the insulating layer. The stacked structure includes first dielectric layers separated from each other, and the stacked structure in the staircase region has a staircase profile. The VC structure is disposed in the stacked structure in the memory array region and penetrates through the stacked structure. There is a vertical hole in the stacked structure and the insulating layer in the staircase region, and a third dielectric layer is filled in the vertical hole.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U

Abrégé

An in-dynamic memory search device and an operation method thereof are provided. The in-dynamic memory search device includes at least one word line, at least two bit lines, at least one match line, at least one unit cell, at least two search lines, at least one pre-charge unit and at least one sense unit. The unit cell includes two storage elements and two search transistors. Each of the storage elements includes a write transistor and a read transistor. The write transistor is connected to the word line and one of the bit lines. The read transistor is connected to the write transistor and the match line. The search transistors are respectively connected to the read transistors. The search lines are respectively connected to the search transistors. The pre-charge unit is connected to the match line. The sense unit is connected to the match line.

Classes IPC  ?

• G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristique utilisant des éléments semi-conducteurs

Abrégé

Provided are a semiconductor structure for a three-dimensional (3D) memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a dielectric layer disposed on a substrate, a ground layer, a ground via, a dielectric stacked structure, and a through via. The ground layer is disposed on the dielectric layer. The ground via is disposed in the ground layer and the dielectric layer and electrically connected to the substrate. The dielectric stacked structure is disposed on the ground layer. The through via is disposed in the dielectric stacked structure and connected to the ground layer. The dielectric stacked structure has a vertical channel hole.

Classes IPC  ?

• H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p.ex. écrans Faraday
• H10B 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe

Abrégé

A hybrid in-memory search (IMS) content addressable memory (CAM) cell includes: a first IMS CAM cell; and a second IMS CAM cell, coupled to the first IMS CAM cell. The first IMS CAM cell and the second IMS CAM cell are of different types. When the hybrid IMS CAM cell stores a storage data, the first IMS CAM cell stores a first part of the storage data and the second IMS CAM cell stores the storage data or a second part of the storage data.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristique utilisant des éléments semi-conducteurs

Abrégé

B. An output signal of the semiconductor circuit is a sum of output string signals of the strings.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
• G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention

Abrégé

A universal memory for In-Memory Computing and an operation method thereof are provided. The universal memory includes at least one write word line, at least one unit cell and at least one read word line. The unit cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a transistor with adjustable threshold voltage. The gate of the read transistor is connected to the drain or the source of the write transistor. The read word line is connected to the drain or the source of the read transistor. The universal memory is used for a training mode and an inference mode. In the training mode and the inference mode, a weight is stored at different locations of the unit cell.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p.ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/405 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c. à d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c. à d. rafraîchissement externe avec trois portes à transfert de charges, p.ex. transistors MOS, par cellule

Abrégé

A memory structure and methods for operating memory structures are provided. The memory structure includes a first, a second and a third gate structures disposed along a first direction and separated from each other, channel bodies having first ends and second ends, source regions separated from each other, having first conductivity types and connected to the first ends of the channel bodies respectively, drain regions separated from each other, having second conductivity types and connected to the second ends of the channel bodies respectively, and first side plugs disposed along a second direction, extending along a third direction, and electrically connected to the source regions and the channel bodies. The first gate structure includes island structures disposed along the second direction and extending along the third direction.

Classes IPC  ?

• G11C 11/4097 - Organisation de lignes de bits, p.ex. configuration de lignes de bits, lignes de bits repliées
• G11C 11/4067 - Circuits auxiliaires, p.ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation pour des cellules de mémoire du type bipolaire
• H10B 12/10 - Dispositifs DRAM comprenant des composants bipolaires

Abrégé

A semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. A gate structure covers the plurality of recesses and a surface of the substrate between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor device includes a resistor. The resistor includes two bottom electrodes adjacent to each other, a resistive layer, a top electrode and a conductive sidewall. The resistive layer is disposed on the two bottom electrodes. The top electrode is disposed on the resistive layer. The conductive sidewall surrounds the top electrode and is electrically connected to the top electrode and a bottom electrode of the two bottom electrodes. The top electrode overlaps the two bottom electrodes in the first direction, and extends above the two bottom electrodes along a second direction different from the first direction.

Classes IPC  ?

• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p.ex. dispositifs RAM résistifs [ReRAM]
• H10N 70/00 - Dispositifs à l’état solide sans barrière de potentiel ni de surface, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
• H10N 70/20 - Dispositifs de commutation multistables, p.ex. memristors

Abrégé

A storage device for generating an identity code, includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores several first data having several bits. The second storage circuit stores several second data having several bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, and simultaneously reads the first data from the first storage circuit to form a second sequence. The reading circuit includes a processing circuit which simultaneously receives the first sequence and the second sequence, selects a first portion of the second sequence to form a target sequence according to the first sequence, and outputs the target sequence to serve as an identity code. Logical values of the bits of the first data and the second data are randomly distributed or pre-defined by a user.

Classes IPC  ?

• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données
• G11C 16/34 - Détermination de l'état de programmation, p.ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• G11C 29/40 - Dispositifs de vérification de réponse utilisant des techniques de compression

Abrégé

A semiconductor structure is provided. The semiconductor structure has a device defining region. The device defining region includes a first portion and a second portion separated from each other. The semiconductor structure includes a stack. The stack includes first conductive layers and first dielectric layers disposed alternately. The stack has an opening through the stack in the device defining region. The semiconductor structure further includes a second conductive layer, a first conductive pillar, a third conductive layer, a second conductive pillar, and a third conductive pillar. The second conductive layer is disposed along a sidewall of the opening. The first conductive pillar is disposed in the opening in the first portion. The third conductive layer is disposed in the opening along an edge of the second portion. The second conductive pillar and the third conductive pillar are disposed in the second portion and separated from each other.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a 3D memory device such as a 3D AND flash memory and a method of forming a seal structure. The 3D memory device includes a chip region including a chip array and a seal region including a seal structure. The seal structure includes a ring-shaped stack structure disposed on a substrate and surrounding the chip array and a dummy channel pillar array penetrating through the ring-shaped stack structure and including a first dummy channel pillar group and a second dummy channel pillar group. The first dummy channel pillar group includes first dummy pillars that are arranged in a first direction and a second direction crossing the first direction to surround the chip array. The second dummy channel pillar group includes second dummy pillars that are arranged in the first direction and the second direction to surround the chip array. The first and the second dummy channel pillars are staggered with each other in the first and second directions.

Classes IPC  ?

• H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
• H01L 27/11556 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U

Abrégé

The disclosure provides an in-memory computing (IMC) memory device and an IMC method thereof. The IMC memory device includes; a memory array including a plurality of computing units, each of the computing units including a plurality of parallel-coupling computing cells, the parallel-coupling computing cells of the same computing unit receiving a same input voltage; wherein a plurality of input data is converted into a plurality input voltages; after receiving the input voltages, the computing units generate a plurality of output currents; and based on the output currents, a multiply accumulate (MAC) of the input data and a plurality of conductance of the computing cells is generated.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A semiconductor structure is provided. The semiconductor structure has a device region and a periphery region adjacent to the device region. The periphery region comprises an array contact defining region and a periphery contact defining region. The semiconductor structure comprises a substrate, a staircase structure, an etch stop layer, a plurality of array contacts, and a plurality of periphery contacts. The staircase structure is disposed on the substrate in the periphery region. The staircase structure comprises conductive layers and dielectric layers disposed alternately. The etch stop layer is disposed on the staircase structure in the array contact defining region. The array contacts are disposed on the staircase structure and through the etch stop layer in the array contact defining region. The periphery contacts are through the staircase structure in the periphery contact defining region.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H01L 23/528 - Configuration de la structure d'interconnexion
• H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique

Abrégé

Systems, methods, circuits, and apparatus for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, a page buffer circuit including a plurality of page buffers, and a cache data latch (CDL) circuit including a plurality of caches coupled to the plurality of page buffers through a plurality of data bus sections. The plurality of data bus sections are configured to be conductively connected together as a data bus for data transfer. Each data bus section corresponds to a page buffer in the page buffer circuit and is configured to conductively separate from at least one adjacent data bus section for data sensing in the memory cell array.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S

Abrégé

A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.

Classes IPC  ?

• G11C 16/24 - Circuits de commande de lignes de bits

Abrégé

A memory device and programming method thereof are provided. A memory cell array includes a first dummy word line set, plural word lines and a second dummy word line set in sequence. The method includes: grouping the word lines into word line groups; generating at least one pass bias set having plural pass biases that are respectively corresponding to each word line group; selecting one word line for programming, and determining that the selected word line belongs to a specific word line group; and according to a programming sequence, applying a corresponding pass bias in the plural pass biases of the at least one pass bias set to at least one dummy word line in one of the first and the second dummy word line sets, wherein the corresponding pass bias corresponds to the specific word line group.

Classes IPC  ?

• G11C 16/08 - Circuits d'adressage; Décodeurs; Circuits de commande de lignes de mots
• G11C 16/28 - Circuits de détection ou de lecture; Circuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p.ex. des cellules factices

Abrégé

A memory cell and a memory device are provided. The memory cell comprises: a write transistor; and a read transistor coupled to the write transistor, the write transistor and the read transistor coupled at a storage node, the storage node being for storing data; wherein, at least one among the write transistor and the read transistor includes a threshold voltage adjusting layer, and a threshold voltage of the write transistor and/or the read transistor is adjustable.

Classes IPC  ?

• G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p.ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées

Abrégé

A memory device includes a stacked structure having an array region and a staircase region adjacent to the array region, a lower isolation structure in the stacked structure, two memory strings in the array region and at least one lower support member in the staircase region. The stacked structure includes conductive layers. The lower isolation structure has an upper surface in a lower portion of the stacked structure, extends from the array region to the staircase region and separates one conductive layer into a first conductive strip and a second conductive strip electrically isolated from each other and electrically connected to two memory strings respectively. A material of the lower support member is the same as a material of the lower isolation structure, and a height of the lower support member is the same as a height of the lower isolation structure.

Classes IPC  ?

• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• H01L 23/528 - Configuration de la structure d'interconnexion
• H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p.ex. NON-ET
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. des canaux en forme de U
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET

Abrégé

An in-memory computing (IMC) memory device and an IMC method are provided. The IMC memory device includes: a plurality of memory cells, the memory cells forming a plurality of computing layers; and a plurality of computing layer connectors, the computing layer connectors connecting between the computing layers. A first computing layer input is inputted into a first computing layer of the computing layers. The first computing layer generates a first computing layer output. A first computing layer connector of the computing layer connectors converts the first computing layer output into a second computing layer input. The first computing layer connector inputs the second computing layer input into a second computing layer of the computing layers. The computing layer connectors are a plurality of inverters, a plurality of voltage-to-voltage converters or a plurality of current-to-voltage converters.

Classes IPC  ?

• G01R 19/257 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique utilisant des convertisseurs analogiques/numériques du type effectuant la comparaison de différentes valeurs de référence avec la valeur de la tension ou du courant, p.ex. utilisant une méthode par approximations successives
• G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe

Abrégé

A memory device and a test method thereof are provided. The memory device (e.g., a 3D stack AND type flash memory) includes a memory cell array, a first global bit line, a second global bit line, and a switch component. The memory cell array is divided into a first memory cell group and a second memory cell group. The first memory cell group has a plurality of first local bit lines and a plurality of first local source lines, and the second memory cell group has a plurality of second local bit lines and a plurality of second local source lines. The switch component is configured to couple the first local source lines to a common source line or couple the second local source lines to the common source line during a plurality of different test modes.

Classes IPC  ?

• G11C 29/12 - Dispositions intégrées pour les tests, p.ex. auto-test intégré [BIST]
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

A memory device and an in-memory search method thereof are provided. The memory device includes a first memory cell block, a second memory cell block, at least one search memory cell pair, and a sense amplifier. The search memory cell pair includes a first search memory cell and a second search memory cell. The first search memory cell and the second search memory cell are respectively disposed in the first memory cell block and the second memory cell block. The first search memory cell and the second search memory cell respectively receive a first search voltage and a second search voltage. The first search voltage and the second search voltage are generated according to searched data. The sense amplifier generates a search result according to signals on a first bit line and a second bit line.

Classes IPC  ?

• G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristique utilisant des éléments semi-conducteurs
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p.ex. FAMOS
• G11C 16/26 - Circuits de détection ou de lecture; Circuits de sortie de données

Abrégé

A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.

Classes IPC  ?

• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes

Abrégé

A system includes a semiconductor device configured to store data and a controller communicatively coupled to the semiconductor device. The semiconductor device and the controller are configured to; in response to determining that particular data stored in the semiconductor device satisfies a reliability condition, obtain first readout data by reading the particular data at a first read voltage, and obtain second readout data by reading the particular data at a second read voltage. The second read voltage is different from the first read voltage. The semiconductor device and the controller are configured to compare the first readout data and the second readout data and obtain a comparison result; and, based on the comparison result, determine whether to perform an error correction process on the particular data.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

Systems, methods, circuits, and apparatus for managing data transfer in semiconductor devices are provided. In one aspect, an integrated circuit includes: a first circuit, a data bus coupled to the first circuit, and a precharging circuit coupled to the data bus. The precharging circuit is configured to precharge the data bus to have a predetermined voltage before data is transferred through the data bus. The first circuit is conductively coupled to the data bus by applying a control voltage to the first circuit. The control voltage is determined based on the predetermined voltage.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 16/30 - Circuits d'alimentation

Abrégé

The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.

Classes IPC  ?

• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G11C 7/14 - Gestion de cellules factices; Générateurs de tension de référence de lecture
• G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots