Implementations of a method of forming an interconnect may include forming a seed layer (10) over a plurality of pads (6); patterning a layer of photoresist (12) with a plurality of openings (14) exposing the plurality of pads (6); forming a plurality of copper interconnects (18) by electroplating each copper interconnect of the plurality of copper interconnects (18) into each opening of the plurality of openings (14); removing the layer of photoresist (12); etching the seed layer (10); forming one or more layers (24) on the plurality of copper interconnect (18); and patterning a layer of polyimide (26) over the plurality of copper interconnects (18) to form at least one opening (28) over at least one copper interconnect of the plurality of copper interconnects (18).
A junction field effect transistor (JFET) (100) includes a drift region (110) disposed on a substrate (111) that includes a drain region of the JFET. A lower gate region (106) is disposed on the drift region, a source region (102) is disposed above the lower gate region, and an upper gate region (104) at least partially surrounding the source region and extending laterally beyond the lower gate region is disposed above the source region. The upper gate region extends laterally beyond the lower gate region by a distance defining a gate offset width (Gos) between the upper gate region and the lower gate region.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
A compact power inverter (100, 400, 450) is efficiently laid out on a multi-layer direct bond metal (DBM) structure (102), having a reduced footprint and straight, short-run wire bonds (107, 407, 457). The compact layout reduces an amount of material needed to fabricate a multi-layer DBM (102) that includes a silicon nitride ceramic layer (102b, 402b). The layout is further designed so that wire bonds (107, 407, 457) can be routed without bending around corners. The compact DBM structure (102) and short wire bonds (107, 407, 457) provide a solution that is both low-cost and highly reliable.
Implementations of a leadframe for a semiconductor package may include a half-etched gate lead directly coupled to a gate tie bar; a half-etched source lead directly coupled to a source tie bar; and a die flag directly coupled to at least two die flag tie bars. The gate tie bar and the source tie bar may be configured to enable electroplating of a flank of the half-etched gate lead and the half-etched source lead.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
In a general aspect, an electroplating system (100) includes a vessel (105), an electrolytic plating solution (110) in the vessel, a cathode terminal (120), a first anode terminal (130) and a second (140) anode terminals, a first variable power supply (135), and a second variable power supply (145). The cathode terminal is configured to electrically connect with a workpiece (125) that is submerged in the electrolytic plating solution. The first anode terminal is in the electrolytic plating solution on a first side of the workpiece. The second anode terminal is in the electrolytic plating solution on a second side of the workpiece opposite the first side. The first variable power supply coupled between the cathode terminal and the first anode terminal. The second variable power supply coupled between the cathode terminal and the second anode terminal.
Devices and methods are disclosed for high power inverter modules (100) with enhanced thermal and mechanical performance, for use in electric vehicles. The disclosed devices feature enlarged clips (108) that cover an entire die (104), to distribute mechanical forces, thus preventing die cracks for improved reliability. In these power modules, semiconductor dies (104) are sandwiched between a three-layer direct bond metal (DBM) structure (102) and the enlarged clip. A pre-molded clip assembly (105) can be used that includes integrated metalliization (107) to eliminate the need for external wire bonds. Alternatively, semiconductor dies (104) can be inverted in a flip-chip configuration (701) to face a modified DBM structure (702) that integrates the metallization (707). Simulations of the disclosed power inverters indicate improved efficiency in dissipating heat.
Implementations of an object file for modeling using a three dimensional modeling module may include a first object defined as a root object, the first object corresponding with a first component of a semiconductor package; a second object corresponding with a second component of the semiconductor package directly physically coupled to the first component of the semiconductor package, the second object including a reference to the root object; and at least a third object corresponding with a third component of the semiconductor package, the third object including a reference to the root object, the third component of the semiconductor package directly coupled with a fourth component of the semiconductor package indirectly physically coupled to the second component of the semiconductor package.
A package includes a semiconductor die (15) disposed on a three-layer substrate (100). The three-layer substrate includes a ceramic layer (100-2) disposed between a top metal layer (100-2) and a bottom metal layer (10-3). The semiconductor die is disposed on the top metal layer. An array of mesas (10, 12) is defined in the bottom metal layer with grooves (11) between the mesas forming a path (P) for cooling fluid flow across a surface of the bottom metal layer.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
C04B 37/00 - Liaison des articles céramiques cuits avec d'autres articles céramiques cuits ou d'autres articles, par chauffage
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 23/433 - Pièces auxiliaires caractérisées par leur forme, p. ex. pistons
9.
POWER MODULE PACKAGE WITH MOLDED VIA AND DUAL SIDE PRESS-FIT PIN
A module (100, 700) includes an assembly of a semiconductor device die (110) coupled to a lead frame (120, 130, 720, 730). A board (150) is disposed below the lead frame. The board includes a plated-through hole (PTH) (162, 762) aligned with an opening (132, 732) in (the lead frame above the board. The module further includes a mold body (150) encapsulating at least a portion of the assembly. The mold body (150) includes a through-mold via (TMV) (160, 760-1, 760-2) aligned with the opening in the lead frame and with the PTH (162, 732). The PTH is physically accessible from outside the mold body through the TMV (160, 760-1, 760-2) and the opening in the lead frame.
A semiconductor device component includes a contact pad (12) disposed on a surface of a semiconductor substrate (10), a seed metal layer (14) disposed on the contact pad, and an interconnect disposed on the seed metal layer. The seed metal layer has a width that is greater than the width of the interconnect with a footer portion (14F) of the seed metal layer extending outside the width of the interconnect. The semiconductor device component further includes an etch-resistant protective structure (18) disposed on surfaces of the interconnect and the footer portion of the seed metal layer extending outside the width of the interconnect.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
A high-power semiconductor device module (100) is implemented with a cavity (112) in the molding package (110). The cavity (112) reduces a volume of the molding compound, preventing an accumulation of stress in the module (100), and associated warpage of the molding package (110). Chip assemblies (106) within the module (100) are designed to fit within the cavity (112), so that semiconductor dies, and sensing devices (204) therein are protected from damage during a sintering process in which the module (100) is mounted to a heat sink. After the sintering process, the cavity (112) can be sealed with a gel material (114). The molding package (110) described herein can also enhance reliability of the module (100) during operation, ensuring that the product is robust for electric and hybrid electric vehicle applications.
H01L 23/047 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base conductrice qui sert de support et en même temps de connexion électrique pour le corps semi-conducteur les autres connexions étant parallèles à la base
H01L 23/24 - Matériaux de remplissage caractérisés par le matériau ou par ses propriétes physiques ou chimiques, ou par sa disposition à l'intérieur du dispositif complet solide ou à l'état de gel, à la température normale de fonctionnement du dispositif
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
A fan out package (102) (202) (302-1) (302-2) (402-1) (402-2) (502-1) (502-2) (602) (702) (802-1) (802-2) (902-1) (902-2) (1002-1) (1002-2) may include a plurality of semiconductor dies (104) (204) (304) (404) (504) (604) (704) (804) (904) (1004), each of the semiconductor dies including a first surface and a second surface opposite to the first surface. The fan out package includes a redistribution layer (108) (208) (308) (408) (508) (608) (708) (808) (908) (1008) coupled to the first surface of each of the plurality of semiconductor dies, a dieback conductive member (106) (206) (306) (406) (506) (606) (706) (806) (906) (1006) coupled to the second surface of each of the plurality of semiconductors dies, and an encapsulation material (114) (214) (314) (414) (514) (614) (814) (914) (1014) coupled to the plurality of semiconductor dies and the dieback conductive member.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
An imager (300) is configured for capturing short-wavelength infrared (SWIR) images. The imager includes an optical sensor die (310) including a semiconductor substrate (312), at least one device (346) fabricated in the semiconductor substrate, a layer of colloidal quantum dots (CQD) photodetectors (340) disposed above of the semiconductor substrate, and an intermetal dielectric (IMD) layer (313) disposed on a bottom surface of the semiconductor substrate. The IMD layer includes at least a metal level (M1-M4) of a redistribution layer (RDL) (313M) of the optical sensor die.
H01L 31/0352 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails caractérisés par leurs corps semi-conducteurs caractérisés par leur forme ou par les formes, les dimensions relatives ou la disposition des régions semi-conductrices
H01L 31/101 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet
H04N 25/75 - Circuits pour fournir, modifier ou traiter des signaux d'image provenant de la matrice de pixels
H04N 25/79 - Agencements de circuits répartis entre des substrats, des puces ou des cartes de circuits différents ou multiples, p. ex. des capteurs d'images empilés
14.
POWER MODULE UTILIZING INJECTABLE CONDUCTIVE COMPONENT FOR DIRECT COOLING
An injectable conductive component (114) can be used to couple a high-power semiconductor chip assembly (101) to a heat sink (106), in automotive and industrial applications. The injectable conductive component (114) provides a low-resistance interface material and also acts as a bonding agent (105). A cavity (113) bounded by the chip assembly (101) and the heat sink (106) can form a container for the injectable conductive component (114), which remains in a liquid phase during operation of the chip assembly (101). The container can be formed as a cavity (113) by either removing a portion of the heat sink (106), or by introducing a spacer between the chip assembly (101) and the heat sink (106), using a sealing material. The injectable conductive component (114) can be introduced into the cavity (113) by injection through a hole (116) formed in a back side of the heat sink (106).
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/433 - Pièces auxiliaires caractérisées par leur forme, p. ex. pistons
H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
H01L 23/14 - Supports, p. ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 23/10 - ConteneursScellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p. ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/051 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base conductrice qui sert de support et en même temps de connexion électrique pour le corps semi-conducteur une autre connexion étant constituée par le couvercle parallèle à la base, p. ex. du type "sandwich"
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/11 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/40 - Supports ou moyens de fixation pour les dispositifs de refroidissement ou de chauffage amovibles
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
A power module (100) is disclosed for use in electric vehicles and industrial applications. The power modules (100) route large currents through a set of metal power tabs (120, 122, 124) instead of passing high currents through conductive layers of a direct bonded metal structure (102). By orienting the metal power tabs (120, 122) in a mini-heart design, stray inductance and resistance can both be reduced, thereby improving performance while simultaneously reducing the footprint of the high power module (100). In addition, wire bonds (112) between chip assemblies (110) in a high-power semiconductor device module (100) can be replaced by solid metal clips (212) that can better withstand high currents and voltages. The SSDC package incorporates the metal power tabs and provides heat dissipation via a metal base plate (510) that includes a heat sink. The heat sink can be immersed in a cooling fluid to provide faster heat dissipation.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
A package (10) includes a semiconductor die (130) attached to a substrate (100) and a mold body (140) encapsulating the semiconductor die. A first portion of a lead (1-1, 2-1, 3-1) is directly bonded to a contact pad (SP, SSP, GP) on the semiconductor die with no intervening component between the first portion of the lead and the contact pad. A second portion of the lead extends outside the mold body to form an external terminal (1-0, 2-0, 3-0, 4-0, 5-0, 6-0, 7-0) of the package. The lead is a dual gauge lead with the first portion of the lead having a thickness perpendicular to the contact pad that is smaller than a thickness of the second portion of the lead extending outside the mold body.
Implementations of a product system model file generating system may include one or more hardware processors and a first interface generated by a computing device to receive from a user a selection of a product SPICE model for a product including at least one switch; using a second interface to receive from a user a selection of at least a partial soft switching process condition; using a third interface to receive from a user a selection of one or more system characteristics and one or more operating characteristics; using a fourth interface to receive from the user a selection of one or more circuit parameters including a simulation circuit including at least two switches; using a SPICE model simulation module to generate a SPICE model output; and using a formatting module to format the SPICE model output into a product system model file.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
Implementations of high-power semiconductor device modules are described, including automotive power transistor assemblies for use in power amplifier circuits such as a cascode circuit (200). In some implementations, power amplifier circuit components are provided on separate semiconductor dies (104a, 104b) attached to discrete dual die attach pads (109a, 109b). A separation (g) between the die attach pads (109a, 109b), as well as a through-hole (412), provide sufficient isolation between the dies (104a, 104b) to permit operation of the circuit at high voltages without relying on a thick multi-layer direct bond copper (DBC) isolation structure. In some implementations, higher voltage operation can be supported by a thin multi-layer, resin coated copper DAP (600) in which the top layer is split.
Implementations of a sintering film frame (68) may include a frame including an outer perimeter (78) and an inner perimeter (76), the inner perimeter (76) defining an opening (74) through the frame; a position detection opening (80) through the frame; at least two alignment holes (82) through the frame; and a frame identifier (86) on a side of the frame.
A transistor configured for higher power can be constructed using multiple transistor dies coupled in parallel. This approach of distributing power and heat over multiple transistor dies can allow each transistor die to be made smaller, which can be helpful in improving yield. This is especially true for emerging technologies, such as silicon carbide (SiC). Power modules for power conversion may require a plurality of these multi-die transistors in a package. A package that accommodates the numerous connections required for a multi-die power module is disclosed. The package utilizes a lead frame to provide a three-dimensional sandwich structure in which multiple dies are positioned between two direct bonded copper (DBC) substrates.
A protective dam (114) can relieve stress in a chip assembly (104) of a high-power semiconductor device module (100) used in electric vehicle or industrial applications. Some chip assemblies (104) that incorporate copper spacers (110b) for thermal dissipation can cause the device module (100) to become vulnerable to cracking. Adding a protective dam (114) can absorb stress to prevent damage to materials surrounding the chip assembly (104). Various types of protective dams (114) are presented, including high profile flexible protective dams (114a), low profile flexible protective dams (114b), metallic protective dams (114c), and integral protective dams (114d). The protective dams (114) can be incorporated into a high-power semiconductor device module (100) that features single sided or dual sided cooling via direct bond metal structures.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/16 - Matériaux de remplissage ou pièces auxiliaires dans le conteneur, p. ex. anneaux de centrage
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
22.
JET IMPINGEMENT HEATSINK FOR HIGH POWER SEMICONDUCTOR DEVICES
A jet impingement cooling assembly (102) for semiconductor devices (124, 125) may include a heat exchange base (102) having an inlet chamber (112) and an outlet chamber (126), an inlet connection (1704, 1804, 2004) in fluid connection with the inlet chamber (112), and an outlet connection (1706, 1806, 2106) in fluid connection with the outlet chamber (126). A plurality of jet nozzles (110) may be attached to a semiconductor module (122), with the plurality of jet nozzles (110) including corresponding openings (110) positioned to cause jet impingement of fluid flow (114) from the inlet chamber (112) onto the semiconductor module (122) and then into the outlet chamber (126).
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
23.
SINGLE SWITCH DIRECT COOLING ASSEMBLIES AND RELATED METHODS
Implementations of a dual sided cooling module may include a high side module coupled over a low side module through a coupling heat sink at a first largest planar surface of the high side module and at a first largest planar surface of the low side module; a high side heat sink coupled at a second largest planar surface of the high side module; and a low side heat sink coupled at a second largest planar surface of the low side module. A single cooling fluid may contact the coupling heat sink, the high side heat sink, and the low side heat sink.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 25/11 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
Implementations of a substrate may include an electrically insulative layer (18) having a first largest planar side (26) and a second largest planar side (24) opposing the first largest planar side (26); a first electrically conductive layer (20) coupled to the first largest planar side (26) and including a first scalloped edge (28) having a first pattern; and a second electrically conductive layer (22) coupled to the second largest planar side (24) and including a second scalloped edge (36) having a second pattern. The first pattern and the second pattern may alternate along at least one edge of the first largest planar side (26) and at least one edge of the second largest planar side (24), respectively.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
26.
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
A method of making a semiconductor device (10) includes providing semiconductor region (14) of a first conductivity type. A first region (141) comprising the first conductivity type within the semiconductor region. The first region provides a JFET channel region (141A) for a JFET device (110). A second region (31) comprising a second conductivity type is provided within the first region. The second region provides a body region for a MOSFET device and a gate region for the JFET device. The second region comprises a first portion (31A) and a second portion (31B) below the first portion. The second portion has a higher peak dopant concentration than the first portion. A third region (37) comprising the first conductivity type is provided within and self-aligned to the second region. The third region provides a JFET source for the JFET device.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
27.
AUTOMATED POWER DISCRETE AND MODULE MODEL GENERATION FOR SYSTEM LEVEL SIMULATORS
Implementations of a method of generating a product system model may include, using a first interface (120), receiving from a user a selection of a product type; selecting a product SPICE model associated with the product type from a database of product SPICE models; and using a second interface (130), receiving from the user a selection of a process condition. The method may include, using a third interface (134), receiving from the user one or more system characteristics and one or more operating characteristics; using a fourth interface (140), receiving from the user one or more circuit characteristics; using a SPICE model simulation module (110), generating a SPICE model output with the product SPICE model, and, using a formatting module (112), formatting the SPICE model output into a product system model file.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
A package (100) includes a frame (140) having a cooling fluid channel (155) therethrough. The frame has at least one opening (147) in a first sidewall alongside the cooling fluid channel and at least one opening (149) in a second sidewall alongside the cooling fluid channel. A first power electronics module (200A) covers the at least one opening in the first sidewall with a surface of a substrate in the first power electronics module being exposed to the cooling fluid channel in the frame through the at least one opening in the first sidewall, and a second power electronics module (200A) covers the at least one opening in the second sidewall with a surface of a substrate in the second electronics module being exposed to the cooling fluid channel in the frame through the at least one opening in the second sidewall.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
29.
POWER MODULE PACKAGE WITH MOLDED VIA AND DUAL SIDE PRESS-FIT PIN
A module includes an assembly of a semiconductor device die (110), a lead frame (120, 130) connected to the semiconductor device die, and a substrate (112) connected to the lead frame. The substrate includes at least one plated-through hole (PTH) (162). A mold body (150) encapsulates the assembly. The mold body includes a through-mold via (TMV) (160) aligned with a portion of the substrate including the at least one PTH. The PTH is exposed in the TMV to an environment outside the mold body and is physically accessible from outside the mold body through the TMV.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/498 - Connexions électriques sur des substrats isolants
In a general aspect, a power module package (400) includes a substrate (105) that has a ceramic layer (105a) with a first primary surface and a second primary surface opposite the first primary surface. The substrate also includes a patterned metal layer (110) disposed on the first primary surface. The package also includes a first plurality of semiconductor die (120) disposed on a first portion of the patterned metal layer (110a). The first plurality of semiconductor die are linearly arranged along a first axis (120a). The package further includes a second plurality of semiconductor die (125) disposed on a second portion of the patterned metal layer (110b). The second plurality of semiconductor die are linearly arranged along a second axis (125a) parallel to the first axis.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
A semiconductor device may include a plurality of transistors (110), with a first array (204, 206) of low-resistance material formed in a first dielectric layer (216), with a gate subset (204) of the first array formed on a plurality of gate electrodes (202) of the transistors, and a source subset (206) of the first array formed on a plurality of source regions (212) of the transistors. A second array (205, 207) of low-resistance material may be formed in a second dielectric layer (220), with a gate subset (205) of the second array formed on the gate subset (204) of the first array and thereby electrically connected to the plurality of gate electrodes (202), and a source subset (207) of the second array formed on the source subset (206) of the first array and thereby electrically connected to the plurality of source regions (212).
H01L 23/482 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
32.
MOLDED POWER MODULES WITH FLUIDIC-CHANNEL COOLED SUBSTRATES
In a general aspect, a semiconductor device module (1000) includes a ceramic substrate (1005) having a first surface and a second surface opposite the first surface. A patterned metal layer (410) is disposed on the first surface of the ceramic substrate, and a semiconductor die (1011) is disposed on the patterned metal layer. A cooling structure (1020) is disposed on the second surface of the ceramic substrate, where the cooling structure includes a plurality of fluidic-cooling channels (310). The module also includes a molding compound (1060) that encapsulates the ceramic substrate, the patterned metal layer and the semiconductor die, and partially encapsulates the cooling structure, such that a fluidic interface surface of the cooling structure is exposed through the molding compound.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/433 - Pièces auxiliaires caractérisées par leur forme, p. ex. pistons
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
33.
CURRENT SHARING MISMATCH AND SWITCHING OSCILLATION REDUCTION IN POWER SEMICONDUCTOR DEVICE MODULES
In a general aspect, a half-bridge power module (800) includes a substrate (505) having a plurality of patterned metal layers(517a, 530a, 540) disposed thereon. The module also includes respective pluralities of high-side and low-side transistors (510, 520) disposed on the metal layers. A plurality of conductive clips (532, 542) respectively electrically couple the high-side transistors and the low-side transistors with the metal layers. ADC+ terminal (815a), a DC- terminal (825) and an output terminal (835) of the half-bridge module are also respectively, electrically coupled with the plurality of patterned metal layers.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/488 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de structures soudées
34.
ASSEMBLIES WITH EMBEDDED SEMICONDUCTOR DEVICE MODULES AND RELATED METHODS
In a general aspect, an assembly (200a) includes a panel of organic substrate core material (220a) having a cavity (221a, 221b) defined therein, a module substrate (212) disposed in the cavity, and a semiconductor die (216, 217) disposed on the module substrate. The assembly also includes a layer of prepreg organic substrate material (220b1), and a metal layer (240a). The module substrate and the semiconductor die are embedded in the cavity by the layer of prepreg organic substrate material and the metal layer. The metal layer is electrically coupled with at least one of the semiconductor die or the module substrate.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
An integrated substrate (88) may include a conductor layer (92); a heat sink (94) including a plurality of fins extending therefrom; and a dielectric layer (90) including boron nitride chemically bonded to the conductor layer (92) and to the heat sink (94) with an epoxy.
C04B 37/02 - Liaison des articles céramiques cuits avec d'autres articles céramiques cuits ou d'autres articles, par chauffage avec des articles métalliques
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/14 - Supports, p. ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
A sensor includes an array of optically active pixels disposed on a semiconductor die. The array of optically active pixels includes at least one pixel (PI) configured to detect short wavelength infrared radiation (SWIR), and at least one pixel (P2) configured to detect visible light incident on the sensor.
H04N 5/33 - Transformation des rayonnements infrarouges
G01N 21/35 - CouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes en recherchant l'effet relatif du matériau pour les longueurs d'ondes caractéristiques d'éléments ou de molécules spécifiques, p. ex. spectrométrie d'absorption atomique en utilisant la lumière infrarouge
A method includes identifying a region of interest (110) on an array of single-photon avalanche photodiodes (300, 310, 320) disposed on a surface (S) of a semiconductor device (100), enabling the single-photon avalanche photodiodes in the region of interest, and disabling the single-photon avalanche photodiodes that are outside the region of interest. The method further includes, in response to illumination incident on the surface of the semiconductor device, combining photocurrent outputs of the single-photon avalanche photodiodes in the region of interest in an analog photocurrent output channel (CH A, CH, B, CH C, CH S) of the semiconductor device.
G05B 19/042 - Commande à programme autre que la commande numérique, c.-à-d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
H01L 31/107 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel fonctionnant en régime d'avalanche, p.ex. photodiode à avalanche
H04N 25/773 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F comprenant des circuits de comptage de photons, p. ex. des diodes de détection de photons uniques [SPD] ou des diodes à avalanche de photons uniques [SPAD]
38.
SEMICONDUCTOR DEVICE TERMINATION STRUCTURES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE TERMINATION STRUCTURES
In an example, a semiconductor device (10) includes an active trench region (22A) and an intersecting trench region (22C, 22CA, 22CB). The active trench region (22A) includes an active shield electrode (21A) and the intersecting trench region (22C, 22CA, 22CB) includes an intersecting shield electrode (21C, 21C'). A coupling trench region (22B, 22B', 22BA) connects the active trench region (21A) to the intersecting trench region (22C, 22CA, 22CB). The coupling trench region (22B, 22B', 22BA) includes a coupling shield electrode (21B, 21B'). The coupling shield electrode (21B, 21B') and the intersecting shield electrode (21C, 21C') are provided proximate to a termination mesa region (16B, 16B', 16B''). One or more of the coupling shield electrode (21B, 21B') or the intersecting shield electrode (21C, 21C') is thinner than the active shield electrode (21A). The thinner shield electrode reduces depletion in the termination mesa region to improve, among other things, breakdown voltage performance.
Shielded gate semiconductor devices are disclosed for use in high power applications such as electric vehicles and industrial applications. The devices are formed as mesa (106)/trench (400) structures in which shielded gate electrodes are formed in the trenches. Various trench structures (400, 500, 600, 700) are presented that include tapered portions (401) and end tabs (502, 602, 702, 802) that can be beneficial in managing the distribution of electric charge and associated electric fields. The tapered trenches(400) can be used to increase and stabilize breakdown voltages in a termination region (104) of a semiconductor die (100).
In a general aspect, a diode (100) includes a substrate (102) of a first conductivity type, a semiconductor layer (104) of the first conductivity type disposed on the substrate and including a drift region (120), a shield region (110a) of a second conductivity type disposed in the semiconductor layer adjacent to the drift region, and a surface region (132a) of the first conductivity type disposed in a first portion of the drift region adjacent to the shield region. The surface region has a doping concentration greater than a doping concentration of a second portion of the drift region adjacent to the surface region. The second portion excludes the surface region. The diode includes a Schottky material (130) disposed on at least a portion of the shield region, the surface region in the first portion of the drift region; and the second portion of the drift region.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
In a general aspect, a diode (100, 200) includes a substrate (102, 202) and a semiconductor layer (104, 204) of a first conductivity type disposed on the substrate and including a drift region (120, 220); a shield region (110a, 110b, 210a, 210b) of a second conductivity type disposed in the semiconductor layer adjacent to the drift region; a first Schottky material (132a, 132b, 236a, 236b) disposed on a portion of the shield region and a first portion of the drift region, and defining a first Schottky contact (142a, 142b, 246a, 246b) with the drift region; and a second Schottky material (130, 232a, 232b) disposed on a second portion of the drift region adjacent to the first Schottky material, and defining a second Schottky contact (240, 242a, 242b) with the drift region. A barrier height of the first Schottky contact is less than a barrier height of the second Schottky contact.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
42.
TRENCH CHANNEL SEMICONDUCTOR DEVICES AND RELATED METHODS
Implementations of a semiconductor device may include a trench including a gate and a gate oxide formed therein, the trench extending into a doped pillar of a first conductivity type formed in a substrate material. The device may include a trench channel adjacent to the trench and two doped pillars of a second conductivity type extending on each side of the first conductivity type doped pillar where a ratio of a depth of each of the two second conductivity type doped pillars to a depth of the trench into the substrate material may be at least 1.6 to 1.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
43.
PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A COMPONENT STRUCTURE ADJACENT TO A TRENCH
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
In one general aspect, an apparatus can include a substrate (110, 410) having a semiconductor region (112, 122), and a trench (10, 40) defined in the semiconductor region and having a sidewall. The apparatus can include a shield electrode (130, 430) disposed in the trench and insulated from the sidewall of the trench by a shield dielectric (SD10), the shield dielectric having a low-k dielectric portion (LK10, LK40) and a high-k dielectric portion (HK10, HK40). The apparatus can include a gate electrode (120, 420) disposed in the trench and at least partially surrounded by a gate dielectric (GD10, GD40), and an inter-electrode dielectric (IE10, IE40) disposed between the shield electrode and the gate electrode.
An integrated circuit package (34, 34', 34'') may be implemented by stacked first, second, and third integrated circuit dies (40, 50, 60). The first and second dies (40, 50) may be bonded to each other using corresponding inter-die connection structures (74-1, 84-1) at respective interfacial surfaces facing the other die. The second die (50) may also include a metal layer (84-2) for connecting to the third die (60) at its interfacial surface with the first die (40). The metal layer (84-2) may be connected to a corresponding inter-die connection structure (64) on the side of the third die (60) facing the second die (50) through a conductive through-substrate via (84-2) and an additional metal layer (102) in a redistribution layer (96) between the second and third dies (50, 60). The third die (60) may have a different lateral outline than the second die (50).
A device (100, 250) includes a mesa (102, 202, 302, 402, 502) disposed between a pair of vertical trenches (101, 201, 301, 401, 501, 801) in a semiconductor substrate (105, 210, 310). A gate electrode (104g, 201G, 301G) is disposed in each of the pair of vertical trenches (101, 201, 301, 401, 501, 801), and a shield electrode (104s, 201S, 301S) is disposed below each of the gate electrodes (104g, 201G, 301G) in the pair of vertical trenches (101, 201, 301, 401, 501, 801). The device (100, 250) further includes a bridge connection trench (205, 305, 405, 505) traversing the mesa (102, 202, 302, 402, 502). The bridge connection trench (205, 305, 405, 505) is in fluid communication with each of the pair of vertical trenches (101, 201, 301, 401, 501, 801). A bridge shield electrode (204S, 304S) is disposed in the bridge connection trench (205, 305, 405, 505) and is coupled to the shield electrode (104s, 201S, 301S) disposed below each of the gate electrodes (104g, 201G, 301G) in the pair of vertical trenches (101, 201, 301, 401, 501, 801).
A method includes defining a plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of a first type that extend in a longitudinal direction in a semiconductor substrate, and defining a trench (105, 105-1, 105-2, 105-3, 105-4) of a second type extending in a lateral direction and intersecting the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type. The trench (105, 105-1, 105-2, 105-3, 105-4) of the second type is in fluid communication with each of the intersected plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type. The method further includes disposing a shield poly layer (111) in the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type and the trench (105, 105-1, 105-2, 105-3, 105-4) of the second type, disposing an inter-poly dielectric layer (112) and a gate poly layer (108) above the shield poly layer (111) in the plurality of trenches (101, 101-1, 101-2, 102-3, 10-4, 101-c, 101-L, 101-M, 101-U) of the first type and the trench (105, 105-1, 105-2, 105-3, 105-4) of the second type, and forming an electrical contact to the shield poly layer (111) through an opening (106, 16) in the inter-poly dielectric layer (112) and the gate poly layer (108) disposed in the trench of the second type.
A method may include determining, by an access point, which stations among multiple stations are permitted access to a wireless communication medium in a subsequent uplink frame. The method may also include broadcasting an uplink map to the stations, where the uplink map identifies a first station of the multiple stations as permitted access to the wireless communication medium. The uplink map may also identify an allocation of the subsequent uplink frame for the first station. The method may also include, during the allocation of the subsequent uplink frame allocated to the first station, receiving: an acknowledgment (ACK) of downlink data transmitted to the first station, uplink data, a resource allocation request from the first station requesting access to a second subsequent uplink frame, and/or combinations thereof.
The operational amplifier disclosed includes an input stage configured to receive power from a floating supply in a low voltage range that can float according to the common mode voltage at the input. The floating supply facilitates the use of low voltage components that can improve the precision of the operational amplifier by lowering the offset voltage. The input stage includes a first gain stage including field effect transistors and a second gain stage using bipolar transistors. The gain stages can be implemented differently to accommodate different applications and fabrication capabilities.
In a general aspect, a semiconductor device can (100) include a plurality of vertical transistor segments (200, 300) disposed in an active region (110) of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes (206b, 306b). A first dielectric (415, 915, 1015) can be disposed on the active region. An electrically conductive grid (130, 230, 330, 430, 630, 930, 1030) can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts (430a, 630a, 930a, 1030a) formed through the first dielectric. A second dielectric (925) can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion (951) that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact (930a) to the electrically conductive grid formed through the second dielectric.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
51.
PRECISION OPERATIONAL AMPLIFIER WITH A FLOATING INPUT STAGE
The operational amplifier disclosed includes an input stage configured to receive power from a floating supply circuit in a low voltage range that can float according to the common mode voltage at the input. The low voltage supply facilitates the use of low voltage components that can improve the precision of the operational amplifier by lowering the offset voltage. The input stage utilizes a first gain block and a second gain block. The first gain block is configured to have a low offset voltage while the second gain block is configured to have a high gain. Dividing these aspects over separate gain blocks improves the precision and noise performance of the operational amplifier. The operational amplifier has high gain at low frequencies and at high frequencies due to a topology that combines a low gain, high bandwidth path with a high gain, low bandwidth path at the output.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
52.
MIMO CHANNEL EXTENDERS WITH ASSOCIATED SYSTEMS AND METHODS
Multiple-input multiple-output (MIMO) radar systems are equipped with channel extenders to further increase the number of receive and/or transmit antennas that can be supported by a given radar transceiver. One illustrative radar system includes: a radar transceiver to generate a transmit signal and to downconvert at least one receive signal; and a receive-side extender that couples to a set of multiple receive antennas to obtain a set of multiple input signals, that adjustably phase-shifts each of the multiple input signals to produce a set of phase-shifted signals, and that couples to the radar transceiver to provide the at least one receive signal, the at least one receive signal being a sum of the phase-shifted signals. An illustrative receive-side extender includes: multiple phase shifters each providing an adjustable phase shift to a respective input signal; a power combiner that forms a receive signal by combining outputs of the multiple phase shifters.
A centralized occupancy detection system enables monitoring of multiple seats, or more generally, multiple stations, with a single sensor. One illustrative vehicle includes: one or more stations each configured to accommodate an occupant of the vehicle, a radar-reflective surface, and a radar transceiver configured to use the radar-reflective surface to detect an occupant of at least one of the stations. Another illustrative vehicle includes: multiple stations to each accommodate an occupant of the vehicle, and a radar transceiver configured to examine each of the multiple stations to determine whether that station has an occupant.
G01S 13/04 - Systèmes déterminant la présence d'une cible
G01S 13/56 - Discrimination entre objets fixes et mobiles ou entre objets se déplaçant à différentes vitesses pour la détection de présence
G01S 13/88 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques
B60R 21/01 - Circuits électriques pour déclencher le fonctionnement des dispositions de sécurité en cas d'accident, ou d'accident imminent, de véhicule
A SiC MOSFET device with alternating p-well widths (116a, 118a), including an undulating channel (110, 110a, 110b), is described. The undulating channel (110, 110a, 110b) provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs) (112a, 112b). The multi-width JFETs (112a, 112b) enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width (112a) into a JFET of a second width (112b).
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
55.
TERMINATION STRUCTURES WITH REDUCED DYNAMIC OUTPUT CAPACITANCE LOSS
In a general aspect, a semiconductor device (100, 400, 700, 900) can include a substrate (110, 410, 710, 910) of a first conductivity type, an active region (120, 420, 720, 920) disposed in the substrate, and a termination region (T) disposed in the substrate adjacent to the active region. The termination region can include a junction termination extension (130, 420, 730, 930) of a second conductivity type, where the second conductivity type is opposite the first conductivity type. The junction termination extension can have a first depletion stopper region (132, 432, 732, 932) disposed in an upper portion of the junction termination extension, a second depletion stopper region (134, 434, 734, 934) disposed in a lower portion of the junction termination extension, and a high carrier mobility region (136, 436, 736, 936) disposed between the first depletion stopper region and the second depletion stopper region.
A data logger system is disclosed. Specific implementations include a flexible data logger system. The data logger system may include a flexible substrate and a radio-frequency identification (RFID) communications module coupled to the flexible substrate. The RFID communications module may include an antenna coupled with a RFID chip. The data logger system may also include a microprocessor and a memory module coupled to the flexible substrate, the microprocessor and the memory module electrically coupled with the RFID communications module. The data logger system may also include a temperature sensor coupled to the flexible substrate, the temperature sensor electrically coupled with the microprocessor and memory module, and a power source coupled to the flexible substrate, the power source electrically coupled with the microprocessor, the memory module, the temperature sensor, and the RFID communications module.
G06K 7/01 - Méthodes ou dispositions pour la lecture de supports d'enregistrement Détails
G06K 7/10 - Méthodes ou dispositions pour la lecture de supports d'enregistrement par radiation électromagnétique, p. ex. lecture optiqueMéthodes ou dispositions pour la lecture de supports d'enregistrement par radiation corpusculaire
G06K 19/067 - Supports d'enregistrement avec des marques conductrices, des circuits imprimés ou des éléments de circuit à semi-conducteurs, p. ex. cartes d'identité ou cartes de crédit
H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
An example method may include receiving, from a wireless sniffer, sniffer data for a window of time, where the sniffer data may include wireless signal data. The method may also include obtaining corresponding access point data from an access point in a wireless network for at least part of the window of time for which the sniffer data is received. The method may additionally include analyzing the sniffer data and the corresponding access point data to assess performance of the wireless network.
A transceiver (103, 228) communicates with a station (105a, 105b) in a first network (101) and includes a detection circuit (236) that detects a signal in a second network (109) from a second transceiver (111, 228) to a second station (105, 105d). A coverage area of the second network (109) overlaps the first network (101). The detection circuit (236) determines a second symbol alignment of the signal in the second network (109) based on a preamble. The transceiver (103, 228) includes a precoding determination circuit (237) coupled to transmit chains (230) that determines a precoding matrix and the first symbol alignment. The first symbol alignment is synchronized with the second symbol alignment. The transmit chains (230) pre-code a signal in the first network (101) using the precoding matrix and align symbols of the signal in the first network (101) according to the first symbol alignment.
H04B 7/024 - Utilisation coopérative d’antennes sur plusieurs sites, p. ex. dans les systèmes à plusieurs points coordonnés ou dans les systèmes coopératifs à "plusieurs entrées plusieurs sorties" [MIMO]
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
SiC Schottky rectifiers with surge current ruggedness are described that may be configured to provide multiple types of surge current protection. Different current magnitudes and characteristics may be associated with the different types of surge current events. The described Schottky rectifier structures provide surge current protection in multiple types of surge current scenarios, while minimizing or reducing situations in which solution techniques in one context undesirably mitigate effects of solution techniques in another context.
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/36 - Corps semi-conducteurs caractérisés par la concentration ou la distribution des impuretés
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
60.
EMBEDDED CAPACITIVE SENSOR WITH CORESPONDING RAIN DETECTION METHOD AND RAIN DETECTION SYSTEM
Various embodiments of the present technology may provide methods and apparatus for a capacitive sensor (101) configured to detect rain (125). The capacitive sensor may be integrated within an interior surface of a laminated glass structure (130) comprising an adhesive interlayer (1410) disposed between two glass layers (1400, 1405). The capacitive sensor electrodes (105, 110) may be arranged in a variety of configurations between the two glass layers (1400, 1405). The capacitive sensor (101) may be used with a printed circuit board (135) that is configured to electrically couple to the capacitive sensor electrodes (105, 110).
G01N 27/22 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la capacité
B60S 1/08 - Essuie-glaces ou analogues, p. ex. grattoirs caractérisés par l'entraînement entraînés électriquement
61.
CAPACITIVE SENSOR WITH GROUND ELECTRODE AND CORESPONDING RAIN DETECTION METHOD AS WELL AS RAIN DETECTION SYSTEM
The present technology may provide methods and apparatus for a capacitive sensor (101) configured to detect rain (125). The capacitive sensor (101) may provide a reception electrode (105) in communication with a drive electrode (110) to form an electric field (150) and a ground electrode (115) surrounding the reception and drive electrodes (105, 110). The ground electrode (115) may couple the rain (125) to a ground potential resulting in a decrease in the capacitance of the capacitive sensor (101).
G01N 27/22 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la capacité
B60S 1/08 - Essuie-glaces ou analogues, p. ex. grattoirs caractérisés par l'entraînement entraînés électriquement
1,111) transmitted by the radar transmitter and to derive signal measurements therefrom. At least one of the radar transmitter and the radar receiver are switchable to provide the digital signal processor with signals from each of multiple combinations of transmit antenna (301) and receive antenna (302).
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
G01S 7/03 - Détails de sous-ensembles HF spécialement adaptés à ceux-ci, p. ex. communs à l'émetteur et au récepteur
H04B 7/08 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station de réception
An electronic device (10) may include an array of pixels (52). Each pixel may include a first single photon avalanche photodiode circuit (54-1) that generates a first output signal (VIN1) on a first conductive line (76-1), a second avalanche photodiode circuit (54-2) that generates a second output signal (VIN2) on a second conductive line (76-2), and a logic NAND gate (78) having a first input coupled to the first conductive line, a second input coupled to the second conductive line, and an output coupled to an output line (80). The logic NAND gate (78) may generate a third output signal (VOUT) based on the first and second output signals that is independent of dark current generated by the avalanche photodiodes. The third output signal (VOUT) may be processed to generate range values that are further processed to generate three-dimensional images of a scene.
Image sensors (200) may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates (210). A first n-epitaxial layer (204A) may be formed on a residual substrate (202); a first p-epitaxial layer (206A) may be formed on the first n-epitaxial layer; a second n-epitaxial layer (204B) may be formed on the first p-epitaxial layer; a second p-epitaxial layer (206B) may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers (204) may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates (210) may be a deep trench that is filled with doped conductive material (212), lined with gate dielectric liner (214), and surrounded by a p-doped region (216). Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.
Image sensors (200) may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates (210). A first n-epitaxial layer (204A) may be formed on a residual substrate (202); a first p-epitaxial layer (206A) may be formed on the first n-epitaxial layer; a second n-epitaxial layer (204B) may be formed on the first p-epitaxial layer; a second p-epitaxial layer (206B) may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers (204) may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates (210) may be a deep trench that is filled with doped conductive material (212), lined with gate dielectric liner (214), and surrounded by a p-doped region (216). Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.
In electron multiplying charge coupled device (EMCCD) image sensors (14), electron traps (209) in the dielectric stack underneath charge multiplication electrodes (201) may cause undesirable gain ageing. To reduce the gain ageing drift effect, a dielectric stack (304, 305) may be formed that does not include electron traps in regions underneath charge multiplication electrodes. To accomplish this, silicon nitride (305) in the dielectric stack may be removed in regions underneath the charge multiplication electrodes. The EMCCD image sensors can thus be fabricated with a stable charge carrier multiplication gain during their operational lifetime.
Various embodiments of the present technology may comprise a method and apparatus for a power management unit (205). The power management unit (205) may be configured to operate in conjunction other integrated circuits to mitigate power dissipation. The power management unit (205) may receive temperature information from a temperature sensor (120) and deploy various power management schemes to reduce the leakage power of an SRAM (210). The power management schemes may be based on the particular characteristics of the SRAM (210).
H04N 5/369 - Transformation d'informations lumineuses ou analogues en informations électriques utilisant des capteurs d'images à l'état solide [capteurs SSIS] circuits associés à cette dernière
An image sensor pixel (22) may include multiple split photodiodes (50, 52) that are covered by a single microlens. The image sensor may include a charge overflow capacitor (66) coupled to a pixel charge storage (64) within the image sensor (22) via a gain control transistor (68). The image sensor pixel (22) may have phase detection capabilities in a first mode of operation enabled by comparing phase signals generated from the split photodiodes (50, 52). The image sensor pixel (22) also may generate and readout image signals simultaneously in both rolling shutter operations and global shutter operations in a second mode of operation. The image sensor pixel (22) may also generate an image using a linear combination of at least two signals read out using the charge overflow capacitor (66) and light flickering mitigation operations. The image may be a high dynamic range image that is generated from at least a low exposure signal and a high exposure signal.
H04N 5/3745 - Capteurs adressés, p.ex. capteurs MOS ou CMOS ayant des composants supplémentaires incorporés au sein d'un pixel ou connectés à un groupe de pixels au sein d'une matrice de capteurs, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
H04N 5/359 - Traitement du bruit, p.ex. détection, correction, réduction ou élimination du bruit appliqué aux porteurs de charge en excès générés par l'exposition, p.ex. bavure, tache, image fantôme, diaphonie ou fuite entre les pixels
In accordance with at least one embodiment, a method for detecting a liquid level includes providing a container (402) having a cavity, and disposing a sensor (102) in the cavity of the container (402), such that a ground pattern (310) on a first surface of the sensor (102) is positioned to contact a liquid in the cavity. A first electrode (104) and a second electrode (106) are located on a second surface of the sensor (102). The sensor (102) is coupled to a sensor input and a sensor driver. A cable coupling the sensor (102) to a touch sensor (116) comprises a shield line (112, 114) that is coupled to ground.
G01F 23/26 - Indication ou mesure du niveau des liquides ou des matériaux solides fluents, p. ex. indication en fonction du volume ou indication au moyen d'un signal d'alarme en mesurant des variables physiques autres que les dimensions linéaires, la pression ou le poids, selon le niveau à mesurer, p. ex. par la différence de transfert de chaleur de vapeur ou d'eau en mesurant les variations de capacité ou l'inductance de condensateurs ou de bobines produites par la présence d'un liquide ou d'un matériau solide fluent dans des champs électriques ou électromagnétiques
G01F 25/00 - Test ou étalonnage des appareils pour la mesure du volume, du débit volumétrique ou du niveau des liquides, ou des appareils pour compter par volume
70.
IMAGE SENSOR SEMICONDUCTOR PACKAGES AND RELATED METHODS
An image sensor semiconductor package (52) includes a printed circuit board (PCB) (56) having a first surface (58) and a second surface (60) opposite the first surface. A complementary metal- oxide semiconductor (CMOS) image sensor (CIS) die (4) has a first surface (6) with a photosensitive region (8) and a second surface (10) opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover (30) is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) (42) is embedded within the PCB. One or more electrical couplers (26) electrically couple the CIS die with the PCB. A plurality of electrical contacts (36) on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.
Implementations of semiconductor packages may include: a first semiconductor die coupled to a first side of a substrate having one or more internal traces. One or more connectors coupled to the first semiconductor die and the first side of the substrate. A glass lid coupled to the first side of the substrate over the first semiconductor die. A mold compound that encapsulates at least a portion of the substrate. A second semiconductor die coupled to a second side of the substrate opposing the first side. The second semiconductor die is electrically coupled with the first semiconductor die through the one or more traces of the substrate.
An image sensor (16) may include pixels (22) having nested sub-pixels. A pixel (22) with nested sub-pixels may include an inner sub-pixel (202) that has either an elliptical or a rectangular light collecting area. The inner sub-pixel may be formed in a substrate and may be immediately surrounded by a sub-pixel group (204) that includes one or more sub-pixels. The inner sub-pixel (202) may have a light collecting area at a surface (216) that is less sensitive than the light collecting area of the one or more outer sub-pixel groups. Microlenses (1040) may be formed over the nested sub-pixels, to direct light away from the inner sub-pixel group (202) to the outer sub-pixel groups (204) in nested sub-pixels. A color filter (1250) of a single color may be formed over the nested sub-pixels. Hybrid color filters having a single color filter region (1150) over the inner sub-pixel and a portion of the one or more outer sub-pixel groups may also be used.
An imaging pixel (100) may be provided with an upper substrate layer (30), a lower substrate layer (32), a floating diffusion region (52) in the upper substrate layer, and a photodiode (36) in the upper substrate layer that is coupled to the floating diffusion region. The imaging pixel may also include a source follower transistor (62) in the lower substrate layer and an interconnect layer (34) in between the upper substrate layer and the lower substrate layer. The interconnect layer may couple the floating diffusion region directly to the source follower transistor. The imaging pixel may include a reset transistor (54) in the upper substrate layer. The imaging pixel may include a metal layer (58) in the lower substrate layer, a transfer transistor (50) in the upper substrate layer, and an interconnect layer (34-2) that couples the transfer transistor to the metal layer.
Pulse width modulated controller systems. Implementations may include: a microcontroller coupled with a memory, a switch controller coupled with the microcontroller, and a calibration unit. The calibration unit may include one or more comparators, one or more passive electrical components, and an encoder logic all operatively coupled together and coupled with the microcontroller and with the switch controller where the at least one comparator and the one or more passive electrical components are electrically coupled with a supply voltage to the semiconductor switch and with a load voltage (output voltage) from the semiconductor switch.
H03K 17/042 - Modifications pour accélérer la commutation par réaction du circuit de sortie vers le circuit de commande
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation avec commande numérique
75.
SEMICONDUCTOR PACKAGES WITH AN INTERMETALLIC LAYER HAVING A MELTING TEMPERATURE ABOVE 260°C, COMPRISING AN INTERMETALLIC CONSISTING OF SILVER AND TIN OR AN INTERMETALLIC CONSISTING OF COPPER AND TIN, AND CORRESPONDING MANUFACTURING METHODS
Methods of forming a semiconductor package (2, 12) are provided. Implementations include forming on a die backside (16) an intermediate metal layer (26) having multiple sublayers (40-46), each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer (48) is deposited onto the intermediate metal layer (26) and is then reflowed with a silver layer (52) of a substrate (50) to form an intermetallic layer (56) having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump (22) on each of a plurality of exposed pads (20) of a top side (18) of a die (14), each exposed pad (20) surrounded by a passivation layer (24), each bump (22) including an intermediate metal layer (36) as described above and a tin layer (48) coupled to the intermediate metal layer (36), the tin layer (48) being then reflowed with a silver layer (52) of a substrate (50) to form an intermetallic layer (64), as described above.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/482 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p. ex. contacts planaires
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
A semiconductor package. Implementations may include a substrate including a metallic baseplate coupled with an electrically insulative layer and a plurality of metallic traces coupled to the electrically insulative layer on a surface of the electrically insulative layer opposing a surface of the electrically insulative layer coupled to the metallic baseplate. The plurality of metallic traces may include at least two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the surface of the electrically insulative layer coupled with the metallic baseplate. The package may include at least one semiconductor device coupled to the substrate, a mold compound that encapsulates the power electronic device and at least a portion of the substrate, and at least one package electrical connector coupled with the substrate.
An imaging system (100) may include an image sensor die (102) stacked on top of a digital signal processor (DSP) die (104). Through-oxide vias (TOVs) (128) may be formed in the image sensor die (102) and may extend at least partially into in the DSP die (104) to facilitate communications between the image sensor die (102) and the DSP die (104). The image sensor die (102) may include light shielding structures (126) for preventing reference photodiodes (116') in the image sensor die (102) from receiving light and in-pixel grid structures (200) for preventing cross-talk between adjacent pixels (116). The light shielding structure (126) may receive a desired biasing voltage through a corresponding TOV (128), an integral plug structure (190), and/or a connection that makes contact directly with a polysilicon gate (192). The in-pixel grid (200) may have a peripheral contact (200') that receives the desired biasing voltage through a light shield (210), a conductive strap (210), a TOV (300), and/or an aluminum pad (450).
H01L 27/14 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des composants semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit ra
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H04N 5/369 - Transformation d'informations lumineuses ou analogues en informations électriques utilisant des capteurs d'images à l'état solide [capteurs SSIS] circuits associés à cette dernière
In accordance with an embodiment, a method for detecting a fluid level, includes providing a fluid container (80) having a cavity and coupling a first sensor (30, 32, 34, 36 to the fluid container, the first sensor protected from a fluid in the cavity and positioned at a first vertical level of the fluid container. The method further includes causing movement of either the first sensor or the fluid container. The first sensor is used to detect the fluid level upon causing the movement of either the first sensor or the fluid container.
G01F 23/26 - Indication ou mesure du niveau des liquides ou des matériaux solides fluents, p. ex. indication en fonction du volume ou indication au moyen d'un signal d'alarme en mesurant des variables physiques autres que les dimensions linéaires, la pression ou le poids, selon le niveau à mesurer, p. ex. par la différence de transfert de chaleur de vapeur ou d'eau en mesurant les variations de capacité ou l'inductance de condensateurs ou de bobines produites par la présence d'un liquide ou d'un matériau solide fluent dans des champs électriques ou électromagnétiques
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
Provided is a production method for a circuit device whereby a resin sealing step for sealing with a thin coat of resin on a rear surface of a circuit substrate having a circuit element integrated on an upper surface thereof is achieved at low cost. In the present invention, an upper surface and a side surface of a circuit substrate (14) having a hybrid integrated circuit are coated with a first sealing resin (18) formed by transfer molding, and a lower surface of the circuit substrate (14), and a lower surface and a side surface of the first sealing resin (18) are subsequently coated with a second sealing resin (20). Furthermore, in a step for forming the second sealing resin (20), stable transfer molding is achieved by fixing the position of the workpiece such that resin-protruding portions (12), obtained by having the first sealing resin (18) protrude partially downwards, are in contact with an inner wall of a second die (50).
Provided is a circuit device manufacturing method wherein a resin sealing step of thinly sealing the rear surface of a circuit board with a resin is performed at low cost, said circuit board having circuit elements mounted on the upper surface thereof. In the present invention, the upper surface and the side surfaces of a circuit board (14) are coated with a first sealing resin (18) that is formed by transfer molding, said upper surface having a hybrid integrated circuit mounted thereon, then, the lower surface of the circuit board (14), and the lower surface and the side surfaces of the first sealing resin (18) are coated with a second sealing resin (20). Furthermore, in a step of forming the second sealing resin (20), stable transfer molding is performed by fixing the position by having the upper surface of the first sealing resin (18) in contact with the inner wall of a second molding die (50).
An integrated circuit includes a first configuration terminal, a second configuration terminal, a bus terminal, and an auto addressing circuit coupled to the first and second configuration terminals. The auto addressing circuit is responsive to a data pattern received at the first configuration terminal to assign a node address to an operational circuit, and subsequently to couple the first configuration terminal to the second configuration terminal. The integrated circuit is subsequently responsive to the node address when the node address is received.
In a MOSFET, the lead parts of gate lead wiring that lead out a gate electrode on the periphery of a substrate constitute a non-operative region where it is impossible to dispose a MOSFET transistor cell (C) that will function as efficiently as inside an element region. If the gate lead wiring is disposed along the four edges of a chip, for example, the area of the non-operative region increases, limiting the extent to which the surface area of the element region can be enlarged and the chip surface area reduced. In the present invention, gate lead wiring and a conductor, which is connected to the gate lead wiring and a protection diode, are disposed in a non-curved, linear configuration along one edge of a chip. In addition, a first gate electrode layer that extends superimposed on the gate lead wiring and the conductor, and connects the gate lead wiring and the conductor to the protection diode, has no more than one curved part. Furthermore, the protection diode is disposed adjacent to the conductor or the gate lead wiring, and a portion of the protection diode is disposed near a gate pad.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 23/52 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
83.
ELECTONIC DEVICE WITH FLEXIBLE DATA AND POWER INTERFACE
Electronic modules with small and flexible interfaces are disclosed. One example electronic module includes a power supply terminal configured to receive power for the electronic module and circuitry configured to carry out various functions. The functions carried out by the electronic module circuitry include simultaneously receiving both of the following via the power supply terminal: a power signal for carrying out a mission mode operation of the electronic module, and a data signal.
In accordance with an embodiment, a converter includes a power factor controller that varies the switching frequency of a switching transistor in accordance with a signal representative of power at the input of the converter.
In one embodiment, a method of forming a conditioning circuit includes configuring an output biasing network to provide a biasing voltage to an MOS transistor to enable the MOS transistor to operate in a saturated operating mode for input voltages that are less than a threshold voltage.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
In accordance with an embodiment, a pixel includes at least two switches, each switch having a control terminal and first and second current carrying terminals. The control terminals of the first and second switches are commonly connected together. In accordance with another embodiment, a method for transferring charge from a first switch to a capacitance includes applying voltage to the commonly connected control terminals of the first and second switches.
H04N 5/3745 - Capteurs adressés, p.ex. capteurs MOS ou CMOS ayant des composants supplémentaires incorporés au sein d'un pixel ou connectés à un groupe de pixels au sein d'une matrice de capteurs, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
H04N 5/374 - Capteurs adressés, p.ex. capteurs MOS ou CMOS
In accordance with an embodiment, a 4T pixel includes a first switch having a control terminal and first and second current carrying terminals and an amplifier having an input terminal and an output terminal. A second switch is coupled between the first switch and the amplifier.
H04N 5/3745 - Capteurs adressés, p.ex. capteurs MOS ou CMOS ayant des composants supplémentaires incorporés au sein d'un pixel ou connectés à un groupe de pixels au sein d'une matrice de capteurs, p.ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
88.
METHOD AND APPARATUS FOR DETECTING HOLD CONDITION ON AN ACOUSTIC TOUCH SURFACE
A bending wave touch system (100) includes at least one sensor (106) and a touch controller (124). The at least one sensor is coupled to a substrate (104) and is responsive to vibrations in the substrate. The at least one sensor outputs signals. The controller receives the signals from the at least one sensor and identifies touch coordinates based on high frequency components of the signals when a touch on the substrate includes at least one of a tap, a drag and a lift-off. The controller identifies a status of a hold condition of the touch based on at least two different time averages of low frequency components of the signals.
G06F 3/043 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction utilisant la propagation d'ondes acoustiques
89.
METHOD OF FORMING A POWER SUPPLY CONTROLLER AND SYSTEM THEREFOR
In one embodiment a power supply is configured to reuse a single power supply controller to regulate two different output voltages to two voltages including two different voltage values.
H05B 41/24 - Circuits dans lesquels la lampe est alimentée par courant alternatif à haute fréquence
H02M 3/28 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire
90.
PLL CIRCUIT, AND RADIO COMMUNICATION DEVICE EQUIPPED THEREWITH
NATIONAL UNIVERSITY CORPORATION GUNMA UNIVERSITY (Japon)
Inventeur(s)
Dan, Toru
Tanabe, Tomoyuki
Kobayashi, Haruo
Abrégé
In an ADPLL circuit (100), a DCO gain estimation unit (20) estimates, on the basis of the gain of a digital control oscillator (10), which is estimated in the state in which the loop gain with some value is set for a loop filter (18), and the element parameter of the digital control oscillator (10), the gain of the digital control oscillator (10) in the state in which the loop gain with another value is set for the loop filter (18).
H03L 7/107 - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage utilisant une fonction de transfert variable pour la boucle, p. ex. un filtre passe-bas ayant une largeur de bande variable
H03L 7/06 - Commande automatique de fréquence ou de phaseSynchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase
A method and circuit for suppressing a bias current and decreasing power consumption. A current suppression circuit is coupled to a circuit element, which is capable of conducting the bias current. Coupling the current suppression circuit to the circuit element forms a node. In one operating mode, the current suppression circuit applies a voltage to the node in response to a heavy load. In another operating mode, the current suppression circuit lowers the voltage at the node in response to a light load or no load. Lowering the voltage at the node decreases the flow of bias current through the circuit element thereby lowering power loss.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
A circuit and method for detecting a brown-out condition and providing a feed-forward transfer function in a power supply circuit. A comparison circuit is coupled to a delay element through a latch. A second delay element is connected between the first delay element and an input of the latch. The output of the first delay element is connected to a clamping circuit via a logic circuit. A first voltage is compared with a reference voltage to generate a comparison voltage, which is transmitted through the latch and the first delay element. The comparison voltage is monitored at an output of the first delay element. A brown-out condition occurs if the comparison voltage being monitored at the output of the first delay element results from the first voltage being less than the reference voltage.
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
93.
METHOD FOR PROVIDING OVER CURRENT PROTECTION AND CIRCUIT
A method and circuit for protecting against an over current condition. A conduction time of one or more transistors is reduced during the over current condition. The conduction time is reduced in an amount that is an increasing function of the amount of the over current. The conduction time may be reduced proportionally to the excess current.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
94.
CIRCUIT FOR GENERATING A CLOCK SIGNAL FOR INTERLEAVED PFC STAGES AND METHOD THEREOF
A method and circuit for generating a clock signal. A power factor correction circuit has n channels operating out of phase and independently. The circuit is able to generate a clock signal for each channel according to the current cycle duration of each channel.
In one embodiment, a quasi-resonant power supply controller is configured to select particular valley values of a switch voltage to determine a time to enable a power switch. The valleys values are selected responsively to a range of values of a feedback signal.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
96.
AMPLIFIER WITH REDUCED OUTPUT TRANSIENTS AND METHOD THEREFOR
An amplifier (210) includes an input stage (310, 320) and an output stage (330). The input stage (310, 320) has an input for receiving an input signal, and an output. The output stage (330) has an input coupled to the output of the input stage (310, 320), and an output for providing an amplified output signal. The output stage (330) includes a gain stage and a bias circuit. The gain stage has an input forming the input of the output stage, an output for providing the amplified output signal, and a first bias terminal. The bias circuit has a first output terminal coupled to the first bias terminal of the gain stage. During a turn-on period the bias circuit gradually ramps the first bias terminal from a first initial voltage to a first bias voltage.
H03F 1/30 - Modifications des amplificateurs pour réduire l'influence des variations de la température ou de la tension d'alimentation
H03F 3/30 - Amplificateurs push-pull à sortie uniqueDéphaseurs pour ceux-ci
H03F 3/187 - Amplificateurs à basse fréquence, p. ex. préamplificateurs à fréquence musicale comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03G 3/34 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs rendant l'amplificateur muet en l'absence de signal
H03F 3/72 - Amplificateurs commandés, c.-à-d. amplificateurs mis en service ou hors service au moyen d'un signal de commande
97.
METHOD OF FORMING A SWITCHING REGULATOR AND STRUCTURE THEREFOR
In one embodiment, a power supply controller is configured to receive a sense signal (CS) having a negative value that is proportional to the input voltage. The power supply controller uses the sense signal to limit the switch (27) current through the switch responsively to the value of the input voltage.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
98.
METHOD OF FORMING A DETECTION CIRCUIT AND STRUCTURE THEREFOR
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
A signal generation circuit that uses a waveform generation mechanism to generate predetermined waveform(s) when triggered. A triggering mechanism is configured to repeatedly trigger the waveform generation mechanism at times that are dependent on data provided by a data source. The predetermined waveform may be a bandwidth-limited pulse, but might also be a rising edge or a falling edge of a pulse. Various consecutive waveforms may be summed together to thereby formulate a continuous signal. The waveform may have particular characteristics by design.
A method for regulating the output voltage of a power supply. A boost PWM switching converter adjusts the gate drive signals to a switching transistor and a pass transistor so that the power supply has an operating frequency, Fs, based on a comparison between a parameter and a reference. The parameter may be a ratio of an input voltage to an output voltage, a difference between the output voltage and the input voltage, or the value of an input voltage. In accordance with the comparison between the parameter and the reference, the switching control circuit linearly decreases the operating frequency of the power supply. By changing the operating frequency, the output and input voltages of the power regulator may be almost equal to each other when operating with a control signal having a low duty cycle while maintaining a low output voltage ripple and a low inductor current ripple.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
brevets
