This semiconductor device comprises: a heat dissipation member; a base material that includes a heat dissipation layer that faces the heat dissipation member in a first direction; a first conductive layer that is positioned on the opposite side of the base material from the heat dissipation member, and that is joined to the base material; a first semiconductor element that is joined to the first conductive layer; and a joining layer that joins the heat dissipation member and the heat dissipation layer. The joining layer includes a sintered body of metal particles. The joining layer is provided with a void portion penetrating in the first direction.
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
2.
LIGHT-EMITTING ELEMENT DRIVE DEVICE, LIGHT-EMITTING SYSTEM, BACKLIGHT, AND DISPLAY DEVICE
A light-emitting element drive device (1) includes: a voltage monitor unit (12) configured to monitor a voltage of a connection terminal (CH) for each switch (SW) that was turned on and to hold a monitor result; and a control signal generation unit (13) configured to update a control signal (Ifb) used for feedback control of a power supply voltage (Vout) in a power supply circuit (3) on the basis of the held monitor result, when the monitor result is held for all light-emitting units (LL).
A signal generation circuit according to one embodiment comprises: a delay signal generation unit configured so as to generate at least one delay pulse signal using an input pulse signal common to a first switching element and a second switching element; and a logic synthesis unit configured so as to generate a first control pulse signal and a second control pulse signal for the first switching element and the second switching element by performing different logic synthesis on two signal sets of a plurality of signal sets specified by the at least one delay pulse signal and the input pulse signal. The first control pulse signal is different from the input pulse signal, and the second control pulse signal is different from the input pulse signal and the first control pulse signal.
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
4.
SEMICONDUCTOR DEVICE, INVERTER DEVICE, METHOD FOR MANUFACTURING INVERTER DEVICE, AND VEHICLE
This semiconductor device comprises a substrate, a first conductive layer, a first semiconductor element, and a bonding material. The substrate includes a heat dissipation layer. The first conductive layer is bonded to the substrate. The first semiconductor element is bonded to the first conductive layer. The bonding material is positioned on the side opposite to the first conductive layer relative to the substrate in a first direction, and is disposed on the heat dissipation layer. The bonding material includes metal particles. As one embodiment, the semiconductor device further comprises a sealing resin that covers the first semiconductor element.
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
This semiconductor device comprises a semiconductor layer, a gate trench and a dummy trench which extend in the semiconductor layer, a plurality of contact plugs which penetrate the insulating layer to be in contact with the semiconductor layer. The gate trench and the dummy trench each extend in a first direction in plan view. The semiconductor layer includes a gate-dummy mesa part which is defined between the gate trench and the dummy trench. The plurality of contact plugs include a row of contact plugs which is in contact with the gate-dummy mesa part. The row of contact plugs at least partially overlaps the dummy trench in plan view and is separate from the gate trench. The contact plugs included in the row are arranged so as to be spaced in the first direction.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 84/40 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou avec au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET avec des transistors BJT
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
This semiconductor device comprises: a chip having a main surface; a first conductivity type semiconductor region formed on the surface layer portion of the main surface; an active region that is provided in an inner portion of the main surface; an outer peripheral region that is provided in a peripheral edge portion of the main surface; a trench type separation structure that is formed in the main surface so as to be positioned in the semiconductor region and that delimits the active region and the outer peripheral region; and a second conductivity type well region that is formed in a region below the separation structure so as to be positioned in the semiconductor region and is electrically connected to the semiconductor region.
A semiconductor element according to the present invention comprises a body, an electrode, rewiring, a first protective film, and a first intermediate layer. The electrode is positioned on one side of the body in a first direction. The rewiring is positioned on the side opposite the body with respect to the electrode. The first protective film is positioned on the same side as the rewiring with respect to the electrode. When viewed in the first direction, the first protective film overlaps the rewiring. The first intermediate layer includes a first portion positioned between the rewiring and the first protective film. The first portion is in contact with the first protective film. The first intermediate layer is an insulator and contains an inorganic compound. The adhesive force of the first protective film with respect to the first intermediate layer is stronger than the adhesive force of the first protective film with respect to the rewiring.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
H01L 23/12 - Supports, p. ex. substrats isolants non amovibles
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
8.
SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND VEHICLE
An overcurrent protection circuit 34 limits an output current IOUT to an overcurrent protection threshold IocpL or less from an instruction to turn on an output switch 9 until a terminal-to-terminal voltage Vds becomes less than a detection threshold Vx (until t51). After the terminal-to-terminal voltage Vds has become less than the detection threshold Vx, the overcurrent protection circuit 34 forces the output switch 9 off when the output current IOUT exceeds an overcurrent protection threshold IocpH (>IocpL), and cancels the forced turn-off when the output current IOUT becomes less than the overcurrent protection threshold IocpH (t51-54). Once the number of times the output switch 9 is forced off reaches an upper limit value after the terminal-to-terminal voltage Vds has become less than the detection threshold Vx, the overcurrent protection circuit 34 forces the output switch 9 off when the output current IOUT exceeds the overcurrent protection threshold IocpH, and cancels the forced turn-off when time T2 has elapsed (after t54).
H02J 1/00 - Circuits pour réseaux principaux ou de distribution, à courant continu
H02H 5/04 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions non électriques normales de travail avec ou sans reconnexion sensibles à une température anormale
H02H 7/00 - Circuits de protection de sécurité spécialement adaptés aux machines ou aux appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou de ligne, et effectuant une commutation automatique dans le cas d'un changement indésirable des conditions normales de travail
This semiconductor device comprises: a chip that has a main surface; a semiconductor region of a first conductivity type that is formed on a surface layer part of the main surface; an active region that is provided to an inner part of the main surface; an outer peripheral region that is provided to a peripheral edge part of the main surface; a trench-type separation structure that is formed in the main surface so as to be positioned in the semiconductor region, and that divides the active region and the outer peripheral region; and a termination region of a second conductivity type that is disposed to the peripheral edge side of the chip with respect to the separation structure so as to be positioned inside the semiconductor region in the outer peripheral region.
A semiconductor device according to the present invention is configured to reduce displacement of the device on a heat dissipation member. The semiconductor device comprises a first conductive layer, a first semiconductor element, a target member, and a sealing resin. The first semiconductor element is electrically connected to the first conductive layer. The sealing resin covers the first conductive layer and a portion of each of the first semiconductor element and the target member. The sealing resin has a first surface that is directed in a first direction and a first opening that opens from the first surface. The target member has a first engagement part that is exposed from the first opening.
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/40 - Supports ou moyens de fixation pour les dispositifs de refroidissement ou de chauffage amovibles
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
11.
SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND VEHICLE
A semiconductor device (200) is provided with, for example, at least one voltage drive circuit (DRV1H) that voltage-drives a switch control signal (Vg), and a current drive circuit (DRV2H) that current-drives the switch control signal (Vg). The at least one voltage drive circuit (DRV1H) is turned on in some periods (T1, T2, T4) among a plurality of periods (T1 to T4) included in a logic level transition period (Ton_tr) of the switch control signal (Vg), and is turned off in the remaining period (T3). The current drive circuit (DRV2H) is turned on in all of the plurality of periods (T1 to T4).
H03K 17/691 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ avec une isolation galvanique entre le circuit de commande et le circuit de sortie utilisant un couplage par transformateur
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
This semiconductor device includes: a semiconductor substrate; a transistor; a temperature-sensitive diode; a fourth insulating layer formed above the temperature-sensitive diode; a diode pad provided at a position separated from the temperature-sensitive diode when viewed from the thickness direction of the semiconductor substrate; an embedded wiring; and a first transistor pad. The semiconductor substrate includes a substrate upper surface and a substrate lower surface facing opposite the substrate upper surface. The transistor is formed above the substrate upper surface of the semiconductor substrate. The temperature-sensitive diode is formed above the substrate upper surface of the semiconductor substrate. The embedded wiring is embedded in the fourth insulating layer and is used to connect the temperature-sensitive diode and the diode pad. The first transistor pad: includes a section formed above the temperature-sensitive diode with the fourth insulating layer disposed therebetween; and is electrically connected to the transistor.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
A gate driver circuit (200) drives an N-type power transistor (110) on the basis of a control signal CTRL. A first transistor M1 is connected between a high-side line (202) and an output line (206). A second transistor M2 is connected between the output line (206) and a low-side line (204). A third transistor M3 is connected in parallel with the second transistor M2 between the output line (206) and the low-side line (204). When the control signal CTRL transitions from an off level to an on level, an auxiliary circuit (220) turns on the third transistor M3 for a prescribed duration.
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
This transducer performs electro-acoustic conversion and comprises: a diaphragm that can vibrate in a plate thickness direction; a driver that causes the diaphragm to vibrate by electrical energy; and a first lid body that covers the diaphragm. The first lid body has formed therein a through hole that allows sound waves from the diaphragm, which is a surface sound source, to be emitted to the outside as a point or line sound source by causing an internal space formed between the first lid body and the diaphragm to communicate with the outside. By forming a plurality of through holes, the sound waves from the point or line sound source are combined, and the widths and depths of the plurality of through holes are set such that, of maximum values of the volume of air blown out from or sucked into an internal space which are obtained on the basis of the vibration amplitude and the vibration frequency of the diaphragm, the maximum volume of air in terms of the vibration frequency can pass through the through holes.
H04R 1/40 - Dispositions pour obtenir la fréquence désirée ou les caractéristiques directionnelles pour obtenir la caractéristique directionnelle désirée uniquement en combinant plusieurs transducteurs identiques
For example, a semiconductor device 400 comprises: a first drive circuit 410 that drives a first drive signal GH of a first transistor QH between a positive power supply voltage VCC2 and a first intermediate voltage (for example, a ground voltage GND2) lower than the positive power supply voltage VCC2 and higher than a negative power supply voltage VEE2; and a second drive circuit 420 that generates a second drive signal GL of a second transistor QL between a second intermediate voltage (for example, a floating voltage VREG2) lower than the positive power supply voltage VCC2 and higher than the negative power supply voltage VEE2 and the negative power supply voltage VEE2.
H03K 17/691 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ avec une isolation galvanique entre le circuit de commande et le circuit de sortie utilisant un couplage par transformateur
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
This semiconductor device is provided with: a first semiconductor element having a first electrode positioned on one side in a first direction; a first terminal facing the first semiconductor element; a first pillar electrically connected to the first electrode; and a first heat dissipation member electrically connected to the first terminal. In the first direction, a first flow path is provided between the first semiconductor element and the first terminal. The first pillar and the first heat dissipation member are accommodated in the first flow path. The first heat dissipation member is conductively bonded to the first pillar.
H01L 23/44 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température le dispositif complet étant totalement immergé dans un fluide autre que l'air
H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
This chip component includes a substrate, a first capacitor structure that is formed on the substrate, and a second capacitor structure that is formed on the substrate. The first capacitor structure and the second capacitor structure are electrically connected in parallel to each other. The first capacitor structure is a trench capacitor. For example, the capacitance of the first capacitor structure is higher than the capacitance of the second capacitor structure. The substrate contains a semiconductor. For example, the substrate contains silicon.
This semiconductor device comprises: a semiconductor element; a plurality of connection parts each having conductivity; a sealing part covering a part of each of the semiconductor element and the plurality of connection parts; a plurality of signal terminals inserted into any one of the plurality of connection parts; and a holding part. The plurality of signal terminals protrude from the sealing part on one side in the thickness direction of the sealing part. The holding part covers a part of each of the plurality of signal terminals. As an example, the plurality of signal terminals are collectively held and inserted into the plurality of connection parts.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01R 12/58 - Connexions fixes pour circuits imprimés rigides ou structures similaires caractérisées par les bornes bornes pour insertion dans des trous
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
This semiconductor device comprises: a first lead that has a first pad part; a first semiconductor element that is disposed to one side of the first pad part in the thickness direction; a second lead that has a second pad part which is disposed separately from the first pad part in the first direction; a second semiconductor element that is disposed to one side of the second pad part in the thickness direction; a first bonding wire that is bonded to the first semiconductor element; a second bonding wire that is bonded to the second semiconductor element; and a sealing resin. As seen in the first direction, the first semiconductor element overlaps the second semiconductor element. The first semiconductor element is disposed disproportionately more toward one side in the second direction. The second semiconductor element is disposed disproportionately toward said one side in the second direction.
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
20.
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND VEHICLE
This semiconductor device comprises a first semiconductor element including a first electrode, a first terminal facing the first electrode, a first heat dissipation member electrically connected to the first terminal, and a first protective layer covering a part of the first semiconductor element. The first heat dissipation member is electrically connected to the first electrode. The first protective layer is an insulator. A first flow path is provided between the first semiconductor element and the first terminal. The first heat dissipation member is accommodated in the first flow path. The first protective layer is provided with a first opening through which the first electrode is exposed. The first heat dissipation member includes a first end inserted into the first opening. In the first opening, a gap is provided between the first end and the first protective layer.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
This semiconductor device includes a first terminal and a first semiconductor element conductively joined to the first terminal. The first terminal has a first main surface facing one side in a first direction. The first terminal is provided with a first heat dissipation part protruding from the first main surface. The first terminal is provided with a first opening part that opens from the first main surface. The first opening part is connected to the first heat dissipation part.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
This terahertz system includes: a transmission device that includes a first active element which oscillates a terahertz wave W on the basis of the application of a first drive voltage VD1, the transmission device being configured to be capable of transmitting the terahertz wave W; a reception device that includes a second active element capable of detecting the terahertz wave W on the basis of the application of a second drive voltage VD2, and is configured to be able to receive the terahertz wave W; and a control unit that outputs the first drive voltage VD1 and the second drive voltage VD2. The control unit periodically and continuously changes the first drive voltage VD1 and the second drive voltage VD2.
H03B 7/08 - Production d'oscillations au moyen d'un élément actif ayant une résistance négative entre deux de ses électrodes avec un élément déterminant la fréquence comportant des inductances et des capacités localisées l'élément actif étant un dispositif à semi-conducteurs l'élément actif étant une diode tunnel
This semiconductor module manufacturing device comprises: a first punch; a second punch; and a carrier for holding a support body on which a semiconductor element is placed. The first punch approaches relative to the carrier from a first side in a first direction and the second punch approaches relative to the carrier from a second side in the first direction, and as a result thereof, bonding of the support body and the semiconductor element is carried out. The semiconductor element is positioned on the second side in the first direction with respect to the support body, and has a first ferromagnetic layer. The carrier includes a magnet part positioned on the first side in the first direction with respect to the support body.
This semiconductor device comprises: a first chip mounted on a first die pad; a second chip mounted on a second die pad; an insulating chip mounted on the first die pad; a first bonding material for bonding the first die pad and the first chip; a second bonding material for bonding the second die pad and the second chip; and a third bonding material for bonding the first die pad and the insulating chip. The insulating chip includes: a third semiconductor substrate; a third insulating layer that is provided on the third semiconductor substrate; and a transformer that is disposed inside of the third insulating layer, and that includes a first coil and a second coil which are insulated from each other. The third semiconductor substrate is bonded to the first die pad by the third bonding material. The third bonding material is an insulating bonding material.
H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
H01F 17/00 - Inductances fixes du type pour signaux
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/04 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
This semiconductor device comprises a substrate, a plurality of substrate terminals provided so as to pierce the substrate in the thickness direction of the substrate, a semiconductor chip including a plurality of chip terminals, and a first encapsulating resin. The plurality of chip terminals are electrically connected to the plurality of substrate terminals. The first encapsulating resin covers a chip front surface, a first chip side surface, and a second chip side surface of the semiconductor chip. The plurality of substrate terminals include a heat dissipation terminal including a portion lying on the outer side of the semiconductor chip in a plan view. The semiconductor device includes a heat dissipation member provided so as to be in contact with each of the chip back surface, the encapsulating surface of the first encapsulating resin, and the terminal front surface of the heat dissipation terminal.
This semiconductor device comprises a first terminal, a second terminal, a first semiconductor element, and a first heat dissipation member. The second terminal is positioned on one side of the first terminal in a first direction. The first semiconductor element is positioned on the opposite side of the second terminal with respect to the first terminal. The first semiconductor element is electrically connected to the first terminal. The first heat dissipation member is connected to the first terminal. A first flow path is provided between the first terminal and the second terminal in the first direction. The first heat dissipation member is accommodated in the first flow path.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
27.
ACTIVE CLAMP CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND VEHICLE
An active clamp circuit 20 comprises, for example: a first transistor 21 in which a first main electrode is connected to a control electrode of an output transistor 9; a first diode 22 and a second diode 23 that are connected, in series and with opposite polarities from each other, between a control electrode of the first transistor 21 and a second main electrode of the same; a second transistor 24a in which a first main electrode is connected to the second main electrode of the first transistor 21 and a second main electrode is connected to a first main electrode of the output transistor 9; a first resistor 25 that is connected between a control electrode of the second transistor 24a and the first main electrode of the same; and a third diode 26 that is connected between the control electrode of the second transistor 24a and the second main electrode of the same.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
H10D 30/65 - Transistors FET DMOS latéraux [LDMOS]
28.
SEMICONDUCTOR DEVICE, SIGNAL TRANSMISSION DEVICE, ELECTRONIC APPARATUS, AND VEHICLE
A semiconductor device 410 includes an input terminal 411a, a threshold voltage generation circuit 411d, and at least one comparison circuit 411e. The threshold voltage generation circuit 411d is configured to generate at least one threshold voltage Vthx1 to VthxN having a variation component dependent on a power supply voltage VCC1. The comparison circuit 411e is configured to compare an input signal AIN with the threshold voltages Vthx1 to VthxN, and to generate comparison signals S1 to SN based on the comparison result.
This power control unit includes: a plurality of power modules; and a mounting substrate on which the plurality of power modules are mounted. The plurality of power modules are disposed along a second direction. The mounting substrate has: an insulating layer; a first conductive part; a second conductive part; and a plurality of third conductive parts. The first conductive part has a band shape along the second direction, and first terminal surfaces of the plurality of power modules are conductively joined to the first conductive part. The second conductive part has a band shape along the second direction and is spaced apart from the first conductive part, and second terminal surfaces of the plurality of power modules are conductively joined to the second conductive part. The plurality of third conductive parts are spaced apart from the first conductive part and the second conductive part, and third terminal surfaces of the plurality of power modules are conductively joined to the third conductive parts, respectively.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
This semiconductor device includes: a chip having a main surface; a drift region of a first conductivity type formed on a surface layer part of the main surface; a gate structure of a trench electrode type formed on the main surface so as to be positioned in the drift region; and a well region of a second conductivity type formed in a region below the gate structure, along a bottom wall of the gate structure, in the drift region. The well region includes a plurality of first well regions that have a first bottom part having a first depth, and are formed at a first interval in the depth direction of the gate structure. Adjacent first well regions oppose each other, across a portion of the drift region, in the depth direction of the gate structure.
This semiconductor device includes a plurality of terminals, a semiconductor chip that is mounted on the plurality of terminals, and a sealing resin for sealing the plurality of terminals and the semiconductor chip. Each of the plurality of terminals includes a terminal part and a mounting part. The terminal part is disposed on the outer side of the semiconductor chip. The mounting part extends from the terminal part toward the semiconductor chip in a plannar view, and the semiconductor chip is mounted thereon. The semiconductor device includes a cover layer which is in contact with at least one of a mounting surface of the mounting part and a terminal surface of the terminal part. The linear expansion coefficient of the cover layer is smaller than the linear expansion coefficient of the plurality of terminals.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
32.
SEMICONDUCTOR DEVICE, AND PACKAGE OF SEMICONDUCTOR DEVICE
This semiconductor device is configured so as to improve bonding strength to a wiring board. The semiconductor device includes a first lead, a semiconductor element, and a sealing resin. The semiconductor element is electrically connected to the first lead. The sealing resin covers a part of the first lead and the semiconductor element. The first lead has a first outer part that protrudes from the sealing resin. The first outer part has a first mounting surface that faces one side in a first direction. The first outer part is provided with a first opening that penetrates through the first outer part from the first mounting surface.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
This semiconductor module includes a substrate, an encapsulating resin, a filling part, and a metal layer. The substrate has a front surface and a back surface. The back surface is located on the reverse side from the front surface. The encapsulating resin is provided on the front surface. The metal layer covers the filling part in a plan view of the front surface. The substrate has a recess extending from the front surface to the back surface. The filling part is connected to the recess.
H01L 33/62 - Dispositions pour conduire le courant électrique vers le corps semi-conducteur ou depuis celui-ci, p.ex. grille de connexion, fil de connexion ou billes de soudure
A semiconductor device according to the present invention comprises at least one lead, at least one semiconductor element that is provided on one side in the thickness direction of the at least one lead, a plurality of wires that are each electrically connected to at least one of the at least one lead and the at least one semiconductor element, and a sealing resin that covers the at least one semiconductor element, the plurality of wires, and at least a portion of the at least one lead. The plurality of wires include a first wire and a second wire. The second wire is curved so as to protrude toward the first wire as seen in the thickness direction. The second wire straddles the first wire as seen in the thickness direction and is separated from the first wire in the thickness direction.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
35.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device comprises a plurality of terminals, a semiconductor chip mounted on the plurality of terminals, and a sealing resin for sealing the plurality of terminals and the semiconductor chip. Each of the plurality of terminals includes: a rear surface, at least a part of which is exposed from the sealing resin; a front surface on which the semiconductor chip is mounted; a tip surface which is provided within the sealing resin and which is an end surface in a first direction orthogonal to the Z direction; and a projecting portion which is positioned at an intermediate portion in the Z direction on the tip surface.
This semiconductor device comprises: a plurality of terminals that include a terminal obverse surface and a terminal reverse surface facing the opposite side from the terminal obverse surface; a semiconductor chip that is mounted on the plurality of terminals; and an encapsulating resin for encapsulating the plurality of terminals and the semiconductor chip. The plurality of terminals include: a terminal portion that includes a terminal portion reverse surface, which is exposed from the encapsulating resin on the terminal reverse surface; a mounting portion that extends from the terminal portion in a first direction orthogonal to a Z direction, which is the thickness direction of the terminal, and has the semiconductor chip mounted thereon; a groove portion that is provided at least in the mounting portion and extends in the first direction; and wall portions that are positioned at both ends in a second direction orthogonal to both the Z direction and the first direction by the groove portion and extend in the first direction.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
This semiconductor device includes: a first impurity region, a second impurity region, and a third impurity region, which are formed on a chip; a trench which is formed in the chip; a trench insulating film which is formed on the inner surface of the trench; a conductive embedded body which is embedded in the trench; and an electric field attenuated layer which is formed on a bottom part of the trench. The electric field attenuated layer includes: a first layer which is formed away from the bottom part of the trench toward a second main surface side, and has a first impurity concentration; and a second layer which is formed between the first layer and the bottom part of the trench, and has a second impurity concentration that is higher than the first impurity concentration.
This semiconductor device includes: a chip having a main surface; a semiconductor region of a first conductivity type formed on a surface layer part of the main surface; a device structure having a source structure and formed in the semiconductor region in a part inside the main surface; a peripheral source electrode part having a first outer edge, disposed on a peripheral edge part of the main surface, and electrically connected to the source structure; and a termination region of a second conductivity type having a second outer edge positioned closer to the peripheral edge side of the main surface than the first outer edge and formed in the surface layer part of the semiconductor region at the peripheral edge part of the main surface, the termination region being electrically connected to the peripheral source electrode part. A first distance between the first outer edge of the peripheral source electrode part and the second outer edge of the terminal region is 10 μm or more.
This resistance circuit 71 includes pads P11 and P12, unit resistance elements R(1)-R(5) having a unit resistance value r, wiring L11 conductively connecting the pad P11 and the unit resistance element R(1), and wiring L12 conductively connecting the pad P12 and the unit resistance element R(5). The unit resistance elements R(1)-R(5) are each formed in a rectangular shape having a direction x as a lateral direction and a direction y as a longitudinal direction in plan view, and are arranged so as to be adjacent to each other along the direction x. The unit resistance elements R(1)-R(4) are connected so as to have a combined resistance value equal to the unit resistance value r between a contact point S and a contact point E. The contact point S is formed at the upper end in the longitudinal direction of the unit resistance element R(1). The contact point E is formed at the lower end in the longitudinal direction of the unit resistance element R(5). The wiring L11 is extended out in the direction x from the contact point S. The wiring L12 is extended out in the direction y from the contact point E.
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
This semiconductor device includes: a chip that has a main surface; a semiconductor region of a first conductivity type that is formed in a surface layer section of the main surface; a trench-type gate structure that is formed in the main surface and is located within the semiconductor region; a rectification region of the first conductivity type that is formed in the surface layer section of the main surface, neighboring the gate structure; and a main surface electrode that is electrically isolated from the gate structure on the main surface, and forms a Schottky junction with the rectification region.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
This semiconductor device includes: a chip having a major surface; a trench-electrode type capacitor structure which is formed on the major surface and to which a first potential is applied; a dielectric film which covers the capacitor structure on the major surface; and a pad electrode disposed on the dielectric film so as to form a capacitive coupling with the capacitor structure via the dielectric film and to which a second potential different from the first potential is applied.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
This semiconductor device includes: a chip having a main surface; a pad region provided on the main surface; a first electrode that is disposed on the main surface of the pad region, a first potential being applied to the first electrode; a side wall dielectric film that covers the side wall of the first electrode in the pad region; and a second electrode that is disposed on the main surface so as to form a capacitive coupling with the first electrode via the side wall dielectric film in the pad region, a second potential different from the first potential being applied to the second electrode.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
This semiconductor device comprises: a semiconductor substrate 1; an insulation layer 2 provided on the semiconductor substrate 1; a resistor R embedded in the insulation layer 2 and composed of a plurality of resistance layers electrically connected together; a first electrode E1 electrically connected to a first end part of the resistor R; a second electrode E2 electrically connected to a second end part of the resistor R; and a plurality of first dummy wires 5 arranged around the first electrode E1 and respectively capacitively coupled to the plurality of resistance layers in the resistor R.
This semiconductor device is provided with: a first lead that includes a first pad part; a first semiconductor element; a first wire; and a sealing resin. The first pad part has a first mounting surface that faces in a first direction. The first semiconductor element is bonded to the first mounting surface. The first wire has a first bonding part and a second bonding part. The first wire is provided with a first protrusion that covers the second bonding part and is covered by the sealing resin. The first pad part is provided with a first hole which is located closer to the second bonding part than to the first bonding part, and which penetrates through the first pad part in the first direction from the first mounting surface. A part of the sealing resin is housed in the first hole.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
A semiconductor device includes: a chip which has a main surface; an active region which is provided in the main surface; a pad region which is provided outside the active region in the main surface; an insulated gate typed transistor structure which is formed on the main surface of the active region; a trench electrode typed capacitor structure which is formed on the main surface of the pad region and forms a capacitive coupling with the chip; and a pad electrode which is disposed on the main surface of the pad region and is electrically connected to the capacitor structure.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
This semiconductor device includes: a chip having a main surface; an active region provided on the main surface; a pad region provided outside the active region on the main surface; an insulated gate transistor structure formed on the main surface of the active region; a trench-electrode-type capacitor structure formed on the main surface of the pad region, the trench-electrode-type capacitor structure forming a capacitive coupling with the chip; and a pad electrode disposed on the main surface of the pad region, the pad electrode being electrically connected to the capacitor structure.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
A signal transmission device 200X comprises a transmission circuit 410, a reception circuit 420 configured to output a driving control signal Ga in accordance with a first internal signal S2 and a second internal signal S1; an insulated circuit 430; and a driving circuit 510. The transmission circuit 410 drives at least one of the first internal signal S2 and the second internal signal S1 at a specific period in accordance with an external signal ASC. The reception circuit 420 detects that the period of at least one of the first internal signal S2 and the second internal signal S1 is a specific period and outputs a driving suspension signal Gb which differs from the driving control signal Ga. The driving circuit 510 receives the driving suspension signal Gb, suspends driving of a driving target switch element SW, and puts an output node OUT of the driving circuit 510 in a high impedance state.
H03K 17/691 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ avec une isolation galvanique entre le circuit de commande et le circuit de sortie utilisant un couplage par transformateur
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H03K 17/567 - Circuits caractérisés par l'utilisation d'au moins deux types de dispositifs à semi-conducteurs, p. ex. BIMOS, dispositifs composites tels que IGBT
48.
SIGNAL TRANSMISSION APPARATUS, ELECTRONIC DEVICE PROVIDED WITH SIGNAL TRANSMISSION APPARATUS, AND VEHICLE PROVIDED WITH ELECTRONIC DEVICE
A signal transmission apparatus 200X comprises: a transmission circuit 410x that outputs a first internal signal S1 and a second internal signal S2 according to an input signal IN; a reception circuit 420x; a first drive circuit 501; and a second drive circuit 502. The transmission circuit 410x drives at least one of the first internal signal S1 and the second internal signal S2 at a specific cycle different from the cycle of the input signal IN according to an external signal ASC. The reception circuit 420x, upon detecting that the cycle of at least one of the first internal signal S1 and the second internal signal S2 is the specific cycle, disables the first drive circuit 501, and enables the second drive circuit 502.
H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H03K 17/08 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension
H03K 17/567 - Circuits caractérisés par l'utilisation d'au moins deux types de dispositifs à semi-conducteurs, p. ex. BIMOS, dispositifs composites tels que IGBT
H03K 17/691 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ avec une isolation galvanique entre le circuit de commande et le circuit de sortie utilisant un couplage par transformateur
49.
THERMAL PRINTING HEAD, THERMAL PRINTING SYSTEM, AND METHOD FOR MANUFACTURING THERMAL PRINTING HEAD
A thermal printing head according to the present invention comprises a substrate, a first insulating film, and a second insulating film. The substrate has a first main surface and a second main surface on the reverse surface from the first main surface. A protruding portion that protrudes toward the side opposite the second main surface is formed on the first main surface. A recessed section is formed in the surface of the protruding portion. The first insulating film is disposed on the first main surface so as to cover the protruding portion. The second insulating film is disposed on a surface with the first insulating film interposed therebetween. A through hole is formed in a portion of the first insulating film that faces the bottom surface of the recessed section with a gap therebetween.
ABNORMAL VOLTAGE PROTECTION CIRCUIT, SIGNAL TRANSMISSION DEVICE COMPRISING ABNORMAL VOLTAGE PROTECTION CIRCUIT, ELECTRONIC EQUIPMENT COMPRISING SIGNAL TRANSMISSION DEVICE, AND VEHICLE COMPRISING ELECTRONIC EQUIPMENT
An abnormal voltage protection circuit 502 comprises voltage-current conversion circuits 507, 511, a current-voltage conversion circuit, and abnormal voltage detection circuits C3, C4. The voltage-current conversion circuits 507, 511 are configured to convert a monitored voltage VEE2 that is negative with respect to a reference voltage into current signals I1, I3. The current-voltage conversion circuit is configured to convert the current signals I1, I3 into voltage signals V7, V11 that are positive with respect to the reference voltage. The abnormal voltage detection circuits C3, C4 are configured to compare the voltage signals V7, V11 with threshold voltages V8, V12 to detect whether the monitored voltage VEE2 is equal to or higher than an upper-limit voltage V8, or equal to or lower than a lower-limit voltage V12.
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
H02H 11/00 - Circuits de protection de sécurité pour empêcher la commutation de mise en service dans le cas où une condition électrique de travail indésirable pourrait en résulter
H03K 17/08 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension
H03K 17/691 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ avec une isolation galvanique entre le circuit de commande et le circuit de sortie utilisant un couplage par transformateur
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
51.
ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE
This electronic device comprises: a first member having a first main surface; an electronic element disposed on the first member; a connection member electrically connected to the electronic element; a second member having a second rear surface; and a sealing resin covering portions of the first member and the second member, as well as covering the electronic element and the connection member. The second member has a connection unit to which a terminal unit and the connection member are connected. The first main surface has a first flat section and a first convex section. The first convex section protrudes further to a first side in the thickness direction as compared to the first flat section. The second rear surface has a second flat section and a second convex section. The second convex section protrudes further to a second side in the thickness direction as compared to the second flat section.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
52.
SIGNAL TRANSMISSION APPARATUS, ELECTRONIC DEVICE, AND VEHICLE
A signal transmission apparatus 400 comprises: an insulation element 435 for performing signal transmission between a primary circuit system 400p and a secondary circuit system 400s while providing insulation therebetween; a self-diagnosis circuit 424 which is provided in the secondary circuit system 400s and performs self-diagnosis of the secondary circuit system 400s; a storage circuit 425 which is provided in the secondary circuit system 400s and in which memory access is permitted after completion of the self-diagnosis; and a transmission circuit 422 which is provided in the secondary circuit system 400s and outputs a transmission pulse signal S1 to the insulation element 435. The transmission circuit 422 generates one pulse or a group of a plurality of pulses in the transmission pulse signal S1 at the completion timing of each of the self-diagnosis and the memory access, and continues generating pulses at the period of a first time T1 in the transmission pulse signal S1 when an abnormality in the memory access is being detected.
H03K 17/691 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ avec une isolation galvanique entre le circuit de commande et le circuit de sortie utilisant un couplage par transformateur
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
This semiconductor device includes: a base impurity region of a second conductivity type strip-shaped to be long in a first direction and formed in a surface layer part of a semiconductor region of a first conductivity type; a first impurity region formed in a surface layer part of the base impurity region; a gate electrode formed in a strip shape long in the first direction and opposed to a channel region of the base impurity region with a gate insulating film interposed; a Schottky region formed by a part of the semiconductor region and dividing the base impurity region into a plurality of unit cells along a second direction intersecting the first direction; and a main surface electrode making a Schottky junction to the Schottky region.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
This electronic device includes: a first connection object; a first connection member having a first connecting part connected, on a first side in a thickness direction, to the first connection object and a first loop part linked to the first connecting part, a first metal being used as a principal component of the first connection member; and a second connection member having a second connecting part connected to the first connecting part and a second loop part linked to the second connecting part and spaced apart from the first loop part, a second metal having a different thermoelectric power from that of the first metal being used as a principal component of the second connection member. The first connecting part has: a first peak-shaped section which has a protruding shape on the first side in the thickness direction and which extends in a first direction intersecting the thickness direction; and two first extending sections which extend on both sides in a direction intersecting the first direction.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
G01K 7/20 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments résistifs l'élément étant une résistance linéaire, p. ex. un thermomètre à résistance de platine dans un circuit spécialement adapté, p. ex. un circuit en pont
This semiconductor device includes a semiconductor element including a surface electrode formed on the element surface thereof. The element surface includes an active region in which power transistors are formed, and a control circuit region in which a control circuit for controlling the power transistors is formed. The active region is formed so as to surround the control circuit region from both sides in a second direction and one side in a first direction. The surface electrode is disposed on the active region at a position different from the control circuit region, and is formed so as to surround the control circuit region from both sides in the second direction and one side in the first direction when viewed from the thickness direction thereof.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
56.
OVERCURRENT PROTECTION CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC EQUIPMENT, AND VEHICLE
An overcurrent protection circuit 34 comprises: a sense signal generation circuit 50 that generates a sense signal Vsns 1 in accordance with a monitored current IOUT; a count maximum value setting circuit 60 that sets a count maximum value Cmax in accordance with the results of comparing a second sense signal Vsns 2 corresponding to the sense signal Vsns 1 with thresholds Vth(0) to Vth(n); and a counter 70 that counts up a count value CNT when the monitored current IOUT is larger than a count start threshold Ith(0) (when Vsns 2 < Vth1(0) in this drawing), and forcibly stops the monitored current IOUT when the count value CNT reaches the count maximum value Cmax.
H02H 3/093 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge avec des moyens de temporisation
H02H 3/087 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge pour des systèmes à courant continu
57.
SEMICONDUCTOR DEVICE, VEHICLE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device comprises a support, a first semiconductor element that is supported by the support, and a first bonding layer that is interposed between the support and the first semiconductor element. The first bonding layer has a flat portion and a protruding portion. The dimension of the protruding portion in the thickness direction of the support is greater than that of the flat portion, and the protruding portion is in contact with an edge of the first bonding layer that extends in a first direction orthogonal to said thickness direction. The protruding portion has a top portion farthest from the support in the thickness direction. When viewed in the thickness direction, the flat portion overlaps the first semiconductor element. When viewed in the thickness direction, the top portion is separated from the first semiconductor element toward a first side in a second direction orthogonal to the thickness direction and the first direction.
This semiconductor device comprises: a main transistor that has a main surface on which a main source electrode and a main gate electrode are formed; and a sub-transistor at least a part of which is disposed over the main gate electrode. The sub-transistor has a sub-drain electrode electrically connected to the main gate electrode, and a sub-source electrode electrically connected to the main source electrode.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
This semiconductor device comprises a first terminal, a second terminal, a third terminal, a fourth terminal, a first lead, a second lead, a semiconductor element, and a sealing resin. A dimension of a first exposed surface of the first lead is larger than a dimension of a first mounting surface of the first terminal. A dimension of a second exposed surface of the second lead is larger than a dimension of a second mounting surface of the second terminal. When viewed in a third direction, which is a direction normal to the bottom surface of the sealing resin, a first end of the first exposed surface and a third end of the second exposed surface are positioned further inward than the peripheral edge of the sealing resin. When viewed in the third direction, a fourth end of the second exposed surface overlaps the peripheral edge of the sealing resin.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
This semiconductor device is provided with a first lead, a semiconductor element, and a sealing resin. The first lead has a pad part and a first support part. The first support part has a first surface, a second surface, and a first end surface. The pad part is exposed from a bottom surface of the sealing resin. The dimension of the sealing resin in a first direction from the bottom surface to the second surface is smaller than the dimension of the sealing resin in the first direction z from a top surface of the sealing resin to the first surface. The dimension of the second surface in a second direction is 50% or more of the dimension of a region of the bottom surface, the region being adjacent to the pad part on one side in the second direction and overlapping with the second surface when viewed in the first direction.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
61.
METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
A method for producing a semiconductor device according to the present invention comprises a first step, a second step, a third step, and a fourth step. In the third step, a pad part is exposed from the bottom surface of a sealing resin. In the third step, the dimensions of the sealing resin from the bottom surface to a second surface of a first support part in a first direction are made smaller than the dimensions of the sealing resin from the top surface of the sealing resin to a first surface of the first support part in the first direction. In the fourth step, the first support part is cut by applying a compressive force to the top surface while supporting the second surface with a support body. In the fourth step, a first end surface that faces one side of a second direction and that is exposed from the sealing resin is formed on the first support part.
This semiconductor device includes a support, a first semiconductor element supported by said support, and a first bonding sheet interposed between the support and the first semiconductor element. The first bonding sheet has a first portion and a second portion. The first portion includes an area that overlaps the first semiconductor element when viewed in the thickness direction of the support. The second portion includes an area that does not overlap the first semiconductor element when viewed in said thickness direction. The second portion is thinner than the first portion in said thickness direction.
This semiconductor device includes: a chip having a main surface; a body region formed in a surface layer portion of the main surface; a plurality of gate electrodes disposed on both sides of the body region on the main surface; and a connection electrode formed in a region between the plurality of gate electrodes on the main surface so as to overlap the body region in the thickness direction, and connected to the plurality of gate electrodes.
A semiconductor device according to the present invention comprises a plurality of first leads, a semiconductor element, and a sealing resin. The plurality of first leads each has: a first lead first surface that faces a first side of the thickness direction and that is exposed from a resin first surface; a first lead second surface that faces a second side of the thickness direction; and a first lead first end surface that is located between the first lead first surface and the first lead second surface in the thickness direction, that faces the outer side of a first direction, and that is exposed from a resin side surface. The first lead first surface has a first narrow-width part that connects to the first lead first end surface and a first wide-width part that is located on the inner side of the first direction with respect to the first narrow-width part. The first narrow-width part has a first edge that is in contact with the first lead first end surface. A first width that is the size of the first edge in a second direction is smaller than a second width that is the size of the first wide-width part in the second direction.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
This semiconductor device is provided with: a semiconductor element that has an electrode positioned on one side in a first direction; a conduction member that is conductively bonded to the electrode; and a sealing resin that covers the semiconductor element and the conduction member. The conduction member has a first joint part that is conductively bonded to the electrode, and a main part that extends from the first joint part. The dimension of the first joint part in a direction orthogonal to the first direction is larger than the dimension of the main part in a direction orthogonal to the direction in which the main part extends. The sealing resin has a top surface that faces the one side in the first direction. The main part has a first part that is positioned closest to the top surface in the first direction. When viewed in the first direction, the first part is at a distance from the semiconductor element.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
This semiconductor laser element comprises an element body which outputs laser light from a first end surface. The element body includes a first recessed part that is provided between a first side surface and an element front surface and that is recessed toward the inside of the element body, and a second recessed part that is provided between a second side surface and the element front surface and that is recessed toward the inside of the element body. The first recessed part includes a first inner surface that faces the same side as the first side surface, and first connection surface that connects the first inner surface and the first side surface. The second recessed part includes a second inner surface that faces the same side as the second side surface, and a second connection surface that connects the second inner surface and the second side surface. The first connection surface and the second connection surface each include an inclined surface which is inclined with respect to the element front surface at an angle differing from the that of first side surface and that of the second side surface.
H01S 5/02 - Détails ou composants structurels non essentiels au fonctionnement laser
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
67.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC EQUIPMENT, AND VEHICLE
This signal transmission device 400 comprises a transmission circuit 411, a reception circuit 421, and an insulation element 431 for transmitting a pulse signal between the transmission circuit 411 and the reception circuit 421 while insulating these circuits. The transmission circuit 411 includes an input terminal 411a for receiving input of an analog signal AIN, a comparison circuit 411b for comparing the analog signal AIN with a plurality of threshold values Vth1 to VthN to generate a plurality of comparison signals S1 to SN, and a pulse signal generation circuit 411c for generating a pulse signal PS in accordance with the plurality of comparison signals S1 to SN.
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
This semiconductor light-emitting device comprises: a substrate; a plurality of obverse-surface electrodes; a plurality of reverse-surface electrodes; a semiconductor light-emitting element; a first drive circuit; and a second drive circuit. The substrate has a substrate obverse surface and a substrate reverse surface. The obverse-surface electrodes are formed on the substrate obverse surface. The reverse-surface electrodes are formed on the substrate reverse surface, and are configured such that the semiconductor light-emitting device is mounted thereon. The semiconductor light-emitting element includes a first light-emitting unit and a second light-emitting unit. The first drive circuit drives the first light-emitting unit. The second drive circuit drives the second light-emitting unit. The semiconductor light-emitting element, the first drive circuit, and the second drive circuit are mounted on the obverse-surface electrodes.
This semiconductor device includes: a chip that has a main surface; a semiconductor region that has a first conductivity type and is formed in a surface layer part of the main surface; a termination region that has a second conductivity type and is formed in a surface layer part of the semiconductor region in a peripheral edge part of the main surface; and a high concentration region that has the first conductivity type, is formed in the surface layer part of the main surface so as to be positioned in a thickness range between the main surface and the bottom of the termination region, and has an impurity concentration that is higher than the impurity concentration of the semiconductor region.
This light-emitting semiconductor device includes: a plurality of front-surface electrodes formed on the front surface of a substrate; a plurality of back-surface electrodes formed on the back surface of the substrate; a first light-emitting semiconductor element; a second light-emitting semiconductor element; a first drive circuit for driving the first light-emitting semiconductor element; and a second drive circuit for driving the second light-emitting semiconductor element. The first light-emitting semiconductor element and the second light-emitting semiconductor element each include an element front-surface electrode and an element back-surface electrode. Mounted on the plurality of front-surface electrodes are: the element back-surface electrode of the first light-emitting semiconductor element; the element back-surface electrode of the second light-emitting semiconductor element; the first drive circuit; and the second drive circuit.
This semiconductor device includes: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer part of the main surface; and a termination region of a second conductivity type formed in a surface layer part of the semiconductor region at an interval from the main surface in the thickness direction of the chip, at a peripheral edge part of the main surface.
A current detection circuit (104) detects an inductor current (IL) flowing through the inductor (L1) of a switch output stage (SW1). The current detection circuit (104) is provided with a first current detection circuit (10) that generates a first current detection signal (S10) from a switch voltage (Vst1) generated by the switch output stage (SW1). The first current detection circuit (10) includes: a level shifter (11) that generates a pulse width modulation voltage (SWLVS) from the switch voltage (Vst1), said pulse width modulation voltage (SWLVS) being pulse-driven between an input voltage (Vi) and a ground voltage (GND); a first low-pass filter (12) that generates an average pulse width modulation voltage (PWMave) from the pulse width modulation voltage (SWLVS); a second low-pass filter (13) that generates an average switch voltage (SWave) from the switch voltage (Vst1); and a subtractor (14) that subtracts the average switch voltage (SWave) from the average pulse width modulation voltage (PWMave) to generate the first current detection signal (S10).
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
73.
ELECTRIC CURRENT DETECTION CIRCUIT, FEEDBACK CONTROL CIRCUIT, ELECTRIC POWER SUPPLY CONTROL DEVICE, AND SWITCHING ELECTRIC POWER SUPPLY
This electric current detection circuit detects an inductor electric current that flows through an inductor of a switch output stage used for a switching power supply of a stack system for generating an output voltage from an input voltage, and generates an electric current detection signal for electric current mode control by a predetermined current gain Gc. The current gain Gc is set to a different value (GcH, GcL) according to the frequency band.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
74.
SEMICONDUCTOR DEVICE, POWER SUPPLY DEVICE, AND VEHICLE
The pattern (2, 2A, 2B, 2C) of the semiconductor device (100, 100A, 100B, 100C) has a first node (21, 21a, 21b, 21c) formed on an outer peripheral part and configured to be connected to a first potential, and has a second node (22, 22b, 22c) insulated from the first node (21, 21a, 21b, 21c) and configured so that a second potential different from the first potential is applied. The first node (21, 21a, 21b, 21c) and the second node (22, 22b, 22c) are configured such that at least a portion thereof faces each other.
This semiconductor device comprises: a chip having a main surface; a first region of a first conductivity type formed in a surface layer portion of the main surface in the chip; a second region of a second conductivity type formed in a region on the main surface side with respect to the first region in the chip; a trench type gate structure formed in the main surface and positioned in the second region; and a high concentration region of the second conductivity type formed laterally of the gate structure in the second region and having an impurity concentration higher than the impurity concentration of the second region.
This semiconductor device includes: a chip having a main surface; a first region of a first conductivity type formed in a surface layer part of the main surface in the chip; a second region of a second conductivity type formed in a region on the main surface side with respect to the first region in the chip; a trench-type gate structure formed on the main surface and spaced apart from a bottom part of the second region; an impurity region of the first conductivity type formed on the surface layer part of the main surface along the gate structure; and a drift region of the first conductivity type which is formed in a thickness range between the bottom part of the second region and a bottom wall of the gate structure and separates the impurity region and a channel.
An example integrated circuit includes a first transistor coupling to a first end of a coil of a DC contactor via a first pin, a second transistor coupling to a second end of the coil via a second pin, and a third pin received an enable signal. The second transistor and a timer are activated based on the enable signal. The integrated circuit includes circuitry operable to: in response to activating the second transistor, increase an average current in the coil to a first target level; in response to the timer indicating that a predetermined amount of time has elapsed, adjust the average current to a second target level which be lower than the first target level; maintain the average current at the second target level until a disable signal is received via the third pin; and deactivate the second transistor in response to receiving the disable signal.
A transducer (1) comprises: a piezoelectric element (10) provided with a pair of electrodes (11, 12) and a piezoelectric film (13) sandwiched between the pair of electrodes (11, 12); a film support part (17); and a vibration film (16) supported by the film support part (17) so as to be able to vibrate in the thickness direction of the piezoelectric element (10). A plurality of openings (15) that continuously penetrate the vibration film (16) from the piezoelectric element (10) are provided, and the shortest distance between two points facing each other across the center of the opening (15) in each of the plurality of openings (15) is 20 μm or less.
This method for manufacturing a semiconductor device in which a base material is bonded to a heat dissipation member is configured so that the shape of sealing resin can be more favorably maintained. The manufacturing method comprises a first step, a second step, and a third step. In the first step, a base material having an insulating layer and an electroconductive layer positioned on one first-direction side of the insulating layer is bonded to the heat dissipation member. In the second step, a semiconductor element is bonded to the electroconductive layer. In the third step, sealing resin covering the semiconductor element is formed. In the first step, the base material is bonded to the heat dissipation member such that the insulating layer is positioned between the heat dissipation member and the electroconductive layer. The third step is performed after each of the first step and the second step is completed.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
INBOOT1BOOT3BOOT1BOOT3BOOT1BOOT3BOOT3) and first to third boot switches (Ma to Mc), the first to third boot capacitors and the first to third boot switches being provided to correspond to the first to third boot wirings, respectively.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
This semiconductor device comprises: a first impurity region of a first conductivity type formed on a surface layer portion of a first main surface of a chip; a second impurity region of a second conductivity type formed on a surface layer portion of the first impurity region; a third impurity region of the first conductivity type formed on a surface layer portion of the second impurity region; a trench reaching the first impurity region from the first main surface; an electric field relaxation structure of the second conductivity type that is formed on a bottom portion of the trench; a first contact region that is formed along a side surface on one side of the trench from the first main surface toward a second main surface of the chip and that is electrically connected to the second impurity region and the electric field relaxation structure; and a second contact region that is formed along a side surface on the other side of the trench from the first main surface toward the second main surface and that is electrically connected to the second impurity region and the electric field relaxation structure. A plurality of first contact regions and a plurality of second contact regions are arranged along the length direction of the trench.
A semiconductor device according to the present invention comprises: a first lead; a semiconductor element that is mounted on one side of the first lead in the thickness direction and has a semiconductor layer; and a bonding layer that is interposed between the first lead and the semiconductor layer to bond the first lead and the semiconductor element. The bonding layer includes a first intermetallic compound layer containing Sn and Cu.
INMIDOUTOUT). The states of the first through fourth switching elements are switched between first through third states on the basis of information about the output voltage and current information about an inductor (L1). In the first state, the second and fourth switching elements are on and the first and third switching elements are off. In the second state, the second and fourth switching elements are off and the first and third switching elements are on. In the third state, all of the first through fourth switching elements are off.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
This thermal print head comprises a substrate and a glaze layer. The substrate has a main surface. The glaze layer is disposed on the main surface. The glaze layer includes a hollow filler.
This chip resistor is provided with an insulating substrate, a resistor, a back-surface electrode, and a side-surface electrode. The insulating substrate includes a front surface, a back surface, and a side surface. The resistor is disposed on the back surface. The back-surface electrode is disposed on the back surface. The side-surface electrode is disposed on the side surface and the back-surface electrode. A direction perpendicular to the back surface is defined as a Z direction. The side-surface electrode has a lowermost point. The lowermost point is disposed at a position farthest from the back surface in the Z direction. The side-surface electrode has a lowermost surface. The lowermost surface is a region from the side surface to the lowermost point. The lowermost surface is inclined with respect to the back surface. The lowermost surface has a first region. The first region includes the lowermost point. In the first region, the inclination angle of the lowermost surface with respect to the back surface is 1° or more and 10° or less.
H01C 1/142 - Bornes ou points de prise spécialement adaptés aux résistancesDispositions de bornes ou points de prise sur les résistances les bornes ou points de prise étant constitués par un revêtement appliqué sur l'élément résistif
H01C 7/00 - Résistances fixes constituées par une ou plusieurs couches ou revêtementsRésistances fixes constituées de matériaux conducteurs en poudre ou de matériaux semi-conducteurs en poudre avec ou sans matériaux isolants
This semiconductor device comprises: a first impurity region of a first conductivity type formed on a surface layer portion of a first main surface of a chip; a second impurity region of a second conductivity type formed on a surface layer portion of the first impurity region; a third impurity region of the first conductivity type formed on a surface layer portion of the second impurity region; a plurality of trenches arranged at intervals in a first direction, the trenches extending in a second direction intersecting the first direction; a first electric field relaxation structure of the second conductivity type formed integrally with the second impurity region in contact with a first trench among the plurality of trenches and formed on one side in the first direction with respect to the first trench; and a second electric field relaxation structure of the second conductivity type formed integrally with the second impurity region in contact with the first trench and formed on the other side in the first direction with respect to the first trench. The plurality of first electric field relaxation structures and the plurality of second electric field relaxation structures are alternately arranged along the second direction.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
This nitride semiconductor device includes: a conductive substrate having a substrate upper surface; a high-resistance layer; a nitride semiconductor layer formed on the high-resistance layer; a first electrode (source electrode) formed on the nitride semiconductor layer; and a via. The high-resistance layer is formed on the substrate upper surface, and has a higher resistance value than does the conductive substrate. The via is electrically connected to the first electrode (source electrode), is provided so as to pass through the nitride semiconductor layer and the high-resistance layer, and contacts the substrate upper surface.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
H01L 29/812 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à grille Schottky
88.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC APPARATUS, AND VEHICLE
A signal transmission device (400) is configured to have: a transmission portion (410) configured to output a primary-side transmission pulse signal (Stp) having the number of pulses determined in accordance with an input signal (Sin) each time an input signal is input and a predetermined first time (T1) elapses; and a reception portion (420) configured to receive a secondary-side transmission pulse signal (Srp) having the same number of pulses as that of the primary-side transmission pulse signal (Stp) by performing insulation communication with the transmission portion (410) and to output an output signal (Sout) in accordance with the number of pulses.
H03K 17/691 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ avec une isolation galvanique entre le circuit de commande et le circuit de sortie utilisant un couplage par transformateur
This electronic device comprises an electronic chip, a mounting part on which the electronic chip is mounted, and a bonding part for bonding the electronic chip to the mounting part. The electronic chip has a first dimension along the thickness direction of 150 μm or less. The bonding part has an interposed portion and an outer peripheral portion and, when viewed along the thickness direction, overlaps 80% or more of the peripheral edge of the electronic chip. The interposed portion is interposed between the electronic chip and the mounting part. The outer peripheral portion is in contact with at least the lower end edges of the side surfaces of the chip. The outer peripheral portion has a second dimension along the thickness direction, which is up to 2/3 times the first dimension.
H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
This semiconductor device includes: a chip that has a main face; a first conductivity-type semiconductor region that is formed in a surface layer portion of the main face; a trench-type source structure that is formed on the main face and is located in the semiconductor region; and a second conductivity-type impurity region that is formed in a region directly below the source structure in the chip and that forms a pn junction portion with the semiconductor region.
A semiconductor device (1) comprises: a communication unit (11) configured to receive, from the outside, communication data (RX) transmitted by serial communication; and a register (11A). The communication data includes first data (RW) for designating a read or a write, and second data (AM) capable of designating a read-back when the first data designates a write. When the first data designates the write, the communication unit only reads a number of bytes of data of an address designated by the second data in the register, the number being designated by the second data, and transmits the data to the outside.
A semiconductor device (1) is provided with: a reception unit (11) configured to receive communication data (RX) through serial communication from the outside; and a control unit (15). A group of semiconductor devices can be set in the semiconductor device. The communication data includes first data (B/PA) indicating whether or not the communication data is a broadcast, and second data (DA) indicating the group of semiconductor devices. The control unit determines that the communication data is a broadcast for the semiconductor device thereof when the group set in the semiconductor device thereof coincides with the group indicated by the second data.
Write data (WDT) transmitted via serial communication includes polarity data (CHnSG) representing a decrease or an increase, gain data (CHnGAIN) representing a gain value, and relative value data (DUTYn) representing a relative change value. A relative calculation unit (221) computes a calculation result by either subtracting a value obtained by multiplying the relative change value by the gain value from, or adding said value to, a present duty setting data (DIMSETn) value, in accordance with the polarity data. An update control unit (22) updates the duty setting data using the calculation result.
This electronic device is provided with a first electronic component, a sealing resin, and a first lead that comprises a first inner part and a first outer part. The first inner part comprises a first die pad part on which the first electronic component is mounted, and a first connection part that connects the first outer part and the first die pad part to each other. The first outer part is disposed on one side in a first direction with respect to the first die pad part. The first connection part is connected to a first side surface of the first die pad part. In a second direction, the center of the first outer part is located further toward one side in the second direction than the center of the first die pad part. The first side surface comprises a connection region that is connected to the first connection part, and a pair of side regions that are located on both sides of the connection region in the second direction.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 25/04 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés
This transformer chip comprises: a first insulation transformer including a first surface coil and a second surface coil that are arranged apart from each other in a first direction that is orthogonal to a thickness direction, and a first rear surface coil and a second rear surface coil that are arranged opposite to the first surface coil and the second surface coil; a second insulation transformer including a third surface coil and a fourth surface coil, and a third rear surface coil and a fourth rear surface coil that are arranged opposite to the third surface coil and the fourth surface coil; first dummy wiring provided on both sides of the first insulation transformer in a second direction that is orthogonal to the thickness direction and the first direction; and second dummy wiring provided on both sides of the second insulation transformer in the second direction and electrically insulated from the first dummy wiring. The first dummy wiring and the second dummy wiring are aligned in the first direction.
H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
96.
SIGNAL TRANSMISSION APPARATUS, ELECTRONIC DEVICE, AND VEHICLE
A signal transmission apparatus 400 comprises: a first chip 410 into which an input pulse signal IN is input; and a second chip 420 which, by carrying out isolated communication with the first chip 410, generates an output pulse signal OUT corresponding to the input pulse signal IN and drives a switching element. The second chip 420 includes a self-diagnosis circuit 600 for diagnosing whether or not each part of the second chip 420 functions correctly in response to a self-diagnosis command B_CMD transmitted from the first chip 410. The self-diagnosis circuit 600 disables the self-diagnosis command B_CMD when the self-diagnosis operation of the second chip 420 is finished.
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
H02P 29/024 - Détection d’un défaut, p. ex. court circuit, rotor bloqué, circuit ouvert ou perte de charge
H03K 17/00 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts
H03K 17/567 - Circuits caractérisés par l'utilisation d'au moins deux types de dispositifs à semi-conducteurs, p. ex. BIMOS, dispositifs composites tels que IGBT
H03K 17/691 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ avec une isolation galvanique entre le circuit de commande et le circuit de sortie utilisant un couplage par transformateur
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
This terahertz device includes a substrate, an electroconductive layer formed on a portion of a surface of the substrate, and an annular slot formed in the electroconductive layer. A first active element and a second active element are provided in the slot. The electroconductive layer includes a first electrode partitioned by the slot, and a second electrode formed so as to surround the first electrode via the slot. The first active element and the second active element are disposed across the first electrode on a reference line passing through the center of the first electrode in plan view. A first distance between the first end and the second end of the second electrode on the reference line is less than a first substrate distance between the first substrate end and the second substrate end of the substrate on the reference line.
G01R 29/08 - Mesure des caractéristiques du champ électromagnétique
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
H01L 29/66 - Types de dispositifs semi-conducteurs
H03B 7/14 - Production d'oscillations au moyen d'un élément actif ayant une résistance négative entre deux de ses électrodes avec un élément déterminant la fréquence comportant des inductances et des capacités réparties l'élément actif étant un dispositif à semi-conducteurs
98.
LOAD CONTROL DEVICE, IGNITER, ENGINE IGNITION DEVICE, AND VEHICLE
A load control device according to one embodiment of the present invention includes: a switch element having a first main terminal, a second main terminal, and a control terminal that are connected to a load; a shunt resistor that is electrically connected between the second main terminal and a ground terminal and that detects a current flowing in the switch element; a switch control device configured to output a drive signal for driving the switch element to the control terminal, on the basis of a detection signal based on a detection result of the shunt resistor and a control signal from an external control device; and a capacitor electrically connected in parallel with the shunt resistor between the second main terminal and the ground terminal.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
This semiconductor device comprises: a chip which has a first main surface and a second main surface that is on the reverse side to the first main surface; a first impurity region that has a first conductivity type and is formed in a surface layer part of the first main surface; a second impurity region that has a second conductivity type and is formed in a surface layer part of the first impurity region; a third impurity region that has the first conductivity type and is formed in a surface layer part of the second impurity region; a plurality of trenches which extend from the first main surface to the first impurity region through the third impurity region and the second impurity region; and an electric field attenuating structure that has the second conductivity type and is formed integrally with the second impurity region so as to extend over bottom walls of the plurality of trenches.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/12 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
This terahertz device includes slots formed in a conductive layer, connection slits formed in the conductive layer, and active elements provided inside the slots. The slots are formed in an annular shape. The conductive layer includes first electrodes partitioned by the slots, and a second electrode located outside the slots. The active elements are respectively provided to the first electrodes and are disposed at positions sandwiching the first electrodes with respect to the center of the slots, when viewed from a direction perpendicular to the surface.
G01R 29/08 - Mesure des caractéristiques du champ électromagnétique
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
H01L 29/66 - Types de dispositifs semi-conducteurs
H03B 7/14 - Production d'oscillations au moyen d'un élément actif ayant une résistance négative entre deux de ses électrodes avec un élément déterminant la fréquence comportant des inductances et des capacités réparties l'élément actif étant un dispositif à semi-conducteurs
brevets
